Alan Cheng

Constraint Satisfaction Problems (CSP) are a standard benchmark for current hardware technologies. Evaluate the speed and processing power of new hardware. In new technologies, it is appropriate to compare results with current benchmarks.

A type of CSP Unique, in which there are not many results (unlike SAT and Graph-Coloring) Are consisted of letters and symbols which can represent numerical values. Substituted values must solve the given equation. Hence the name of cryptoarithmetic problems.

This problem is a crypto-arithmetic problem. TWO +TWO FOUR The letters must be replaced with numbers 09, but no two different letters can have the same value (T=0, W=0). The problem is solved if the numbers substituted satisfy the equation.

Field Programmable Gate Arrays (FPGA) are used in current hardware technologies. Examples of usage:
Used in supercomputers Printers

Are programmable boards which directly converts program coding into logic circuits. Have fast calculation rates.

Faster Directly connect to the hardware components (unlike from IDE or OS) Simulation uses a processor (hardware) to process. However, it gives slower processing to due the amount of coding in between the internal hardware and software.

The goal of the project is to create an oracle that would be able to solve arbitrary cryptoarithmetic problems. The user would be able to input the values he/she desires to have

The circuit has to have limitation to prevent the circuit from having too much memory consumption. Therefore it is limited to only a 6+6=6 structure shown below:

X1 X2 X3 X4 X5 X6 + X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18

The circuit will have three parts

A Counter For testing all possible combinations and permutations A Good Number Checker For checking the validity of the input (if two number repeats or if similar letters have different values) The Main Oracle Which checks the validity of the given input

The Counter is consisted of 18 smaller counters (for each variable) connected by wires. It would only count 0-9, and will increase the counter to the left after each full cycle (from 0 to 9)

Counter 18 0 to 9
clk

over

over

Counter 2 0 to 9
clk

Counter 1 0 to 9
clk

Clock

This portion of the oracle consists of equality and inequality gates in which the whole circuit is re-compiled for each new problem. It maps each letter and uses equality for the same letter (i.e. o and o) and uses inequality for the rest
X1 X1 X2 X18 != = X2 X18

= !=

!= !=

= =
= !=

This oracle checks for the validity of the given inputs. This can easily be found out using the following series of equations:
X6 + X12 = 10C1 + X18 C1 + X5 + X11 = 10C2 + X17 ... C5 + X1 + X7 = X13

The full oracle can be expressed simply by the following diagram:

Counters

Main Oracle

Good Number

Output

I am still working on the TWO+TWO=FOUR problem in hardware

Partially working (2 solutions, with messed up HEX display outputs) Quartus ii error with the simulated RAM that I modeled.

In Verilog: Simulate arbitrary oracle circuit On FPGA: Run arbitrary oracle circuit Compare run time and analyze speed-up Write reports Emulate in Veloce

Sorry, no picture this time D: