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The circuit shown is a CMOS differential stage in which the aspect
ratio W/L is indicated. The NMOS devices have k = 25 0 / V2,
VT = 1.5 V and V0 = 1/ = 50 V; the PMOS devices have k =
12.5 0 / V2, VT = -1.5 V, V0 = 1/ = 100V.
(a)Determine the bias drain currents in 3, 5, and 7.
(b) Evaluate 0DM and the CMRR.
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Each stage of a CE-CE configuration uses transistor 0, and each is
biased at IC = 1 m0. The component values are Rs = 0.6 k,
RC1 = RC2 = 1.2k .
(a)Determine 0VO and the approximate value of fH.
(b) Estimate the location of the closest nondominant pole.
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