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Content at a Glance
Week 3
integer and floating point number representation review Logic circuit building blocks CPU Structure and architecture Component and System buses Von Neumann and wider architectures
March 20, 2012
machine does not care about nor does it attempt to interpret the data it holds. It is the programmers responsibility to interpret the stored bit pattern data. However, the machine provides support to enable signed and unsigned interpretation all processed data.
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so
A B = A + [ -B ] i.e. 2s comp addition 6 -2 --8 0110 6 0110 0010 becomes + [-2] 1110 ---------- ------1000 4 0100
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
bits n 8 16 32 64
signed (2sComp) -2n-2 to + (2n-21) - 128 to +127 -32768 to +32767 2.14748 * 109 9.223 * 1018
point data representation allow us to store fractional numbers, and is modelled on scientific notation. e.g.1: (+) 3.5 * 102 [ 350 ] e.g.2: - 25 * 10-3 [ - 0.025 ]
We
can store floating point numbers in three parts, namely: sign, significant, exponent The same applies to binary numbers
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IEEE754 Standard
lsb
is a small number range near (and including) zero which can not be represented in the normalized format. This is known as underflow. Zero is treated as a special case
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Expressible Numbers
(Stallings p.310)
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IEEE754 Standard
in 64-bit normalized binary format: lsb msb 1 11 bits biased exponent 52 bits Significand In a normalized binary number the msd is 1, which is implied (not stored).
arithmetic operations performed by numeric data processors (co-processors) are: addition subtraction multiplication and division
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
addition and subtraction it is necessary to have both operands with the same exponent value
1. 2.
3. 4.
The steps in are: check for zero values denormalize significant and equalize exponent values add/subtract the significant values normalize the result
point multiplication and division are simpler than addition and subtraction because the is no need to align exponents
The
steps in are: 1. check for zero values 2. add/subtract exponents 3. check for errors 4. multiply/divide significands 5. normalize 6. round
arithmetic operations suffer from rounding errors rounding errors occur because we cant represent all values exactly, so we approximate their values
March 20, 2012
guard
bits are additional bits attached to the rhs of the significand guard bits help to retain accuracy in the final result
NaN
NaN is
a symbolic quantity encoded in floating point numbers for a result which can not be represented in the available space or format e.g. result, or meaningless result from 0/0, / , or 0*
March 20, 2012
logic supports two conditions; true (T) and false (F) These conditions are represented by two distinct voltage levels; VH or 1, and VL or 0 There are three fundamental logic operators: AND (coincidence), OR (selection), NOT (negation or complement) All logic conditions can be met by expressions using a combination of the above three operations
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D Latch
Memory cell
n-bit Register
Dn D EN clk Qn
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D1 Q D EN Q
D0 D EN Q
Q1
Q0
Adder- Subtractor
(Stallings)
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Element is a Binary Adder. The two numbers (integers) are treated as Unsigned Numbers. The two numbers are presented to the adder from two registers. The result is stored in one of the registers or a third. Overflow is stored in an Overflow Flag.
March 20, 2012
Data Exchanges
Memory
to Processor Processor to Memory I/O to Processor Processor to I/O I/O to or from Memory
Buses
A
bus is a group of parallel conductors Carry information from one part of a computer to another. Four Types - Address bus, Data bus, Control bus, Power bus Bus pins are sometimes shared in order to reduce the overall size of the IC. This sharing of pins is achieved by switching or multiplexing.
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Types of Buses
Address
buses, send address information to memory and other devices. Data buses carry data in and out of the processor. Control buses carry supervisory signals such as clocks, interrupts, read / write etc. Power bus, does not carry information. They Transmit DC and ground voltages. Generally not considered a bus.
March 20, 2012
Bus Architecture
data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity
Most
Type
Dedicated Multiplexed
Method of Arbitration
Centralized Distributed
Timing
Synchronous Asynchronous March 20, 2012
Multiplexing
Processor Organization
Fetch
Instruction Read instruction from memory Interpret Instruction Decode instruction Fetch Data Read data from memory Process Data Perform an arithmetic or Logic operation on the data Write Data Write data to memory or I/O module
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Register Organization(1)
Computer System uses
hierarchy. The higher levels of memory are faster, smaller and more expensive (per bit). In the processor, the registers are above the main memory and cache in the hierarchy.
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a memory
Register Organization(2)
The registers
two functions User-visible registers, enable the programmer to optimize main memory references by using registers Control and Status registers, used by control unit to control the processor or the execution of programs.
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Purpose Registers Assigned to a variety of functions by the programmer Data Registers Used to hold data Address Registers Devoted to a particular addressing mode. Examples are
Segment
Condition
Codes (Flags) Hold conditions. Set by the processor hardware as a result of operations.
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Counter (PC) Contains the address of an instruction to be fetched. Instruction Register (IR) Contains the instruction most recently fetched. Memory Address Register (MAR) Contains the address of a location in memory. Memory Buffer Register (MBR) Contains a word of data to be written to the memory or the word most recently read.
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contains condition codes (flags) and other status information. Examples are
Sign Zero Carry Equal Overflow Interrupt
MC68000 32 bit registers, partitioned into eight data registers and nine address registers. Two registers are used as stack pointers. 32 bit program counter 16 bit status register
Intel 8086 Four 16 bit data registers and four 16 bit pointer/index registers Three pointer/index registers are dedicated to point to the segment and current instruction Includes an Instruction Pointer and 1 bit status/control flags.
Pentium Registers(1)
is a 16 bit register contains a 2 bit tag for floating point numeric registers. The tags enable to check the contents. There are four possible values
Valid Zero
Special Empty
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register indicates the condition of the processor. It includes six condition codes
Carry Parity Zero Sign
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Auxiliary
Overflow
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Intel in 1996 MMX is a set of highly optimized instructions for Multimedia tracks. MMX uses a 3 bit register address fields so that eight 64 bit MMX registers are supported. The existing floating register is used to store the MMX values.
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Registers thirty two 64 bit registers. (load, store, manipulate data) Exception Register (XER) report exceptions in integer arithmetic operations Floating Point Status and Control register (FLSCR) operations of the floating point unit.
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Register condition code fields Link Register indirect addressing of target address call/return behavior. Count control an iteration loop indirect addressing of target address
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Summary
Boolean Logic, System Buses Dedicated and
Multiplexed Buses Bus Interconnection to optimize performance Register Organization Pentium Registers Power PC Registers
March 20, 2012
Reference
Stallings
William, 2003, Computer Organization & Architecture designing for performance, 7th edn, Pearson Education Computer System Architecture, Frank Duyker, Box Hill TAFE
Further Reading
Manufacturers