SEMINAR ON LOGIC ENCODING & STATE MACHINE ENCODING

Prepared by: KIRAN KUMARI MISHR 2ND SEM MTECH VLSI DESIGN AND EMBEDDED SYSTEM

Power Consumption by Bus

High capacitance lines High switching activities

1 P = i f i CiV 2 i
2

Reduce power dissipation by reducing the number of transitions

LOGIC ENCODING

Different encoding implementations lead to different power,area,and delay trade-off. Hence different power consumption. Eg. Binary versus gray code counting. When n is large ,the binary counter has twice as many transitions as the gray counter . Power dissipation is related to toggling activities.

BUS INVERT ENCODING

Suitable for a set of parallel synchronous signals. At every clock the both true and current values are examined.
Source data Invert/pass Data bus Invert/pass

Received data Polarity signal Polarity decision logic Bus register

Bus-Inversion Encoding Logic

Received data Polarity decision logic Bus register Polarity bit Sent data

BUS INVERT ENCODING(cont..)

Transmitter 32 Receiver

Conventional Bus

ENCODER

DECODER

Transmitter

32 INV

Receiver

Bus with Inversion Encoding

BUS INVERT ENCODING(cont)

To minimize transitions in bus with large capacitance Additional Line: INV Encoding:

Di, if INV=0 Di XOR 1, if INV=1 Di XOR INV

Decoding:

Proposed by M. R. Stan

BUS INVERT ENCODING(cont)

Bus invert coding is a technique in which, if the hamming distance between the current data and the next data is more than N/2 (where N is the bus width), then one can invert the bits and send it, so as to minimize the number of transitions on the bus. In that case a control bit goes along with the data to indicate the receiving end, whether the data is inverted or not. Other coding techniques involve partial bus encoding, data re-ordering etc.

Bus Encoding for Reduced Example: Four bit bus Power

0000 1110 has three transitions. If bits of second pattern are inverted, then 0000 0001 will have only one transition.
N

Bit-inversion encoding for N-bit bus:

Number of bit transitions after inversion encoding

N/2

N/2 Number of bit transitions

BUS INVERT ENCODING(cont..)

A register is required to store the current value of the bus. A polarity decision module is used to compare & make decisions. Area, power & propagation delay are the overheads. Adds a substantial amount of circuit.

STATE MACHINE ENCODING

State machine is a computational model State machine encoding determines the quality of the gate level circuits. Optimization :no. of bits assigned.

One-hot and Gray encoding consume lesser power as compared to binary encoding. This is because one-hot and gray encodings have only a single bit change while going from one state to another.

Transition analysis of state machine

1. 2.

1. 2.

Important parameters: No. of bit transitions of state register. No.of transitions of output signals. Low E(M) machines, more power efficiency because: Low power dissipation Propogated into combinational logic.

State machine encoding effects the power dissipation as well as the area of the machine Dont care encoding and power optimization: probabilities of state transition and input signals.

State Encoding for a Counter

Two-bit binary counter:

State sequence, 00 01 10 11 00 Six bit transitions in four clock cycles 6/4 = 1.5 transitions per clock State sequence, 00 01 11 10 00 Four bit transitions in four clock cycles 4/4 = 1.0 transition per clock

Two-bit Gray-code counter

Gray-code counter is more power efficient.

G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998.
15

Transition probability based on PI statistics

FSM State Encoding

0.6 0.3 00 0.6 11 0.4 0.1 0.1 01 0.9 0.3 00 0.6 01 0.4 0.1 0.1 11 0.9 0.6

Expected number of state-bit transitions:

2(0.3+0.4) + 1(0.1+0.1) = 1.6

1(0.3+0.4+0.1) + 2(0.1) = 1.0

State encoding can be selected using a power-based cost function.

Problem: Bus Encoding

A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n 4 is essential for the 1-hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224-225. [Hint: You should be able to solve this problem without the help of the reference.]

Solution: Bus Encoding

Un-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each occurring with a probability 0.25. Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is . Therefore, the average per pattern energy for all n wires of the bus is CV 2n/4. Encoded bus: Encoded bus contains 2n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2n, and CV 2 with probability 1 2n. The average per pattern energy for the 1-hot encoded bus is CV 2(1 2n).

Solution: Bus Encoding (Cont.)

Power ratio = Encoded bus power / un-coded bus power = 4(1 2n)/n 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 2n)/n 1, or 1 2n n/4, or n/4 1 (approximately) n 4. The following table shows 1-hot encoded bus power ratio as a function of bus width: n 1 2 3 4 4(1 2n)/n 2.0000 1.5000 1.1670 0.9375 n 8 16 32 64 4(1 2n)/n 0.4981 0.2500 = 1/4 1/8 1/16