A High Bit Rate Serial-Serial Multiplier by Asynchronous Counters

Guided By Mrs.V.FILOMIN JOSEENA M.E

Presented By, J.JENITA J.DHANASRI G.MALARVIZHI M.JEESHAN FATHIMA

OBJECTIVE

To achieve a high bit sampling rate by asynchronous counter.

INTRODUCTION

The design and implementation of multipliers contribute to the area, speed and power consumption. The entire partial product matrix in n x n sampling cycles for an multiplication instead of at least 2n cycles in the conventional serial-serial multipliers.

S.No AUTHOR
1

LITERATURE REVIEW
TITLE
Manas Ranjan Meher High bit rate serial 2006 serial multiplier with on the fly accumulation by asynchronous counter.

YEAR WORKDONE
Research Engineer with the VLSI Design Laboratory.

Ching Chuen Jong Digital integrated circuit design

2009

Division of Circuits and Systems.

Chip-Hong Chang Low power arithmetic 2010 circuits, digital filter design

Digital watermarking For IP protection.

EXISTING SYSTEM

A multiplication operation consists of three stages, the generation and the reduction of PPs and the final carry-propagation addition. In the existing system, RCA and CLA were used. Ripple carry adder for low power. Carry look-ahead adder for high speed.

On-chip communication in SoC

(a) Conventional bus structure.

(b) Serial-link bus structure

The on-chip serial-link is capable of transmitting data at Gb/s. When the destination module finishes the computation a chunk of parallel data is available. The low complexity precomputation unit forms part of the serial-serial multiplier and perform partial computation on the high speed serial bit stream.

ADVANTAGES

On-chip data transfer conventional bus is used. Less complex.

DISADVANTAGES

Larger interconnect area. Higher power dissipation. Buses connecting these modules to become highly congested. Low speed.

PROPOSED SYSTEM

The proposed counter-based multiplier exhibits the lowest critical path delay. This is achieved by eliminating the complex 5:3 counter and replacing it by a simple 1s counter. In addition, all the PP bits can be accumulated in just n cycles in the proposed method while the others need 2n cycles.

BLOCK DIAGRAM

Fig: Proposed architecture for 8 x 8 serial-serial unsigned multiplication.

Shift Registers

Two shift registers to perform the left and right shift. Two clocks, namely clock1 and clock2 are employed to synchronize the data flow. The shift registers are reset to 0 in every cycles to allow a new set of operands to be loaded.

SIMULATION FOR LEFT AND RIGHT SHIFT REGISTER

Two serial inputs. One starting from the LSB and the other from MSB. 2n-1 counters of different bit widths used. 2n-1 an array of AND gates to generate the PP bits serially.

SIMULATION FOR AND GATE

Serial Accumulator
It is an integral part of serial multiplier design. It is an adder that successively adds the current input with the value stored in its internal register. The accumulation is speed up by using a CSA. Two registers are used to store the intermediate sum and carry vectors.

3-bit 1s counter

Fig:Hardware architecture of a 3-bit 1s counter.

Here, the clock is provided to the first DFF. Then all the other DFFs are triggered by the preceding DFF outputs. The counters change states only when the input is 1. Therefore, it leads to low switching power.

SIMULATION FOR 3-BIT COUNTER

SIMULATION OUTPUT

Advantages

Lowest critical path delay. Smaller adder tree of height [log2n]+1 is required. Better ADP.

Applications

Complex SoCs Advanced FPGAs. High-speed bit-serial applications.

REFERENCE
1. M. R. Meher, C. C. Jong, and C. H. Chang, High-speed and low power serial accumulator for serial/parallel multiplier, in Proc. IEEE Asia-Pacific Conf. Circuits Syst. (APCCAS), Macau, China, 2008, pp. 176179. 2. M. Ghoneima, Y. Ismail, M. Khellah, J. Tschanz, and V. De, Serial link bus: A low-power on-chip bus architecture, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 20202032, Sep 2009. 3. R. Dobkin, M. Moyal, A. Kolodny, and R. Ginosar, Asynchronous current mode serial communication, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 7, pp. 11071117, Jul. 2010.

4. O. Nibouche, A. Bouridarie, and M. Nibouche, New architectures for serial-serial multiplication, in Proc. IEEE Conf. Circuits Syst.(ISCAS), Sydney, Australia, 2001, vol. 2, pp. 705708. 5. P. T. Balsara and D. T. Harpe, Understanding VLSI bit serial multipliers,IEEE Trans. Edu., vol. 39, no. 1, pp. 1928, Feb. 1996. 6. A. Aggoun, A. Ashur, and M. K. Ibrahim, Area-time efficient serialserial multipliers, in Proc. IEEE Conf. Circuits Syst. (ISCAS), Geneva,Switzerland, 2000, pp. 585588.

Thank you