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Dongdong Chen
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Objectives
IEEE 754-2008 standard for Decimal Floating-Point (DFP) arithmetic (Lecture 1)
DFP numbers formats DFP number encoding DFP arithmetic operations DFP rounding modes DFP exception handling
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Objectives (Con.)
Algorithm, architecture and VLSI circuit design for DFP arithmetic (Lecture 2)
DFP adder/substracter DFP multiplier DFP divider DFP transcendental function computation
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Background
The decimal computer arithmetic went out of style 25 to 30 years ago; no one uses it now." Is that true?
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Introduction
Decimal is still essential for specific applications
Numbers in commercial databases are decimal Extensive use decimal in commercial applications Survey of commercial databases report Decimal fixed-point or floating-point number
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Introduction (Con.)
Errors from decimal and binary conversion
Example 1: represent 0.1 in DFP or BFP Decimal representation (BCD code):0.0001 Binary representation: 0.00011 0.09 Example 2: telephone billing Cost: 0.70; Tax: 5% BFP arithmetic: 0.69998*(1.05)=0.734999 DFP arithmetic: 0.70*(1.05)=0.74
Current Researches
DFP arithmetic defined in IEEE 754-2008 IBM computing systems include DFP hardware
IBM Power6, z9, z10
Review BFP arithmetic in IEEE 754-2008 How to define new DFP in IEEE 754-2008
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This is called a normalized number; there is exactly one non-zero digit to the left of the point.
Unique representation of a number We get a little more precision: there are 24 bits in the significand, but only 23 of them are stored.
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Exponent
Exponent is biased to make sorting easier
all 0s is smallest exponent, all 1s is largest The actual exponent is e-127 for single precision, and e-1023 for double precision Bias of 127 for single precision and 1023 for double precision By biasing the exponent and storing it before the significand, we can compare magnitudes as if they were unsigned integers.
If e = 1000 0011 (13110), the actual exponent is 131-127=4 If e = 0101 1101 (9310), the actual exponent is 93-127=-34
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Sign Exponent
11 bits, bias = 1023, 1022 to 1023
Significand
52 bits for fractional part (plus hidden 1 in integer part)
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0 1 00000000 00000000000000000000000
Biased exponent Fraction
1 11111111 00000000000000000000000 0
Fraction
Positive underflow
Expressible positive numbers Positive Overflow
- (2 2-23)2128
-2-127
2-127
(2 2-23)2128
Example
Summary: FP representation (1)sign(1+significand)2exponent bias Example:
decimal: -.75 = -3/4 = -3/22 binary: -.11 = -1.1 x 2-1 floating point: exponent = 126 = 01111110 IEEE single precision: 1 01111110 10000000000000000000000
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DFP formats:
decimal32: DFP storage format encoded in 32-bit
DFP Exponent
Exponent is biased to make sorting easier
Binary format (not decimal) The actual exponent is e-101 for decimal32, e-398 for decimal64, e-6167 for decimal128 Range of exponent is (eminq+1) e (emaxq+1);
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Example
Summary: DFP representation (1)sign(significand)10exponent-bias Convert -8.3510-2 to decimal64
Sign bit: 1 negative, 0 positive (sign 1) Exponent: -2+398=396 (8-bit 0110001100) Significand: 835(50-bit DPD coding 000 02 3D) Encoding of 5-bit MSBs (G0G4) of Combinational field 01000 Decimal-64 : 10100010001100..001000111101 A2 30 00 00 00 00 02 3D (binary/hex)
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DFP comparison operations do not distinguish between redundant of the same number DFP conversion operations
DFP to BFP conversion (correctly rounded); DFP to integer conversion
DFP comparison operations do not distinguish between redundant of the same number DFP conversion operations
DFP to BFP conversion (correctly rounded); DFP to integer conversion
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Correct rounding and Faithful rounding IEEE 754-2008 require to satisfy the correct rounded results for all DFP arithmetic operations DFP operations should satisfy all rounding modes
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DFP Addition/Subtraction
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DFP Addition
Step 1: equalize the exponents
add the mantissas only when exponents are the same. the number with smaller exponent should be shifting its point to the left, and the number with larger exponent should be shifting its point to right. Rewriting the operand with the smaller exponent could result in a loss of the least significant digits keep guard digit, round digit, and stick digit for the operand with smaller exponent
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DFP addition
Step 2: add the mantissas 0099999x101 +0016234x10-3 0999990x100 0000016(234)x100 1000006(234) x100 Step 3: Normalize the result if necessary
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DFP addition
Step 4: Round the number if needed 1000006234x100 =1000006x100 Step 5: Repeat step 3 if the result is no longer normalized The final result is 1000006 The correct answer is 1000006.234
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Guard bits
To help minimize rounding problems, IEEE specifies that intermediate steps of operations must store guard digits additional internal digits that increase the precision of the operations. Previous example: add one extra digit. IEEE 754-2008 requires one guard digit, one rounded digit and one sticky digit to make rounding more accurate.
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DFP add/sub
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Example: Addition
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[12] A. Vzquez and E. AnteloA High-performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding ARITH19, Portland. June 08-10 2009
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[Proposed]: A. Vzquez and E. AnteloA High-performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding ARITH19, Portland. June 08-10 2009
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DFP Multiplication
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Inexact
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Implementation Highlights
Leverage operands' LZCs
SC, SLA, and IESIP
Synthesis Results
64-bit (16 digit) operands, DPD encoded LSI Logic's gflxp 0.11um CMOS, 55ps FO4 Synopsys Design Compiler Results
Fixed-point Floating-point 119,653 um2 237,607 um2 14.72 FO4s 15.45 FO4s
Critical path
Fixed-point Floating-point 4:2 compressor (accumulator) 128-bit barrel shifer
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Parallel
Less latency Higher throughput
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DFP Division
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Sign (1 bit)
Unpacking
5 C1 1 1
5 C2
2 E1_a 2 E2_a E1
Combin_Register
10 10 E2
DPD_to_BCD
M1_b 60 60 M2_b
S1
Exponent Substraction
4 M2_a 4 M1_a E12 10
Combin_Register
Sign Logic
M1 64
64
M2
72
Exponent Adjustment
1 1
Fa 1
Normalization
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10 Mn
72
Rounding Control
Exponent Adjustment
Ea Eq_C 10
Fa2 1
Rounding
64 Mq
1 Fr
2 Mq_C 4
Exponent Div
Significand_Div
60 Mq
Eq Cq 5
BCD_to_DPD
50 Mq
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Sign (1 bit) Eb
packing
Unpacking Decimal FloatingPoint Number Check for zeros and infinity Subtract exponents Divide Mantissa Normalize and detect overflow and underflow Perform rounding Replace sign Packing
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Sign (1 bit)
Unpacking
S1 1
Step1: Unpacking Floating-Point Number Check for zeros and infinity (if F=0, Stop)
1 S2
Sign Logic
Sq S1 S2
1 Sq
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Exponent Subtraction
E1 11 11 E2
Exponent Substraction
E12 11
Eb E1 E2 + bias
Bias Addition
Eb
11
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Mantissa Division
M1 64 64 M2
Algorithms Choose here? 1. Restoring division 2. Non-restoring division 3. High-Radix division 4. Convergence division
Mantissa Division
0.1 M1 1 0.1 M 2 1
M12 68
Normalization
Eb 10 M12 68
Exponent Adjustment
Ea 10
1 Fa
Normalization
Mn
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Step5 : Left shift over one bit is needed to make Mantissa result Normalized, also need to detect overflow and underflow For example: 09342140819564 Left shift one bit 93421408195640 Should tell exponent and Ea=Eb-1
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Exponent Adjustment
10 Eq
Fr 1
Rounding
Fr 1
Rounding Control
64
Mq
Step6 : Truncate, Round-up, Round-to-nearest. Sometimes, the Rounding Policy above is not fair, according to IEEE Rounding standard: Round to nearest even is more better.
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Sign (1 bit) Eb
packing
Step7: Packing the Sign bit and Exponent bits and Significand bits together, detect the NaN, Infinity,
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[1] L.-K. Wang and M. J. Schulte, Decimal Floating-Point Division Using Newton-Raphson Iteration, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 84-95, Sep. 2004.
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[2] Toms Lang and Alberto Nannarelli, A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture,IEEE Transactions on Computers, pp727739, IEEE, June 2007.
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1:
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Contents
Introduction Decimal Logarithmic Converter Decimal Antilogarithmic Converter Conclusions Future Work
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8 + 5 + log10 (0.2458900)
To guarantee a 32-bit DFP Calculation, there need to keep 14-digit FXP logarithmic calculation.
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P Anti log10 ( X ) 10 X
X [101,96.99999]
X Int X Frac
10
1
X Int
10
X frac
Example:
E ( j + 1) E[ j ](1 + e j 10 j ) L( j + 1) L[ j ] log10 (1 + e j 10 j )
Here:
E[1] m
L[1] 0
ej -9 -8 -70 17 8 9
L( j + 1) L[ j ] ln(1 + e j 10 )
E ( j + 1) E[ j ] (1 + e j 10 j )
f i 1 + e j 10 j Here: E[1] 1 L[1] m '
e j selected so that L( j + 1) converges to 0
ej -9 -8 -70 17 8 9
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W [ j ] 10 ( E[ j ])
j
Mult1
Tab I
4
0000
Reg 1 28
Mux 7
Stage 1
0000
e1 4 ej
Stage 2
4 (1/ln(10)) 4 56 Adjusted Costant 0 & Log 10(5,2,3) 64 Mux 9 64 Reg 6 64
W[j]
4e j
Mux 2
Mult2
Shifter (x10-j) 56 Reg 4 Mux 5 56 9'sCom 56
4 56
4 56 1 Mux 4 56 56 W[j]
Tab II Mult3
64 Mux 8 64 64
Reg 5
Reg 3
critical path
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Implementation Results
Logic Utilization Used Available* Utilization
2842
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ln(10)
Stage 1
Stage 2
Critical Path
ej 4 ej 40 e1 40 40 1 Mux 5 40 Reg 6 40
TAB I e 8
1
12
Mult 40 0000
40
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Implementation Results
Logic Utilization Used Available* Utilization
2315
Mult
7.839
Mux4
1.539
Shifter
1.100
CLA
6.794
Round
0.545
Total
19.42
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Comparison
(with Binary FXP Log and Exponential Converters) similar dynamic range for the normalized coefficients.
223 107 224 252 1016 253 Binary reference available having the same digitrecurrence algorithm with Selection by Rounding. The radix-10 is close to radix-8.
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Comparison (cont.)
(with Binary FXP Log and Exponential Converters)
Radix-10 Decimal1 Log. Exp. Radix-8 Binary [1] Log. Exp.
Precision (digit)
Area (fa2) Cycle time (T3) # of cycles Latency (T3)
1:
16
16
24
53
24
53
Synthesized with a TMSC 0.18-um standard cell library 2: the area of 1-bit full adder 3: the delay of 1-bit full adder
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Conclusions
Achieved 32-bit DFP accuracy of decimal log and antilog results. Implemented them on FPGA and ASIC. Compare them with binary converters.
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Future Work
The 64-bit and 128-bit DFP logarithm and antilog converters. The presented architecture can be optimized to achieve a faster speed or occupy a smaller area.
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79/18
Summary
IEEE 754-2008 defines a DFP standard that defines
number representation in several precisions correct DFP arithmetic operations rounding modes
Implementation of DFP Adder, Multiplier, Divider, Logarithmic and Antilogarithmic Converter Implementing and programming DFP are both really hard.
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