The WIRE & its Inductive nature

The Wire

transmitters

receivers

schematics
physical

Deep sub micron effect presents a variety of problems to process engineers, circuit engineers And cad tool developers.

Wire Models

Capacitance-only All-inclusive model

Impact of Interconnect Parasitics

Interconnect parasitics Reduce reliability Affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive

Capacitive
VDD M2 Vin Cgd12 Cdb2 Vout Cg4 M4 Vout2 VDD

Cdb1 M1

Cw

Cg3

M3

Interconnect

Fanout

Simplified Model

Vin

Vout
CL

Capacitance: The Parallel Plate Model

Current flow L W Electrical-field lines

H tdi Dielectric Substrate

cint

di
t di

WL

SCwire

S 1 S SL SL

Fringing Capacitance

(a)
H W - H/2

(b)

Interwire Capacitance

fringing

parallel

Impact of Interwire Capacitance

Dealing with Capacitive Cross Talk

Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as

possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers

Resistance
R= L HW
L H

Sheet Resistance Ro R1 R2

Sheet Resistance

Dealing with Resistance

Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length

Polycide Gate MOSFET

Silicide PolySilicon SiO2

n+ p

n+

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

resistivity

Modern Interconnect

Example: Intel 0.25 micron Process

5 metal layers Ti/Al Cu/Ti/TiN Polysilicon dielectric

Interconnect Modeling

The Lumped Model

Vout cwi re Driver

Rdriver

Vout

Vin Clumped

The Lumped RC-Model The Elmore Delay

The Ellmore Delay RC Chain

Diffused signal propagation Delay ~ L2

Wire Model
Assume: Wire modeled by N equal-length segments

For large values of N:

L di/dt
V DD L V DD V in V out CL GND L i ( t)

Impact of inductance on supply voltages: Change in current induces a change in voltage Longer supply lines have larger L

EFFECTS OF INDUCTANCE
RINGING AND OVERSHOOT EFFECTS
REFLECTIONS OF SIGNALS DUE TO

IMPEDANCE MISMATCH INDUCTANCE COUPLING BETWEEN LINES SWITCHING NOISE DUE TO L.di/dt VOLTAGE DROP.

Dealing with Ldi/dt

With the development of sub-micron dimensional circuit features, inductive effects on low-power consumption, densely-packed circuits are now governing the design of new chips. Presently this transient voltage problem is addressed by placing the power supply as close as possible to the chip and/or using sense lines on the power supply to create a tight regulation at the load.

Decoupling capacitors also help to reduce the voltage transients generated between the power supply and the load.

While helpful, these design techniques cannot eliminate the voltage transients caused by large current changes and have no effect on the voltage transients caused by the inductance on the ic power net from the package pins to the silicon.

How to model inductor based delay?

The effective inductance modeling of

interconnects in mixed-signal ICs using the wavelets is exhaustively analyzed

sparse inductance matrix

conclusio n Wires are as important as transistors

as they contribute to speed , power and noise.

The main goal of vlsi designer is to identify the dominant parameters that set the values of wire parasitics. Researchers expect inductive effects to become more significant in future DSM designs because signal bandwidth is increasing as on chip rise times decrease.if the product of inductance and angular frequency is comparable to the line resistance ,inductive effects are considered important.

references
http://www.patentstorm.us/patents/7046069/descr

iption.html. http://ieeexplore.ieee.org/ CMOS DIGITAL INTEGRATED CIRCUITS-S.M. Kang and Y.Leblebici DIGITAL INTEGRATED CIRCUITS A Design PerspectiveJan M. Rabaey Anantha Chandrakasan Borivoje Nikolic