INTERRUPT CONTROLLER FOR FPGA BASED MULTIPLE PROCESSOR

Click to edit Master subtitle style by Manoj Naresh Avinash

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What is a Interrupt Controller?

The Interrupt Controller is a device commonly found in computer systems (both single-processor and multiprocessors) It deals with interrupts generated by the peripherals and the processors. It handles the interrupt priorities, and delegates the execution to a processor
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What is our Interrupt controller about?

This interrupt controller is for MPSoCs(Multiprocessors System-onChip) type of systems which are based on FPGA technology.

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Our design allows a peripheral to interrupt any of the processors of the system. In detail, our Interrupt Controller distributes the workload of the interrupt handling among the available processors.

This feature decreases the interrupt management latency.

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The Interrupt Controller allows to delegate specific processors to handle interrupts generated by certain peripherals (booking).

It supports interrupt broadcasting and allows inter-processor interrupts.

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Applications

Reactive systems. High performance computers. Complex embedded systems. Devices using peripheral sharing.

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INTERRUPT CONTROLLER ARCHITECTURE

It is composed of two main components. 1. OPB Interface. 2. Controller logic(Int core)

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Interrupt controller architecture

Interface

The interface is based on the On-chip Peripheral Bus (OPB)specification to allow memory mapped access from the processors. It interfaces the core with the main bus of the system. The interface sends the following signals for controller logic.

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Reg Addr: the register address where the processor wants to write to or to read from. Valid rd: read operation from the register specified by Reg Addr. Valid wr: write operation towards the register specified by Reg Addr. Data in: the data to write. Data out: the data to read.

Proc id: the identification of the processor accessing the controller. 4/29/12

Controller logic

Implements the core logic of a computer. It consists of 3 main parts. 1. Register block. 2. Edge interrupt detection. 3. Irq generator.
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Register block

It allows handling of interrupt priorities, deciding which interrupts can be handled and managing of interrupt acknowledge signals. The various registers are

Interrupt Status Register (ISR) stores the active interrupts.

Interrupt Pending Register(IPR) stores the interrupts that are both 4/29/12 active and enabled.

 Interrupt Enable Register (IER) keeps track of which interrupts are allowed to be handled. Interrupt Acknowledge Register (IAR) is a support for disabling interrupts that receive the corresponding acknowledgment signal. Set Interrupt Enable (SIE) is a support for writing into IER. Clear Interrupt Enable (CIE) is a 4/29/12 support for deleting from IER.

 Interrupt Vector Register (IVR) contains the identification of the next interrupt that must be served. Master Enable Register (MER) is used for enabling our Interrupt Controller to manage interrupts. Device Processor Waiting (DPW) is a support to store which interrupts have been booked. Broadcast (BRO) is a support to store which interrupts have to be handled in broadcast way. 4/29/12

Edge Interrupt Detection

It detects interrupts coming from the IPs of the system and activates the logic which communicates pending requests to the connected processors.

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Irq Generator

It contains the generation logic of the interrupt signals toward processors. It is composed of two main subblocks.

1.Broadcast Interrupt Generator generates signals in case of interrupts that need to be propagated to all processors. 2.Standard Interrupt Generator 4/29/12 handles all the other kinds of interrupt.

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Irq generator

Working
Consider two application specific cores connected to the Interrupt Controller generate interrupts in the same time interval.

Interrupt management for these two cores has been previously enabled by writing on the IER register. The interrupts are detected by the Edge Interrupt Detection module.

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The Edge Interrupt Detection Module stores the arrival of the interrupts in ISR register. Writing on ISR also influences the content of the IPR register.
IRQ Generation raises two outputs toward two free processors (not handling other interrupts). The Interrupt Controller waits for acknowledgment. The first processor which detects the interrupt request chooses the active interrupt with the highest priority and sends the related acknowledgment.

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The second processor which detects the interrupt request chooses the second active interrupt and sends the related acknowledgment. The second processor starts executing the handler associated to the selected interrupt. From now on, the two processors will concurrently handle the two generated interrupts.

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BOOKING, BROADCASTING, AND INTER-PROCESSOR COMMUNICATION: Booking:

Interrupt Controller allows to delegate specific processors to handle interrupts generated by certain peripherals. This is accomplished by calling the Book Peripheral primitive, and specifying which is the peripheral to book. 4/29/12

Broadcast

This interrupt is distributed by the interrupt controller to all processors. The addresses of the selected peripheral are registered by writing the BRO register. When interrupt is generated, it enables the broadcast logic,disables the normal flow. Broadcast interrupt having high 4/29/12 priority served first .

Conclusions

This design efficiently distributes multiple interrupts on a multiprocessor, exploiting CPU-level parallelism. In addition, it supports several features useful in a multiprocessor system, like booking, broadcasting and inter-processor interrupt.

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Question???

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