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Intel s

8051

Micro controller

Basics
What are Micro controller's ? Why the name Micro controller ?
Basically used for control actions.It is used to control the operation of machine using fixed program that is stored in ROM/EPROM and that does not change over the life time.

What is MCS 51 ? Why to study 8051 ?

Microprocessors
General-purpose microprocessor
No RAM, ROM, I/O on CPU chip itself ExampleIntels x86, Motorolas 680x0

CPU GeneralPurpose Microprocessor

Data Bus

Many chips on mother board I/O Port Serial COM Port

RAM

ROM

Timer

Address Bus General-Purpose Microprocessor System

Microcontroller
A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU

RAM

ROM

A single chip
I/O Port Timer Serial COM Port Microcontroller

Microprocessor vs. Microcontroller


Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate designer can decide on the amount of ROM, RAM and I/O ports. expansive versatility general-purpose Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical single-purpose

Features of 8051
8 bit ALU. 16 bit PC and DPTR. 8 bit stack pointer and 8 bit PSW. 4K internal ROM 128 bytes of Internal RAM. four,8 bit ports P0-P3. Two 16 bit timer/counters, T0 & T1. Full duplex serial Port. Control Registers TMOD,TMOD,SCON,PCON,IP,IE etc (SFRs).

Features contd
Two External and three internal interrupts 1-12 MHz clock. 40 pin DIP package. Works in Power Down and Idle mode. Powerful Instruction set.

Block Diagram

Program Status Word (PSW)


7

CY

AC

FO RS1 RS0 OV ----

CY Carry Flag AC Aux Carry FO available to user as general purpose flag OV Over flow P Parity RS0 RS1 Register Bank Select

Registers
A B R0 R1
DPH

16-bit Registers DPTR


DPL

R2
R3 R4 R5 R6 R7
8-bit Registers

PC

Memory Organization
RAM
7FH

Scratch pad RAM


30H 2FH

Bit-Addressable RAM
20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0

Memory Organization
ROM
FFFFH

External Program Memory


Internal Program Memory
EA = 1

FFFFH

External Program Memory

1000H 0FFFH

0000H

0000H
EA = 0

Stack in the 8051


The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07

Instruction Set
45 1-byte instructions

45 2-byte instructions
17 3-byte instructions
Syntax

Mnemonic

Dest Operand

Src Operand

Data Transfer Instructions


MOV A, Rn - Move from reg. to acc. e. g : MOV A, R0 MOV A, direct Move from memory e. g : MOV A,45H MOV A, @Rn Move Indirect e. g : MOV A,@R3 MOV A, #data Move Immediate e. g : MOV A,#45H MOV Rn, A Move acc to register e. g : MOV R1,A

Data Transfer Instructions


MOV Rn, direct - Move from memory to reg. e. g : MOV R0,45H MOV Rn, #data Move Immediate to reg. e. g : MOV R1,#45H MOV direct, A Move acc to mem(direct addr) e. g : MOV 45H, A MOV direct, Rn Move register to mem e. g : MOV 45H, R1 MOV direct, direct Move mem to mem direct e. g : MOV 35H, 45H

Data Transfer Instructions


MOV direct, @Rn - Move Indirect e. g : MOV 45H, @R0 MOV direct, #data Move Immediate to mem. e. g : MOV 45H,#45H MOV @Rn, A Move acc to mem(indirectaddr) e. g : MOV @R1, A MOV @Rn, direct Move direct mem to ind. mem e. g : MOV @R1, 45H MOV @Rn, #data Move immediate data to ind. mem e. g : MOV @R1,#45H

Arithmetic Instructions
ADD A, Rn Add register to acc e. g : ADD A, R0 ADD A, direct Add direct byte of mem to acc e. g : ADD A, 45H ADD A, @Rn ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Rn ADDC A, #data

Arithmetic Instructions
SUBB A, Rn Subtract register to acc e. g : SUBB A, R0 SUBB A, direct Subtract direct byte of mem to acc e. g : ADD A, 45H SUBB A, @Rn SUBB A, #data INC A INC Rn INC direct INC @Rn

Arithmetic Instructions
DEC A DEC Rn DEC direct DEC @Rn INC dptr MUL AB Multiply A & B 16 bit product in B:A DIV AB Divide A by B quotient in A, remainder in B DA A Decimal Adjust Acc

Logical Instructions
ANL c, b AND carry and b bit; put result in c ANL c, /b AND carry and compliment of b bit; put result in c ORL c, b ORL c, /b CPL c Complement Carry Flag CPL b Complement b bit CLR c Clear Carry Flag CLR b Clear b bit SETB c Set Carry Flag SETB b Set b bit MOV c, b copy b bit to Carry Flag MOV b, c copy Carry Flag to b bit

Bit Jump Instructions


JC radd Jump to specified relative address if Carry flag is set JNC radd Jump to specified relative address if Carry flag is reset JB b, radd Jump to specified relative address if specified bit is set JNB b, radd Jump to specified relative address if specified bit is reset JBC b, radd Jump to specified relative address if specified bit is set and clear the addressable bit

Byte Jump Instructions


CJNE A, add, radd Compare A with specified address, if they are not equal jump to specified address
if a<add then set Carry else Reset

CJNE A, #n, radd CJNE Rn, #n, radd CJNE @Rn, #n, radd DJNZ Rn, radd Decrement Rn by 1 and jump to specified address if not 0 DJNZ add, radd JZ radd Jump to specified relative address if contents of register A is 0 JNZ radd

Byte Jump Instructions


JMP @A+DPTR SJMP radd
Range +127 to -128

AJMP sadd
Range 2k

LJMP ladd
Range 64k

Logical Instructions
ANL/ORL/XRL A, #n AND A with direct data n ANL/ORL/XRL A, add ANL/ORL/XRL A, Rn ANL/ORL/XRL A, @Rn ANL/ORL/XRL add, A ANL/ORL/XRL add, #n CLR A Clear register A CPL A Complement A

Logical Instructions
RL A Rotate Left by one bit

RLC A
RR A RRC A SWAP A Interchange higher and lower nibbles of A

External Data Moves


MOVX A, @Rn

MOVX A, @DPTR
MOVX @Rn , A MOVX @DPTR, A MOVC A, @A+DPTR MOVC A, @A+PC

Push and Pop


PUSH address

POP address

Addressing Modes
Immediate Addressing
MOV A, #10H

Register Addressing
MOV A, R0

Direct Addressing
MOV A, 80H

Indirect Addressing
MOV A, @R0

Ports
4 Ports

PORT 0
Bi-directional Low order address and data bus is multiplexed

PORT 1 & 2
Quasi bi-directional (input or output) Port 2 Higher order address bus

Ports
PORT 3
quasi bi-directional Alternate Functions P3.0 - RxD Serial Input P3.1 - TxD Serial Output P3.2 - INT0 External Interrupt P3.3 - INT1 External Interrupt P3.4 - T0 Timer/Counter 0 External Input P3.5 - T1 Timer/Counter 1 External Input P3.6 - WR external data mem. P3.7 - RD external data mem.

Interrupts
5 vectored Interrupts
Interrupt External Interrupt 0 Flags Vector Cause Affected Address IE0 0003H
000BH 0013H 001BH 0023H TI or RI flag is Set

High to Low transition on INT0


Overflow of Timer INT1

Timer/Counter 0 TF0 Interrupt External Interrupt 1 Serial Port IE1

Timer/Counter 1 TF1 RI+TI

Interrupt Enable (IE) Register


7
6

EA

--

ET2

ES

ET1 EX1 ET0 EX0

EA Enable ALL
0:Disables all Interrupts 1:Enables all Interrupts

ET2 Enable Timer Interrupt 2 (in 8032/8052) ES Enable Serial Interrupts ET1 Enable Timer Interrupt 1 EX1 Enable External Interrupt 1 ET0 Enable Timer Interrupt 0 EX0 Enable External Interrupt 0

Interrupt Priority (IP) Register


7
6

--

--

PT2

PS PT1 PX1 PT0 PX0

PT2 Timer 2 Priority (in 8032/8052) PS Serial Interrupt Priority PT1 Timer 1 Interrupt PX1 External Interrupt 1 PT0 Timer 0 Interrupt PX0 External Interrupt 0

Timers and Counters


Required for real time applications Pulse counting, frequency and pulse width measurement, baud rate generation What is Timer?
Counts machine cycles and provides a reference time delay or clock Machine cycle of 8051 is of 12 oscillator periods, so counting rate is 1/12 of i/p freq.

What is Counter?
counts external events, incremented in response to transition from 1 to 0 at its external pins T0 & T1

Continued.
2 Timers/Counters Each of 16 bit T0 TH0 and TL0 T1 TH1 and TL1

Timer Control Register (TCON)


7
6

TF 1 TR1 TF0

TR0 IE 1

IT1 IE0 IT 0

TCON.7 TF1 : Timer 1 overflow flag TCON.6 TR1 :Timer 1 run control bit TCON.5 TF0 : Timer 0 overflow flag TCON.4 TR0 :Timer 0 run control bit TCON.3 IE1 :Interrupt 1 TCON.2 IT1 :Timer 1 interrupt TCON.1 IE0 : Interrupt 0 TCON.0 IT0 : Timer 0 Interrupt 0:low level trigger 1:edge trigger

Timer Mode (TMOD)


7 6 5 4 3 2 1 0

Gate

C/T

M1

M0 Gate C/T M1
Timer 0

M0

Timer 1

GATE : external Timer enabling if 1 controlled by external GATE pin INT0 for Timer 0 and INT 1 of Timer 1 C/T : 0:Timer 1:Counter M0 and M1 Modes of Timer

Timer/Counter Modes
Mode 0
13 bit timer/counter For T0 and T1 For back compatibility with 8048

Mode 1
16 bit timer/counter For T0 and T1

Mode 2
8 bit timer/counter with auto reload Counter value in THx , loaded in TLx when counter starts When TLx overflows counter value is reloaded from THx

Mode 3
Split timer mode For T0 only T1 is in passive TH0 and TL0 two separate timers controlled by TR1 and TR0

Programming Examples
Mode 1
MOV TMOD , # 0001 0000B SETB TCON.6 Timer 1 in mode 1 and as GATE bit is 0 TR1 fully controls operation of timer

Mode 2
MOV TMOD , # 0000 0010 MOV TH0, #33H MOV TL0, #33H SETB TCON.4

Serial Input/Output
Registers used are SCON and SBUFF.

There are physically two SBUFF registers having same address i.e 99 H. Interrupt is generated whenever data is transmitted and received. Support full duplex
P3.0 RxD P3.1 TxD

Serial Port Interface

Serial Control (SCON) register


7 6 5 4 3 2 1 0

SM0 SM1 SM2 REN TB8 RB8 TI


SMO SM1 0 0 0 1 1 0 1 1 Shift register mode baud=1/12 8 bit UART baud=variable 9 bit UART baud= f/32 or f/64 9 bit UART baud = variable

RI

SM 2 in modes 2 and 3 ,if set enable multiprocessor communication REN Receive Enable TB8 9th data bit to be transmitted RB8 9th data bit received TI Transmit Interrupt flag Set by hardware must be cleared by software RI Receive Interrupt flag Set by hardware must be cleared by software

Serial Communication Mode 0


8 0 5 1

TxD RxD

Clock Receiver Data

Synchronous communication TXD serves as the clock while RXD is used for both receiving and transmitting data. In mode 0, the serial port is only half duplex; it cannot transmit and receive data at the same time because the same line (RXD) is being used for both transmit and receive.

Serial Communication Mode 1


8 0 5 1
TxD Data Receiver RxD Data Transmiter

Asynchronous communication

Power Control (PCON) Register


7
6

SMOD

---

---

---

GF1

GF0

PD IDL

SMOD : Serial Baud Rate Modify 1:Double baud Rate POWER DOWN :On chip oscillator is stopped. But RAM and SFRs are held. IDLE Mode :The internal clock is gated off to the CPU,but not to the timer,serial port and all registers maintain the data.

Counter Value Calculation


For example, to achieve a baud rate of 1200 using a system clock frequency of 12MHz and with SMOD = 0
TH1 = 256 - ((system frequency / (12 * 32)) / baud)

TH1 = 256 - ((12MHz / (12 * 32)) / 1200) TH1 = 256 - 26.04 TH1 = 256 - 26 TH1 = 230
The timer clock frequency is the system clock frequency divided by 12 - hence the divide by 12 in the above equation

Pin Description
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

8051 (8031)

Pins of 8051
Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V.

GNDpin 20ground
XTAL1 and XTAL2pins 19,18

Pins of 8051
RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers

Pins of 8051
/EApin 31external access
There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM.

Pins of 8051
ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

* Bit addressable registers

SFR

Register A* B* DPH DPL IE* IP* P0* P1* P2* P3*

Address E0 F0 83 82 A8 B8 80 90 A0 B0

Register PCON PSW* SBUF SCON* SP TCON* TMOD TH0 TH1 TL0 TL1

Address 87 D0 99 98 81 88 89 8C 8D 8A 8B