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Microcontroller
Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate versatility general-purpose Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports single-purpose
FEATURES
Intel introduced 8051, referred as MCS-51, in 1981. 8051 by all manufactures remain code-compatible 8-bit CPU optimized for control applications Extensive Boolean processing (Single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator
PIN DETAILS
BLOCK DIAGRAM
Interrupt Control
4K ROM
128 RAM
Timer 0 Timer 1
CPU
OSC
Bus Control
4 I/O Ports
Serial Port
TXD RXD
P0
P1
P2
P3
MEMORY STRUCTURE
External
60K
64K
External
SFR
64K
EXT
EA = 0
INT
EA = 1
4K
Program Memory
SFR
BIT Addressable Area 128 BYTE INTERNAL RAM Reg Bank 3 Reg Bank 2 Register Banks Reg Bank 1 Reg Bank 0
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
Bank 1
Bank 0
R0
R0
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
CY
AC
F0
RS1
RS0
OV
SFR
F8 F0 E8 E0 D8 D0 C8 PSW Acc B FF F7 EF E7 DF D7 CF
C0
B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 PCON SBUF
C7
BF B7 AF A7 9F 97 8F 87
Registers
Register are used to store information temporarily The Accumulator The Accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8052 has due to the sheer number of instructions that make use of the accumulator. More than half of the 8052's 255 instructions manipulate or use the Accumulator in some way. The "R" Registers The "R" registers are sets of eight registers that are named R0, R1, through R7. These registers are used as auxiliary registers in many operations. To continue with the above example, perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition you would execute the command:
Registers
The B Register The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value. The "B" register is only used implicitly by two 8052 instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you may store the other number in "B" and make use of these two instructions. The Program Counter The Program Counter (PC) is a 2-byte address that tells the 8052 where the next instruction to execute is found in memory. When the 8052 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isn't always incremented by one. Since some instructions are 2 or 3 bytes in length the PC will be incremented by 2 or 3 in these cases.
Registers
The Data Pointer The Data Pointer (DPTR) is the 8052s only user-accessible 16-bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values. The PC just described is a 16-bit value but isn't directly user-accessible as a working register. The Stack Pointer The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from.
Flash Memory
Flash memory (sometimes called "flash RAM") is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. It is a variation of electrically erasable programmable read-only memory (EEPROM) which, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating. memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or "flash." The erasure is caused by Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove an electronic charge from a floating gate associated with each memory cell. Intel offers a form of flash memory that holds two bits (rather than one) in each memory cell, thus doubling the capacity of memory without a corresponding increase in price.
A machine cycle consists of a sequence of 6 states numbered S1 through S6. Each state time lasts for two oscillator periods. Thus a machine cycle takes 12 Oscillator periods or 1 s if the oscillator frequency is 12 MHz. Each state is divided into a Phase 1 half and a Phase 2 half.
Crystal Oscillator
Oscillator Circuit
The 8051 uses the crystal for precisely that: to synchronize its operation. Frequency of clock can vary 4mhz-30mhz. A single machine cycle is the minimum amount of time in which a single 8051 instruction can be executed. 8051 has an on-chip oscillator. It needs an external crystal that decides the operating frequency of the 8051. The crystal is connected to pins 18 and 19 with stabilizing capacitors. 12 MHz(11.059MHz) crystal is often used and the capacitance ranges from 20pF to 40pF.
Clock
A cycle is 12 pulses of crystal If crystal pulse is 11,059,000 times per second, instruction cycles per second is 11,059000/12=921,583khz ie 1/921.6khz=1.085 s 921.6khz can be divided evenly by the standard communication baud rates of 19200,4800,2400,1200 and 300 hz.
D3 RS0
D2 OV
D1 --
D0 P
SETB PSW.4
; select bank 2
0
1 2 3
0
0 1 1
0
1 0 1
00 07H
08 0FH 10H 17H 18H 1FH
Timers
Timers can be used for time delay and for counters 8051 has two 16 bit timers. Can count from 0000H to FFFFH.
TH0 D15 D14 D13 D12 D11 D10 D9 D8 TL0 D7 D6 D5 D4 D3 D2 D1 D0
Timer 1
TIMERS Timer 0
Mode 0 Mode 1 Mode 2 Mode 3
Timer 1
Mode 0 Mode 1 Mode 2
Gate
C/
M1
M0
Gate
C/
M1
M0
Timer 1
TCON
TR0 IE1
Timer 0
TF1
TR1 Timers
TF0
IT1
IE0
IT0
Interrupt
Flag bits
Timer Modes
Mode Mode 0 Mode 1 Mode 2 M1 0 0 1 M0 0 1 0 Operation 13-bit Timer 16-bit Timer 8-bit Auto Reload
Mode 3
Mode 2: 8 bits 00 to FFH. Initial value loaded into the higher byte, copy of same is passed to lower byte. Timer rolls over from FFH to initial value automatically.
Mode 3: Acts as two separate 8 bit timers
SM2
REN
TB8
RB8
TI
RI
Flag bits
PCON
SMOD
GF1
GF0
PD
IDL
INTERRUPTS
The Interrupt structure has the following features: 5 interrupt sources
Interrupt External 0 Flag IE0 Location TCON.1
External 1
Timer 0 Timer 1 Serial Port Receive Serial Port Transmit
IE1
TF0 TF1 RI TI
TCON.3
TCON.5 TCON.7 SCON.0 SCON.1
Interrupt Vectors
The address of ISR (interrupt service routine) is known as interrupt vector
Interrupt System Reset External 0 Timer 0 External 1 Flag RST IE0 TF0 IE1 vector 0000H 0003H 000BH 0013H
Timer 1
Serial Port
TF1
RI or TI
001BH
0023H
Interrupt Priority
Each interrupts can have two priority levels 0&1 1 for high priority Set appropriate bit in IP SFR
EA
ES
IP
ET1
EX1
ET0
EX0
PS
PT1
PX1
PT0
PX0
TCON
TR0 IE1 IT1 IE0
IT0
The SJMP command can only jump to an address within +/- 128 bytes of the SJMP command. The AJMP command can only jump to an address that is in the same 2k block of memory as the AJMP command. That is to say, if the AJMP command is at code memory location 650h, it can only do a jump to addresses 0000h through 07FFh (0 through 2047, decimal).
Addressing Modes
immediate Addressing - MOV A,#20h
The value to be stored in memory immediately follows the operation code in memory
<----8 or 16 --->
The value to be stored in memory is obtained by directly retrieving it from another memory location , address can reference a: 1) Byte within the SFR (if value of XXX is 128 -> 255) 2) Bit within the SFR (if value of XXX is 128 -> 255) 3) Byte within the lower 128 bytes of Internal RAM (if value of XXX is 0 -> 127) 4) Bit within the Bit address area ( if value of XXX is 0 -> 127)
Addressing Modes
Indirect Addressing - MOV A,@R0
OPCODE REG
Addressing Modes
External Direct - MOVX A,@DPTR External Indirect - MOVC A,@A+DPTR
The Address = Contents of DPTR or PC + Contents of Accumulator
Number formats
Decimal without suffix
12, -1000
LCD DISPLAY
LCD DISPLAY
Pin number
1 2 3 4
Symbol
Vss Vcc Vee RS
Level
0/1
I/O
I
Function
Power supply (GND) Power supply (+5V) Contrast adjust 0 = Instruction input, 1 = Data input 0 = Write to LCD module, 1 = Read from LCD module Enable signal Data bus line 0 (LSB)
5 6 7
R/W E DB0
I I I/O
8
9 10 11 12 13 14
DB1
DB2 DB3 DB4 DB5 DB6 DB7
0/1
0/1 0/1 0/1 0/1 0/1 0/1
I/O
I/O I/O I/O I/O I/O I/O
Code Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Executi on time
Clear display Cursor home Entry mode set Display On/Off control Cursor/disp lay shift Function set Set CGRAM address Set DDRAM address Read busyflag and address counter Write to CGRAM or DDRAM Read from CGRAM or DDRAM
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 *
Clears display and returns cursor to the home position (address 0). Returns cursor to home position (address 0). Also returns display being shifted to the original position. DDRAM contents remains unchanged. Sets cursor move direction (I/D), specifies to shift the display (S). These operations are performed during data read/write. Sets On/Off of all display (D), cursor On/Off (C) and blink of cursor position character (B). Sets cursor-move or display-shift (S/C), shift direction (R/L). DDRAM contents remains unchanged. Sets interface data length (DL), number of display line (N) and character font(F). Sets the CGRAM address. CGRAM data is sent and received after this setting. Sets the DDRAM address. DDRAM data is sent and received after this setting.
1.64mS
1.64mS
I/D
40uS
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1
0 1 DL
1
S/C
D
R/L
C * *
B * *
40uS
40uS 40uS
CGRAM address
40uS
DDRAM address
40uS
BF
Reads Busy-flag (BF) indicating internal operation is being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction).
0uS
write data
40uS
read data
40uS