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X-Calibration-A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

WARM SRAM- A Novel Scheme to Reduce Static Leakage Energy in SRAM

Ultralow-power SRAM Technology

Ultra-Low Power 90nm 6T SRAM Cell for Wireless Sensor Network Applications

Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic Vdd control (RRDV) scheme

Tomorrows high-quality SoCs require high-quality embedded memories today

TERM PAPER

Statistically-Aware SRAM Memory Array Design

Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations

Static Energy Reduction Techniques for Microprocessor Caches

SRAM Variability Measurements Description Project objectives and

SRAM Technology

SRAM Leakage Suppression by Minimizing Standby Supply Voltage

SRAM Leakage Suppression by Minimizing Standby Supply Voltage

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

SEU_SRAM AS A PROCESS MONITOR

Review and future prospects of low-voltage RAM circuits

Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Using dual-Vth-Tox-Assignment

Radiation Effects Challenges in 90nm Commercial-Density SRAMs

Power supply current detectability of SRAM defects

Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode

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Memory design for electrically addressed spatial light modulators

Memories8

Low-Power High-Performance and Dynamically Configured Multi-Port Cache Memory Architecture

Low-leakage SRAM Design with Dual Vt Transistors

Low-Leakage Asymmetric-Cell SRAM1

Low-leakage asymmetric-cell SRAM

Low Power Static RAM Architectures Organization of Static RAM

Low Power Static RAM Architectures

Low power and robust 7T dual-Vt SRAM circuit

Logic Circuits with Carbon Nanotube Transistors

Leakage Reduction techniques in a 0.13um SRAM Cell

Leakage Read Fault in Nanoscale SRAM-Analysis, Test and Diagnosis

Leakage Power Estimation in SRAMs

Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction

Heat wave- FPGAs confront increasing, evolving power consumption

Gate Leakage Current Analysis in READ_WRITE_IDLE state of SRAMCell

Gate leakage and its reduction in deep submicron SRAM

GaAs MESFET SRAM using a New High Speed Memory Cell

Dynamic V_sub t_SRAM- a leakage tolerant cache memory for low voltage microprocessors

Dynamic Data Stability in Low-power SRAM Design

Direct Tunneling Current Model for Circuit Simulation

Designing_for_Power_Brochure

Design of 256-Kb Low-Power Embedded SRAM

Computing Elements from Carbon Nanotubes

Comprehensive Analysis of Leakage Current in Ultra Deep Sub-Micron

Comparative Study on Leakage Current of Power-Gated SRAMs for 65

CMOS VLSI Design