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A Double-Tail Latch-Type Voltage Sense Amplifier With 18ps Setup+Hold Time

A 30fJ_comparison Dynamic Bias Comparator

A 30fJ_comparison Dynamic Bias Comparator

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-Nm CMOS With 0.4-MV Input Noise

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-Nm CMOS With 0.4-MV Input Noise

Bandwidth Extension Techniques for CMOS Amplifiers

A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers, Theory and Design

Reference Design ADI

How the Voltage Reference Affects ADC Design Part 2

How the Voltage Reference Affects ADC Design Part 1

21 File PaperForChairs

Time to Digital Converter Slides

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