Elet IV

ELETRNICA IV
Apostila de Aulas Prticas
Autor: Fernando Antnio Pinto Barqui
2
Sumrio
1. INTRODUO.............................................................................................................................. 3
2. AMPLIFICADOR PUSH-PULL COM SADA COMPLEMENTAR.................................. 4
3. AMPLIFICADOR SINTONIZADO ............................................................................................ 7
4. MODULADOR DE AMPLITUDE............................................................................................. 10
5. MULTIPLICADORES ANALGICOS.................................................................................... 12
6. MODULADOR DE FREQNCIA .......................................................................................... 14
7. FONTES CHAVEADAS ............................................................................................................. 16
DATASHEETS................................................................................................................................. 20
3
1.
INTRODUO
O contedo desta apostila consiste das aulas experimentais do curso de Eletrnica IV, ministrado no
Departamento de Eletrnica da Escola de Engenharia. Cada captulo corresponde a um experimento a ser
montado e estudado em laboratrio. Esses experimentos foram, ao longo dos anos, sendo aprimorados
didaticamente, de forma a apresentar ao aluno a constatao experimental dos conceitos bsicos, e essenciais,
estudados na disciplina terica. Tambm so fornecidos todos os manuais dos componentes usados nos
experimentos, disponibilizando ao aluno todas as informaes necessrias realizao dos projetos.
4
2.
AMPLIFICADOR PUSH-PULL COM SADA COMPLEMENTAR
ASSUNTO
Projeto de um amplificador de potncia, classe AB, com transistores de sada em simetria complementar.
OBJETIVO
Familiarizar o aluno com as condies de operao e caractersticas particulares do circuito.
PROJETO
Fase 1- Projete o circuito da Figura 2.1 obedecendo as seguintes especificaes:
1 - Potncia C.A. de sada de 1W.
2 - Carga de 8.
3 - Eficincia superior a 40%.
4 - Freqncia de corte inferior menor que 50Hz.
5 - Ganho de tenso o maior possvel.
6 - Considerar nos clculos os transistores: TIP29C, TIP30C, BC547 e BC557.
Consideraes:
1 - Calcule os ganhos de tenso e potncia.
2 - Mostre que a eficincia mxima real do estgio de sada dada por:
Vop
4V cc
onde Vop a tenso de pico de sada.
3 - Explique a funo dos seguintes componentes do circuito: R1, R2, D1, D2, D3, D4, C2 e C5.
4 - Considere R1=R2=0.5.
5 - Ajuste P1 at obter a tenso DC no ponto A igual a zero.
Medidas:
1 - Medir a polarizao aps os ajustes necessrios.
2 - Medir os ganhos de tenso e de potncia.
3 - Medir e traar o grfico de resposta em freqncia.
6 - Medir a eficincia do circuito para a mxima tenso de sada, sem saturao.
5
7 - Curto-circuitar os pontos B e C, e observar as alteraes na forma de onda de sada. Explicar estas
alteraes.
Fase 2- Projete o circuito da Figura 2.2 obedecendo as seguintes recomendaes:
1 - Conservar os valores dos componentes calculados para o circuito da Figura 2.1, exceto o capacitor
C1.
2 - Identificar o tipo de realimentao empregada.
3 - Calcular R6 para se obter um ganho de tenso realimentado de 4. Este ganho necessrio para que
um sinal de entrada com 1V de amplitude produza potncia mxima na sada do amplificador. Esta
uma especificao comum aos amplificadores de potncia comerciais.
4 - Recalcular C1 para manter a freqncia de corte inferior menor que 50Hz.
Medidas:
1 - Medir a tenso DC no ponto A e comparar com a da Fase 1.
2 - Medir o ganho de tenso.
3 - Medir e traar o grfico de resposta em freqncia.
6 - Curto-circuitar os pontos B e C, e observar as alteraes na forma de onda de sada. Comparar com o
observado na Fase 1.
Fase 3- Projete o circuito da Figura 2.4 obedecendo as seguintes recomendaes:
1 - Monte o circuito da Figura 2.3 (a) utilizando um microfone de eletreto e um resistor R10=10k.
2 - Fale ao microfone e observe a amplitude mxima do sinal AC em VMic.
3 - Com a tenso VMic, projete o pr-amplificador da Figura 2.3 (b) de tal forma a se obter uma tenso
mxima Vpr=1V e freqncia de corte inferior menor que 50Hz. Conecte o pr-amplificador ao
amplificador da Fase 2, conforme a Figura 2.4, substitua a carga RL por um alto-falante de 8, fale
ao microfone e relate suas impresses.
Figura 2.1: Amplificador Push-Pull.
Figura 2.2: Amplificador Push-Pull com realimentao.
Figura 2.3: Microfone de eletreto. a) Polarizao. b) Microfone mais amplificador.
Figura 2.4: Amplificador Push-Pull mais microfone de eletreto.
7
3.
AMPLIFICADOR SINTONIZADO
OBJETIVO
Estudo de um amplificador sintonizado e sua aplicao como amplificador seletivo, multiplicador de
freqncias e conversor.
ESPECIFICAES
Projetar um amplificador sintonizado, tomando por base, a Figura 3.1, com as seguintes
caractersticas:
1 - Vcc = 12V.
( )
2 - Freqncia da portadora ( eci c = 400kHz ).
3 - Ganho de tenso AV =
eco ( c )
eci ( c )
20 .
4 - Seletividade igual a 10.
PROCEDIMENTOS
1 - Medida das relaes de espiras das bobinas.
2 - Medidas dos fatores de Qualidade e de LX, segundo o esquema abaixo.
onde:
Cv uma dcada capacitiva;
Cp a capacitncia parasita, que inclui a capacitncia do osciloscpio, da fiao, residual da dcada e da
prpria bobina;
o =
L x Cv + C p
Fazer as medidas de Lx em dois valores, o1 e o2, em torno de c, de

modo que seja anulada a capacitncia Cp.
- Medida de Qb.
8
Vo = Vi
Z( o )
R s + Z( o )
Z( o ) = o LQb
( Qb >> 1 )
Dados Vi e Rs medir Vo mximo com o osciloscpio (ponta atenuadora) e calcular Z o .
( )
3 - Calcule os componentes para atender as especificaes dadas;

4 - Calcule a seletividade do circuito;
5 - Responda:
Qual o sinal observado na sada quando a entrada:
- for um sinal senoidal de 400kHz;
- for um sinal senoidal de 800 kHz;
- for um sinal quadrado de 200kHz;
6 - Monte o circuito e compare os valores previstos e calculados com os medidos.
Medidas:
- o ganho mximo em c;
- a curva de resposta, assinalando os pontos de meia potncia;
- a seletividade;
- os sinais de sada de acordo com as entradas especificadas no item 5;
- explique os resultados;
- faa as observaes que julgue necessrias;
7 - No circuito j montado, aplique base outro gerador de sinais, conforme a Figura 3.2.
- atravs do gerador G1 um sinal de 800kHz;
- atravs do gerador G2 um sinal de 1200kHz;
8 - Qual o sinal que ser observado na sada (sobre RL)?
9 - Comente e apresente as explicaes tericas para o observado.
Figura 3.1: Amplificador sintonizado.
Figura 3.2: Amplificador sintonizado como mixer.
10
4.
MODULADOR DE AMPLITUDE
OBJETIVO
Estudo de um circuito Modulador de Amplitude (AM).
ESPECIFICAES
Projetar um circuito Modulador de Amplitude, tomando por base, o circuito da Figura 4.1, de forma
a atender as especificaes abaixo:
1 - Freqncia da portadora igual a 400kHz.
2 - Freqncia de corte inferior, para o sinal modulador, de 50Hz.
3 - Freqncia de corte superior, para o sinal modulador, de 5kHz.
PROCEDIMENTOS
1 - Mea a indutncia L da bobina, sua relao de espiras e seu fator de qualidade Qb.
2 - Calcule os capacitores C1 e C2 para que o circuito oscile na freqncia de 400kHz.
3 - Calcule R1, R2, P, C3, C5 de forma a atender os itens 2 e 3 das especificaes.
4 - Mostre que para se obter simetria nos ciclos positivo e negativo do sinal modulado Vo(t),
V
necessrio que a resistncia equivalente no coletor de Q2 seja R eq = cc . Calcule Ro para se obter
2 Icq
Req.
5 - Calcule C4 de tal forma que: na freqncia da portadora o capacitor seja um curto-circuito; nas freqncias moduladoras o capacitor seja um circuito aberto.
MEDIDAS
1 - Mea a freqncia da portadora.
2 - Com um sinal de entrada de 1kHz, ajuste sua amplitude para um ndice de modulao de 50% e
esboce o sinal de sada Vo(t) para as formas de onda quadrada, senoidal e triangular.
3 - Mea o maior ndice de modulao que pode ser obtido sem que haja distoro no sinal de sada.
11
Figura 4.1: Modulador de amplitude.
12
5.
MULTIPLICADORES ANALGICOS
OBJETIVO
Familiarizar o aluno quanto s tcnicas de multiplicao de sinais analgicos variantes no tempo e
sua aplicao como moduladores em amplitude com e sem portadora, detectores sncronos, detectores de
fase, dobradores de freqncia, extratores de raiz quadrada, etc.
INTRODUO
Durante muito tempo a multiplicao analgica foi conseguida atravs de vrias tcnicas como:
- mtodo do quadrado da soma usando dispositivos no lineares que apresentem caractersticas
quadrticas, predominantes ou no, como FETs, diodos ou transistores de juno, seguidos de
filtros passa-faixa.
- mtodo do quadrado da soma balanceada, usando os mesmos dispositivos anteriores, mas em circuitos onde a portadora suprimida (mais de 40dB) ou reduzida (mais de 20dB). Em baixas freqncias pode-se simular um dispositivo com caractersticas quadrticas com operacionais e redes
de realimentao providas de resistores e diodos em srie. Para cada tenso de entrada o ganho
ser diferente e aproximao por partes poder ser quadrtica.
- mtodo da modulao por largura de pulsos.
- mtodo dos amplificadores logartmicos.
- mtodo dos amplificadores de transcondutncia varivel [1].
Todas estas tcnicas sero analisadas nas aulas tericas.
A presente prtica ser sobre os moduladores balanceados de transcondutncia varivel e com os coletores dos diferenciais cruzados, conhecidos como clulas de Gilbert [1]. Estas clulas so comuns a vrios
integrados como multiplicadores de quatro quadrantes, moduladores, etc.
TRABALHO PREPARATRIO
1 - Estudar as caractersticas tcnicas do modulador balanceado MC1496.
2 - Estudar os circuitos apresentados com as funes:
- Modulador AM DSB
- Modulador AM DSB SC
3 - Usando a identidade
1
1
sen( a + b) + sen( a b)
2
2
sendo a = c t + e b = c t
sen( a ) sen( b) =
idealizar um circuito que possa fornecer uma tenso de sada proporcional ao desvio de fase entre os
sinais a e b, sendo < 4 , onde sen( ) .
13
PRTICA
1 - Montar um circuito modulador em amplitude da Figura 5.1 que possa funcionar como AM DSB e
AM DSB SC numa freqncia de portadora c = 2 100 10 3 rad s e freqncia da moduladora
m = 2f m , fm variando de 100Hz a 3kHz.
2 - Mea as polarizaes e observe no osciloscpio as formas de onda do item 1, medindo os ndices de
modulao em amplitude para AM DSB.
3 - Observe no analisador de espectro as formas de onda do item 1, anotando os resultados. Varie o potencimetro que reduz a portadora, medindo o melhor resultado.
4 - Montar o circuito projetado como detector de fase. Caso necessite de um defasador de 2 utilize redes RC.
Figura 5.1: Modulador balanceado.

Responda:
- Em que se baseia a modulao sncrona? Onde usada?
- Como se poderia obter um oitavador musical?
- Como se poderia obter um extrator de raiz quadrada?
Referncias
[1]
Manual da Motorola em anexo.
[2]
Design of Analog Integrated Circuits. P. Gray, M. Meyer. John Wiley, Mp.
14
6.
MODULADOR DE FREQNCIA
OBJETIVO
Estudo de um circuito Modulador de Freqncia (FM).
ESPECIFICAES
Projetar um circuito Modulador de Freqncia, tomando por base o circuito da Figura 6.1, de forma
a atender as especificaes abaixo:
1 - Freqncia da portadora igual a 40MHz.
2 - Freqncia de corte inferior, para o sinal modulador, de 50Hz.
3 - Freqncia de corte superior, para o sinal modulador, de 50kHz.
PROCEDIMENTOS
1 - Determine R4 e C4 de forma a atender as especificaes de freqncias de corte inferior e superior
para o sinal modulador. Considere a capacitncia do diodo varactor em torno de 15pF.
2 - Calcule C1, C2 e L para que o circuito oscile na freqncia de 40MHz. Para isto, reflita todas as capacitncias e resistncias para o coletor do transistor BF494. A freqncia pode ser determinada pela
frmula abaixo:
f=
1
.
2 LCeq
3 - A bobina deve ser confeccionada com fio rgido esmaltado (fio de enrolar motor), com uma nica camada de espiras e com forma cilndrica. Para o clculo do nmero de espiras e das dimenses da bobina, deve ser usada a frmula abaixo:
L=
0. 394 r 2 N 2
9 r + 10 h
onde
L - a indutncia em H.
r - o raio da bobina em cm.
N - o nmero de espiras.
h - o comprimento da bobina em cm.
MEDIDAS
1 - Sem aplicar o gerador de sinais, varie o potencimetro P entre o mnimo e o mximo. Faa um
grfico da freqncia de oscilao pela tenso no ponto A (que a tenso que polariza o diodo
varactor), e calcule a constante ko do oscilador.
2 - Conecte o gerador de sinais ao modulador, e com o auxlio do Analisador de Espectro, observe e
anote a forma do sinal Vo(t) no domnio da freqncia. Fixe a freqncia do gerador de sinais em
30kHz, e aumente a amplitude do sinais at que se observe o primeiro apagamento da portadora, que
15
ocorre quando mf 2.4 , sendo mf =
f
o ndice de modulao, f = k oVB o desvio de freqncia
fm
e fm a freqncia de modulao.
3 - Retire os capacitores C1 e C2, de forma que o circuito pare de oscilar. Mea a amplitude do sinal
2.4 f m
e compare com o valor obtido no item 1.
Vo(t), calcule ko =
max Vo ( t )
Figura 6.1: Circuito modulador de freqncia.
OBS: Na modulao FM temos:

f i ( t ) = f c + f cos( f m t )
i ( t ) = 2 f i ( t )dt
i ( t ) = 2f c t +
f
sen(2f m t )
fm
16
7.
FONTES CHAVEADAS
OBJETIVO
Projetar e verificar o funcionamento dos conversores BOOST, BUCK-BOOST e BUCK.
PRTICA
a)
Conversor BOOST
O circuito da Figura 7.1 um conversor BOOST operando no modo descontnuo. Dimensione RS e CS

de forma a se obter VS=20V com =0.5 e uma variao mxima de 0.1V. A tenso VCC deve ser ajustada em
5V, e Vp conforme a Figura 7.2. Assuma uma freqncia de chaveamento de 10kHZ.
- equaes de projeto:
Tempo de carregamento do indutor L, TC=T
Tempo de descarregamento do indutor L, TD=1T, 01(1-)
Tenso de sada VS = ( VCC VT )
VD + VCC , onde VT e VD so as tenses de conduo do transistor e

1
diodo D1 respectivamente.
A corrente no indutor na
( V VT ) (1 ) T
IS _ fronteira = CC
2L
Indutor L =
( VCC VT )1T , onde

2IS
fronteira
do
modo
contnuo
para
descontnuo
IS a corrente DC na carga RS, e T o perodo de chaveamento.
Corrente mxima acumulada no indutor L, I max =
(VCC VT )T
L
Capacitor em funo da mxima variao de tenso na sada, CS
IS T MAX
VL
- medidas:
1)
2)
3)
4)
5)
6)
7)
Simule o circuito.
Mea a tenso de sada.
Mea a variao de tenso na sada (ripple).
Registre a tenso no ponto B.
Verifique a corrente de carga e descarga do indutor, observando a tenso no ponto A. V A = VCC 100 I .
Varie de 0.1 a 0.5, e plote um grfico de VS em funo de .
Compare os resultados prticos com os calculados e os obtidos previamente por simulao. Justifique as
discrepncias.
17
Figura 7.1: Conversor BOOST.
Figura 7.2: Fonte de excitao dos conversores BOOST e BUCK-BOOST.
b)
Conversor BUCK-BOOST
O circuito da Figura 7.3 um conversor BUCK-BOOST operando no modo descontnuo. Dimensione

RS e CS de forma a se obter VS=-20V com =0.5 e uma variao mxima de 0.1V. A tenso VCC deve ser
ajustada em 5V, e Vp conforme a Figura 7.2. Assuma uma freqncia de chaveamento de 10kHZ.
Tempo de carregamento do indutor L, TC=T
Tempo de descarregamento do indutor L, TD=1T, 01(1-)
Tenso de sada VS = ( VCC VT )
+ VD , onde VT e VD so as tenses de conduo do transistor e

1
diodo D respectivamente.
2 ( VCC VT ) T
, onde IS a corrente DC na carga RS, e T o perodo de chaveamento.
2 ( VD VS ) IS
2
Indutor L =
Corrente mxima acumulada no indutor L, I max =
(VCC VT )T
L
Capacitor em funo da mxima variao de tenso na sada, CS
IS T MAX
VL
18
- medidas:
1)
2)
3)
4)
5)
6)
7)
Simule o circuito.
Mea a tenso de sada.
Mea a variao de tenso na sada (ripple).
Registre a tenso no ponto A.
Verifique a corrente de carga e descarga do indutor, observando a tenso no ponto B. V B = 100 I .
discrepncias.
Figura 7.3: Conversor Buck-Boost.
c)
Conversor BUCK
O circuito da Figura 7.4 um conversor BUCK. Dimensione RS, CS e , de forma a se obter VS=5V e
uma atenuao mnima, do filtro LC, de 0.01 na freqncia de chaveamento. A tenso VCC deve ser ajustada
em 10V, e Vp conforme a Figura 7.5. Assuma uma freqncia de chaveamento de 10kHZ. Considere tambm
a possibilidade poder variar de um valor mnimo de 0.2 a um mximo de 1.
Tempo de carregamento do indutor L, TC=T, 0.2<1
Tenso de sada VS = ( VCC VT ) VD (1 ) , onde VT e VD so as tenses de conduo do transistor e
diodo D respectivamente.
T2
Capacitor CS =
, onde A a atenuao do filtro LC na freqncia de chaveamento, T o
2
( 2 ) AL
perodo de chaveamento.
A corrente mnima na carga ISMIN que garante a corrente I no indutor maior que zero, com mnimo
(1 min ) T
ISMIN = min
( VCC + VD VT ) .
2L
V
O resistor mximo admissvel R SMAX = SMIN
ISMIN
19
- medidas:
1)
2)
3)
4)
5)
6)
Simule o circuito.
Mea a tenso de sada (ripple).
Mea a variao de tenso na sada.
Registre a tenso no ponto A.
discrepncias.
Figura 7.4: Conversor BUCK.
Figura 7.5: Fonte de excitao do conversor BUCK.
20
DATASHEETS
Philips Semiconductors
Product specification
High-speed diodes
1N4148; 1N4448
FEATURES
DESCRIPTION
Hermetically sealed leaded glass

SOD27 (DO-35) package
The 1N4148 and 1N4448 are high-speed switching diodes fabricated in planar
technology, and encapsulated in hermetically sealed leaded glass SOD27
(DO-35) packages.
High switching speed: max. 4 ns

General application
Continuous reverse voltage:
max. 75 V
Repetitive peak reverse voltage:
max. 75 V
handbook, halfpage
k
Repetitive peak forward current:

max. 450 mA.
MAM246
The diodes are type branded.
APPLICATIONS
High-speed switching.
Fig.1 Simplified outline (SOD27; DO-35) and symbol.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VRRM
repetitive peak reverse voltage
75
VR
continuous reverse voltage
75
IF
continuous forward current
200
mA
IFRM
repetitive peak forward current
450
mA
IFSM
non-repetitive peak forward current
t = 1 s
t = 1 ms
t=1s
0.5
500
mW
see Fig.2; note 1

square wave; Tj = 25 C prior to
surge; see Fig.4
Tamb = 25 C; note 1
Ptot
total power dissipation
Tstg
storage temperature
65
+200
Tj
junction temperature
200
Note
1. Device mounted on an FR4 printed circuit-board; lead length 10 mm.
1999 May 25
High-speed diodes
1N4148; 1N4448
ELECTRICAL CHARACTERISTICS
Tj = 25 C unless otherwise specified.
SYMBOL
VF
IR
PARAMETER
forward voltage
CONDITIONS
MIN.
MAX.
UNIT
see Fig.3
1N4148
IF = 10 mA
1N4448
IF = 5 mA
0.62
0.72
IF = 100 mA
reverse current
25
nA
VR = 20 V; Tj = 150 C; see Fig.5
VR = 20 V; see Fig.5
50
IR
reverse current; 1N4448
VR = 20 V; Tj = 100 C; see Fig.5
Cd
diode capacitance
f = 1 MHz; VR = 0; see Fig.6
pF
trr
reverse recovery time
when switched from IF = 10 mA to

IR = 60 mA; RL = 100 ;
measured at IR = 1 mA; see Fig.7
ns
Vfr
forward recovery voltage
when switched from IF = 50 mA;

tr = 20 ns; see Fig.8
2.5
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth j-tp
thermal resistance from junction to tie-point
lead length 10 mm
240
K/W
Rth j-a
thermal resistance from junction to ambient
lead length 10 mm; note 1
350
K/W
Note
1. Device mounted on a printed circuit-board without metallization pad.
1999 May 25
High-speed diodes
1N4148; 1N4448
GRAPHICAL DATA
MBG451
300
MBG464
600
handbook, halfpage
handbook, halfpage
IF
(mA)
IF
(mA)
200
400
(1)
100
(3)
200
0
0
100
Tamb (oC)
200
VF (V)
(1) Tj = 175 C; typical values.

(2) Tj = 25 C; typical values.
(3) Tj = 25 C; maximum values.
Device mounted on an FR4 printed-circuit board; lead length 10 mm.
Fig.2
(2)
Maximum permissible continuous forward

current as a function of ambient
temperature.
Fig.3
Forward current as a function of forward

voltage.
MBG704
102
handbook, full pagewidth
IFSM
(A)
10
101
1
10
102
103
tp (s)
Based on square wave currents.

Tj = 25 C prior to surge.
Fig.4 Maximum permissible non-repetitive peak forward current as a function of pulse duration.
1999 May 25
104
High-speed diodes
1N4148; 1N4448
MGD290
103
handbook, halfpage
MGD004
1.2
handbook, halfpage
IR
(A)
10
Cd
(pF)
1.0
(1)
(2)
10
0.8
1
0.6
101
102
0
100
Tj (oC)
0.4
200
(1) VR = 75 V; typical values.

(2) VR = 20 V; typical values.
Fig.5
VR (V)
20
f = 1 MHz; Tj = 25 C.
Reverse current as a function of junction

temperature.
1999 May 25
10
Fig.6
Diode capacitance as a function of reverse

voltage; typical values.
High-speed diodes
1N4148; 1N4448
tr
tp
t
D.U.T.
10%
IF
RS = 50
IF
SAMPLING
OSCILLOSCOPE
t rr
t
R i = 50
V = VR I F x R S
MGA881
(1)
90%
VR
input signal
output signal
(1) IR = 1 mA.
Fig.7 Reverse recovery voltage test circuit and waveforms.
1 k
450
I
90%
R S = 50
D.U.T.
OSCILLOSCOPE
V fr
R i = 50
10%
MGA882
t
tr
input
signal
Fig.8 Forward recovery voltage test circuit and waveforms.
1999 May 25
tp
output
signal
NPN general purpose transistors
BC546; BC547
FEATURES
PINNING
Low current (max. 100 mA)
PIN
Low voltage (max. 65 V).

APPLICATIONS
DESCRIPTION
emitter
base
collector
General purpose switching and amplification.

DESCRIPTION
handbook, halfpage1
NPN transistor in a TO-92; SOT54 plastic package.

PNP complements: BC556 and BC557.
2
3
2
1
MAM182
Fig.1
Simplified outline (TO-92; SOT54)

and symbol.
LIMITING VALUES
SYMBOL
VCBO
VCEO
PARAMETER
collector-base voltage
CONDITIONS
MAX.
UNIT
open emitter
BC546
80
BC547
50
65
45
BC546
BC547
collector-emitter voltage
open base
BC546
BC547
VEBO
MIN.
emitter-base voltage
open collector
IC
collector current (DC)
100
mA
ICM
peak collector current
200
mA
IBM
peak base current
Ptot
Tstg
200
mA
500
mW
storage temperature
65
+150
Tj
150
Tamb
operating ambient temperature
65
+150
Tamb 25 C; note 1
Note
1. Transistor mounted on an FR4 printed-circuit board.
1999 Apr 15
BC546; BC547
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
note 1
VALUE
UNIT
0.25
K/mW
Note
CHARACTERISTICS
SYMBOL
PARAMETER
ICBO
collector cut-off current
IEBO
emitter cut-off current
hFE
DC current gain
CONDITIONS
MIN.
TYP.
MAX.
IE = 0; VCB = 30 V
15
nA
IE = 0; VCB = 30 V; Tj = 150 C
IC = 0; VEB = 5 V
100
nA
IC = 10 A; VCE = 5 V;
see Figs 2, 3 and 4
90
BC546B; BC547B
150
BC547C
270
BC546A
DC current gain
BC546A
UNIT
IC = 2 mA; VCE = 5 V;
see Figs 2, 3 and 4
110
180
220
BC546B; BC547B
200
290
450
BC547C
420
520
800
BC547
110
800
BC546
110
450
VCEsat
collector-emitter saturation
voltage
IC = 10 mA; IB = 0.5 mA
90
250
mV
IC = 100 mA; IB = 5 mA
200
600
mV
VBEsat
base-emitter saturation voltage
IC = 10 mA; IB = 0.5 mA; note 1
700
mV
IC = 100 mA; IB = 5 mA; note 1
900
mV
VBE
base-emitter voltage
IC = 2 mA; VCE = 5 V; note 2
580
660
700
mV
IC = 10 mA; VCE = 5 V
770
mV
Cc
collector capacitance
IE = ie = 0; VCB = 10 V; f = 1 MHz
1.5
pF
Ce
emitter capacitance
IC = ic = 0; VEB = 0.5 V; f = 1 MHz
11
pF
fT
transition frequency
IC = 10mA; VCE = 5 V; f = 100 MHz 100
MHz
noise figure
IC = 200 A; VCE = 5 V;
RS = 2 k; f = 1 kHz; B = 200 Hz
10
dB
Notes
1. VBEsat decreases by about 1.7 mV/K with increasing temperature.
2. VBE decreases by about 2 mV/K with increasing temperature.
1999 Apr 15
BC546; BC547
MBH723
250
hFE
200
VCE = 5 V
150
100
50
0
102
101
102
10
IC (mA)
103
BC546A.
Fig.2 DC current gain; typical values.
MBH724
300
VCE = 5 V
hFE
200
100
0
102
101
10
BC546B; BC547B.
1999 Apr 15
102
IC (mA)
103
BC546; BC547
MBH725
600
VCE = 5 V
hFE
400
200
0
102
101
10
BC547C.
1999 Apr 15
102
IC (mA)
103
PNP general purpose transistors
BC556; BC557
FEATURES
PINNING
PIN

APPLICATIONS
DESCRIPTION
emitter
base
collector
General purpose switching and amplification.

DESCRIPTION
handbook, halfpage1
PNP transistor in a TO-92; SOT54 plastic package.

NPN complements: BC546 and BC547.
2
3
2
1
MAM281
Fig.1

and symbol.
LIMITING VALUES
SYMBOL
VCBO
VCEO
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
open emitter
BC556
80
BC557
50
BC556
65
BC557
45
open base
VEBO
IC
100
mA
ICM
200
mA
IBM
peak base current
200
mA
open collector
Ptot
500
mW
Tstg
storage temperature
65
+150
Tj
150
Tamb
65
+150
1999 Apr 15
Tamb 25 C
BC556; BC557
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
note 1
VALUE
UNIT
250
K/W
Note
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
ICBO
IE = 0; VCB = 30 V
15
nA
IE = 0; VCB = 30 V; Tj = 150 C
IEBO
IC = 0; VEB = 5 V
100
nA
hFE
DC current gain
IC = 2 mA; VCE = 5 V;
see Figs 2, 3 and 4
125
475
BC557
125
800
BC556A
125
250
BC556B; BC557B
220
475
BC556
420
800
IC = 10 mA; IB = 0.5 mA
60
300
mV
IC = 100 mA; IB = 5 mA
180
650
mV
BC557C
VCEsat
VBEsat
collector-emitter saturation
voltage
base-emitter saturation voltage
IC = 10 mA; IB = 0.5 mA; note 1
750
mV
IC = 100 mA; IB = 5 mA; note 1
930
mV
600
650
750
mV
VBE
820
mV
Cc
collector capacitance
IE = ie = 0; VCB = 10 V; f = 1 MHz
pF
Ce
emitter capacitance
IC = ic = 0; VEB = 0.5 V; f = 1 MHz
10
pF
fT
IC = 10 mA; VCE = 5 V; f = 100 MHz 100
MHz
noise figure
IC = 200 A; VCE = 5 V; RS = 2 k;
f = 1 kHz; B = 200 Hz
10
dB
Notes
1. VBEsat decreases by about 1.7 mV/K with increasing temperature.
2. VBE decreases by about 2 mV/K with increasing temperature.
1999 Apr 15
BC556; BC557
MBH726
300
hFE
200
VCE = 5 V
100
0
101
102
10
IC (mA)
103
BC556A.
MBH727
400
hFE
VCE = 5 V
300
200
100
0
102
101
10
BC556B; BC557B.
1999 Apr 15
102
IC (mA)
103
BC556; BC557
MBH728
600
hFE
500
VCE = 5 V
400
300
200
100
0
102
101
10
BC557C.
1999 Apr 15
102
IC (mA)
103
NPN medium frequency transistors

FEATURES
BF494; BF495
PINNING
PIN
base
emitter
collector
APPLICATIONS
DESCRIPTION
HF applications in radio and television receivers

FM tuners
Low noise AM mixer-oscillators
handbook, halfpage1
IF amplifiers in AM/FM receivers.
2
3
DESCRIPTION
MAM258
NPN medium frequency transistor in a TO-92; SOT54

plastic package.
Fig.1

and symbol.
QUICK REFERENCE DATA

SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCBO
open emitter
30
VCEO
open base
20
ICM
30
mA
Ptot
Tamb 25 C
300
mW
hFE
DC current gain
IC = 1 mA; VCE = 10 V
BF494
67
220
BF495
35
125
120
fT
1997 Jul 08
IC = 1 mA; VCE = 10 V; f = 100 MHz
MHz
NPN medium frequency transistors
BF494; BF495
LIMITING VALUES
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCBO
open emitter
30
VCEO
open base
20
VEBO
open collector
IC
30
mA
ICM
30
mA
Ptot
300
mW
Tstg
storage temperature
65
+150
Tj
150
Tamb
65
+150
Tamb 25 C; note 1
Note
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
VALUE
UNIT
420
K/W
note 1
Note
CHARACTERISTICS
Tamb = 25 C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
IE = 0; VCB = 20 V
100
nA
IE = 0; VCB = 20 V; Tamb = 150 C
IC = 0; VEB = 4 V
100
nA
BF494
67
220
BF494B
100
220
BF495
35
125
ICBO
IEBO
hFE
DC current gain
IC = 1 mA; VCE = 10 V
100
125
VBE
BF495B
IC = 1 mA; VCE = 10 V
650
740
mV
Cre
feedback capacitance
IC = 0; VCB = 10 V; f = 1 MHz
pF
fT
IC = 1 mA; VCE = 10 V; f = 100 MHz
120
MHz
1997 Jul 08
TIP29, TIP29A, TIP29B, TIP29C

NPN SILICON POWER TRANSISTORS
Copyright 1997, Power Innovations Limited, UK
JULY 1968 - REVISED MARCH 1997
Designed for Complementary Use with the

TIP30 Series
TO-220 PACKAGE
(TOP VIEW)
30 W at 25C Case Temperature
1 A Continuous Collector Current
3 A Peak Collector Current
Customer-Specified Selections Available
Pin 2 is in electrical contact with the mounting base.

MDTRACA
absolute maximum ratings at 25C case temperature (unless otherwise noted)

RATING
SYMBOL
TIP29
Collector-base voltage (IE = 0)
Collector-emitter voltage (IB = 0)
TIP29A
TIP29B
VCBO
100
120
TIP29C
140
40
TIP29A
TIP29B
VCEO
TIP29C
Continuous collector current
Peak collector current (see Note 1)
Continuous base current
Continuous device dissipation at (or below) 25C case temperature (see Note 2)
Continuous device dissipation at (or below) 25C free air temperature (see Note 3)
Unclamped inductive load energy (see Note 4)
Operating junction temperature range
Storage temperature range
Lead temperature 3.2 mm from case for 10 seconds
UNIT
80
TIP29
Emitter-base voltage
NOTES: 1.
2.
3.
4.
VALUE
60
80
100
V EBO
IC
ICM
IB
0.4
Ptot
30
Ptot
LIC 2
32
mJ
C
Tj
-65 to +150
Tstg
-65 to +150
TL
250
This value applies for tp 0.3 ms, duty cycle 10%.

Derate linearly to 150C case temperature at the rate of 0.24 W/C.
Derate linearly to 150C free air temperature at the rate of 16 mW/C.
This rating is based on the capability of the transistor to operate safely in a circuit of: L = 20 mH, IB(on) = 0.4 A, R BE = 100 ,
VBE(off) = 0, RS = 0.1 , VCC = 20 V.
PRODUCT
INFORMATION
Information is current as of publication date. Products conform to specifications in accordance

with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.

electrical characteristics at 25C case temperature

PARAMETER
V (BR)CEO
ICES
ICEO
IEBO
hFE
VCE(sat)
VBE
hfe
|hfe|
TEST CONDITIONS
Collector-emitter
breakdown voltage
IC = 30 mA
MIN
IB = 0
(see Note 5)
TIP29
40
TIP29A
60
TIP29B
80
TIP29C
100
TYP
MAX
VCE = 80 V
VBE = 0
TIP29
0.2
Collector-emitter
V CE = 100 V
V BE = 0
TIP29A
0.2
cut-off current
V CE = 120 V
V BE = 0
TIP29B
0.2
V CE = 140 V
V BE = 0
TIP29C
0.2
Collector cut-off
VCE = 30 V
IB = 0
TIP29/29A
0.3
current
V CE = 60 V
IB = 0
TIP29B/29C
0.3
VEB =
IC = 0
Emitter cut-off
current
5V
UNIT
mA
mA
mA
Forward current
VCE =
4V
IC = 0.2 A
transfer ratio
V CE =
4V
IC =
1A
IB = 125 mA
IC =
1A
(see Notes 5 and 6)
0.7
VCE =
IC =
1A
(see Notes 5 and 6)
1.3
Collector-emitter
saturation voltage
Base-emitter
voltage
Small signal forward
current transfer ratio
4V
(see Notes 5 and 6)
40
15
VCE = 10 V
IC = 0.2 A
f = 1 kHz
20
VCE = 10 V
IC = 0.2 A
f = 1 MHz
75
NOTES: 5. These parameters must be measured using pulse techniques, tp = 300 s, duty cycle 2%.
6. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts.
thermal characteristics
MAX
UNIT
RJC
Junction to case thermal resistance
PARAMETER
MIN
TYP
4.17
C/W
RJA
Junction to free air thermal resistance
62.5
C/W
MAX
UNIT
resistive-load-switching characteristics at 25C case temperature

PARAMETER
MIN
ton
Turn-on time
IC = 1 A
IB(on) = 0.1 A
IB(off) = -0.1 A
toff
Turn-off time
V BE(off) = -4.3 V
RL = 30
tp = 20 s, dc 2%
Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
PRODUCT
TEST CONDITIONS
INFORMATION
TYP
0.5

TYPICAL CHARACTERISTICS
TYPICAL DC CURRENT GAIN
vs
COLLECTOR CURRENT
TCS631AD
VCE = 4 V
TC = 25C
tp = 300 s, duty cycle < 2%
100
10
1
0001
001
01
IC = 100 mA
IC = 300 mA
IC = 1 A
10
01
001
01
10
TCS631AE
10
VCE(sat) - Collector-Emitter Saturation Voltage - V
hFE - DC Current Gain
1000
COLLECTOR-EMITTER SATURATION VOLTAGE

vs
BASE CURRENT
IC - Collector Current - A
10
10
100
1000
IB - Base Current - mA
Figure 1.
Figure 2.
BASE-EMITTER VOLTAGE
vs
COLLECTOR CURRENT
10
TCS631AF
VBE - Base-Emitter Voltage - V
VCE = 4 V
TC = 25C
09
08
07
06
05
001
01
10
Figure 3.
PRODUCT
INFORMATION

MAXIMUM SAFE OPERATING REGIONS
MAXIMUM FORWARD-BIAS
SAFE OPERATING AREA
100
SAS631AC
tp = 300 s, d = 0.1 = 10%

tp = 1 ms, d = 0.1 = 10%
tp = 10 ms, d = 0.1 = 10%
DC Operation
10
10
01
TIP29
TIP29A
TIP29B
TIP29C
001
10
10
100
1000
VCE - Collector-Emitter Voltage - V
Figure 4.
THERMAL INFORMATION
MAXIMUM POWER DISSIPATION
vs
CASE TEMPERATURE
TIS631AB
Ptot - Maximum Power Dissipation - W
40
30
20
10
0
0
25
50
75
100
TC - Case Temperature - C
Figure 5.
PRODUCT
INFORMATION
125
150
TIP30, TIP30A,TIP30B, TIP30C

PNP SILICON POWER TRANSISTORS
Copyright 1997, Power Innovations Limited, UK
Designed for Complementary Use with the

TIP29 Series
TO-220 PACKAGE
(TOP VIEW)
30 W at 25C Case Temperature
1 A Continuous Collector Current
3 A Peak Collector Current
Customer-Specified Selections Available
Pin 2 is in electrical contact with the mounting base.

MDTRACA
absolute maximum ratings at 25C case temperature (unless otherwise noted)

RATING
SYMBOL
TIP30
Collector-base voltage (IE = 0)
TIP30A
TIP30B
VCBO
TIP30C
Collector-emitter voltage (IB = 0)
TIP30B
Continuous collector current

Peak collector current (see Note 1)
Continuous base current
Continuous device dissipation at (or below) 25C case temperature (see Note 2)
Continuous device dissipation at (or below) 25C free air temperature (see Note 3)
Unclamped inductive load energy (see Note 4)
Operating junction temperature range
Storage temperature range
Lead temperature 3.2 mm from case for 10 seconds
NOTES: 1.
2.
3.
4.
-100
-120
-140
-40
VCEO
TIP30C
Emitter-base voltage
UNIT
-80
TIP30
TIP30A
VALUE
-60
-80
-100
V EBO
-5
IC
-1
ICM
-3
IB
-0.4
Ptot
30
Ptot
LIC 2
32
mJ
C
Tj
-65 to +150
Tstg
-65 to +150
TL
250
This value applies for tp 0.3 ms, duty cycle 10%.

Derate linearly to 150C case temperature at the rate of 0.24 W/C.
Derate linearly to 150C free air temperature at the rate of 16 mW/C.
This rating is based on the capability of the transistor to operate safely in a circuit of: L = 20 mH, IB(on) = -0.4 A, RBE = 100 ,
VBE(off) = 0, RS = 0.1 , VCC = -20 V.
PRODUCT
INFORMATION
Information is current as of publication date. Products conform to specifications in accordance

with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.

electrical characteristics at 25C case temperature

PARAMETER
V (BR)CEO
ICES
ICEO
IEBO
hFE
VCE(sat)
VBE
hfe
|hfe|
TEST CONDITIONS
Collector-emitter
breakdown voltage
IC = -30 mA
MIN
IB = 0
(see Note 5)
TIP30
-40
TIP30A
-60
TIP30B
-80
TIP30C
-100
TYP
MAX
VCE = -80 V
VBE = 0
TIP30
-0.2
Collector-emitter
V CE = -100 V
V BE = 0
TIP30A
-0.2
cut-off current
V CE = -120 V
V BE = 0
TIP30B
-0.2
V CE = -140 V
V BE = 0
TIP30C
-0.2
Collector cut-off
VCE = -30 V
IB = 0
TIP30/30A
-0.3
current
V CE = -60 V
IB = 0
TIP30B/30C
-0.3
VEB =
IC = 0
Emitter cut-off
current
-5 V
UNIT
-1
mA
mA
mA
Forward current
VCE =
-4 V
IC = -0.2 A
transfer ratio
V CE =
-4 V
IC =
-1 A
IB = -125 mA
IC =
-1 A
(see Notes 5 and 6)
-0.7
VCE =
IC =
-1 A
(see Notes 5 and 6)
-1.3
Collector-emitter
saturation voltage
Base-emitter
voltage
-4 V
(see Notes 5 and 6)
40
15
VCE = -10 V
IC = -0.2 A
f = 1 kHz
20
VCE = -10 V
IC = -0.2 A
f = 1 MHz
75
NOTES: 5. These parameters must be measured using pulse techniques, tp = 300 s, duty cycle 2%.
6. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts.
thermal characteristics
MAX
UNIT
RJC
Junction to case thermal resistance
PARAMETER
MIN
TYP
4.17
C/W
RJA
Junction to free air thermal resistance
62.5
C/W
MAX
UNIT
resistive-load-switching characteristics at 25C case temperature

PARAMETER
MIN
ton
Turn-on time
IC = -1 A
IB(on) = -0.1 A
IB(off) = 0.1 A
toff
Turn-off time
V BE(off) = 4.3 V
RL = 30
tp = 20 s, dc 2%
Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
PRODUCT
TEST CONDITIONS
INFORMATION
TYP
0.3

TYPICAL DC CURRENT GAIN
vs
COLLECTOR CURRENT
TCS632AD
VCE = -4 V
TC = 25C
t p = 300 s, duty cycle < 2%
100
10
1
-0001
-001
-01
-10
TCS632AE
-10
VCE(sat) - Collector-Emitter Saturation Voltage - V
hFE - DC Current Gain
1000
COLLECTOR-EMITTER SATURATION VOLTAGE

vs
BASE CURRENT
IC = -100 mA
IC = -300 mA
IC = -1 A
-10
-01
-001
-01
-10
-10
-100
-1000
IB - Base Current - mA
Figure 1.
Figure 2.
BASE-EMITTER VOLTAGE
vs
COLLECTOR CURRENT
-10
TCS632AF
VBE - Base-Emitter Voltage - V
VCE = -4 V
TC = 25C
-09
-08
-07
-06
-05
-001
-01
-10
Figure 3.
PRODUCT
INFORMATION

MAXIMUM SAFE OPERATING REGIONS
MAXIMUM FORWARD-BIAS
SAFE OPERATING AREA
-100
SAS632AB
tp = 300 s, d = 0.1 = 10%

tp = 1 ms, d = 0.1 = 10%
tp = 10 ms, d = 0.1 = 10%
DC Operation
-10
-10
-01
TIP30
TIP30A
TIP30B
TIP30C
-001
-10
-10
-100
-1000
VCE - Collector-Emitter Voltage - V
Figure 4.
THERMAL INFORMATION
MAXIMUM POWER DISSIPATION
vs
CASE TEMPERATURE
TIS631AB
Ptot - Maximum Power Dissipation - W
40
30
20
10
0
0
25
50
75
100
TC - Case Temperature - C
Figure 5.
PRODUCT
INFORMATION
125
150
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080D SEPTEMBER 1978 REVISED AUGUST 1996
D
D
Low Power Consumption

Wide Common-Mode and Differential
Voltage Ranges
Low Input Bias and Offset Currents
Output Short-Circuit Protection
Low Total Harmonic Distortion
0.003% Typ
D
D
D
D
D
D
D
D
Low Noise
Vn = 18 nV/Hz Typ at f = 1 kHz
High Input Impedance . . . JFET Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 13 V/ s Typ
Common-Mode Input Voltage Range
Includes VCC +
description
The JFET-input operational amplifiers in the TL07_ series are designed as low-noise versions of the TL08_
series amplifiers with low input bias and offset currents and fast slew rate. The low harmonic distortion and low
noise make the TL07_ series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier
features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single
monolithic chip.
The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized
for operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to 125C.
AVAILABLE OPTIONS
PACKAGE
TA
0C to
70C
VIOmax
AT 25C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
TSSOP
PACKAGE
(PW)
FLAT
PACKAGE
(W)
10 mV
6 mV
3 mV
TL071CD
TL071ACD
TL071BCD
TL071CP
TL071ACP
TL071BCP
TL071CPWLE
10 mV
6 mV
3 mV
TL072CD
TL072ACD
TL072BCD
TL072CP
TL072ACP
TL072BCP
TL072CPWLE
10 mV
6 mV
3 mV
TL074CD
TL074ACD
TL074BCD
TL074CN
TL074ACN
TL074BCN
TL074CPWLE
TL071ID
TL072ID
TL074ID
TL074IN
TL071IP
TL072IP
TL071MFK
TL072MFK
TL074MFK
TL074MJ
TL071MJG
TL072MJG
TL074MN
TL072MP
TL074MW
40C to
85C
6 mV
55C to
125 C
125C
6 mV
6 mV
9 mV
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL071CDR). The PW package is only available left-ended
taped and reeled (e.g., TL072CPWLE).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
TL072, TL072A, TL072B

D, JG, P, OR PW PACKAGE
(TOP VIEW)
TL071, TL071A, TL071B

D, JG, P, OR PW PACKAGE
(TOP VIEW)
8
NC
VCC +
OUT
OFFSET N2
1OUT
1IN
1IN +
VCC
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
VCC +
2OUT
2IN
2IN +
1OUT
1IN
1IN +
VCC +
2IN +
2IN
2OUT
NC
1OUT
NC
VCC +
NC
NC
VCC +
NC
OUT
NC
NC
1IN
NC
1IN +
NC
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
14
13
12
11
10
NC
2OUT
NC
2IN
NC
1IN+
NC
VCC+
NC
2IN+
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC No internal connection
symbols
TL071
TL072 (each amplifier)
TL074 (each amplifier)
OFFSET N1
IN +
IN +
IN
OUT
IN
OUT
OFFSET N2
4OUT
4IN
4IN +
VCC
3IN +
3IN
3OUT
TL074
FK PACKAGE
(TOP VIEW)
NC
VCC
NC
2IN+
NC
NC
VCC
NC
OFFSET N2
NC
NC
IN
NC
IN +
NC
TL072
FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
NC
NC
TL071
FK PACKAGE
(TOP VIEW)
1IN
1OUT
NC
4OUT
4IN
2IN
2OUT
NC
3OUT
3IN
OFFSET N1
IN
IN +
VCC
TL074, TL074A, TL074B

D, J, N, OR PW PACKAGE
TL074 . . . W PACKAGE
(TOP VIEW)
DALLAS, TEXAS 75265
4IN+
NC
VCC
NC
3IN+
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
schematic (each amplifier)

VCC +
IN +
64
IN
128
OUT
64
C1
18 pF
1080
1080
VCC
OFFSET
NULL
(N1)
OFFSET
NULL
(N2)
TL071 Only
All component values shown are nominal.

COMPONENT COUNT
COMPONENT
TYPE
Resistors
Transistors
JFET
Diodes
Capacitors
epi-FET
TL071
TL072
TL074
11
14
2
1
1
1
22
28
4
2
2
2
44
56
6
4
4
4
Includes bias and trim circuitry
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Input voltage, VI (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package . . . . . . . . . . . . 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, P, or PW package . . . . . . . . . 260C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC .
2. Differential voltages are at IN+ with respect to IN .
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either supply. Temperature and /or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA 25C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE TA
TA = 70C
POWER RATING
TA = 85C
POWER RATING
TA = 125C
POWER RATING
D (8 pin)
680 mW
5.8 mW/C
33C
465 mW
378 mW
N/A
D (14 pin)
680 mW
7.6 mW/C
60C
604 mW
490 mW
N/A
FK
680 mW
11.0 mW/C
88C
680 mW
680 mW
273 mW
680 mW
11.0 mW/C
88C
680 mW
680 mW
273 mW
JG
680 mW
8.4 mW/C
69C
672 mW
546 mW
210 mW
680 mW
9.2 mW/C
76C
680 mW
597 mW
N/A
680 mW
8.0 mW/C
65C
640 mW
520 mW
N/A
PW (8 pin)
525 mW
4.2 mW/C
70C
525 mW
N/A
N/A
PW (14 pin)
700 mW
5.6 mW/C
70C
700 mW
N/A
N/A
680 mW
8.0 mW/C
65C
640 mW
520 mW
200 mW
DALLAS, TEXAS 75265
electrical characteristics, VCC = 15 V (unless otherwise noted)

PARAMETER
TEST CONDITIONS
TL071C
TL072C
TL074C
TA
MIN
VIO
Input offset voltage
VO = 0
0,
RS = 50
VIO
Temperature
coefficient of input
offset voltage
VO = 0,
RS = 50
IIO
Input offset current
VO = 0
Input bias current
VICR
Common-mode
Common
mode
in
ut voltage range
input
VOM
Maximum peak
eak
output voltage
swing
TYP
MAX
10
Full range
Full range
18
25C
100
65
200
Full range
RL 10 k
MIN
TYP
MAX
7.5
MIN
100
65
200
MAX
6
8
18
100
65
200
100
pA
nA
65
200
pA
20
nA
11
12
12
to
15
11
12
12
to
15
11
12
12
to
15
11
12
12
to
15
25C
12
13.5
12
13.5
12
13.5
12
13.5
12
12
12
12
10
10
10
10
mV
V/C
18
UNIT
TYP
18
TL071I
TL072I
TL074I
25C
Full range
RL 2 k
MAX
10
25C
RL = 10 k
TYP
13
Full range
VO = 0
MIN
TL071BC
TL072BC
TL074BC
Large-signal
differential voltage
amplification
B1
Unity-gain
bandwidth
25C
ri
Input resistance
25C
1012
1012
1012
1012
CMRR
Common-mode
rejection ratio
VIC = VICRmin,
RS = 50
VO = 0,
25C
70
100
75
100
75
100
75
100
dB
kSVR
Supply-voltage
rejection ratio
(VCC /VIO)
VCC = 9 V to 15 V,
VO = 0,
RS = 50
25C
70
100
80
100
80
100
80
100
dB
ICC
Supply
y current
(each amplifier)
VO = 0
0,
25C
14
1.4
VO1/ VO2
Crosstalk
attenuation
AVD = 100
25C
120
VO = 10 V
V,
RL 2 k
No load
25C
25
Full range
15
200
50
200
50
200
50
200
V/mV
25
25
2.5
25
14
1.4
120
25
2.5
25
14
1.4
120
25
2.5
14
1.4
120
MHz
25
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified.
Full range is TA = 0C to 70C for TL07_C,TL07_AC, TL07_BC and is TA = 40C to 85C for TL07_I.
Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 4. Pulse techniques must be used
that maintain the junction temperature as close to the ambient temperature as possible.
AVD
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
IIB
25C
TL071AC
TL072AC
TL074AC
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
electrical characteristics, VCC = 15 V (unless otherwise noted)

PARAMETER
TEST CONDITIONS
TL071M
TL072M
TA
MIN
VIO
Input offset voltage
VO = 0
0,
RS = 50
VIO
Temperature coefficient of
input offset voltage
VO = 0,
RS = 50
IIO
Input offset current
VO = 0
IIB
Input bias current
VICR
Common-mode input
voltage range
VOM
Maximum
M
i
peakk output
t t
voltage swing
25C
TYP
MAX
Full range
MIN
TYP
3
Full range
18
25C
100
65
200
Full range
RL 10 k
pA
20
nA
65
200
pA
50
nA
12
to
15
11
12
to
15
25C
12
13.5
12
13.5
25C
12
10
10
35
V/C
100
11
12
200
35
mV
25C
Full range
RL 2 k
18
50
RL = 10 k
UNIT
MAX
15
20
25C
VO = 0
TL074M
V
200
AVD
Large-signal
g
g
differential
voltage amplification
VO = 10 V
V,
B1
Unity-gain bandwidth
TA = 25C
1012
1012
RL 2 k
15
V/mV
15
MHz
ri
Input resistance
TA = 25C
CMRR
Common-mode rejection
ratio
VIC = VICRmin,
VO = 0,
RS = 50
25C
80
86
80
86
dB
kSVR
Supply-voltage rejection
ratio (VCC /VIO)
VCC = 9 V to 15 V,
RS = 50
VO = 0,
25C
80
86
80
86
dB
ICC
Supply current (each

amplifier)
VO = 0,
25C
No load
1.4
2.5
1.4
2.5
mA
VO1/ VO2 Crosstalk attenuation

AVD = 100
25C
120
120
dB
Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in
Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Full range is
TA = 55C to 125C.
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
operating characteristics, VCC = 15 V, TA = 25C

PARAMETER
TL07xM
TEST CONDITIONS
SR
Slew rate at unity gain
VI = 10 V,
CL = 100 pF,
RL = 2 k,
See Figure 1
tr
Rise time overshoot

factor
VI = 20 mV,,
CL = 100 pF,
RL = 2 k,,
See Figure 1
Vn
Equivalent
q
input noise
voltage
RS = 20
In
Equivalent input noise

current
RS = 20 ,
f = 1 kHz
THD
Total harmonic
distortion
VIrms = 6 V,
RL 2 k,
f = 1 kHz
AVD = 1,
RS 1 k ,
MIN
TYP
13
ALL OTHERS
MAX
MAX
UNIT
MIN
TYP
13
V/s
s
0.1
0.1
20%
20%
18
18
nV/Hz
0.01
0.01
0.003%
0.003%
f = 1 kHz
f = 10 Hz to 10 kHz
pA/Hz
PARAMETER MEASUREMENT INFORMATION
10 k
VI
+
CL = 100 pF
1 k
VO
RL = 2 k
+
RL
IN
CL = 100 pF
Figure 2. Gain-of-10 Inverting Amplifier
Figure 1. Unity-Gain Amplifier
TL071
OUT
IN +
N2
VI
VO
N1
100 k
1.5 k
VCC
Figure 3. Input Offset Voltage Null Circuit
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
Table of Graphs
FIGURE
IIB
Input bias current
vs Free-air temperature
VOM
Maximum output voltage
vs Frequency
vs Load resistance
vs Supply voltage
5, 6, 7
8
9
10
AVD
Large signal differential voltage amplification

Large-signal
vs Frequency
11
12
Phase shift
vs Frequency
12
Normalized unity-gain bandwidth
13
Normalized phase shift
13
CMRR
Common-mode rejection ratio
14
ICC
Supply current
vs Supply
y voltage
g
15
16
PD
Total power dissipation
17
Normalized slew rate
18
Vn
Equivalent input noise voltage
vs Frequency
19
THD
Total harmonic distortion
vs Frequency
20
Large-signal pulse response
vs Time
21
Output voltage
vs Elapsed time
22
VO
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
INPUT BIAS CURRENT

vs
FREE-AIR TEMPERATURE
100
15
VOM
VOM Maximum Peak Output Voltage V
IIIB
IB Input Bias Current nA
VCC = 15 V
10
0.1
0.01
75
25
25
50
75
100
10
VCC = 10 V
7.5
VCC = 5 V
2.5
125
0
100
1k
TA Free-Air Temperature C

vs
FREQUENCY
VCC = 15 V
10
15
RL = 2 k
TA = 25C
See Figure 2
VCC = 10 V
7.5
5
VCC = 5 V
2.5
0
100
1k
10 k
100 k
f Frequency Hz
1M
10 M

vs
FREQUENCY
1M
10 M
VOM
VOM
12.5
10 k
100 k
f Frequency Hz
Figure 5
Figure 4
15
RL = 10 k
TA = 25C
See Figure 2
12.5
50
VCC = 15 V
12.5
10
VCC = 15 V
RL = 2 k
See Figure 2
TA = 25C
TA = 55C
7.5
TA = 125C
2.5
0
10 k
Figure 6
40 k 100 k
400 k 1 M
f Frequency Hz
4M
10 M
Figure 7
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
vs
LOAD RESISTANCE

vs
15
RL = 10 k
12.5
VOM

VOM
15
RL = 2 k
10
7.5
2.5
VCC = 15 V
See Figure 2
0
75
50
25
25
50
75
100
125
VCC = 15 V
TA = 25C
See Figure 2
12.5
10
7.5
2.5
0
0.1
0.2
0.4
7 10
Figure 9
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs

vs
SUPPLY VOLTAGE
15
VOM
RL Load Resistance k
Figure 8
1000
RL = 10 k
TA = 25C
400
AVD
A
VD Large-Signal Differential
Voltage Amplification V/mV
12.5
10
7.5
0.7 1
2.5
200
100
40
20
10
4
2
0
0
10
12
14
16
1
75
VCC = 15 V
VO = 10 V
RL = 2 k
50
25
25
50
75
100
|VCC | Supply Voltage V
Figure 11
Figure 10
10
DALLAS, TEXAS 75265
125
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE SHIFT
vs
FREQUENCY
VCC = 5 V to 15 V
RL = 2 k
TA = 25C
105
104
Differential
Voltage
Amplification
103
45
Phase Shift
AVD
A
VD Large-Signal Differential
Voltage Amplification
106
90
102
Phase Shift
101
135
1
1
10
100
1k
10 k 100 k
f Frequency Hz
1M
180
10 M
Figure 12
NORMALIZED UNITY-GAIN BANDWIDTH
AND PHASE SHIFT
vs
1.03
Unity-Gain Bandwidth
1.2
1.1
1.01
Phase Shift
0.9
0.8
0.7
75
1.02
0.99
VCC = 15 V
RL = 2 k
f = B1 for Phase Shift
50
25
0
25
50
75
100
Normalized Phase Shift
Normalized Unity-Gain Bandwidth
1.3
0.98
0.97
125
Figure 13
DALLAS, TEXAS 75265
11
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
SUPPLY CURRENT PER AMPLIFIER
vs
SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO

vs
2
VCC = 15 V
RL = 10 k
ICC Supply Current Per Amplifier mA

I CC
CMRR Common-Mode Rejection Ratio dB
89
88
87
86
85
83
75
1.6
1.4
1.2
1
0.8
84
50
25
25
50
75
100
TA = 25C
No Signal
No Load
1.8
0.6
0.4
0.2
0
125
12
14
VCC = 15 V
No Signal
No Load
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
250
VCC = 15 V
No Signal
No Load
225
200
175
TL074
150
125
100
TL072
75
TL071
50
25
50
25
25
50
75
100
125
0
75
50
25
25
50
75
100
Figure 16
Figure 17
12
16
TOTAL POWER DISSIPATION

vs
PD
PD Total Power Dissipation mW
2
ICC Supply Current Per Amplifier mA
I CC
10
Figure 15
SUPPLY CURRENT PER AMPLIFIER

vs
0
75
|VCC | Supply Voltage V
Figure 14
DALLAS, TEXAS 75265
125
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
NORMALIZED SLEW RATE
vs
Vn
V
nV/ Hz
n Equivalent Input Noise Voltage nV/Hz
Normalized Slew Rate V/ s
1.15
VCC = 15 V
RL = 2 k
CL = 100 pF
1.10
1.05
0.95
0.90
0.85
75
EQUIVALENT INPUT NOISE VOLTAGE

vs
FREQUENCY
50
VCC = 15 V
AVD = 10
RS = 20
TA = 25C
40
30
20
10
0
50
25
25
50
75
100
10
125
40 100
Figure 18
VCC = 15 V
AVD = 1
VI(RMS) = 6 V
TA = 25C
0.1
0.04
0.01
0.004
0.001
100
400
1k
4 k 10 k
f Frequency Hz
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VI and VO Input and Output Voltages V
THD Total Harmonic Distortion %
0.4
40 k 100 k
Figure 19
TOTAL HARMONIC DISTORTION

vs
FREQUENCY
1
400 1 k
4 k 10 k
f Frequency Hz
40 k 100 k
VCC = 15 V
RL = 2 k
CL = 100 pF
TA = 25C
4
Output
2
Input
0.5
1
1.5
t Time s
2.5
3.5
Figure 21
Figure 20
DALLAS, TEXAS 75265
13
TL071, TL071A, TL071B, TL072

TL072A, TL072B, TL074, TL074A, TL074B
OUTPUT VOLTAGE
vs
ELAPSED TIME
28
24
VO
V
O Output Voltage mV
Overshoot
20
90%
16
12
8
4
VCC = 15 V
RL = 2 k
TA = 25C
10%
tr
4
0
0.1
0.2 0.3 0.4 0.5

t Elapsed Time s
0.6
Figure 22
14
DALLAS, TEXAS 75265
0.7
Order this document by MC1496/D

BALANCED
MODULATORS/DEMODULATORS
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier). Typical
applications include suppressed carrier and amplitude modulation,
synchronous detection, FM detection, phase detection, and chopper
applications. See Motorola Application Note AN531 for additional design
information.
Excellent Carrier Suppression 65 dB typ @ 0.5 MHz
Excellent Carrier Suppression 50 dB typ @ 10 MHz
Adjustable Gain and Signal Handling
SEMICONDUCTOR
TECHNICAL DATA
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO14)
14
Balanced Inputs and Outputs
High Common Mode Rejection 85 dB typical

P SUFFIX
PLASTIC PACKAGE
CASE 646
This device contains 8 active transistors.
14
1
PIN CONNECTIONS
Figure 1. Suppressed
Carrier Output
Waveform
Signal Input 1
14 VEE
Gain Adjust 2
13 N/C
Gain Adjust 3
12 Output
Signal Input 4
11 N/C
10 Carrier Input
Bias 5
IC = 500 kHz, IS = 1.0 kHz
9 N/C
Output 6
8 Input Carrier
N/C 7
0
Log Scale Id
IC = 500 kHz
IS = 1.0 kHz
20
ORDERING INFORMATION
Figure 2. Suppressed
Carrier Spectrum
Device
60
TA = 0C to +70C
Plastic DIP
MC1496BP TA = 40C to +125C

499 kHz
500 kHz
Package
SO14
MC1496D
MC1496P
40
Operating
Temperature Range
Plastic DIP
501 kHz
Figure 4. AmplitudeModulation Spectrum

10
IC = 500 kHz
IS = 1.0 kHz
Linear Scale
8.0
6.0
Figure 3. Amplitude
Modulation Output
Waveform
4.0
2.0
IC = 500 kHz
IS = 1.0 kHz
0
499 kHz
Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
500 kHz
501 kHz
Rev 4
MC1496, B
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating
Symbol
Value
Unit
Applied Voltage
(V6 V8, V10 V1, V12 V8, V12 V10, V8 V4,
V8 V1, V10 V4, V6 V10, V2 V5, V3 V5)
30
Vdc
Differential Input Signal
V8 V10
V4 V1
+5.0
(5 + I5Re)
Vdc
Maximum Bias Current
I5
10
mA
RJA
100
C/W
TA
0 to +70
Tstg
65 to +150
Thermal Resistance, JunctiontoAir

Plastic Dual InLine Package
Operating Temperature Range
Storage Temperature Range
NOTE:
ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = 8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh,
all input and output characteristics are singleended, unless otherwise noted.)
Characteristic
Carrier Feedthrough
VC = 60 mVrms sine wave and
offset adjusted to zero
VC = 300 mVpp square wave:
offset adjusted to zero
offset not adjusted
Fig.
Note
Symbol
VCFT
fC = 1.0 kHz
fC = 1.0 kHz
0.04
20
0.4
200
mVrms
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc)
10
SingleEnded Input Impedance, Signal Port, f = 5.0 MHz

Parallel Input Resistance
Parallel Input Capacitance
SingleEnded Output Impedance, f = 10 MHz

Parallel Output Resistance
Parallel Output Capacitance
Input Bias Current
bC
Unit
Vrms
40
140
Transadmittance Bandwidth (Magnitude) (RL = 50 )

Carrier Input Port, VC = 60 mVrms sine wave
fS = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, VS = 300 mVrms sine wave
|VC| = 0.5 Vdc
+ I1 )2 I4 ;
Max
bS
Typ
fC = 1.0 kHz
fC = 10 MHz
Carrier Suppression
fS = 10 kHz, 300 mVrms
fC = 500 kHz, 60 mVrms sine wave
fC = 10 MHz, 60 mVrms sine wave
Min
+ I8 )2 I10
VCS
dB
40
65
50
300
80
AVS
2.5
3.5
V/V
rip
cip
200
2.0
k
pF
rop
coo
40
5.0
k
pF
IbS
IbC
12
12
30
30
IioS
IioC
0.7
0.7
7.0
7.0
BW3dB
k
MHz
Input Offset Current

IioS = I1I4; IioC = I8I10
Average Temperature Coefficient of Input Offset Current

(TA = 55C to +125C)
TCIio
2.0
nA/C
Output Offset Current (I6I9)
Ioo
14
80
Average Temperature Coefficient of Output Offset Current

(TA = 55C to +125C)
TCIoo
90
nA/C
CommonMode Input Swing, Signal Port, fS = 1.0 kHz
CMV
5.0
Vpp
CommonMode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc
ACM
85
dB
CommonMode Quiescent Output Voltage (Pin 6 or Pin 9)
10
Vout
8.0
Vpp
Differential Output Voltage Swing Capability
10
Vout
8.0
Vpp
Power Supply Current I6 +I12

Power Supply Current I14
ICC
IEE
2.0
3.0
4.0
5.0
mAdc
DC Power Dissipation
PD
33
mW
MC1496, B
GENERAL OPERATING INFORMATION
Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signal
voltage = 0).
Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).
Carrier Suppression
Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.
Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
Carrier feedthrough is independent of signal level, VS.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signalinput transistor pair or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit on
inputsignal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.
At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
Signal gain (singleended) at low frequencies is defined
as the voltage gain,
R
Vo
26 mV
L
A
where r e
VS
V
R e 2r e
I5(mA)
S
+ + )
A constant dc potential is applied to the carrier input terminals

to fully switch two of the upper transistors on and two
transistors off (VC = 0.5 Vdc). This in effect forms a cascode
differential amplifier.
Linear operation requires that the signal input be below a
critical value determined by RE and the bias current I5.
VS
p I5 RE (Volts peak)
Note that in the test circuit of Figure 10, VS corresponds to a

maximum value of 1.0 V peak.
switching devices. This swing is variable depending on the

particular circuit and biasing conditions chosen.
Power Dissipation
Power dissipation, PD, within the integrated circuit package
should be calculated as the summation of the voltagecurrent
products at each port, i.e. assuming V12 = V6, I5 = I6 = I12
and ignoring base current, PD = 2 I5 (V6 V14) + I5)
V5 V14 where subscripts refer to pin numbers.
Design Equations
The following is a partial list of design equations needed to
operate the circuit with other supply voltages and input
conditions.
A. Operating Current
The internal bias currents are set by the conditions at Pin 5.
Assume:
I5 = I6 = I12,
IB
IC for all transistors
then :
where: R5 is the resistor between
V
R5
500
where: Pin 5 and ground
I5
where: = 0.75 at TA = +25C
The MC1496 has been characterized for the condition
I5 = 1.0 mA and is the generally recommended value.
B. CommonMode Quiescent Output Voltage
tt
+ **f *
V6 = V12 = V+ I5 RL
Biasing
The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collectorbase bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
30 Vdc
[(V6, V12) (V8, V10)]
2 Vdc
30 Vdc
[(V8, V10) (V1, V4)]
2.7 Vdc
30 Vdc
[(V1, V4) (V5)]
2.7 Vdc
w
w
w
w
w
The foregoing conditions are based on the following

approximations:
V6 = V12, V8 = V10, V1 = V4
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
g21C +
i o (each sideband)
v s (signal)
Vo + 0
Signal transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:
g21S + vos (signal) Vc + 0.5 Vdc,

i
(signal)
Vo
+0
Common Mode Swing

The commonmode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
MC1496, B
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or singleended. Figure 11 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
singleended output connection.
Negative Supply
VEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internal
current sources.
Signal Port Stability

Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the sourcetuned
circuits that cause the oscillation.
Signal Input
(Pins 1 and 4)
510
10 pF
An alternate method for lowfrequency applications is to

insert a 1.0 k resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation of
carrier suppression.
TEST CIRCUITS
Figure 5. Carrier Rejection and Suppression
1.0 k
1.0 k
Re
51
C2
Carrier
Input 0.1 F
VC
VS
Modulating
Signal Input
10 k
C1
0.1 F
10 k 51
8
10
1
4
1.0 k
RL
3.9 k
6
12
14
50 k
I10
V
Re = 1.0 k
+ Vo
Zin
I5
NOTE:
1.0 k
MC1496
12
I10
8.0 Vdc
VEE
1.0 k
5
6.8 k
I9
2.0 k
Carrier
Input 0.1 F
VC
VS
Modulating
Signal Input
10 k
VCC
12 Vdc
1.0 k
0.1 F
51
I6
14
Shielding of input and output leads may be needed

to properly perform these tests.
Figure 8. Transconductance Bandwidth
Re = 1.0 k
8
10
1
4
8.0 Vdc
VCC
12 Vdc
I7
I8
I1
I4
12
14
Vo
6.8 k
+ Vo
Zout
Vo
MC1496
6.8 k
8.0 Vdc
VEE
Figure 7. Bias and Offset Currents
1.0 k
0.5 V
8
+ 10
1
4
RL
3.9 k
I9 I6
R1
Carrier Null
MC1496
51
Figure 6. InputOutput Impedance
VCC
12 Vdc
8
10
1
4
10 k
51
51
Re
1.0 k
2.0 k
3
50 50
6
MC1496
12
14
50 k
0.01
F
+ Vo
Vo
5
6.8 k
Carrier Null
V
8.0 Vdc
VEE
MC1496, B
Figure 9. Common Mode Gain
Figure 10. Signal Gain and Output Swing
VCC
12 Vdc
Re = 1.0 k
1.0 k
VS
14
Re = 1.0 k
1.0 k
3.9 k
3.9 k
3
0.5 V 8 2
+ 10
1
MC1496 6
4
12
1.0 k
VCC
12 Vdc
1.0 k
+ Vo
VS
Vo
0.5 V
8
+ 10
1
4
50
8.0 Vdc
VEE
CM
3.9 k
+ Vo
12
V
20 log o
V
S
3.9 k
MC1496
6.8 k
50
14
I5 =
1.0 mA
6.8 k
Vo
8.0 Vdc
VEE
Figure 11. Sideband Output versus

Carrier Levels
Figure 12. SignalPort ParallelEquivalent

Input Resistance versus Frequency
1.0 M
2.0
rip, PARALLEL INPUT RESISTANCE (k )
1.6
Signal Input = 600 mV
1.2
400 mV
0.8
300 mV
200 mV
0.4
100 mV
0
0
50
100
150
VC, CARRIER LEVEL (mVrms)
200
500
+rip
50
10
5.0
1.0
1.0
5.0
4.0
3.0
2.0
1.0
2.0
5.0
20
10
f, FREQUENCY (MHz)
50
5.0
10
f, FREQUENCY (MHz)
50
100
Figure 14. SingleEnded Output Impedance

versus Frequency
100
rop , PARALLEL OUTPUT RESISTANCE (k )
cip , PARALLEL INPUT CAPACITANCE (pF)
Figure 13. SignalPort ParallelEquivalent

Input Capacitance versus Frequency
0
1.0
rip
100
140
14
120
12
100
10
rop
80
60
cop
8.0
6.0
40
4.0
20
2.0
0
0
1.0
10
f, FREQUENCY (MHz)
0
100
cop, PARALLEL OUTPUT CAPACITANCE (pF)
VO , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms)
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25C, unless otherwise noted.
MC1496, B
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25C, unless otherwise noted.
Figure 15. Sideband and Signal Port

Transadmittances versus Frequency
0
1.0
0.9
Signal Port
VCS, CARRIER SUPPRESION (dB)
21, TRANSADMITTANCE (mmho)
Figure 16. Carrier Suppression

versus Temperature
0.8
0.7
0.6
Side Band
Sideband Transadmittance
I out (Each Sideband)
g21
V out
V (Signal)
in
0.5
0.4
0.3
0.2
g21
0.1
0
0.1
Signal Port Transadmittance

I out
V out
0 |V |
0.5 Vdc
C
V
in
1.0
10
100
fC, CARRIER FREQUENCY (MHz)
10
20
MC1496
30
(70C)
40
50
60
70
75
1000
50
25
RL = 3.9 k (Standard
Re = 1.0 k Test Circuit)
10
RL = 3.9 k
Re = 2.0 k
RL = 500
Re = 1.0 k
|VC| = 0.5 Vdc

20
+ Re ) 2re
R
A
30
0.01
0.1
1.0
f, FREQUENCY (MHz)
10
100
SUPPRESSION BELOW EACH FUNDAMENTAL

CARRIER SIDEBAND (dB)
AVS , SINGLE-ENDED VOLTAGE GAIN (dB)
RL = 3.9 k
Re = 500
10
0
0
10
20
40
50
fC
60
70
0.05
0.1
50

VCFT , CARRIER OUTPUT VOLTAGE (mVrms)
1.0
0.5 1.0
5.0
10
3fC
0.1
0.5 1.0
5.0 10
50
Figure 20. Sideband Harmonic Suppression

versus Input Signal Level
10
0.1
2fC
30
Figure 19. Carrier Feedthrough

versus Frequency
0.01
0.05
150 175
Figure 18. Carrier Suppression

versus Frequency
Figure 17. SignalPort Frequency Response

20
0
25
50
75 100 125
TA, AMBIENT TEMPERATURE
(C)
0
10
20
30
40
fC 3fS
50
fC 2fS
60
70
80
200
400
600
VS, INPUT SIGNAL AMPLITUDE (mVrms)
800
MC1496, B
Figure 22. Carrier Suppression versus
Carrier Input Level
0
0
V CS , CARRIER SUPPRESSION (dB)

Figure 21. Suppression of Carrier Harmonic

Sidebands versus Carrier Frequency
10
3fC fS
20
30
40
2fC fS
50
2fC 2fS
60
70
0.05
0.1
0.5 1.0
5.0
10
50
10
20
30
fC = 10 MHz
40
fC = 500 kHz
50
60
70
100
200
300
400
VC, CARRIER INPUT LEVEL (mVrms)
500
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is
shown in Figure 23.
This circuit consists of an upper quad differential amplifier
driven by a standard differential amplifier with dual current
sources. The output collectors are crosscoupled so that
fullwave balanced multiplication of the two input voltages
occurs. That is, the output signal is a constant times the
product of the two input signals.
Mathematical analysis of linear ac signal multiplication
indicates that the output spectrum will consist of only the sum
and difference of the two input frequencies. Thus, the device
may be used as a balanced modulator, doubly balanced mixer,
product detector, frequency doubler, and other applications
requiring these particular output signal characteristics.
The lower differential amplifier has its emitters connected
to the package pins so that an external emitter resistance
may be used. Also, external load resistors are employed at
the device output.
Signal Levels
The upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differential
amplifier is operated in a linear mode for most applications.
For lowlevel operation at both input ports, the output
signal will contain sum and difference frequency components
and have an amplitude which is a function of the product of

the input signal amplitudes.
For highlevel operation at the carrier input port and linear
operation at the modulating signal port, the output signal will
contain sum and difference frequency components of the
modulating signal frequency and the fundamental and odd
harmonics of the carrier frequency. The output amplitude will
be a constant times the modulating signal amplitude. Any
amplitude variations in the carrier signal will not appear in the
output.
The linear signal handling capabilities of a differential
amplifier are well defined. With no emitter degeneration, the
maximum input voltage for linear operation is approximately
25 mV peak. Since the upper differential amplifier has its
emitters internally connected, this voltage applies to the
carrier input port for all conditions.
Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
linear operation may be approximated from the following
expression:
V = (I5) (RE) volts peak.
This expression may be used to compute the minimum
value of RE for a given input voltage amplitude.
Figure 23. Circuit Schematic
Figure 24. Typical Modulator Circuit

() 12
(+) 6
Vo,
Output
0.1 F
4 ()
Signal V
S 1 (+)
Input
2
3
Gain
Adjust
Bias 5
500
500
VEE 14
(Pin numbers
per G package)
V 0.1 F
Carrier C
Input
VS
Modulating
Signal 10 k
Input
12 Vdc
1.0 k
51
10 ()
Carrier V
C
Input
8 (+)
500
1.0 k
8
10
1
4
10 k
51
51
Re 1.0 k
RL
3.9 k
6
RL
3.9 k
+Vo
MC1496
12
14
Vo
50 k
I5
Carrier Null
6.8 k
8.0 Vdc
VEE
MC1496, B
Figure 25. Voltage Gain and Output Frequencies
Carrier Input Signal (VC)
Approximate Voltage Gain

R
Lowlevel dc
2(R
) 2re)
E
R
Highlevel dc
Lowlevel ac
KT
q
) 2re
L
Output Signal Frequency(s)
fM
fM
2 2
V (rms)
L C
KT (R
2r e)
q
E
0.637 R
Highlevel ac
) 2re
L
fC fM
fC fM, 3fC fM, 5fC fM, . . .
NOTES: 1. Lowlevel Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.
2. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude of
each of the two desired outputs, fC + fM and fC fM.
3. All gain expressions are for a singleended output. For a differential output connection, multiply each
expression by two.
4. RL = Load resistance.
5. RE = Emitter resistance between Pins 2 and 3.
6. re = Transistor dynamic emitter resistance, at 25C;
26 mV
re
I5 (mA)
7. K = Boltzmanns Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
KT
26 mV at room temperature
q
The gain from the modulating signal input port to the

output is the MC1496 gain parameter which is most often of
interest to the designer. This gain has significance only when
the lower differential amplifier is operated in a linear mode,
but this includes most applications of the device.
As previously mentioned, the upper quad differential
amplifier may be operated either in a linear or a saturated
mode. Approximate gain expressions have been developed
for the MC1496 for a lowlevel modulating signal input and
the following carrier input conditions:
1) Lowlevel dc
2) Highlevel dc
3) Lowlevel ac
4) Highlevel ac
These gains are summarized in Figure 25, along with the
frequency components contained in the output signal.
APPLICATIONS INFORMATION
Double sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1496 with a single dc supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed
for operation with a single 12 Vdc supply. Performance of this
circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 27 may be used as an
amplitude modulator with a minor modification.
All that is required to shift from suppressed carrier to AM

operation is to adjust the carrier null potentiometer for the
proper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range.
Therefore, the modulator may be modified for AM operation
by changing two resistor values in the null circuit as shown in
Figure 28.
Product Detector
The MC1496 makes an excellent SSB product detector
(see Figure 29).
This product detector has a sensitivity of 3.0 microvolts
and a dynamic range of 90 dB when operating at an
intermediate frequency of 9.0 MHz.
The detector is broadband for the entire high frequency
range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1 F capacitors on Pins 8 and 10
should be increased to 1.0 F. Also, the output filter at Pin 12
can be tailored to a specific intermediate frequency and audio
amplifier input impedance.
As in all applications of the MC1496, the emitter resistance
between Pins 2 and 3 may be increased or decreased to
adjust circuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector by
introducing carrier signal at the carrier input and an AM signal
at the SSB input.
The carrier signal may be derived from the intermediate
frequency signal or generated locally. The carrier signal may
be introduced with or without modulation, provided its level is
sufficiently high to saturate the upper quad differential
MC1496, B
amplifier. If the carrier signal is modulated, a 300 mVrms
input level is recommended.
Doubly Balanced Mixer
The MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and output
networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mVrms.
Figure 30 shows a mixer with a broadband input and a
tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doubler

and a tuned output very high frequency (VHF) doubler,
respectively.
Phase Detection and FM Detection
The MC1496 will function as a phase detector. Highlevel
input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1496 will deliver an output
which is a function of the phase difference between the two
input signals.
An FM detector may be constructed by using the phase
detector principle. A tuned circuit is added at one of the inputs
to cause the two input signals to vary in phase as a function
of frequency. The MC1496 will then provide an output which
is a function of the input signal frequency.
TYPICAL APPLICATIONS
Figure 26. Balanced Modulator
(12 Vdc Single Supply)
1.0 k
25 F
15 V
Carrier Input
60 mVrms
Modulating
820
51
10 k
10 k
8
10
1
4
2 1.0 k
100
3.0 k
3
12
10 k
10 k
50 k
100
51
VC 0.1 F
Carrier
Input
VS
Modulating
Signal 750
Input
750
50 k
RL
0.1 F 2 Re 1.0 k 3 3.9 k
8
6
10
1
MC1496
4
12
51 51 14
5
Carrier Adjust
15 6.8 k
VEE
8.0 Vdc
RL
3 3.9 k
Re 1.0 k
RL
3.9 k
+Vo
12
Vo
MC1496
51 14
5
I5
VEE
8.0 Vdc
6.8 k
Figure 29. Product Detector

(12 Vdc Single Supply)
VCC
12 Vdc
1.0 k
51
R1
Carrier Null
Figure 28. AM Modulator Circuit

1.0 k
0.1 F 2
8
10
1
4
51
VC 0.1 F
Carrier
0.1 F Output Input
VS
Modulating
10 k
Signal
Input
VCC
12 Vdc
1.0 k
DSB
MC1496
1.0 k
3.0 k
25 F 14
15 V
+
Signal Input 10 F
300 mVrms 15 V
Carrier
Null 50 k
VCC
12 Vdc
1.3 k
0.1 F
0.1 F
Figure 27. Balanced ModulatorDemodulator
RL
3.9 k
820
0.1 F
1.0 k
2
51
+Vo Carrier Input

300 mVrms
Vo
VCC
12 Vdc
1.3 k
SSB Input
8
0.1 F
10
1
4
1.0
k
0.1 F
1.0 k
0.1
F
100
3.0 k
0.005
F
AF
1.0 k 1.0 FOutput
MC1496
14
3.0 k
12
10 k
q 10 k
RL
0.005 0.005
F
F
MC1496, B
Figure 30. Doubly Balanced Mixer
(Broadband Inputs, 9.0 MHz Tuned Output)
1.0 k
100 mVrms
2
8
10
0.001 F 1
0.01
F
1.0 k
10 k
10 k
51
50 k
Null Adjust
C2
100
12
5 5.080
pF
6.8 k
14
L1
10 k
100
10 k
100
3.9 k
3.9 k
6
10
100 F
C2+
9.0 MHz Input
15
Vdc
Max
15 mVrms
100 F 15 Vdc 1
Output
RL = 50
4
90480 pF
VEE
8.0 Vdc
1.0 k
0.001 F
9.5 F
MC1496
51
100 F
25 Vdc
+
1.0 k
RFC
100 H
51
RF Input
VCC
12 Vdc
VCC
+8.0 Vdc
1.0 k
0.001 F
Local
Oscillator
Input
Figure 31. LowFrequency Doubler
Output
MC1496
12
14
50 k
6.8 k
I5
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound

on Micrometals Type 446 Toroid Core.
VEE
8.0 Vdc
Balance
Figure 32. 150 to 300 MHz Doubler

1.0 k
100
0.001 F
150 MHz
Input
100
10 k
10 k
50 k
Frequency
fC
Carrier Fundamental
fS
Modulating Signal
fC fS Fundamental Carrier Sidebands
10
VCC
+8.0 Vdc
0.001
18 pF
F
0.001
RFC
F
0.68 H
2
3
6
8
10
1 MC1496
4
12
5
100 14
6.8 k
VEE
8.0 Vdc
L1
18 nH
1.010 pF
1.010 pF
300 MHz
Output
RL = 50
L1 = 1 Turn AWG
No. 18 Wire, 7/32 ID
(3fC + f S )
(3fC + 2f S )
(3f C )
(3fC 2f S )
(3fC fS )
(2fC + 2f S )
(2fC + 2f S )
(2fC 2f S )
(2fC )
(2fC 2f S )
(fC + f S )
(f + 2f )
C
S
(fC )
(fC 2f S )
AMPLITUDE
(fC f S )
Balance
V+
1.0 k
Balanced Modulator Spectrum

DEFINITIONS
fC nfS Fundamental Carrier Sideband Harmonics
nfC
Carrier Harmonics
nfC nfS Carrier Harmonic Sidebands

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ELETRNICA IV

Apostila de Aulas Prticas

Autor: Fernando Antnio Pinto Barqui

AMPLIFICADOR PUSH-PULL COM SADA COMPLEMENTAR

onde Vop a tenso de pico de sada.

Figura 2.1: Amplificador Push-Pull.

Figura 2.2: Amplificador Push-Pull com realimentao.

Figura 2.3: Microfone de eletreto. a) Polarizao. b) Microfone mais amplificador.

Figura 2.4: Amplificador Push-Pull mais microfone de eletreto.

2 - Freqncia da portadora ( eci c = 400kHz ).

4 - Seletividade igual a 10.

Fazer as medidas de Lx em dois valores, o1 e o2, em torno de c, de

3 - Calcule os componentes para atender as especificaes dadas;

Figura 3.1: Amplificador sintonizado.

Figura 3.2: Amplificador sintonizado como mixer.

Figura 4.1: Modulador de amplitude.

Figura 5.1: Modulador balanceado.

Manual da Motorola em anexo.

Design of Analog Integrated Circuits. P. Gray, M. Meyer. John Wiley, Mp.

Figura 6.1: Circuito modulador de freqncia.

OBS: Na modulao FM temos:

O circuito da Figura 7.1 um conversor BOOST operando no modo descontnuo. Dimensione RS e CS

VD + VCC , onde VT e VD so as tenses de conduo do transistor e

( VCC VT )1T , onde

IS a corrente DC na carga RS, e T o perodo de chaveamento.

Corrente mxima acumulada no indutor L, I max =

Capacitor em funo da mxima variao de tenso na sada, CS

Figura 7.1: Conversor BOOST.

Figura 7.2: Fonte de excitao dos conversores BOOST e BUCK-BOOST.

O circuito da Figura 7.3 um conversor BUCK-BOOST operando no modo descontnuo. Dimensione

+ VD , onde VT e VD so as tenses de conduo do transistor e

Corrente mxima acumulada no indutor L, I max =

Capacitor em funo da mxima variao de tenso na sada, CS

Figura 7.3: Conversor Buck-Boost.

Figura 7.4: Conversor BUCK.

Figura 7.5: Fonte de excitao do conversor BUCK.

Hermetically sealed leaded glass

High switching speed: max. 4 ns

Repetitive peak forward current:

The diodes are type branded.

Fig.1 Simplified outline (SOD27; DO-35) and symbol.

repetitive peak reverse voltage

continuous reverse voltage

continuous forward current

repetitive peak forward current

non-repetitive peak forward current

see Fig.2; note 1

total power dissipation

VR = 20 V; Tj = 150 C; see Fig.5

reverse current; 1N4448

VR = 20 V; Tj = 100 C; see Fig.5

f = 1 MHz; VR = 0; see Fig.6

reverse recovery time

when switched from IF = 10 mA to

forward recovery voltage

when switched from IF = 50 mA;

thermal resistance from junction to tie-point

thermal resistance from junction to ambient

lead length 10 mm; note 1

(1) Tj = 175 C; typical values.

Device mounted on an FR4 printed-circuit board; lead length 10 mm.

Maximum permissible continuous forward

Forward current as a function of forward