ECE-E434

Digital Electronics

Lecture # 5&6: CMOS Inverters

Instructor: Pouya Dianat
Oct 10 & 12 2017
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Announcements
•  HW#2 is due on Friday, Oct 14 2017.
–  Hand your HW to your TA during the lab sessions.
•  HW#3 is due on Friday, Oct 21 2017.
–  Hand your HW to your TA during the lab sessions.
•  Examples 14.6 and 14.7 for the next quiz
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

InteresUng problems for midterm

10/9/17 3
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Single Time Constant (STC) Circuit

Self-Study Appendix E
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Single Time Constant (STC) Circuit

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Speed of OperaUon in CMOS Inverter

PropagaUon delay: What is it?
Propaga@on Delay, tP

Minimum period for each cycle, Tmin

Maximum switching frequency, fmax

Figure 14.27 An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated.
10/9/17 6
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Speed of OperaUon in CMOS Inverter

PropagaUon delay: Where does it come from?

•  What is R?
•  What is C?
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Finding Equivalent Load Capacitance

Figure 14.32 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter
formed by Q3 and Q4.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Sources of Capacitance
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Miller Effect: Feedback Capacitance

Figure 14.33 The Miller multiplication of the feedback capacitance Cgd1.

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Equivalent Capacitance
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Finding Equivalent Resistance

Figure 14.30 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent
circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Important Design Notes

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

An equivalent approach/approxima@on
Empirically found values:

DerivaUon:

Figure 14.31 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Transistor Sizing in CMOS Inverters and Logic Gates

Ques@on: What is an appropriate W/L ra@o?

The Case of the BASIC INVERTER:

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Transistor Sizing in CMOS Inverters and Logic Gates

Ques@on: What happens in the inverter if (W/L) is scale by a factor S?

Pro: Scaling may be used to reduce the effect of external capacitance from interconnects.
Con: The area on the silicon will increase.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Transistor Sizing in CMOS Inverters and Logic Gates

For a BASIC INVERTER: