Dell Inspiron 14 2420 3420 Schematics

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Enrico Caruso 14
D
Muxless Schematics Document D
Ivy Bridge & Sandy Bridge

Intel PCH
2012-01-03
C C
REV : X02
DY : None Installed
PSL: 10mW internal schematic
UMA: UMA ONLY installed
B
OPS: Optimus solution installed. B
Surge: For GO Rural config stuff.

GIGA: For GIGA LAN config stuff.
LPC : Reserve for LPC debug card
POP : Reserve for solve "POP" sound iuuse
A <Variant Name> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
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##OnMainBoard Block Diagram SYSTEM DC/DC

INPUTS
APL5916
OUTPUTS
48
CPU DC/DC
VT1318+1323
INPUTS OUTPUTS
42~44
Hynix:72.52G63.A0U (HT31P$AA) VRAM gDDR3 900MHz

(Discrete) Project code:
Inspiron:91.4TY01.001
DCBATOUT 0D85V_S0 DCBATOUT
SYSTEM DC/DC
VCC_CORE
TPS51219 45
Samsung:72.42164.D0U (JP0F2$AA) 1GB (128Mx16x4)
D 4 Vostro :91.4UA01.001 INPUTS OUTPUTS D
88,89,90,91 DCBATOUT 1D05V_VTT
PCB P/N :48.4TY02.0SC SYSTEM DC/DC
gDDR3
900MHz Intel CPU Revision:11282-SC TPS51125 41
INPUTS OUTPUTS
DDRIII 1333/1600 Channel A 5V_AUX_S5
DDRIII Slot 0 3D3V_AUX_S5
Ivy Bridge & Sandy Bridge 15 DCBATOUT 5V_S5
1333/1600 3D3V_S5
PCIe x 8 15V_S5
N13M-GS DDRIII 1333/1600 Channel B
(Discrete only) DDRIII Slot 1 SYSTEM DC/DC
14
1333/1600 TPS51216R 46
Xtal=27MHz 83.84,85,86,87 INPUTS OUTPUTS

10/100 /1000 LOM 1D5V_S3
4,5,6,7,8,9,10 DCBATOUT 0D75V_S0
Realtek RTL8111F (Giga LAN) RJ45 DDR_VREF_S3
PCIE x 1
Realtek RTL8105E-VD (10M/100M) CONN 59 GFX DC/DC
Xtal=25MHz 31 44
FDIx4x2 DMIx4 VT1318+1323
C 802.11a/b/g C
INPUTS OUTPUTS
PCIE x 1 Mini-Card DCBATOUT VCC_GFXCORE
WLAN+BT3.064
PCIE VGA
CRT CRT ADP3211 92
50
Intel 100MHz
INPUTS OUTPUTS
PCH 2.5Gbps USB 2.0 x 1 DCBATOUT VGA_CORE
LCD LVDS
49 Panther Point TI CHARGER
BQ24707 40
BGA989
HDMI HDMI USB 2.0 USB 2.0 x 1 CAMERA INPUTS OUTPUTS
51 49 +DC_IN_S5
480Mbps +PBATT DCBATOUT
HM75
CardReader SYSTEM DC/DC
SD/MMC/MS/ 12 USB 2.0/1.1 ports M/B
USB2.0 USB 2.0 x 1 RT8068A 47
MS Pro 74 Realtek High Definition Audio USB x1 (Left) 61
32 INPUTS OUTPUTS
RTS5138 6 SATA ports
LPC Bus
B 8 PCIE ports 3D3V_S5 1D8V_S0 B
33MHz USB 2.0 x 2 I/O board
LPC I/F
Audio board Azalia AZALIA ACPI 4.0a
USB x2 (Right) 82
Switches 93
CODEC 24MHz KBC INPUTS OUTPUTS

Internal Analog MIC 17,18,19,20,21,22,23,24,25
58 1D5V_S3 1D5V_S0
Cirrus CS4213D NUVOTON
D/A 5V_S5 5V_S0
29 NPCE885P 27
Thermal 3D3V_S5 3D3V_S0
NCT7718W
HP1 28
82
PS/2 PS/2
SPI
SATA
3Gbps
Thermal
SATA
MIC IN Fan Control G709

Touch Int.
G991P
28
28 PCB LAYER
PAD KB L1:Top L4:Signal
2CH SPEAKER 69 69
L2:GND L5:VCC
Flash ROM L3:Signal L6:Bottom
58
A HDD ODD <Variant Name> A
56 56 8MB 60
Wistron Corporation
Title
Block Diagram
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PCH Strapping Chief River Schematic Checklist Revision 1.5
Name Schematics Notes Power Plane

Processor Strapping Chief River Schematic Checklist Revision 1.5
The signal has a weak internal pull-down. Configuration (Default value for each bit is Default Voltage Rails
Pin Name Strap Description POWER PLANE VOLTAGE DESCRIPTION
Note: the internal pull-down is disabled after PLTRST# deasserts. 1 unless specified otherwise) Value ACTIVE IN
SPKR
If the signal is sampled high, this indicates that the system is strapped to the 5V_S0 5V
¨No Reboot〃 mode (Panther Point will disable the TCO Timer system reboot 3D3V_S0 3.3V
CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0] 1D8V_S0 1.8V
feature). 1D5V_S0 1.5V
trace in a manner which does not introduce any stubs to 1D05V_VTT 1.05V
This signal has a weak internal pull-up.
INIT3_3V# CFG[0] trace. Route as needed from the opposite side of 0D85V_S0 0.95 - 0.85V
Note: The internal pull-up is disabled after PLTRST# deasserts. 0D75V_S0 0.75V
this series isolation resistor to the debug port. ITP
NOTE: This signal should not be pulled low. Leave as "No Connect".
4 INTVRMEN Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high
will drive the net to GND.
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
0.35V to 1.5V
0.4 to 1.25V
1.8V
S0
CPU Core Rail

4
CFG[2] PCIe Static x16 Lane 1: Normal Operation; Lane # definition 3D3V_VGA_S0 3.3V Graphics Core Rail
NOTE: This signal should always be pulled high 1V_VGA_S0 1V
Numbering Reversal. matches socket pin map definition 1
External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low.
NOTE: This signal should be pulled down to GND through 330 kOhms resistor 0:Lane Reversed
5V_USBX_S3 5V
1:Disabled - No Physical Display Port attached to 1D5V_S3 1.5V S3
CFG[4] Display Port Presence DDR_VREF_S3 0.75V
Embedded DisplayPort No connect for disable
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. strap 0:Enabled - An external Display Port device is connected 1
GNT2#/GPIO53 Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they BT+ 6V-14.1V AC Brick Mode only
to the Embedded Display Port Pull-down to GND through a
GNT1#/GPIO51 should be tied to the Vcc3_3 power rail. DCBATOUT 6V-14.1V
1K ∮ 5% resistor to enable port 5V_S5 5V All S states
5V_AUX_S5 5V
This signal is a strap for selecting DMI and FDI termination voltage. 3D3V_S5 3.3V
PCIE Port Bifurcation 00 = 1 x 8, 2 x 4 PCI Express 3D3V_AUX_S5 3.3V
For Ivy Bridge processor only implementation:
CFG[6:5] Straps 01 = reserved
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ∮5% resistor. 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
For future processor compatibility: 10 = 2 x 8 PCI Express 1
It needs to be connected to PROC_SELECT through a 11 = 1 x 16 PCI Express
1.0 kOhms ∮5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ∮5% pull-up resistor 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
to
PCH VccDFTERM. Reserved configuration
CFG[17:7] lands. A test point may
Bit11 Bit 10 Boot BIOS Destination Powered by Li Coin Cell in G3
be placed on the board 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
0 1 Reserved
1 0 PCI for these lands.
SATA1GP/ 1 1 SPI
GPIO19 0 0 LPC
NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther
Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor
in order to boot.
NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS
Destination Select to LPC/PCI by functional strap or via Boot BIOS
Destination Bit will not affect SPI accesses initiated by Management
3 Engine or Integrated GbE LAN.
NOTE: PCI Boot BIOS destination is not supported on mobile.
3
Reserved.
SATA2GP/ This signal has a weak internal pull-down.
GPIO36 Sandy Bridge + Ivy Bridge Compatibility Requirements
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled high when strap is sampled.
Chief River Schematic Checklist Revision 1.5
Reserved Pin Name Configuration Schematic Notes
USB Table
SATA3GP/
GPIO37
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts. DDR3 VREF M1 and M3 Guidelines are required.
PCIE Routing Pair Device
NOTE: This signal should not be pulled high when strap is sampled. DDR3 VREF Note: The M3 traces are routed to the Sandy Bridge Processor 0 X
Sandy Bridge + Ivy Bridge
HDA_DOCK_EN# High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking reserved pins. 1 USB Ext. port 1
/GPIO33 isolation logic. This is an active-low-signal. When deasserted the external docking switch is in
LANE1 X
2 X
isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio
dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.
Ivy Bridge No change. LANE2 X
3 X
Signal has a weak internal pull-down. LANE3 Mini Card1(WLAN) 4 X
If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect Connect DF_TVS signal of the PCH to PROC_SELECT# of the
HDA_SDO Sandy Bridge + Ivy Bridge processor through a 1K∮5% series resistor. PROC_SELECT# 5 CARD READER
(default).If sampled high, the Flash Descriptor Security will be overridden. PROC_SELECT#
This strap should only be asserted high via external pull-up in manufacturing/debug environments &
also needs a 2.2K∮5% pull up resistor to PCH VccDFTERM LANE4 x 6 X
ONLY. rail.
DF_TVS 7 X
Note: The weak internal pull-down is disabled after PLTRST# deasserts. Ivy Bridge No change. LANE5 X
Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine 8 USB Ext. port 2
after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode LANE6 Onboard LAN
and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down 9 USB Ext. port 3
The POR for Ivy Bridge mobile parts is now 1.05 V. There is no
resistor. Sandy Bridge + Ivy Bridge 10 X
This signal has a weak internal pull-down. VCCIO VR
longer a requirement for a separate VCCIO VR for Sandy Bridge LANE7 X
+ Ivy Bridge compatibility. 11
On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled Implementation Mini Card1 (WLAN)
HDA_SYNC LANE8 X
low. 12 CAMERA
Needs to be pulled High for Chief River platform. Ivy Bridge No change.
Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is 13 X
2 sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND),
the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to Sandy Bridge + Ivy Bridge VCCSA_SELECT[0:1] which should be connected to 2
isolate this signal from the codec during the strap phase. Refer to the example circuits provided in VCCSA_SEL VID[1:0] of the System Agent (SA) VR controller.
the latest Chief River platform design guide. connection to
TLS Confidentiality VCCSA_VID[1:0]
GPIO15 Low (0)  Intel ME Crypto Transport Layer Security (TLS) cipher suite with no lines Ivy Bridge No change.
confidentiality
High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. Sandy Bridge + Ivy Bridge The total motherboard length for a pair of consecutive PCI
SATA Table
NOTE: A strong pull-up may be needed for GPIO functionality Layout Requirement Express Tx lanes be length matched within 100 mils (2.54 mm)
on PCI Express SATA
LVDS Detected.
Gen3 Ivy Bridge No change. Pair Device
When '1'- LVDS is detected; When '0'- LVDS is not detected.
L_DDC_DATA
NOTE:The internal pull-down is disabled after PLTRST# deasserts. 0 HDD1
GT Core VR Sandy Bridge + Ivy Bridge Depending on the PDDG specifications, some IVB GT2 SKUs may
Implementation require a new VR controller and 2 phase VCC GT core VR. 1 X
Port B Detected
When '1'- Port B is detected; When '0'- Port B is not detected 2 X
SDVO_CTRLDATA Ivy Bridge No change.
This signal has a weak internal pull-down. 3 X
NOTE:The internal pull-down is disabled after PLTRST# deasserts.
Processor PCI Sandy Bridge + Ivy Bridge To support Gen 3 PCI Express Graphic, the value of the AC 4 ODD1
Port C Detected. Express (PCIe Gen3): coupling capacitor should be 180 - 265 nF.
When '1'- Port C is detected; When '0'- Port C is not detected Graphics 5 X
DDPC_CTRLDATA
This signal has a weak internal pull-down. Guidelines Ivy Bridge No change.
Port D Detected.
When '1'- Port D is detected; When '0'- Port D is not detected
DDPD_CTRLDATA
The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL
1 GPIO28 Voltage Regulator is disabled.If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap
1
setting when use as the chipset test interface.Refer to the latest platform debug design guide and
platform design guide for more details.
NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# <Variant Name>
deasserts.
Wistron Corporation
GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). Taipei Hsien 221, Taiwan, R.O.C.
GPIO29/
If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. Title
SLP_LAN#
A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default,
the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable Table of Content
vinafix
GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can A2
Enrico Caruso 14 MLK DIS
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Date: Friday, December 30, 2011 Sheet 3 of 104
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Layout Note:
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
IVY-BRIDGE PEG_ICOMPI
19 DMI_TXN[3:0] PEG_ICOMPO J21
DMI_TXN0 B27 H22
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
B25 DMI_RX#1
DMI_TXN2 A25
DMI_TXN3 DMI_RX#2
B24 DMI_RX#3 PEG_RX#0 K33
19 DMI_TXP[3:0] PEG_RX#1 M35
DMI_TXP0 B28 L34
DMI_TXP1 DMI_RX0 PEG_RX#2
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32
DMI_TXP3 DMI_RX2 PEG_RX#4
B23 DMI_RX3 PEG_RX#5 H34
19 DMI_RXN[3:0] PEG_RX#6 H31
DMI_RXN0 G21 G33
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 DMI_TX#1 PEG_RX#8 G30
DMI_RXN2 F21 F35 PEG_RXN6
DMI_TX#2 PEG_RX#9 83 PEG_RXN[0..7] PEG_TXN[0..7] 83
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31 83 PEG_RXP[0..7] PEG_TXP[0..7] 83
PCI EXPRESS* - GRAPHICS

DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RX0 J33
PEG_RX1 L35
19 FDI_TXN[7:0] PEG_RX2 K34
C FDI_TXN0
FDI_TXN1
A21
H19
FDI0_TX#0 PEG_RX3 H35
H32
C
FDI_TXN2 FDI0_TX#1 PEG_RX4
E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31
Intel(R) FDI
FDI_TXN4 FDI0_TX#3 PEG_RX6
B21 FDI1_TX#0 PEG_RX7 F33
FDI_TXN5 C20 F30 PEG_RXP7 NOTE.
FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
D18 FDI1_TX#2 PEG_RX9 E35 If PEG is not implemented, the RX&TX pairs can be left as No Connect
FDI_TXN7 E17 E33 PEG_RXP5
FDI1_TX#3 PEG_RX10 PEG_RXP4
PEG_RX11 F32
D34 PEG_RXP3 PEG Static Lane Reversal
19 FDI_TXP[7:0] FDI_TXP0 PEG_RX12 PEG_RXP2
A22 FDI0_TX0 PEG_RX13 E31
FDI_TXP1 G19 C33 PEG_RXP1
FDI_TXP2 FDI0_TX1 PEG_RX14 PEG_RXP0
E20 FDI0_TX2 PEG_RX15 B32
FDI_TXP3 G18
FDI_TXP4 FDI0_TX3
B20 FDI1_TX0 PEG_TX#0 M29
FDI_TXP5 C19 M32
FDI_TXP6 FDI1_TX1 PEG_TX#1
D19 FDI1_TX2 PEG_TX#2 M31
FDI_TXP7 F17 L32
FDI1_TX3 PEG_TX#3
PEG_TX#4 L29
FDI_FSYNC0 J18 K31
19 FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 J17 K28
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 J30
FDI_INT H20 J28 PEG_C_TXN7 C409 1OPS 2 SCD22U10V2KX-1GP PEG_TXN7
19 FDI_INT FDI_INT PEG_TX#8
H29 PEG_C_TXN6 C410 1OPS 2 SCD22U10V2KX-1GP PEG_TXN6
FDI_LSYNC0 PEG_TX#9 PEG_C_TXN5 C411 SCD22U10V2KX-1GP PEG_TXN5
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27 1OPS 2
FDI_LSYNC1 H17 E29 PEG_C_TXN4 C412 1OPS 2 SCD22U10V2KX-1GP PEG_TXN4
19 FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
F27 PEG_C_TXN3 C413 1OPS 2 SCD22U10V2KX-1GP PEG_TXN3
PEG_TX#12 PEG_C_TXN2 C414 SCD22U10V2KX-1GP PEG_TXN2
PEG_TX#13 D28 1OPS 2
F26 PEG_C_TXN1 C415 1OPS 2 SCD22U10V2KX-1GP PEG_TXN1
PEG_TX#14 PEG_C_TXN0 C416 SCD22U10V2KX-1GP PEG_TXN0
E25 1OPS 2
B 1D05V_VTT R402 1 2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO
PEG_TX#15 B
A17 EDP_ICOMPO PEG_TX0 M28
R403 1 2 10KR2J-3-GP eDP_HPD B16 M33
EDP_HPD PEG_TX1
M30
DY PEG_TX2
L31
PEG_TX3
C15 EDP_AUX PEG_TX4 L28
D15 K30
Layout Note: EDP_AUX# PEG_TX5
eDP
PEG_TX6 K27
Signal Routing Guideline: PEG_TX7 J29
EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. C17 J27 PEG_C_TXP7 C425 1OPS 2 SCD22U10V2KX-1GP PEG_TXP7
EDP_TX0 PEG_TX8 PEG_C_TXP6 C426 SCD22U10V2KX-1GP PEG_TXP6 PEG_TXP7 83
F16 H28 1OPS 2
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. C16
EDP_TX1 PEG_TX9
G28 PEG_C_TXP5 C427 1OPS 2 SCD22U10V2KX-1GP PEG_TXP5 PEG_TXP6 83
EDP_TX2 PEG_TX10 PEG_C_TXP4 C428 SCD22U10V2KX-1GP PEG_TXP4 PEG_TXP5 83
G15 EDP_TX3 PEG_TX11 E28 1OPS 2 PEG_TXP4 83
F28 PEG_C_TXP3 C429 1OPS 2 SCD22U10V2KX-1GP PEG_TXP3
PEG_TX12 PEG_C_TXP2 C430 SCD22U10V2KX-1GP PEG_TXP2 PEG_TXP3 83
C18 EDP_TX#0 PEG_TX13 D27 1OPS 2 PEG_TXP2 83
E16 E26 PEG_C_TXP1 C431 1OPS 2 SCD22U10V2KX-1GP PEG_TXP1
EDP_TX#1 PEG_TX14 PEG_C_TXP0 C432 SCD22U10V2KX-1GP PEG_TXP0 PEG_TXP1 83
D16 EDP_TX#2 PEG_TX15 D25 1OPS 2 PEG_TXP0 83
F15 EDP_TX#3
62.10055.551
2nd = 22.10252.171
3rd = 62.10040.821
A <Variant Name>
A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
http://www.vinafix.vn vinafix A3
Date:
Tuesday, January 03, 2012 Sheet 4 of 104
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CPU1B 2 OF 9
IVY-BRIDGE
A28 CLK_EXP_P CLK_EXP_P 20

BCLK
MISC
CLOCKS
22 H_SNB_IVB# H_SNB_IVB# C26 A27 CLK_EXP_N CLK_EXP_N 20
1D05V_VTT PROC_SELECT# BCLK#
R501 TPAD14-OP-GP TP501 1 SKTOCC#_R AN34 RN502

H_PROCHOT# SKTOCC# CLK_DP_P_R 1
1 2 DPLL_REF_CLK A16 4
A15 CLK_DP_N_R 2 3 1D05V_VTT
62R2J-GP DPLL_REF_CLK#
SRN1KJ-7-GP
2
TPAD14-OP-GP TP502 1 H_CATERR# AL33

R505 CATERR#
DY 0R2J-2-GP 1 2 R502
THERMAL
4K99R2F-L-GP
H_PECI AN33 R8 SM_DRAMRST# SM_DRAMRST# 37
22,27 H_PECI
1
PECI SM_DRAMRST#
86 H_PROCHOT#_L
DDR3
MISC
R513
1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R506 1 2 140R2F-GP
27,40 H_PROCHOT# PROCHOT# SM_RCOMP0
A5 SM_RCOMP_1 R507 1 2 25D5R2F-GP
56R2J-4-GP SM_RCOMP1 SM_RCOMP_2 R508 1
SM_RCOMP2 A4 2 200R2F-L-GP
22,36 H_THERMTRIP# H_THERMTRIP# AN32 THERMTRIP#

C Layout Note: C
Layout Note: Signal Routing Guideline:
R501, R513 place near to CPU SM_RCOMP keep routing length less than 500 mils.
C502 need place at the separate point. AP29 XDP_PRDY# 1 TP511 TPAD14-OP-GP
PRDY#
AP27 XDP_PREQ# 1
Trace width = 15mil
PREQ# TP512 TPAD14-OP-GP
AR26 XDP_TCLK
TCK
PWR MANAGEMENT
XDP_TMS
JTAG & BPM

TMS AR27
19 H_PM_SYNC H_PM_SYNC AM34 AP30 XDP_TRST#
PM_SYNC TRST#
SCD1U10V2KX-5GP
1 2C504 AR28 XDP_TDI
TDI XDP_TDO
X02 TDO AP26
1 R504 2 H_CPUPW RGD_R AP33 1D05V_VTT
22,36 H_CPUPW RGD UNCOREPWRGOOD
0R0402-PAD
1 2
R503 10KR2J-3-GP AL35 XDP_DBRESET# RN501
DBR# XDP_DBRESET# 19
37 VDDPW RGOOD VDDPW RGOOD V8 XDP_TDI 1 8
SM_DRAMPWROK XDP_TMS 2 7
AT28 XDP_BPM0 1 TP503 TPAD14-OP-GP XDP_TDO 3 6
BPM#0 XDP_BPM1 XDP_TCLK
BPM#1 AR29 1 TP504 TPAD14-OP-GP 4 5
AR30 XDP_BPM2 1 TP505 TPAD14-OP-GP
BUF_CPU_RST# BPM#2 XDP_BPM3 SRN51J-1-GP
18,27,31,65,71,83 PLT_RST# 1 2 AR33 RESET# BPM#3 AT30 1 TP506 TPAD14-OP-GP
AP32 XDP_BPM4 1 TP507 TPAD14-OP-GP
R510 BPM#4 XDP_BPM5 XDP_TRST# R511 1
BPM#5 AR31 1 TP508 TPAD14-OP-GP 2 51R2J-2-GP
1
1K5R2F-2-GP AT31 XDP_BPM6 1 TP509 TPAD14-OP-GP

R509 BPM#6 XDP_BPM7
BPM#7 AR32 1 TP510 TPAD14-OP-GP
1
698R2F-GP
DY C501
SC220P50V2KX-3GP
B B
2
A <Variant Name>
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
Date:
X02
a f i x
Vin
5 4 3 2 1
SSID = CPU
CPU1C 3 OF 9 CPU1D 4 OF 9
D D
IVY-BRIDGE IVY-BRIDGE
SA_CK0 AB6 M_A_DIMA_CLK_DDR0 15 SB_CK0 AE2 M_B_DIMB_CLK_DDR0 14
M_A_DQ[63:0] AA6 M_B_DQ[63:0] AD2
15 M_A_DQ[63:0] SA_CLK#0 M_A_DIMA_CLK_DDR#0 15 14 M_B_DQ[63:0] SB_CLK#0 M_B_DIMB_CLK_DDR#0 14
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIMA_CKE0 15 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIMB_CKE0 14
D5 SA_DQ1 A7 SB_DQ1
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CK1 M_A_DIMA_CLK_DDR1 15 M_B_DQ5 SB_DQ4 SB_CK1 M_B_DIMB_CLK_DDR1 14
C6 SA_DQ5 SA_CLK#1 AB5 M_A_DIMA_CLK_DDR#1 15 A8 SB_DQ5 SB_CLK#1 AD1 M_B_DIMB_CLK_DDR#1 14
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIMA_CKE1 15 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIMB_CKE1 14
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CK2 M_B_DQ11 SB_DQ10 SB_CK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
G7 SA_DQ15 G2 SB_DQ15
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ16 SA_CK3 M_B_DQ17 SB_DQ16 SB_CK3
K5 SA_DQ17 SA_CLK#3 AA3 J8 SB_DQ17 SB_CLK#3 AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIMA_CS#0 15 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIMB_CS#0 14
K2 SA_DQ23 SA_CS#1 AL3 M_A_DIMA_CS#1 15 K7 SB_DQ23 SB_CS#1 AE3 M_B_DIMB_CS#1 14
C M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6 C
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIMA_ODT0 15 N5 SB_DQ29 SB_ODT0 AE4 M_B_DIMB_ODT0 14
DDR SYSTEM MEMORY B

M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A
M_A_DQ31 SA_DQ30 SA_ODT1 M_A_DIMA_ODT1 15 M_B_DQ31 SB_DQ30 SB_ODT1 M_B_DIMB_ODT1 14
M7 SA_DQ31 SA_ODT2 AG2 M1 SB_DQ31 SB_ODT2 AD5
M_A_DQ32 AG6 AH2 M_B_DQ32 AM5 AE5
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3
AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_A_DQS#[7:0] 15 M_B_DQ36 AN3 M_B_DQS#[7:0] 14
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 SA_DQ39 SA_DQS#2 J3 AP2 SB_DQ39 SB_DQS#2 K6
M_A_DQ40 AJ8 M6 M_A_DQS#3 M_B_DQ40 AP5 N3 M_B_DQS#3
AK8 SA_DQ41 SA_DQS#4 AL6 AN9 SB_DQ41 SB_DQS#4 AN5
M_A_DQ42 AJ9 AM8 M_A_DQS#5 M_B_DQ42 AT5 AP9 M_B_DQS#5
AK9 SA_DQ43 SA_DQS#6 AR12 AT6 SB_DQ43 SB_DQS#6 AK12
M_A_DQ44 AH8 AM15 M_A_DQS#7 M_B_DQ44 AP6 AP15 M_B_DQS#7
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 SA_DQ45 AN8 SB_DQ45
M_A_DQ46 AL9 M_B_DQ46 AR6
AL8 SA_DQ47 AR5 SB_DQ47
M_A_DQ48 AP11 M_A_DQS[7:0] 15 M_B_DQ48 AR9 M_B_DQS[7:0] 14
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 SA_DQ51 SA_DQS2 K3 AT9 SB_DQ51 SB_DQS2 J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
B M_A_DQ53 SA_DQ52 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS3 M_B_DQS4 B
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
M_A_DQ54 AP12 AM9 M_A_DQS5 M_B_DQ54 AJ12 AP8 M_B_DQS5
M_A_DQ55 SA_DQ54 SA_DQS5 M_A_DQS6 M_B_DQ55 SB_DQ54 SB_DQS5 M_B_DQS6
AN12 SA_DQ55 SA_DQS6 AR11 AH12 SB_DQ55 SB_DQS6 AK11
M_A_DQ56 AJ14 AM14 M_A_DQS7 M_B_DQ56 AT11 AP14 M_B_DQS7
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 SA_DQ57 AN14 SB_DQ57
M_A_DQ58 AL15 M_B_DQ58 AR14
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] 15 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 14
AK14 SA_DQ61 SA_MA0 AD10 AN15 SB_DQ61 SB_MA0 AA8
M_A_DQ62 AJ15 W1 M_A_A1 M_B_DQ62 AR15 T7 M_B_A1
M_A_DQ63 SA_DQ62 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AH15 SA_DQ63 SA_MA2 W2 AT15 SB_DQ63 SB_MA2 R7
W7 M_A_A3 T6 M_B_A3
SA_MA3 M_A_A4 SB_MA3 M_B_A4
SA_MA4 V3 SB_MA4 T2
V2 M_A_A5 T4 M_B_A5
SA_MA6 W3 SB_MA6 T3
15 M_A_BS0 AE10 W6 M_A_A7 14 M_B_BS0 AA9 R2 M_B_A7
SA_BS0 SA_MA7 M_A_A8 SB_BS0 SB_MA7 M_B_A8
15 M_A_BS1 AF10 SA_BS1 SA_MA8 V1 14 M_B_BS1 AA7 SB_BS1 SB_MA8 T5
15 M_A_BS2 V6 W5 M_A_A9 14 M_B_BS2 R6 R3 M_B_A9
SA_BS2 SA_MA9 M_A_A10 SB_BS2 SB_MA9 M_B_A10
SA_MA10 AD8 SB_MA10 AB7
V4 M_A_A11 R1 M_B_A11
SA_MA12 W4 SB_MA12 T1
15 M_A_CAS# AE8 AF8 M_A_A13 14 M_B_CAS# AA10 AB10 M_B_A13
SA_CAS# SA_MA13 M_A_A14 SB_CAS# SB_MA13 M_B_A14
15 M_A_RAS# AD9 SA_RAS# SA_MA14 V5 14 M_B_RAS# AB8 SB_RAS# SB_MA14 R5
15 M_A_W E# AF9 V7 M_A_A15 14 M_B_W E# AB9 R4 M_B_A15
SA_WE# SA_MA15 SB_WE# SB_MA15
A <Variant Name> A
Wistron Corporation
Title
CPU (DDR)
A3

5
http://www.vinafix.vn 4 3 2
1
6 of 104
a f i
in = CPU x 5 4 3 2 1
VSSID
D D
CPU1E 5 OF 9
CFG2
IVY-BRIDGE
1
PEG Static Lane Reversal
AH27 VCC_DIE_SENSE 1 TP714 TPAD14-OP-GP R702
VCC_DIE_SENSE 1KR2J-1-GP
TPAD14-OP-GP TP703 1 CFG0 AK28 CFG0 VSS_DIE_SENSE AH26 VSS_DIE_SENSE 1 TP715 TPAD14-OP-GP DIS 1: Normal Operation; Lane #
TPAD14-OP-GP TP701 1 CFG1 AK29 CFG[2] definition matches socket pin map definition
CFG2 CFG1
AL26
2
CFG2
TPAD14-OP-GP TP702 1 CFG3 AL27 0:Lane Reversed
CFG4 CFG3
AK26 CFG4 RSVD#L7 L7
CFG5 AL29 AG7
CFG6 CFG5 RSVD#AG7
AL30 CFG6 RSVD#AE7 AE7
TPAD14-OP-GP TP723 1 CFG7 AM31 AK2
CFG8 CFG7 RSVD#AK2
TPAD14-OP-GP TP704 1 AM32 CFG8
CFG
TPAD14-OP-GP TP705 1 CFG9 AM30 W8
CFG10 CFG9 RSVD#W8 CFG4
TPAD14-OP-GP TP706 1 AM28 CFG10
TPAD14-OP-GP TP707 1 CFG11 AM26
CFG12 CFG11
TPAD14-OP-GP TP708 1 AN28 CFG12 RSVD#AT26 AT26 Display Port Presence Strap
1
TPAD14-OP-GP TP709 1 CFG13 AN31 AM33
CFG14 CFG13 RSVD#AM33 R703 1: Disabled; No Physical Display Port
TPAD14-OP-GP TP710 1 AN26 CFG14 RSVD#AJ27 AJ27
TPAD14-OP-GP TP711 1 CFG15 AM27 DY 1KR2J-1-GP CFG[4] attached to Embedded Display Port
C CFG16 CFG15 C
TPAD14-OP-GP TP712 1 AK31 CFG16
TPAD14-OP-GP TP713 1 CFG17 AN29 0: Enabled; An external Display Port device is
2
CFG17
connected to the Embedded Display Port
RSVD#T8 T8
RSVD#J16 J16
TPAD14-OP-GP TP719 1VAXG_VAL_SENSE AJ31 VAXG_VAL_SENSE RSVD#H16 H16
TPAD14-OP-GP TP720 1VSSAXG_VAL_SENSE AH31 VSSAXG_VAL_SENSE RSVD#G16 G16
TPAD14-OP-GP TP721 1VCC_VAL_SENSE AJ33 VCC_VAL_SENSE
TPAD14-OP-GP TP722 1VSS_VAL_SENSE AH33 VSS_VAL_SENSE CFG5
AJ26 AR35 CFG6 PCIE Port Bifurcation Straps

RSVD#AJ26 RSVD_NCTF#AR35
RESERVED
RSVD_NCTF#AT34 AT34
1
RSVD_NCTF#AT33 AT33
AP35 R701 R704 CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
RSVD_NCTF#AP35 CPU_NCTF_AR34
RSVD_NCTF#AR34 AR34 1 TP716 TPAD14-OP-GP DY 1KR2J-1-GP DY 1KR2J-1-GP
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
2
F25 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
RSVD#F25
F24 RSVD#F24
F23 RSVD#F23
D24 B34 CPU_NCTF_B34 1 TP717 TPAD14-OP-GP
RSVD#D24 RSVD_NCTF#B34 CFG7
G25 RSVD#G25 RSVD_NCTF#A33 A33
G24 RSVD#G24 RSVD_NCTF#A34 A34
E23 RSVD#E23 RSVD_NCTF#B35 B35
1
D23 RSVD#D23 RSVD_NCTF#C35 C35
C30 R705
RSVD#C30 1KR2J-1-GP
B
A31 RSVD#A31 DY B
B30 RSVD#B30
B29
2
RSVD#B29
D30 RSVD#D30 RSVD#AJ32 AJ32
B31 RSVD#B31 RSVD#AK32 AK32
A30 RSVD#A30
C29 RSVD#C29
AN35 BCLK_ITP BCLK_ITP 20
BCLK_ITP BCLK_ITP#
J20 RSVD#J20 BCLK_ITP# AM35 BCLK_ITP# 20
B18 RSVD#B18
J15 RSVD#J15 RSVD_NCTF#AT2 AT2

AT1 CPU_NCTF_AT1 1 TP718 TPAD14-OP-GP
RSVD_NCTF#AT1
RSVD_NCTF#AR1 AR1
A <Variant Name> A
Wistron Corporation
Title
CPU (RESERVED)
A3

5
4 3 2
1
7 of 104
a f i x
Vin
5 4 3 2 1
SSID = CPU
D D
Voltage Rail Voltage(V) Iccmax(A)

CPU1F POWER 6 OF 9
VCC_CORE(DC) 0.3~1.35 53 IVY-BRIDGE
VAXG(DC) 0~1.3 33
VCC_CORE
VCCIO 1 8.5 1D05V_VTT
AG35
VCC1
Decap 8.5A Decap
VDDQ 1.5 10 AG34 AH13
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC2 VCCIO1
AG33 AH10
SC10U6D3V3MX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
VCC3 VCCIO2
C809
C841
C808
C838
VCCSA 0.9 6 AG32 AG10
1
VCC4 VCCIO3
C805
C839
C840
AG31 AC10
VCC5 VCCIO4
VCCPLL 1.8 1.5 AG30
VCC6 VCCIO5
Y10 DY DY
AG29 U10
2
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
Refer to PDDG rev 0.8 AG27
VCC9 VCCIO8
L10
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 H14
VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15
AF29 G14
VCC17 VCCIO16
AF28 G13
PEG AND DDR

VCC18 VCCIO17
AF27 G12
VCC19 VCCIO18
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20
AD34 F12
VCC22 VCCIO21
PROCESSOR CORE POWER AD33
VCC23 VCCIO22
F11
AD32 E14
VCC24 VCCIO23 1D05V_VTT
AD31 E12
VCC_CORE 53A X00 2011-10-06
AD30
VCC25
VCC26
VCCIO24
AD29
AD28
VCC27 VCCIO25
E11
D14
Decap
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Decap Decap VCC28 VCCIO26
C842
AD27 D13
1
VCC29 VCCIO27
C829
C830
C843
C844
C845
AD26 D12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC30 VCCIO28
C802
C803
C801
C804
C806
C807
AC35 D11
1
VCC31 VCCIO29
C AC34 C14 C
2
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 C12
2
VCC34 VCCIO32
AC31 C11
VCC35 VCCIO33
AC30 B14
VCC36 VCCIO34
AC29 B12
VCC37 VCCIO35
AC28 A14
VCC38 VCCIO36
AC27 A13
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38
AA35 A11
VCC41 VCCIO39
Decap AA34
VCC42
AA33 J23
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VCC43 VCCIO40
C820
C819
C818
C817
C812
C811
AA32
1
VCC44
AA31
VCC45
DY DY DY AA30
VCC46
AA29
2
VCC47
AA28
VCC48
AA27
VCC49
AA26
CORE SUPPLY
VCC50
Y35
VCC51 1D05V_VTT
Y34
VCC52
Y33
VCC53
Y32
Decap Y31
VCC54 Layout Note:
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
1
VCC55
Y30
VCC56
C822
C816
C821
C823
C824
C825
C826
C827
Y29 R805 R804

1
VCC57 75R2F-2-GP
X00 Y28
VCC58 130R2F-1-GP
Y27
VCC59 R803
Y26
2
2
VCC60 43R2J-GP
V35
SVID
VCC61 H_CPU_SVIDALRT#
V34
VCC62 VIDALERT#
AJ29 1 2 VR_SVID_ALERT# 42 R803, R804, R805 need close to CPU
V33 AJ30 H_CPU_SVIDCLK
VCC63 VIDSCLK H_CPU_SVIDDAT
H_CPU_SVIDCLK 42 Alert# signal must be routed between the Clock and Data
V32 AJ28 H_CPU_SVIDDAT 42
VCC64 VIDSOUT lines to reduce the cross talk between them
V31
VCC65
V30
VCC66
V29
VCC67
V28
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC68
V27
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
VCC69
C834
C833
C831
V26
1
VCC70
X00 U35
VCC71
C837
C836
C835
C832
C828
U34
B VCC72 B
U33
2
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80 VCC_CORE
R35
VCC81
R34
VCC82
R33
1
VCC83
R32
R31
VCC84 R801 Layout Note:
VCC85
R30 100R2F-L1-GP-U 1. PH/PL resisors place close CPU
VCC86
R29 2. SENSE signal recommend differential routing
SENSE LINES
VCC87
R28
2
VCC88
R27 AJ35 VCCSENSE 42
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE 42
VCC90 VSS_SENSE
P35
1
VCC91
P34
VCC92
P33
VCC93
R802 Is it need reserved 0 ohm? asked power team
P32 B10 1D05V_VTT 100R2F-L1-GP-U
VCC94 VCCIO_SENSE PIC: Willis
P31 A10
VCC95 VSS_SENSE_VCCIO
P30
2
1
VCC96
P29
VCC97 R807
P28
VCC98
P27 10R2F-L-GP
VCC99
P26
VCC100
VCCIO_SENSE 45
2
1 VSSIO_SENSE 45
R806
10R2F-L-GP
Layout Note:
2
1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing
A A
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
CPU (VCC_CORE)
A2
5 4
vinafix
http://www.vinafix.vn 3 2
Date: Tuesday, January 03, 2012
1
Sheet 8 of 104
a f i x
Vin
5 4 3 2 1
SSID = CPU VCC_GFXCORE
POWER
1
VCC_CORE(DC) 0.3~1.35 53
R906
CPU1G 7 OF 9 100R2F-L1-GP-U VAXG(DC) 0~1.3 33
VCC_GFXCORE
VCC_GFXCORE VCCIO 1 8.5
2
SENSE
LINES
De-Cap 22uF x 1 AT24 IVY-BRIDGE AK35 VCC_AXG_SENSE
VCC_AXG_SENSE 42
33A X00-05/30 AT23
VAXG1
VAXG2
VAXG_SENSE
VSSAXG_SENSE AK34 VSS_AXG_SENSE 42 VSS_AXG_SENSE VDDQ 1.5 10
D AT21 VAXG3 D
1
Decap AT20 VCCSA 0.9 6
AT18
VAXG4 Layout Note: R907
VAXG5 100R2F-L1-GP-U VCCPLL 1.8 1.5
AT17 VAXG6
+V_SM_VREF_CNT should have 10 mil trace width
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AR24 VAXG7
1
1
AR23
DY
2
VAXG8
DY
C901
C902
C906
C908
C920
AR21 VAXG9
Refer to PDDG rev 0.8
AR20
2
2
VAXG10
AR18 VAXG11 SM_VREF AL1 +V_SM_VREF_CNT 37
AR17 VAXG12
VREF
AP24
AP23
VAXG13 Layout Note:
VAXG14
AP21 VAXG15
1. PH/PL resisors place close CPU
AP20 B4 DDR_W R_VREFA 2. SENSE signal recommend differential routing
VAXG16 SA_DIMM_VREFDQ DDR_W R_VREFB
AP18 VAXG17 SB_DIMM_VREFDQ D1
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20
AN21 VAXG21
AN20 VAXG22 1D5V_S0
DDR3 -1.5V RAILS

AN18
AN17
VAXG23
VAXG24
10A
GRAPHICS
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AM24 VAXG25 VDDQ1 AF7
1
1
AM23 VAXG26 VDDQ2 AF4 Decap
SC22U6D3V5MX-2GP
C900
C927
C928
C929
C921
C924
C926
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AM21 VAXG27 VDDQ3 AF1
AM20 AC7
2
VAXG28 VDDQ4
1
C909
C910
C911
C912
C913
C914
AM18 VAXG29 VDDQ5 AC4
AM17 VAXG30 VDDQ6 AC1
DY DY DY TC915
ST330U2VDM-4-GP
AL24 Y7
2
C VAXG31 VDDQ7 C
AL23 Y4
AL21
VAXG32 VDDQ8
Y1
79.33719.20L
VAXG33 VDDQ9
AL20 U7
AL18
VAXG34 VDDQ10
U4
2nd = 77.C3371.13L
VAXG35 VDDQ11
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
VAXG Output Decoupling Recommendation: AK23 VAXG38 VDDQ14 P4 VDDQ Output Decoupling Recommendation:
2 x 470 uF at Bottom Socket Edge AK21 VAXG39 VDDQ15 P1 1 x 330 uF
AK20
2 x 22 uF at Top Socket Cavity AK18
VAXG40 6 x 10 uF Do not have 1 x 330 uF
4 x 22 uF at Top Socket Edge VAXG41
AK17 VAXG42
2 x 22 uF at Bottom Socket Cavity AJ24 VAXG43
4 x 22 uF at Bottom Socket Edge AJ23 VAXG44
AJ21 VAXG45
AJ20 0D85V_S0
AJ18
VAXG46
VAXG47
6A VCCSA Output Decoupling Recommendation:
Do not have 2 x 470 uF AJ17 M27 1 x 330 uF, 6m
SA RAIL
VAXG48 VCCSA1
AH24 M26
AH23
VAXG49 VCCSA2
L26
2 x 10 uF at Bottom Socket Cavity
VAXG50 VCCSA3 1 x 10 uF at Bottom Socket Edge
AH21 VAXG51 VCCSA4 J26
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
C934
C936
C935
AH17 VAXG54 VCCSA7 H26
H25 Do not have 1 x 330 uF
2
VCCSA8
1.8V RAIL
B VCCSA_SENSE B
VCCSA_SENSE H23 1R910 2 0D85V_S0 R910 close to pin H23.
1D8V_S0 10R2J-2-GP
1.5A
B6 VCCPLL1
MISC
A6 C22 VCCSA_SEL0
VCCPLL2 VCCSA_VID0
X00 X00 A2 VCCPLL3 VCCSA_VID1 C24 VCCSA_SEL1 48
SC10U6D3V5KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
VCCSA Power Select

1
1
C938
C923
C937
A19 H_SNB_IVB#_PW RCTRL 1 TP901 TPAD14-OP-GP Voltage(V) VID[0] VID[1]

2
VCCIO_SEL
0.9 0 0
VCCSA_SEL0
VCCSA_SEL1
NEC, 330uF, 2.5V, B2 VCCIO_SEL: LV & ULV
ESR=9m SNB: Floating 0.85
2
1

IVY: GND 0 1
Iripple=3.073A RN901
DY SRN1KJ-7-GP Others
0.8
VCCPLL Output Decoupling Recommendation:
3
4
1 x 330 uF, 6m CRB: 10K 0.725 1 0
2 x 1 uF (0402) Bottom socket Cavity DG: 1K
1 x 10 uF (0805) Bottom socket edge 0.675 1 1
A DDR_W R_VREFA <Variant Name> A

DDR_W R_VREFB
Do not have 1 x 330 uF
Wistron Corporation
4
3
RN902 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

SRN1KJ-7-GP Taipei Hsien 221, Taiwan, R.O.C.
DY
Title
CPU (VCC_GFXCORE)
1
2
A3

5
4 3 2
1
9 of 104
a f i x
Vin
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT35 VSS1 VSS81 AJ22

AT32 VSS2 VSS82 AJ19
D AT29 IVY-BRIDGE AJ16 T35 IVY-BRIDGE F22 D
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
C AP7 AE33 L27 C25 C
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216
B B
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AK33 VSS69 VSS150 W30 G23 VSS227
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80
A <Variant Name> A
Wistron Corporation
Title
CPU (VSS)
A3

5
4 3 2
1
10 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
XDP
A3

5
4 3 2
1
11 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
12 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
13 of 104
a f i x
Vin
5 4 3 2 1
DM2
SSID = MEMORY M_B_A0 98
A0 NP1
NP1 3D3V_S0
M_B_A1 97 NP2
M_B_A2 A1 NP2
M_B_A[15:0] 6 96
M_B_A3 A2
95 110 M_B_RAS# 6
1
DDR_VREF_S3 M_B_A4 A3 RAS#
92 113 M_B_WE# 6
M_B_A5 A4 WE# R1402
M_B_A6
91
A5 CAS#
115 M_B_CAS# 6
10KR2J-3-GP
Note:
2 90
M_B_A7 A6 If SA0 DIM0 = 0, SA1_DIM0 = 0
86 114 M_B_DIMB_CS#0 6
R1405 M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 6 SO-DIMMA SPD Address is 0xA0
2
A8 CS1#
X02 0R0402-PAD M_B_A9 85
A9
M_B_A10 107
A10/AP CKE0
73 M_B_DIMB_CKE0 6 SO-DIMMA TS Address is 0x30
M_VREF_CA_DIMM1 M_B_A11 84 74 M_B_DIMB_CKE1 6
1
M_B_A12 A11 CKE1 SA1_DIM1

83
A12
M_B_A13 119
A13 CK0
101 M_B_DIMB_CLK_DDR0 6 If SA0 DIM0 = 0, SA1_DIM0 = 1
M_B_A14 80 103 SA0_DIM1
A14 CK0# M_B_DIMB_CLK_DDR#0 6 SO-DIMMA SPD Address is 0xA2
M_B_A15 78
1
1
A15
79 102 M_B_DIMB_CLK_DDR1 6 SO-DIMMA TS Address is 0x32
1
6 M_B_BS2 A16/BA2 CK1
C1423
C1425
C1424
104
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
D M_B_DIMB_CLK_DDR#1 6 D
CK1# R1401
109
2
2
6 M_B_BS0 BA0 10KR2J-3-GP
108 11
6 M_B_BS1 BA1 DM0
6 M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
2
M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
17 153
M_B_DQ4 DQ3 DM5
4 170
M_B_DQ5 DQ4 DM6
6 187
M_B_DQ6 DQ5 DM7
16
DDR_VREF_S3 M_B_DQ7 DQ6
18 200 PCH_SMBDATA 15,20,65
M_B_DQ8 DQ7 SDA
21 202
M_B_DQ9 23
DQ8 SCL PCH_SMBCLK 15,20,65 Thermal EVENT
2
M_B_DQ10 DQ9 3D3V_S0

33 198 TS#_DIMM0_1 15
R1404 M_B_DQ11 DQ10 EVENT# 3D3V_S0
35
M_B_DQ12 DQ11
X02 0R0402-PAD
M_B_DQ13
22
24
DQ12 VDDSPD
199
TS#_DIMM0_1 1 2
M_VREF_DQ_DIMM1 M_B_DQ14 DQ13 SA0_DIM1 R1403 10KR2J-3-GP
34 197
1
1
M_B_DQ15 DQ14 SA0 SA1_DIM1
36 201
M_B_DQ16 DQ15 SA1 C1401 C1402
39
M_B_DQ17 41
DQ16
77 SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP
2
M_B_DQ18 DQ17 NC#1
51 122
1
M_B_DQ19 DQ18 NC#2 1D5V_S3

53 125
M_B_DQ20 DQ19 NC#/TEST
C1411
C1412
C1413
40
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
M_B_DQ21 DQ20
42 75
2
M_B_DQ22 DQ21 VDD1

50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4 1D5V_S3
M_B_DQ26
59
DQ25 VDD5
87 SODIMM A DECOUPLING
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_B_DQ31 DQ30 VDD10
C1403
C1404
C1405
C1406
C1407
C1408
C1409
C1410
70 105
1
M_B_DQ32 DQ31 VDD11 TC1401
129 106
79.33719.20L
ST330U2VDM-4-GP
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 141
DQ33 VDD13
112
DY DY DY DY
2nd = 77.C3371.13L DY
2
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
130 118
M_B_DQ37 DQ36 VDD16
C 132 123 C
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
M_B_DQ42
149
157
DQ41 VSS
3
8
Decap Decap Decap Decap
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DQ42 VSS
C1414
C1415
C1416
C1417
M_B_DQ43 159 9
1
M_B_DQ44 DQ43 VSS
M_B_DQ45
146
DQ44 VSS
13 Layout Note:
0D75V_S0 Place these caps M_B_DQ46
148
DQ45 VSS
14
Place these Caps near
158 19
2
close to VTT1 and M_B_DQ47 DQ46 VSS
160 20 SO-DIMMA.
M_B_DQ48 DQ47 VSS
VTT2. 163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS
177 32
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
M_B_DQ52 DQ51 VSS

C1419
C1420
C1421
C1422
C1418
164 37
1
M_B_DQ53 DQ52 VSS

166 38
M_B_DQ54 DQ53 VSS
DY DY DY M_B_DQ55
174
176
DQ54 VSS
43
44
2
M_B_DQ56 DQ55 VSS

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194
DQ63 VSS
66 X00
71
M_B_DQS#0 VSS 1D5V_S0 1D5V_S3
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS C1426
152 138 1 2 SCD1U10V2KX-5GP
M_B_DQS#6 169
DQS5# VSS
139
DY
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS C1427
145 1 2 SCD1U10V2KX-5GP
M_B_DQS0 12
VSS
150
DY
M_B_DQS1 DQS0 VSS
M_B_DQS#[7:0] 6 29 151
M_B_DQS2 DQS1 VSS C1428
47 155 1 2 SCD1U10V2KX-5GP
M_B_DQS[7:0] 6 M_B_DQS3 64
DQS2 VSS
156
DY
B M_B_DQS4 DQS3 VSS B
137 161
M_B_DQS5 DQS4 VSS C1429
154 162 1 2 SCD1U10V2KX-5GP
M_B_DQS6 171
DQS5 VSS
167
DY
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_B_DIMB_ODT0 ODT0 VSS
120 178
6 M_B_DIMB_ODT1 ODT1 VSS
VSS
179 Layout Note:
M_VREF_CA_DIMM1 126 184
VREF_CA VSS For S3 reduction circuit's 1D5V return pass.
M_VREF_DQ_DIMM1 1 185
VREF_DQ VSS
189
VSS
30 190
15,37 DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-48-GP
62.10017.P41
2nd = 62.10017.P61
3rd = 62.10017.N41
A A
<Variant Name>
Wistron Corporation
Title
DDR3-SODIMM2
A2
X02
vinafix
Date: Tuesday, January 03, 2012 Sheet 14 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = MEMORY DM1
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
M_A_A[15:0] 6 96
M_A_A3 A2
95 110 M_A_RAS# 6
M_A_A4 A3 RAS#
92 113 M_A_WE# 6
M_A_A5 A4 WE#
91 115 M_A_CAS# 6
M_A_A6 A5 CAS#
90
M_A_A7 A6
86 114 M_A_DIMA_CS#0 6
M_A_A8 A7 CS0#
89 121 M_A_DIMA_CS#1 6
M_A_A9 A8 CS1#
85
M_A_A10 A9
M_A_A11
107
A10/AP CKE0
73 M_A_DIMA_CKE0 6 Note:
84 74 M_A_DIMA_CKE1 6
M_A_A12 A11 CKE1 SO-DIMMB SPD Address is 0xA4
83
M_A_A13 A12 SA1_DIM0
119 101 M_A_DIMA_CLK_DDR0 6 SO-DIMMB TS Address is 0x34
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 6
M_A_A15 A14 CK0# SA0_DIM0
D 78 D
A15
79 102 M_A_DIMA_CLK_DDR1 6
6 M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 6 SO-DIMMB is placed farther from
2
CK1#
109
6 M_A_BS0 BA0 R1502 R1501 the Processor than SO-DIMMA
108 11
6 M_A_BS1 BA1 DM0 10KR2J-3-GP
6 M_A_DQ[63:0] 28 10KR2J-3-GP
M_A_DQ0 DM1
5 46
DDR_VREF_S3 M_A_DQ1 DQ0 DM2
7 63
1
M_A_DQ2 DQ1 DM3
15 136
M_A_DQ3 DQ2 DM4
17 153
M_A_DQ4 DQ3 DM5
4 170
2
M_A_DQ5 DQ4 DM6

6 187
R1504 M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6
X02 0R0402-PAD
M_A_DQ8
18
21
DQ7 SDA
200
202
PCH_SMBDATA 14,20,65
M_VREF_CA_DIMM0 DQ8 SCL PCH_SMBCLK 14,20,65
M_A_DQ9 23
1
M_A_DQ10 DQ9 3D3V_S0

33 198 TS#_DIMM0_1 14
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
1
1
M_A_DQ14 DQ13 SA0_DIM0
34 197
M_A_DQ15 DQ14 SA0 SA1_DIM0
C1523
C1524
C1522
C1501 C1502
DY 36 201
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP SC2D2U10V3KX-1GP

39
2
2
M_A_DQ17 DQ16
41 77
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
67 88
DDR_VREF_S3 M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ30 DQ29 VDD9
68 100
2
M_A_DQ31 DQ30 VDD10 1D5V_S3

70 105
R1503 M_A_DQ32 DQ31 VDD11
129
DQ32 VDD12
106 SODIMM B DECOUPLING
X02 0R0402-PAD M_A_DQ33 131
DQ33 VDD13
111
M_A_DQ34 141 112
M_VREF_DQ_DIMM0 M_A_DQ35 DQ34 VDD14
C 143 117 C
1
M_A_DQ36 DQ35 VDD15

130 118
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_A_DQ37 DQ36 VDD16
C1503
C1504
C1505
C1506
C1507
C1508
C1509
C1510
132 123
1
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
DY DY DY DY DY DY
1
M_A_DQ40 DQ39
147 2
2
M_A_DQ41 DQ40 VSS
C1515
C1516
C1517
149 3
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
M_A_DQ42 DQ41 VSS

157 8
2
M_A_DQ43 DQ42 VSS

159 9
M_A_DQ44 DQ43 VSS
146 13
M_A_DQ45 DQ44 VSS
148 14
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS
M_A_DQ48
160
163
DQ47 VSS
20
25
Decap Decap Decap Decap
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DQ48 VSS
C1511
C1512
C1513
C1514
M_A_DQ49 165 26
1
M_A_DQ50 DQ49 VSS
M_A_DQ51
175
DQ50 VSS
31 Layout Note:
177 32
M_A_DQ52 DQ51 VSS Place these Caps near
164 37
2
M_A_DQ53 DQ52 VSS
166 38 SO-DIMMB.
M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
Place these caps M_A_DQ56
176
DQ55 VSS
44
181 48
0D75V_S0 close to VTT1 and M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
VTT2. 191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
C1518
C1519
C1520
C1521
192 65
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
M_A_DQ63 DQ62 VSS

194 66
DQ63 VSS
71
DY DY M_A_DQS#0 10
VSS
72
2
M_A_DQS#1 DQS0# VSS

27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
M_A_DQS#[7:0] 6 169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
M_A_DQS[7:0] 6 145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
B M_A_DQS2 DQS1 VSS B
47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_A_DIMA_ODT0 ODT0 VSS
120 178
6 M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMM0 126 184
VREF_CA VSS
M_VREF_DQ_DIMM0 1 185
VREF_DQ VSS
189
VSS
30 190
14,37 DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-42-GP
62.10017.N61
2nd = 62.10017.Q41
3rd = 62.10017.N11
A A
<Variant Name>
Wistron Corporation
Title
DDR3-SODIMM1
A2
X02
vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
16 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH
D D
3D3V_S0
RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA 27 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42
3
4
SDVO_STALLP AM40
49 LVDS_DDC_CLK_R T40 RN1706
L_DDC_CLK
49 LVDS_DDC_DATA_R K47 L_DDC_DATA SDVO_INTN AP39 SRN2K2J-1-GP
SDVO_INTP AP40
RN1702 L_CTRL_CLK T45
L_BKLT_EN L_CTRL_DATA L_CTRL_CLK
2 3 P39
2
1
LVDS_VDD_EN L_CTRL_DATA
1 4
LVDS_IBG AF37 P38 PCH_HDMI_CLK 51
SRN100KJ-6-GP TPAD14-OP-GP TP1701 LVDS_VBG LVD_IBG SDVO_CTRLCLK
1 AF36 LVD_VBG SDVO_CTRLDATA M39 PCH_HDMI_DATA 51
1
AE48
Layout Note: R1701 AE47
LVD_VREFH
AT49
2K37R2F-GP LVD_VREFL DDPB_AUXN
Place near PCH; DDPB_AUXP AT47
trace spacing=20mil DDPB_HPD AT40 HDMI_PCH_DET 51
49 LVDSA_CLK# AK39
2
LVDSA_CLK#
LVDS
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51
C AV40 C
DDPB_0P HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51
49 LVDSA_DATA1# AM47 LVDSA_DATA#1 DDPB_1P AV46 HDMI_DATA1_R 51
Digital Display Interface

49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
PCH_CRT_BLUE AH47
PCH_CRT_GREEN LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
PCH_CRT_RED AF45 AY49
LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
5
6
7
8
AF43 LVDSB_DATA3 DDPC_3N BB47

RN1705 BB49
SRN150F-1-GP DDPC_3P
50 PCH_CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43

50 PCH_CRT_GREEN P49 M36
4
3
2
1
B CRT_GREEN DDPD_CTRLDATA B
T49
Layout Note: 50 PCH_CRT_RED CRT_RED
Place near PCH DDPD_AUXN AT45
CRT
50 PCH_CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
50 PCH_CRT_DDCDATA M40 CRT_DDC_DATA DDPD_HPD BH41
X01 1109 RN1703 BB43

PCH_CRT_HSYNC DDPD_0N
50 CRT_HSYNC 1 4 M47 CRT_HSYNC DDPD_0P BB45
50 CRT_VSYNC 2 3 PCH_CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
DDPD_1P BE44
SRN22-3-GP BF42
DAC_IREF_R DDPD_2N
T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
1
BG42
Layout Note: R1702 DDPD_3P
Place near PCH; 1KR2D-1-GP PANTHER-GP-NF
trace spacing=30mil 71.PANTH.00U
2
2 1C1722 PCH_CRT_BLUE Notes:

DY SC10P50V2JN-4GP 1K 0.5%
2 1C1723 PCH_CRT_GREEN
DY SC10P50V2JN-4GP
2 1C1724 PCH_CRT_RED
DY SC10P50V2JN-4GP
A <Variant Name> A
Wistron Corporation
Title
PCH ( LVDS/CRT/DDI )
A3

5
4 3 2
1
17 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH USB Table

Pair Device
5 OF 10
0 NC
RN1801 PCH1E
SRN8K2J-2-GP-U AY7 1 USB2.0 port1
PCH_GPIO52 RSVD1
1 10 3D3V_S0 RSVD2 AV7
INT_PIRQB# 2 9 INT_PIRQD# BG26 AU3 2 NC
INT_PIRQH# INT_PIRQE# TP1 RSVD3
3 8 BJ26 TP2 RSVD4 BG4
INT_PIRQA# 4 7 INT_PIRQC# BH25 3 NC
INT_PIRQG# TP3
D 3D3V_S0 5 6 BJ16 TP4 RSVD5 AT10 D
BG16 TP5 RSVD6 BC8 4 NC
AH38 TP6
AH37 TP7 RSVD7 AU2 5 Card reader
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3 6 NC
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3 7 NC
H3 TP12 RSVD12 AT5
RN1803 AH12 TP13 RSVD13 AV3 8 USB2.0 port2
AM4 TP14 RSVD14 AV1
PCH_GPIO50 1 4 3D3V_S0 AM5 BB1 9 USB2.0 port3
PCH_GPIO54 TP15 RSVD15
2 3 Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5 10 NC
L24 TP18 RSVD18 BB3
SRN10KJ-5-GP AB46 BB7 11 Mini Card1
TP19 RSVD19
AB45 TP20 RSVD20 BE8
RSVD
RSVD21 BD4 12 CAMERA
RSVD22 BF6
13 NC
B21 TP21 RSVD23 AV5
M20 TP22 RSVD24 AV10
AY16 TP23
BG46 TP24 RSVD25 AT8
RSVD26 AY5
RSVD27 BA2
BE28
USB3.0/2.0 Mapping Table BC30
USB3RN1
USB3RN2 RSVD28 AT12
C BE32 BF3 C
USB3RN3 RSVD29
USB 3.0 Port USB 2.0 port BJ32 USB3RN4
BC28 USB3RP1
Port 1 Port 0 BE30
BF32
USB3RP2
USB3RP3
USB2.0 Signal Group
Port 2 Port 1 BG32 USB3RP4 USBP0N C24
AV26 USB3TN1 USBP0P A24
Port 3 Port 2 BB26 USB3TN2 USBP1N C25 USB_PN1 61
AU28 USB3TN3 USBP1P B25 USB_PP1 61
Port 4 Port 3 AY30 USB3TN4 USBP2N C26
AU26 USB3TP1 USBP2P A26
AY26 USB3TP2 USBP3N K28
AV28 USB3TP3 USBP3P H28
AW30 USB3TP4 USBP4N E28
USBP4P D28
USBP5N C28 USB_PN5 32
USBP5P A28 USB_PP5 32
USBP6N C29
USBP6P B29
INT_PIRQA# K40 N28
INT_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28
PCI
INT_PIRQC# H38 L30 USB_PN8 82
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30 USB_PP8 82
USBP9N G30 USB_PN9 82
PCH_GPIO50 C46 E30 USB_PP9 82
REQ1#/GPIO50 USBP9P
USB
PCH_GPIO52 C44 C30
TPAD14-OP-GP TP1808 BBS_BIT1 PCH_GPIO54 REQ2#/GPIO52 USBP10N
1 E40 REQ3#/GPIO54 USBP10P A30
USBP11N L32 USB_PN11 65
TPAD14-OP-GP TP1809 1 BBS_BIT0 BBS_BIT0 21 BBS_BIT1 D47 K32 USB_PP11 65
B TPAD14-OP-GP TP1806 PCH_GPIO53 GNT1#/GPIO51 USBP11P B
1 E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 49
PCI_GNT3# F46 E32 USB_PP12 49
GNT3#/GPIO55 USBP12P
USBP13N C32
USBP13P A32
INT_PIRQE# G42 PIRQE#/GPIO2
56 SATA_ODD_DA# G40 PIRQF#/GPIO3
INT_PIRQG# C42 C33 USB_RBIAS 1 2
Boot Bios Strap INT_PIRQH# D44
PIRQG#/GPIO4 USBRBIAS# R1811 Layout Note:
PIRQH#/GPIO5 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended
USBRBIAS B33 impedance spacing to other signal=15mil
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location TPAD14-OP-GP TP1802 1 PCI_PME# K10 PME# 2. Length < 500mil
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 61
PLTRST# OC0#/GPIO59
0 0 LPC OC1#/GPIO40 K20 USB_OC#2_3
B17 USB_OC#4_5
R1804 OC2#/GPIO41
1 2 22R2J-2-GP CLK_PCI_LPC_R H49 C16 USB_OC#6_7
0 1 Reserved
71
20
CLK_PCI_LPC
CLK_PCI_FB R1805 1
LPC 2 22R2J-2-GP CLK_PCI_FB_R H43
CLKOUT_PCI0 OC3#/GPIO42
L16 USB_OC#8_9 USB_OC#8_9 61
R1806 CLKOUT_PCI1 OC4#/GPIO43
27 CLK_PCI_KBC 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 CLKOUT_PCI2 OC5#/GPIO9 A16 USB_OC#10_11
K42 D14 USB_OC#12_13
1 0 Reserved H40 C14 USB_OC#14_15
2
EC1802 EC1801 EC1803

X00
1 1 SPI(Default) PANTHER-GP-NF
DY DY DY
SC4D7P50V2CN-1GP
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
RN1802
X00 SRN8K2J-2-GP-U
USB_OC#14_15 1 10 3D3V_S5
2 1 PCI_GNT3# USB_OC#6_7 2 9 USB_OC#0_1
A
DY USB_OC#10_11 3 8 USB_OC#12_13 <Variant Name> A
R1801 USB_OC#4_5 4 7 USB_OC#8_9
4K7R2J-2-GP 3D3V_S5 5 6 USB_OC#2_3
X02 Wistron Corporation

A16 Swap Override jumper 1 2 PCI_PLTRST# Taipei Hsien 221, Taiwan, R.O.C.
5,27,31,65,71,83 PLT_RST#
1
R1807 Title
1
PCI_GNT#3 Low = A16 swap override/Top-Block R1816

Swap Override enabled 100KR2J-1-GP
DY DY
0R0402-PAD
PCH ( PCI/USB/NVRAM )
High = Default
2
A3

2
C1801
SC220P50V2KX-3GP Date: Tuesday, January 03, 2012 Sheet 18 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = PCH
PCH1C 3 OF 10
4 DMI_RXN[3:0] FDI_TXN[7:0] 4
DMI_RXN0 BC24 BJ14 FDI_TXN0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_RXN2 BG18 BE14 FDI_TXN2
DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TXN3
BG20 DMI3RXN FDI_RXN3 BH13
D BC12 FDI_TXN4 D
4 DMI_RXP[3:0] FDI_RXN4
DMI_RXP0 BE24 BJ12 FDI_TXN5
DMI_RXP1 DMI0RXP FDI_RXN5 FDI_TXN6
BC20 DMI1RXP FDI_RXN6 BG10
DMI_RXP2 BJ18 BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_TXP[7:0] 4
BG14 FDI_TXP0
4 DMI_TXN[3:0] DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_TXN3 AV18 BE12 FDI_TXP4
DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_TXP5
4 DMI_TXP[3:0] DMI_TXP0 FDI_RXP5 FDI_TXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TXP7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18
Layout Note: DMI_TXP3 AU18
DMI2TXP
DMI3TXP FDI_INT
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT 4
routing length less than 500 1D05V_VTT
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 4
mils. DMI_ZCOMP FDI_FSYNC0
DMI_IRCOMP keep W=4 mils and R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1
routing length less than 500
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 FDI_LSYNC1 4
FDI_LSYNC1
A18 DSW ODVREN RTC_AUX_S5

DSWVRMEN
C R1911 1 2 10KR2J-3-GP C
DY
System Power Management

3D3V_S0 TPAD14-OP-GP TP1907 1 SUSACK# C12 E22 PCH_DPW ROK R1910 1 2 0R0402-PAD PM_RSMRST#
SUSACK# DPWROK
R1905 1 21KR2J-1-GP X02
5 XDP_DBRESET# K3 B9 PCH_W AKE#
SYS_RESET# WAKE#
36 SYS_PW ROK P12 N3 PM_CLKRUN# R1929 1 2 0R0402-PAD PM_CLKRUN#_EC 27

SYS_PWROK CLKRUN#/GPIO32
X02 X02 X02
27,36 S0_PW R_GOOD R19241 2 0R0402-PAD PW ROK L22 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
R1906 1 PWROK SUS_STAT#/GPIO61
2
0R0402-PAD
1 2 MEPW ROK L10 N14 SUS_CLK R1913 1 2 0R0402-PAD
45,46,47,93 RUNPW ROK
R1907 DY 0R2J-2-GP APWROK SUSCLK/GPIO62 PCH_SUSCLK_KBC 27
DSWODVREN - On Die DSW VR Enable
X02
37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP HIGH Enabled (DEFAULT)
DRAMPWROK SLP_S5#/GPIO63
X02
R1912 1 2 PM_RSMRST# C21 H4 PM_SLP_S4# LOW Disabled
27 RSMRST#_KBC RSMRST# SLP_S4# PM_SLP_S4# 27,46
0R0402-PAD
SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# 27,36,37,47

SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# RTC_AUX_S5
27 PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903 TPAD14-OP-GP

PWRBTN# SLP_A# DSW ODVREN R1917 1 2 330KR2J-L1-GP
27 AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904 TPAD14-OP-GP

B ACPRESENT/GPIO31 SLP_SUS# B
27 BATLOW # BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC 5

BATLOW#/GPIO72 PMSYNCH
PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905 TPAD14-OP-GP

RI# SLP_LAN#/GPIO29
PANTHER-GP-NF
Sequence: 71.PANTH.00U 3D3V_S0
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PM_CLKRUN# R1919 1 2 8K2R2J-3-GP

3D3V_S5
RN1901
8 1 BATLOW #
7 2 PCH_W AKE# PCH_SUSCLK_KBC
6 3 PM_RI#
5 4 SUS_PW R_ACK
2
PCIE_WAKE#:
SRN10KJ-6-GP CRB: 1K EC1901
SC4D7P50V2CN-1GP
DY
1
CEKLT: 10K
R1909 1 2 100KR2J-1-GP AC_PRESENT
R1922 2 1 10KR2J-3-GP PM_PW RBTN#

A
R1920 2
DY 1 10KR2J-3-GP PM_SLP_LAN#
<Variant Name> A
DY
R1908 2 1 10KR2J-3-GP PM_RSMRST# Wistron Corporation
R1926 1 2 100KR2J-1-GP SYS_PW ROK
R1904 1
DY 2 100KR2J-1-GP PW ROK Title
PCH ( DMI/FDI/PM )
A3

5
4 3 2
1
19 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH 3D3V_S5
3D3V_S5
SMB_CLK 4 1 RN2003
1
S5 power rail CLKREQ#: X02 1223 SMB_DATA 3 2 SRN2K2J-1-GP
R2005
X00 PCIECLKRQ[0]# 10KR2J-3-GP SML0_DATA 4 1 RN2004
PCIE_CLK_RQ0# PCIECLKRQ[7:3]# PCH1B 2 OF 10 SML0_CLK 3 2 SRN2K2J-1-GP
PCIE_CLK_RQ4#
2
PCIE_CLK_RQ3# RN2001 BG34 SML1_CLK 2 3 RN2005
PERN1 EC_SW I# PEG_CLKREQ# SML1_DATA
1 10 3D3V_S5 BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# 27 1 4 SRN2K2J-1-GP
PCIE_CLK_REQ0# 2 9 EC_SW I# AV32 PETN1 NC
1
D PCIE_CLK_REQ4# 3 8 PCIE_CLK_LAN_REQ# AU32 H14 SMB_CLK PCIE_CLK_REQ6# 1 4 RN2006 D
PCIE_CLK_REQ3# CLK_PCIE_NEW _REQ# PETP1 SMBCLK R2004 PCH_GPIO74
4 7 2 3 SRN10KJ-5-GP
5 6 PEG_B_CLKRQ# BE34 C9 SMB_DATA DY 10KR2J-3-GP
3D3V_S5 PERN2 SMBDATA
PCIE_CLK_RQ5# BF34 PERP2
SRN10KJ-L3-GP PCIE_CLK_RQ7# BB32 NC
2
PETN2 DRAMRST_CNTRL_PCH 1 R2009 2
PCIE_CLK_RQ6# AY32 PETP2 3D3V_S0
SMBUS
SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 37
1KR2J-1-GP
BG36 RN2009
BJ36
PERN3
PERP3 SML0CLK C8 SML0_CLK 1 4 CRB : 1K
AV34 PETN3 NC 2 3
AU34 PETP3 SML0DATA G12 SML0_DATA
SRN4K7J-8-GP
CHKLT: 10K
65 PCIE_RXN4 BF36 PERN4
65 PCIE_RXP4
C2005
BE36 PERP4 3rd = 84.DMN66.03F
65 PCIE_TXN4 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34 PETN4 WLAN SML1ALERT#/PCHHOT#/GPIO74 C13 PCH_GPIO74 2nd = 84.2N702.A3F
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34 84.2N702.F3F
65 PCIE_TXP4 PETP4 SML1_CLK
SML1CLK/GPIO58 E14 SML1_CLK 27
PCI-E*
BG37 SML1_DATA 6 1
PERN5
D2 S2
THM_SML1_DATA 28,86
BH37 M16 SML1_DATA
PERP5 SML1DATA/GPIO75 SML1_DATA 27
AY36 PETN5 NC 5 G1 G2 2
BB36 PETP5
4 S1 D1 3
31 PCIE_RXN2 BJ38 PERN6
31 PCIE_RXP2 BG38 PERP6 Q2002
C2001 2 SCD1U10V2KX-5GP PCIE_TXN2_C CL_CLK TP2001 TPAD14-OP-GP ME2N7002DKW -G-GP
Controller
31 PCIE_TXN2 1 AU36 PETN6 LAN CL_CLK1 M7 1
C2002 1 2 SCD1U10V2KX-5GP PCIE_TXP2_C AV36
31 PCIE_TXP2 PETP6 THM_SML1_CLK 28,86
Link
BG40 T11 CL_DATA 1 TP2002 TPAD14-OP-GP SML1_CLK
PERN7 CL_DATA1
BJ40 PERP7
C AY40 3D3V_S0 C
PETN7 NC CL_RST# 1 TP2003 TPAD14-OP-GP RN2007
S0 power rail CLKREQ#: BB40 PETP7 CL_RST1# P10
2 3
PCIECLKRQ[2:1]# BE38 1 4
BC38
PERN8 Layout Note:
CLKOUT termination AW38
PERP8 NEW CARD CLKOUT termination SRN2K2J-1-GP
PETN8
place close to PCH <500mil AY38 PETP8 place close to PCH <500mil
X00 PEG_CLKREQ#
3rd = 84.DMN66.03F
PEG_A_CLKRQ#/GPIO47 M10 PEG_CLKREQ# 83 2nd = 84.2N702.A3F
RN
3D3V_S0
RN2018
Y40 CLKOUT_PCIE0N 84.2N702.F3F
Y39 CLKOUT_PCIE0P N/A
1 4CLK_PCIE_W LAN_REQ# PCIE_CLK_RQ2# CLKOUT_PEG_A_N AB37 CLKOUT_PEG_A_N 1 4 CLK_PCIE_VGA# 83 SMB_DATA 6 D2 S2 1 PCH_SMBDATA 14,15,65
3CLK_PCIE_W W AN_REQ# PCIE_CLK_RQ1# PCIE_CLK_REQ0# CLKOUT_PEG_A_P
CLOCKS
2 J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 2 3 CLK_PCIE_VGA 83
RN
RN2016 5 G1 G2 2
SRN10KJ-5-GP 0R4P2R-PAD
AB49 AV22 CLKOUT_DMI_N 1 4 CLK_EXP_N 5 4 S1 D1 3
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P
AB47 AU22 2 3
Layout Note: CLKOUT_PCIE1P N/A CLKOUT_DMI_P CLK_EXP_P 5
Q2001
CLK_PCIE_W W AN_REQ# M1 RN2010 ME2N7002DKW -G-GP
PCIECLKRQ1#/GPIO18 X02 1229
RN
AM12 0R4P2R-PAD PCH_SMBCLK 14,15,65

CLKOUT_DP_N
CLKOUT_DP_P AM13
1 4 CLK_PCH_SRC2_N AA48 SMB_CLK
65 CLK_PCIE_W LAN#
2 3 CLK_PCH_SRC2_P AA47
CLKOUT_PCIE2N WLAN
65 CLK_PCIE_W LAN CLKOUT_PCIE2P
RN2012 X02 1229 CLK CLKIN_DMI_N BF18 CLK_BUF_EXP_N
CLK_BUF_EXP_P RN2019 1
2 3 XTAL25_IN
X2001
1 2
65 CLK_PCIE_W LAN_REQ# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 4
0R4P2R-PAD SRN10KJ-5-GP C2008
1 4 SC15P50V2JN-2-GP
2
Y37 BJ30 CLK_BUF_CPYCLK_N 2 3
CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P RN2008 1 R2006
Y36 CLKOUT_PCIE3P N/A CLKIN_GND1_P BG30 4
B SRN10KJ-5-GP 1M1R2J-GP B
PCIE_CLK_REQ3# A8 2 3 C2007
PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N SC15P50V2JN-2-GP
G24 2 3
1
CLKIN_DOT_96N CLK_BUF_DOT96_P RN2020 1
CLKIN_DOT_96P E24 4
Y43 SRN10KJ-5-GP XTAL25_OUT XTAL-25MHZ-155-GP1 2
CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P N/A AK7 CLK_BUF_CKSSCD_N 2 3
PCIE_CLK_REQ4# L12
CLKIN_SATA_N
AK5 CLK_BUF_CKSSCD_P RN2021 1 4
82.30020.D41
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P
RN
SRN10KJ-5-GP 3D3V_S0 3D3V_S0

2nd = 82.30020.G71
CLK_PCH_SRC5_N CLK_BUF_REF14 R2008 1
3rd = 82.30020.G61
31 CLK_PCIE_LAN# 1 4 V45 CLKOUT_PCIE5N LAN REFCLK14IN K45 2 X00
1
31 CLK_PCIE_LAN 2 3 CLK_PCH_SRC5_P V46 10KR2J-3-GP
CLKOUT_PCIE5P
RN2014 X02 1229 CLK CLK_PCI_FB R2013 R2012
BIOS UMA/Discrete Strap pin
31 PCIE_CLK_LAN_REQ# L14 PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK H45 CLK_PCI_FB 18
0R4P2R-PAD 10KR2J-3-GP 10KR2J-3-GP
BOARD_ID1 BOARD_ID2
2
AB42 V47 XTAL25_IN 22 BOARD_ID2 BOARD_ID2
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT BOARD_ID1
AB40 CLKOUT_PEG_B_P N/A XTAL25_OUT V49
PX(AMD) 0 0
1
PEG_B_CLKRQ# E6 PEG_B_CLKRQ#/GPIO56 R2007 R2010
Y47 XCLK_RCOMP 1 2 DY 10KR2J-3-GP DIS 0 1
V40
XCLK_RCOMP +VCCDIFFCLKN
R2011 DY
CLKOUT_PCIE6N 90D9R2F-1-GP 10KR2J-3-GP
V42 N/A
2
CLKOUT_PCIE6P
UMA 1 0
PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
V38 K43 JTAG_TCK R2001 1 DY
2 22R2J-2-GP Optimus(NV) 1 1
New Card
FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 JTAG_TCK_VGA 86

A V37 CLKOUT_PCIE7P X00 <Variant Name> A
CLK_PCIE_NEW _REQ# K12

CLK CLKOUTFLEX1/GPIO65 F47 CLK_PCH_48M_L R2002 1 2 22R2J-2-GP CLK_PCH_48M 32
RN2023 PCIECLKRQ7#/GPIO46 CLK_27M_VGA_R TP2006 TPAD14-OP-GP
7 BCLK_ITP# 1
DY 4 PCIE_CLK_XDP_N_R AK14 CLKOUT_ITPXDP_N
CLKOUTFLEX2/GPIO66 H47 1
Wistron Corporation
2 3 PCIE_CLK_XDP_P_R AK13 K49 BOARD_ID1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
7 BCLK_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 Taipei Hsien 221, Taiwan, R.O.C.
SRN0J-6-GP
PANTHER-GP-NF Title
71.PANTH.00U PCH ( PCI-E/SMBUS/CLOCK/CL)
A3

5
4 3 2
1
20 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH Layout Note:

RTC_AUX_S5 Place it at the open door location.
RN2106
1 4
2 3 Integrated SUS 1V VRM Enable
2
1
SRN20KJ-1-GP C2104 G2101 Low = External VRs
INTVRMEN
SC1U6D3V2KX-GP
GAP-OPEN
High = Internal VRs*
2
LPC_AD[3..0]
LPC_AD[3..0] 27,71
1
D RN2104 SRN33J-5-GP-U D
PCH1A 1 OF 10 2 3 LPC_AD0
27 RTCRST_ON
1 4 LPC_AD1
RTC_X1 A20 C38 LPC_AD0_R
G
Q2102 RTCX1 FWH0/LAD0 LPC_AD1_R RN2105 SRN33J-5-GP-U
FWH1/LAD1 A38
LPC
2N7002BK-GP RTC_X2 C20 B37 LPC_AD2_R 1 4 LPC_AD2
RTCX2 FWH2/LAD2 LPC_AD3_R
FWH3/LAD3 C37 2 3 LPC_AD3
S D RTC_RST# D20 RTCRST#
1 FWH4/LFRAME# D36 LPC_FRAME#_L 2 1 R2127 LPC_FRAME# 27,71
R2125 SRTC_RST# G22 33R2J-2-GP
R2104 SRTCRST#
10KR2J-3-GP 84.07002.I31 LDRQ0# E36
RTC
C2103 2 1 SM_INTRUDER# K22 K36 KB_DET# 69
SC1U6D3V2KX-GP 1M1R2J-GP INTRUDER# LDRQ1#/GPIO23
2nd = 84.2N702.W31
2
RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ 27
2
INTVRMEN SERIRQ
3rd = 84.2N702.J31 R2105
330KR2F-L-GP AM3 SATA_RXN0 56
HDA_BITCLK SATA0RXN
N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 56
HDD1
SATA 6G
SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5 SATA_TXP0 56
HDA_SYNC SATA0TXP
29 HDA_SPKR T10 SPKR SATA1RXN AM10

Layout Note: Place close together. SATA1RXP AM8
HDA_RST# K34 AP11
HDA_RST# SATA1TXN
SATA1TXP AP10
33R2J-2-GP2 1R2123 HDA_SDOUT 29 HDA_SDIN0 E34 AD7

29 HDA_CODEC_SDOUT HDA_SDIN0 SATA2RXN
SATA2RXP AD5
G34 AH5
C Layout Note: HDA_SDIN1 SATA2TXN
AH4 C
RN2102 SATA2TXP
HDA_SDO and HDA_BCLK must be C34 HDA_SDIN2
HDA_RST#
IHDA
29 HDA_CODEC_RST# 1 4 length matched to within 500 mils SATA3RXN AB8
2 3 HDA_BITCLK A34 AB10
29 HDA_CODEC_BITCLK HDA_SDIN3 SATA3RXP
SATA3TXN AF3
SRN33J-5-GP-U R2107 AF1
1KR2J-1-GP HDA_SDOUT SATA3TXP
A36 HDA_SDO
SATA
27 ME_UNLOCK 1 2 SATA4RXN Y7 SATA_RXN4 56
Flash Descriptor Security Overide/ Y5
Intel ME Debug Mode
TPAD14-OP-GP TP2105 1PCH_GPIO33 C36 HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN AD3
SATA_RXP4
SATA_TXN4
56
56 ODD
SATA4TXP AD1 SATA_TXP4 56
Low = Default * TPAD14-OP-GP TP2106 1PCH_GPIO13 N32
1D05V_VTT HDA_DOCK_RST#/GPIO13
HDA_SDOUT High = Enable X00 SATA5RXN Y3
follow DPDG 1.3 Y1
R2111
SATA5RXP
SATA5TXN AB3 ESATA
1 2 51R2J-2-GP PCH_JTAG_TCK_BUF J3 AB1
+3VS_+1.5VS_HDA_IO DY JTAG_TCK SATA5TXP
R2118 1 2 51R2J-2-GP PCH_JTAG_TMS H7 Y11 1D05V_VTT
DY DY JTAG_TMS SATAICOMPO
JTAG
1R2102 2 HDA_SDOUT R2119 1 2 51R2J-2-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
1KR2J-1-GP DY JTAG_TDI SATAICOMPI
R2120 1 2 51R2J-2-GP PCH_JTAG_TDO H1 1D05V_VTT
DY JTAG_TDO
AB12
3D3V_S0 SATA3RCOMPO
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
SATA3COMPI
R2106 1 2 1KR2J-1-GP HDA_SPKR
DY 27,60 SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP
R2108 33R2J-2-GP SPI_CLK SATA3RBIAS
B B
No Reboot Strap 27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
Low = Default * T1 SPI_CS1# Layout Note:
SPI
HDA_SPKR High = No Reboot P3 SATA_LED# SATA_LED# 68
SATALED#
Place close PCH(<500mil)
27,60 SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 SATA_DET#0
R2110 33R2J-2-GP
+3VS_+1.5VS_HDA_IO U3 P1 BBS_BIT0
60 SPI_SO_R SPI_MISO SATA1GP/GPIO19 BBS_BIT0 18
R2103 1 2 1KR2J-1-GP HDA_SYNC RUN_ENABLE
PANTHER-GP-NF
71.PANTH.00U 3D3V_S0
PLL ODVR VOLTAGE
RN2103
G
Low = 1.8V Q2101 INT_SERIRQ 1 4

HDA_SYNC High = 1.5V 2N7002BK-GP SATA_DET#0 2 3
*
29 HDA_CODEC_SYNC 2 R2124 1HDA_CODEC_SYNC_R S D HDA_SYNC
Layout Note: SRN10KJ-5-GP
R2117
100KR2J-1-GP
2
33R2J-2-GP 84.07002.I31 close to branch point

2nd = 84.2N702.W31
3rd = 84.2N702.J31 RTC_X1
1
1 2 RTC_X2
R2101 10MR2J-L-GP
A HDA_CODEC_BITCLK HDA_CODEC_SDOUT X2101 <Variant Name> A
1 4
2
HDA_SYNC: Wistron Corporation

EC2102 EC2103
DY DY
SC15P50V2JN-2-GP
This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V
1
1
C2101
X-32D768KHZ-40GPU
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
VccVRM supply mode. 1K external pull-up resistor is required on this 2 3 C2102 Taipei Hsien 221, Taiwan, R.O.C.
SC15P50V2JN-2-GP
2
2
signal on the board. Signal may have leakage paths via powered off devices (Audio Title
Codec) and hence contend with the external pull-up. A blocking FET is 82.30001.841 PCH ( SPI/RTC/LPC/SATA/HDA)
recommended in such a case to isolate HDA_SYNC from the Audio Codec device Size Document Number Rev
2nd = 82.30001.A41
A3
vinafix
until after the Strap sampling is complete. Enrico Caruso 14 MLK DIS X02
5
4 3 2
1
21 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH
PCH1F 6 OF 10
3D3V_S0 PCH_GPIO0 T7 C40 SATA_ODD_PW RGT SATA_ODD_PW RGT 56

BMBUSY#/GPIO0 TACH4/GPIO68
27 EC_SMI# EC_SMI# A42 B41 BOARD_ID2 BOARD_ID2 20
RN2206 TACH1/GPIO1 TACH5/GPIO69
D 8 1 PCH_GPIO49 PCH_GPIO6 H36 C41 PCH_GPIO70 1 TP2204 TPAD14-OP-GP D
H_A20GATE TACH2/GPIO6 TACH6/GPIO70
7 2
6 3 PCH_GPIO0 27 EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 1 TP2205 TPAD14-OP-GP
H_RCIN# TACH3/GPIO7 TACH7/GPIO71
5 4
FOLLOW CKL PCH_GPIO8 C10
SRN10KJ-6-GP GPIO8
60 RTC_DET# RTC_DET# C4 LAN_PHY_PWR_CTRL/GPIO12

RN2207 PCH_GPIO15 G2 P4 H_A20GATE H_A20GATE 27
PCH_GPIO34 GPIO15 A20GATE
8 1
7 2 3G_EN AU16 H_PECI_R R2203 1 2 0R2J-2-GP
6 3 56 SATA_ODD_PRSNT# U2
PECI DY H_PECI 5,27
SATA_ODD_PRSNT# SATA4GP/GPIO16 H_RCIN#
5 4 RCIN# P5 H_RCIN# 27
GPIO
SRN10KJ-6-GP 27,92,93 DGPU_PW ROK DGPU_PW ROK D40 AY11 H_CPUPW RGD H_CPUPW RGD 5,36
TACH0/GPIO17 PROCPWRGD
CPU/MISC
FOLLOW CKL PCH_GPIO22 T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# 5,36
RN2201 SCLOCK/GPIO22 THRMTRIP#
8 1 EC_SMI# PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2201 TPAD14-OP-GP
EC_SCI# GPIO24 INIT3_3V#
7 2
6 3 PCH_GPIO6 TPAD14-OP-GP TP2203 1 PCH_GPIO27 E16 AY1 DF_TVS
PCH_GPIO22 GPIO27 DF_TVS
5 4
PLL_ODVR_EN P8 1D8V_S0
SRN10KJ-6-GP GPIO28
TS_VSS1 AH8
X02 1223 FOLLOW CKL PCH_GPIO34 K1 STP_PCI#/GPIO34
1
AK11
1
DY 2 DGPU_HOLD_RST# TPAD14-OP-GP TP2213 1 PCH_GPIO35 K4
TS_VSS2 R2207
R2202 10KR2J-3-GP GPIO35
TS_VSS3 AH10 Layout Note: 2K2R2J-2-GP
PCH_GPIO36 V8
C SATA2GP/GPIO36 These four balls must connect to GND C
AK10 R2209
2
R2205 1 TS_VSS4 shared 1 Via
210KR2J-3-GP DGPU_HOLD_RST# PCH_GPIO37 M5 SATA3GP/GPIO37
R2206 1 210KR2J-3-GP DGPU_PW R_EN# DF_TVS 1 2 H_SNB_IVB# 5
3G_EN N2 P37 1KR2J-1-GP
SLOAD/GPIO38 NC_1
X02 1223
83 DGPU_HOLD_RST# M3 SDATAOUT0/GPIO39
93 DGPU_PW R_EN# V13 SDATAOUT1/GPIO48 VSS_NCTF_15#BG2 BG2
PCH_GPIO49 V3 BG48
SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48
PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17#BH3
VSS_NCTF_18#BH47 BH47
3D3V_S5
TPAD14-OP-GP TP2206 1 PCH_NCTF_1 A4 BJ4
VSS_NCTF_1#A4 VSS_NCTF_19#BJ4
NCTF
RN2204 A44 BJ44
SRN10KJ-5-GP VSS_NCTF_2#A44 VSS_NCTF_20#BJ44
1 4 RTC_DET# A45 BJ45
PCH_GPIO57 VSS_NCTF_3#A45 VSS_NCTF_21#BJ45
2 3
A46 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46
2 1 PCH_GPIO24 A5 BJ5
R2221 DY 10KR2J-3-GP VSS_NCTF_5#A5 VSS_NCTF_23#BJ5
A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6
A4,A44,A45,A46,A5,A6,B3,B47,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
2 1 PCH_GPIO8
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
R2224 DY 10KR2J-3-GP B3 C2
PCH_GPIO15 VSS_NCTF_7#B3 VSS_NCTF_25#C2
2 1
B R2201 DY 1KR2J-1-GP B47 C48
B
VSS_NCTF_8#B47 VSS_NCTF_26#C48
D49,E1,E49,F1,F49
BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1
RN2205
NCTF TEST PIN:

SRN10KJ-5-GP BD49 D49
PCH_GPIO36 VSS_NCTF_10#BD49 VSS_NCTF_28#D49
1 4
2 3 PCH_GPIO37 TPAD14-OP-GP TP2207 1 PCH_NCTF_2 BE1 E1
VSS_NCTF_11#BE1 VSS_NCTF_29#E1
TPAD14-OP-GP TP2208 1 PCH_NCTF_3 BE49 E49
VSS_NCTF_12#BE49 VSS_NCTF_30#E49
BF1 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 F1
TPAD14-OP-GP TP2209 1 PCH_NCTF_4 BF49 F49

VSS_NCTF_14#BF49 VSS_NCTF_32#F49
PANTHER-GP-NF
PLL_ODVR_EN
71.PANTH.00U
2 1
R2212 DY 1KR2J-1-GP
PLL ON DIE VR ENABLE
A Weakly internal pull up 20k. <Variant Name> A

GPIO28 High - Enable
(PLL_ODVR_EN) LOW - Disable
Wistron Corporation
Title
PCH ( GPIO/CPU )
A3

5
4 3 2
1
22 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH
V_PROC_IO 1.05 0.002
1D05V_VTT
PCH1G POWER 7 OF 10 3D3V_DAC_S0 V5REF 5 0.001
1.73A 0.063A V5REF_Sus 5 0.001

AA23 U48
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
SC10U6D3V5KX-1GP
VCCCORE1 VCCADAC
D Decap AC23 VCCCORE2
Vcc3_3 3.3 0.178 D
1
C2301
C2302
C2303
AD21 C2313 C2314 C2315
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
CRT
VCCCORE3
C2304
AD23 VCCCORE4 VSSADAC U47 VccADAC 3.3 0.063
AF21
2
VCC CORE
VCCCORE5
AF23 VccADPLLA 1.05 0.075
2
2
VCCCORE6 3D3V_S0
AG21 VCCCORE7 R2304 X02
AG23 VCCCORE8 0.001A VccADPLLB 1.05 0.075
AG24 AK36 +3VS_VCCA_LVDS 1 2
VCCCORE9 VCCALVDS
AG26 VCCCORE10
VccCore 1.05 1.73
AG27 VCCCORE11 VSSALVDS AK37 0R0603-PAD
AG29 VCCCORE12
VccDMI 1.1 0.047
AJ23 VCCCORE13 1D8V_S0
LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37 X02 VccIO 1.05 3.799
R2301
AJ27 VCCCORE15 0.04A
AJ29 AM38 +1.8VS_VCCTX_LVDS 1 2 VccASW 1.05 0.803
SC22U6D3V5MX-2GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE16 VCCTX_LVDS2
AJ31 VCCCORE17
1D05V_VTT
C2316
C2317
C2318
VCCTX_LVDS3 AP36 0R0805-PAD VccSPI 3.3 0.01
1
AP37 VccDSW3_3 3.3 0.001
VCCTX_LVDS4
AN19
2
VCCIO28
VccDFTERM 1.8 0.002
TPAD14-OP-GP TP2301 1 VCCAPLLEXP BJ22 3D3V_S0 VccRTC 3.3 6uA
VCCAPLLEXP
0.178A
VCC3_3_6 V33 VccSus3_3 3.3 0.065
HVCMOS
AN16 VCCIO15
1
C2319 VccSusHDA 3.3 0.01
AN17 SCD1U10V2KX-5GP
VCCIO16
V34 VccVRM 1.5 0.147
2
C VCC3_3_7 C
AN21 VccClkDMI 1.05 0.075
VCCIO17
1D05V_VTT AN26 VCCVRM R2307 1D5V_S0 VccSSC 1.05 0.095
VCCIO18 0R0402-PAD
3.799A 0.147A
AN27 AT16 1 2 VccDIFFCLKN 1.05 0.05
VCCIO19 VCCVRM3
1D05VS_VCC_DMI X02 1D05V_VTT
C2305
C2306
C2307
C2308
C2309
AP21 R2306 VccALVDS 3.3 0.001

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
VCCIO20
1
0.047A 0R0402-PAD
AP23 VCCIO21 VCCDMI1 AT20 1 2 VccTX_LVDS 1.8 0.04
X02
2
1
DMI
AP24 VCCIO22
VCCIO
C2320 Refer to PCH EDS V1.5
AP26 AB36 SC1U6D3V2KX-GP (General DC Characteristicschipset)
2
VCCIO23 VCCCLKDMI
AT24 VCCIO24
R2308 1D05V_VTT
0.075A 0R0402-PAD
AN33 +1.05VS_VCC_DMI_CCI 1 2
VCCIO25
X02
1
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0 C2321
0.228A SC1U6D3V2KX-GP
2
BH29 VCC3_3_3 VCCDFTERM2 AG17
DFT / SPI
1
VCCVRM
C2310
AJ16
SCD1U10V2KX-5GP
VCCDFTERM3 1D8V_S0
2
B
AP16 VCCVRM2 0.002A B
VCCDFTERM4 AJ17
1
TPAD14-OP-GP TP2303 1VCCFDIPLL BG6 C2322
VCCAFDIPLL SCD1U10V2KX-5GP
1D05V_VTT
2
AP17 VCCIO27
V1
FDI
1D05VS_VCC_DMI VCCSPI 3D3V_S5

AU20 VCCDMI2 0.01A
PANTHER-GP-NF 1
71.PANTH.00U C2323
SC1U6D3V2KX-GP
2
X00
5V_S0 3D3V_S0 3D3V_DAC_S0
U2301
1 IN OUT 5
2 GND
A 3 EN NC#4 4 <Variant Name> A
1
1
C2311 TLV70233DBVR-GP C2312
74.70233.03F
Wistron Corporation
SC1U10V2KX-1GP
SC1U6D3V2KX-GP
2
2
2nd = 74.08818.B3F
Title
X02 1230
removed 3rd source 74.09091.J3F
for it is going to EOL
PCH ( POWER1)
A3

5
4 3 2
1
23 of 104
a f i x
Vin
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_VTT
TPAD14-OP-GP TP2401 1 VCCACLK AD49 N26

3D3V_S5 VCCACLK VCCIO29
0.001A
1
VCCIO30 P26
T16 C2438
VCCDSW3_3 SC1U6D3V2KX-GP
P28
2
VCCIO31
1
3D3V_S0 TP2405 1 DCPSUSBYP V12 T27
C2416 TPAD14-OP-GP DCPSUSBYP VCCIO32 3D3V_S5 5V_S5
D D
L2401 SCD1U10V2KX-5GP T29
2
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5
1 2 T38 VCC3_3_5
2
IND-10UH-218-GP 0.065A
SC10U6D3V5KX-1GP
1
68.10050.10Y T23 D2401
TPAD14-OP-GP TP2404 +VCCAPLL_CPY_PCH BH23 VCCSUS3_3_7
2nd = 68.1001F.10N 1 VCCAPLLDMI2 83.R0304.A8F CH751H-40PT-GP
1
3rd = 68.1001E.10N C2401 C2402 T24 C2424 2nd = 83.R3004.A8F
2
SC1U10V2KX-1GP VCCSUS3_3_8 SCD1U10V2KX-5GP R2408
4th = 68.10090.10B 1D05V_VTT AL29 3rd = 83.R2004.B8F
1
VCCIO14
V23 1 2
2
VCCSUS3_3_9
USB
TPAD14-OP-GP TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP
DCPSUS3 VCCSUS3_3_10
1
P24 C2426
VCCSUS3_3_6 SCD1U10V2KX-5GP
(0.1uFx1)
2
1
1D05V_VTT AA19 VCCASW1 C2425
0.803A VCCIO34 T26 1D05V_VTT
SCD1U10V2KX-5GP
Decap Decap AA21
2
VCCASW2
0.001A
C2403
SC10U6D3V5KX-1GP
C2404
SC10U6D3V5KX-1GP
C2406
SC1U6D3V2KX-GP
C2405
SC1U6D3V2KX-GP
C2419
SC1U6D3V2KX-GP
AA24 M26 +5VA_PCH_VCC5REFSUS
VCCASW3 V5REF_SUS
1
1
AA26 3D3V_S0 5V_S0
Clock and Miscellaneous

VCCASW4 +VCCA_USBSUS
AN23
2
2
DCPSUS4
AA27 VCCASW5
2
VCCSUS3_3_1 AN24 3D3V_S5
AA29 VCCASW6 DY C2437
SC1U10V2KX-1GP 83.R0304.A8F
D2402
CH751H-40PT-GP
2
AA31 VCCASW7 2nd = 83.R3004.A8F
0.001A 3rd = 83.R2004.B8F R2407
1
AC26 P34 +5VS_PCH_VCC5REF 1 2
C VCCASW8 V5REF C
AC27 10R2J-2-GP
VCCASW9
1
1D05V_VTT N20 3D3V_S5
VCCSUS3_3_2 C2427
0.075A
PCI/GPIO/LPC
AC29 VCCASW10
L2402 N22 SC1U10V2KX-1GP
2
+1.05VS_VCCA_A_DPL VCCSUS3_3_3
1 2 AC31 VCCASW11
1
IND-10UH-218-GP P20 3D3V_S0
VCCSUS3_3_4
1
1
C2408
68.10050.10Y AD29 C2428

SC10U6D3V5KX-1GP
C2407 VCCASW12 SC1U6D3V2KX-GP

2nd = 68.1001F.10N P22 Voltage Rail Voltage(V) Iccmax(A)
DY
2
VCCSUS3_3_5
3rd = 68.1001E.10N SC1U6D3V2KX-GP AD31
2
VCCASW13
1
4th = 68.10090.10B V_PROC_IO 1.05 0.002
W21 AA16 C2430
VCCASW14 VCC3_3_1 SCD1U10V2KX-5GP V5REF 5 0.001
2
W23 W16 3D3V_S0
VCCASW15 VCC3_3_8 V5REF_Sus 5 0.001
L2403
0.075A
W24 VCCASW16 VCC3_3_4 T34
1 2 +1.05VS_VCCA_B_DPL Vcc3_3 3.3 0.178
1
IND-10UH-218-GP W26 C2431
VCCASW17
1
1
C2409
68.10050.10Y SCD1U10V2KX-5GP VccADAC 3.3 0.063

DY
SC10U6D3V5KX-1GP
2nd = 68.1001F.10N C2410 W29 3D3V_S0
2
VCCASW18 VccADPLLA 1.05 0.075
3rd = 68.1001E.10N SC1U6D3V2KX-GP
2
4th = 68.10090.10B W31 VCCASW19 VCC3_3_2 AJ2

VccADPLLB 1.05 0.075
1
W33 VCCASW20
VCCIO5 AF13 C2429 VccCore 1.05 1.73
SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC
VccDMI 1.1 0.047
AH13 1D05V_VTT
VCCIO12
1
0.167A X00 VccIO 1.05 3.799

B C2411 B
VCCVRM Y49 VCCVRM4 VCCIO13 AH14
1
SCD1U10V2KX-5GP VccASW 1.05 0.803
2
C2432
AF14 SC1U6D3V2KX-GP VccSPI 3.3 0.01
2
+1.05VS_VCCA_A_DPL VCCIO6
BD47 VCCADPLLA
SATA
AK1 VccDSW3_3 3.3 0.001
+1.05VS_VCCA_B_DPL VCCAPLLSATA
BF47 VCCADPLLB +V1.05S_VCCAPLL_SATA3 1 TP2403 TPAD14-OP-GP VccDFTERM 1.8 0.002
1D05V_VTT +VCCDIFFCLKN
0.05A X02 VCCVRM1 AF11 VCCVRM
+VCCDIFFCLK AF17 VCCIO7
VccRTC 3.3 6uA
1 2 AF33 VCCDIFFCLKN1
R2412 0R0603-PAD AF34 VCCDIFFCLKN2 VCCIO2 AC16 VccSus3_3 3.3 0.065
1
AG34 VCCDIFFCLKN3
C2414 AC17 1D05V_VTT VccSusHDA 3.3 0.01
SC1U6D3V2KX-GP VCCIO3
2
+V1.05S_SSCVCC AG33 VCCSSC VCCIO4 AD17 VccVRM 1.5 0.147
1
VccClkDMI 1.05 0.075
+VCCSST V16 C2435
DCPSST
1
C2415 1D05V_VTT SC1U6D3V2KX-GP VccSSC 1.05 0.095
2
SCD1U10V2KX-5GP
T17 T21 VccDIFFCLKN 1.05 0.05
2
TP2406 DCPSUS DCPSUS1 VCCASW22

1 V19 DCPSUS2 VccALVDS 3.3 0.001
MISC
1D05V_VTT TPAD14-OP-GP V21

1D05V_VTT VCCASW23 VccTX_LVDS
R2403 0.002A 1.8 0.04
CPU
BJ8
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
V_PROC_IO
C2418
C2420
1 2 +VCCDIFFCLK T19 Refer to PCH EDS V1.5

VCCASW21
1
+3VS_+1.5VS_HDA_IO
A
3D3V_S5 <Variant Name>
(General DC Characteristicschipset) A
1
X02 C2417
0R0402-PAD C2412 SC4D7U6D3V3KX-GP 0.01A
2
R2402
HDA
SC1U6D3V2KX-GP A22 P32 1 2

Wistron Corporation
RTC
2
RTC_AUX_S5 VCCRTC VCCSUSHDA

0R0402-PAD
1
1D05V_VTT 6uA X02 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PANTHER-GP-NF Taipei Hsien 221, Taiwan, R.O.C.
R2404 0.095A C2433
71.PANTH.00U
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Title
C2421
C2422
1 2 +V1.05S_SSCVCC SCD1U10V2KX-5GP
1
PCH ( POWER2 )
1
X02 0R0402-PAD
C2436
C2413 SC1U6D3V2KX-GP VCCSUSHDA need to be at either 3.3V or 1.5V.
2
SC1U6D3V2KX-GP A3
vinafix
All the CODEC I/O Voltages need to be at the same
2
level either 3.3 V or 1.5 V. Date: Friday, December 30, 2011 Sheet 24 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = PCH
PCH1I 9 OF 10
AY4 VSS159 VSS259 H46

AY42 VSS160 VSS260 K18
B11 VSS163 VSS263 K46
B15 VSS164 VSS264 K7
B19 VSS165 VSS265 L18
B23 VSS166 VSS266 L2
D B27 VSS167 VSS267 L20 D
PCH1H 8 OF 10 B31 L26
VSS168 VSS268
H5 VSS0 B35 VSS169 VSS269 L28
B39 VSS170 VSS270 L36
AA17 VSS1 VSS80 AK38 B7 VSS171 VSS271 L48
AA2 VSS2 VSS81 AK4 F45 VSS172 VSS272 M12
AA3 VSS3 VSS82 AK42 BB12 VSS173 VSS273 P16
AA33 VSS4 VSS83 AK46 BB16 VSS174 VSS274 M18
AA34 VSS5 VSS84 AK8 BB20 VSS175 VSS275 M22
AB11 VSS6 VSS85 AL16 BB22 VSS176 VSS276 M24
AC19 VSS13 VSS92 AL27 BC14 VSS183 VSS283 M46
AC2 VSS14 VSS93 AL31 BC18 VSS184 VSS284 M8
AC21 VSS15 VSS94 AL33 BC2 VSS185 VSS285 N18
AC24 VSS16 VSS95 AL34 BC22 VSS186 VSS286 P30
AC33 VSS17 VSS96 AL48 BC26 VSS187 VSS287 N47
AC34 VSS18 VSS97 AM11 BC32 VSS188 VSS288 P11
AC48 VSS19 VSS98 AM14 BC34 VSS189 VSS289 P18
AD10 VSS20 VSS99 AM36 BC36 VSS190 VSS290 T33
AD11 VSS21 VSS100 AM39 BC40 VSS191 VSS291 P40
AD19 VSS24 VSS103 AM46 BD46 VSS194 VSS294 P7
AD24 VSS25 VSS104 AM7 BD5 VSS195 VSS295 R2
C AD26 AN2 BE22 R48 C
AD27 VSS27 VSS106 AN29 BE26 VSS197 VSS297 T12
AD33 VSS28 VSS107 AN3 BE40 VSS198 VSS298 T31
AD34 VSS29 VSS108 AN31 BF10 VSS199 VSS299 T37
AD36 VSS30 VSS109 AP12 BF12 VSS200 VSS300 T4
AD37 VSS31 VSS110 AP19 BF16 VSS201 VSS301 W34
AD40 VSS35 VSS114 AP38 BF26 VSS205 VSS305 V11
AD43 VSS37 VSS116 AP42 BD3 VSS207 VSS307 V26
AD8 VSS40 VSS119 AR2 BF40 VSS210 VSS310 V31
AE2 VSS41 VSS120 AR48 BF8 VSS211 VSS311 V36
AE3 VSS42 VSS121 AT11 BG17 VSS212 VSS312 V39
AF10 VSS43 VSS122 AT13 BG21 VSS213 VSS313 V43
AF12 VSS44 VSS123 AT18 BG33 VSS214 VSS314 V7
AD14 VSS45 VSS124 AT22 BG44 VSS215 VSS315 W17
AD16 VSS46 VSS125 AT26 BG8 VSS216 VSS316 W19
AF16 VSS47 VSS126 AT28 BH11 VSS217 VSS317 W2
AF26 VSS50 VSS129 AT34 BH19 VSS220 VSS320 Y12
AF27 VSS51 VSS130 AT39 H10 VSS221 VSS321 Y38
B B
AF4 VSS55 VSS134 AU24 BH35 VSS225 VSS325 Y8
AF42 VSS56 VSS135 AU30 BH39 VSS226 VSS328 BG29
AF46 VSS57 VSS136 AV16 BH43 VSS227 VSS329 N24
AF5 VSS58 VSS137 AV20 BH7 VSS228 VSS330 AJ3
AF7 VSS59 VSS138 AV24 D3 VSS229 VSS331 AD47
AF8 VSS60 VSS139 AV30 D12 VSS230 VSS333 B43
AG19 VSS61 VSS140 AV38 D16 VSS231 VSS334 BE10
AG2 VSS62 VSS141 AV4 D18 VSS232 VSS335 BG41
AG31 VSS63 VSS142 AV43 D22 VSS233 VSS337 G14
AG48 VSS64 VSS143 AV8 D24 VSS234 VSS338 H16
AH11 VSS65 VSS144 AW14 D26 VSS235 VSS340 T36
AH3 VSS66 VSS145 AW18 D30 VSS236 VSS342 BG22
AH36 VSS67 VSS146 AW2 D32 VSS237 VSS343 BG24
AH39 VSS68 VSS147 AW22 D34 VSS238 VSS344 C22
AH40 VSS69 VSS148 AW26 D38 VSS239 VSS345 AP13
AH42 VSS70 VSS149 AW28 D42 VSS240 VSS346 M14
AH46 VSS71 VSS150 AW32 D8 VSS241 VSS347 AP3
AH7 VSS72 VSS151 AW34 E18 VSS242 VSS348 AP1
AJ19 VSS73 VSS152 AW36 E26 VSS243 VSS349 BE16
AJ21 VSS74 VSS153 AW40 G18 VSS244 VSS350 BC16
AJ24 VSS75 VSS154 AW48 G20 VSS245 VSS351 BG28
AJ33 VSS76 VSS155 AV11 G26 VSS246 VSS352 BJ28
AJ34 VSS77 VSS156 AY12 G28 VSS247
AK12 VSS78 VSS157 AY22 G36 VSS248
AK3 VSS79 VSS158 AY28 G48 VSS249
H12 VSS250
PANTHER-GP-NF H18 VSS251
71.PANTH.00U H22 VSS252
A H24 VSS253 <Variant Name> A
H26 VSS254
H30 VSS255
H32
H34
VSS256
VSS257
Wistron Corporation
F3 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS258 Taipei Hsien 221, Taiwan, R.O.C.
Title
PANTHER-GP-NF
71.PANTH.00U PCH ( VSS )
A3

5
4 3 2
1
25 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3

5
4 3 2
1
26 of 104
a f i x
Vin
SSID = KBC 5 4 3 2 1
PCB VER AD(GPIO91) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
VBAT 3D3V_S0 VBAT X00 100.0K 10.0K 3.0V VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_AUX_KBC X01 100.0K 20.0K 2.75V DV14_UMA 100.0K 10.0K(64.10025.6DL) 3.0V
X02 1228
1
R2702 X00 DV14_DIS 100.0K 20.0K(64.20025.6DL) 2.75V
1 2 VBAT X02 100.0K 33.0K 2.48V R2710 DV15_UMA with HDMI 100.0K 33.0K(64.33025.6DL) 2.48V
1
R2724 20KR2F-L-GP DV15_UMA without HDMI 100.0K 47.0K(64.47025.6DL) 2.24V
0R3J-0-U-GP
2
C2702 C2703 A00 100.0K 47.0K 2.24V TBD 100.0K 64.9K(64.64925.6DL) 2.0V
R2771 0127 A00 Modify: SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP 33KR2F-GP TBD 100.0K 76.8K(64.76825.6DL) 1.87V
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
2D2R3-1-U-GP un-stuff C2707,C2709 PCB_VER_AD Reserved 100.0K 64.9K 2.0V MODEL_ID_DET TBD 100.0K 100.0K(64.10035.6DL) 1.65V
on ST2 batch run stage. TBD 100.0K 143.0K(64.14335.6DL) 1.358V
1
3D3V_AUX_KBC_VCC R2726 Reserved 100.0K 76.8 1.87V R2739 TBD 100.0K 174.0K(64.17435.6DL) 1.204V
1
C2717 100KR2F-L1-GP C2718 100KR2F-L1-GP TBD 100.0K 215.0K(64.21535.6DL) 1.048V

SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_AUX_S5
2
X02
C2701
C2704
C2705
C2706
C2707
C2708
Reserved 100.0K 100.0K 1.65V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
EC_VBKUP 1
C2709
C2710
2
0R0402-PAD R2794
RTC_AUX_S5 DY Reserved 100.0K 143.0K 1.358V DY
DY DY DY
2
D D
2
115
102
114
Reserved 100.0K 174.0K 1.204V
19
46
76
88
75
4
U2701A 1 0F 2 C2711
1 2
DY EC_AGND Reserved 100.0K 215.0K 1.048V EC_AGND
VCC1
VCC2
VCC3
VCC4
VCC5
VSBY
VBKUP
AVCC
VDD
SC220P50V2KX-3GP
EC_AGND R2778
C2714 1 2 SCD1U10V2KX-5GP 104 7 PLT_RST#_EC
1
0R0402-PAD
2
X02
EC_AGND VREF LRESET#/GPIOF7 PLT_RST# 5,18,31,65,71,83
2 CLK_PCI_KBC 18
LCLK/GPIOF5
40 AD_IA 97 3 LPC_FRAME# 21,71 LPC_AD[3..0] 21,71
PCB_VER_AD GPIO90/AD0 LFRAME#/GPIOF6 LPC_AD3
98 1
GPIO91/AD1 LAD3/GPIOF4 LPC_AD2
38 PSID_EC 99 128
CPU_THRM GPIO92/AD2 LAD2/GPIOF3 LPC_AD1
100 127
SYS_THRM GPIO93/AD3 LAD1/GPIOF2 LPC_AD0
X00 108
GPIO5/AD4 LAD0/GPIOF1
126
VGA_THRM 96 125
28 VGA_THRM GPIO4/AD5 SERIRQ/GPIOF0 INT_SERIRQ 21
1 USBCHARGER_CB0 95 8 PM_CLKRUN#_EC 19
TPAD14-OP-GP TP2711 MODEL_ID_DET GPIO3/AD6 GPIO11/CLKRUN# PANEL_BLEN
94 9
GPIO7/AD7 GPIO65/SMI# ECSCI#_KBC U2701B 2 0F 2
29 KCOL[16..0] 69
ECSCI#/GPIO54
28 FAN1_DAC
101
GPIO94/DA0 GPIO10/LPCPD#
124 BOOST_MODE# 40 X00
105 121 31 53 KCOL0
40 AD_IA_HW GPIO95/DA1 GPIO85/GA20 H_A20GATE 22 28 FAN_TACH1 GPIO56/TA1 KBSOUT0/GPOB0/JENK#
SERIES_ID 106 122 H_RCIN# 22 31 PCIE_WAKE# 63 52 KCOL1
GPIO96/DA2 KBRST#/GPIO86 GPIO14/TB1 KBSOUT1/GPIOB1/TCK KCOL2
36,42 IMVP_PWRGD 107 19,36,37,47 PM_SLP_S3# 64 51
GPIO97/DA3 GPIO1/TB2 KBSOUT2/GPIOB2/TMS KCOL3
50
KBSOUT3/GPIOB3/TDI KCOL4
68 CHG_AMBER_LED# 32 49
BATLOW#_EC GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# KCOL5
79 27 BLON_OUT 49 29 KBC_BEEP 118 48
ECSMI#_KBC GPIO02 GPIO52/PSDAT3/RDY# AD_IA_HW2 GPIO21/B_PWM KBSOUT5/GPIOB5/TDO KCOL6
6 25 AD_IA_HW2 40 86 OVER_CURRENT_P8# 62 47
GPIO24 GPIO50/PSCLK3/TDO KBC_GPIO32 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# KCOL7
69 CAP_LED# 109 11 PWR_CHG_AD_OFF 38 TPAD14-OP-GP TP2714 1 65 43
GPIO30/F_WP# GPIO27/PSDAT2 GPIO32/D_PWM KBSOUT7/GPIOB7
36 S5_ENABLE 14
GPIO34/CIRRXL GPIO26/PSCLK2
10 CARD_WLAN_OUT# 65 X02 1230 68 WLAN_LED#
KBC_GPIO66
22
GPIO45/E_PWM KBSOUT8/GPIOC0
42 KCOL8
KCOL9
68 BATT_WHITE_LED# 15 71 TPDATA 69 TPAD14-OP-GP TP2715 1 81 41
GPIO36 GPIO35/PSDAT1 KBC_GPIO33 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# KCOL10
39 BAT_IN# 80 72 TPCLK 69 <------ TP TPAD14-OP-GP TP2716 1 66 40
GPIO41/F_WP# GPIO37/PSCLK1 GPIO33/H_PWM KBSOUT10&P80_CLK/GPIOC2 KCOL11
82 LID_CLOSE# 17 68 PWRLED# 16 39
GPIO42/TCK GPIO40/F_PWM KBSOUT11&P80_DAT/GPIOC3 KCOL12
19 RSMRST#_KBC 20 38
GPIO43/TMS KBSOUT12/GPIO64 KCOL13
X00 19,46 PM_SLP_S4# 21
GPIO44/TDI GPIO17/SCL1/N2TCK
70 BAT_SCL 39,40 <------ BATTERY / CHARGER X00 KBSOUT13/GPIO63
37
26 69 23 36 KCOL14
22,92,93 DGPU_PWROK GPIO51/N2TCK GPIO22/SDA1/N2TMS BAT_SDA 39,40 21 ME_UNLOCK GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62
ECSWI#_KBC 123 67 113 35 KCOL15
82
GPIO67N2TMS GPIO73/SCL2
68
SML1_CLK 20 <------PCH / eDP 65 E51_RxD
111
GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT
34 KCOL16
65 WIFI_RF_EN GPIO75 GPIO74/SDA2 SML1_DATA 20 65 E51_TxD GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16
BLUETOOTH_EN 83 119 PROCHOT_EC 33 KBC_GPIO57 1
65 BLUETOOTH_EN GPIO76 GPIO23/SCL3 GPIO57/KBSOUT17 TP2717 TPAD14-OP-GP
Layout Note: 19,36 S0_PWR_GOOD 84
GPIO77 GPIO31/SDA3
120
24
RTCRST_ON 21
PM_LAN_ENABLE 31 19 PCH_SUSCLK_KBC 77 54 KROW0
KROW[7..0] 69
GPIO47/SCL4 GPIO0/EXTCLK KBSIN0/GPIOA0/N2TCK KROW1
Need very close to EC GPIO53/SDA4
28 LCD_TST_EN 49 29 AMP_MUTE# 30
GPIO55/CLKOUT/IOX_DIN_DIO KBSIN1/GPIOA1/N2TMS
55
33R2J-2-GP 1 R2736 2 EC_SPI_CS#_C 90 1 R2792 2 LCD_TST 49 56 KROW2
21,60 SPI_CS0#_R F_CS0# 0R0402-PAD KBSIN2/GPIOA2
33R2J-2-GP 1 R2719 2 EC_SPI_CLK_C 92 ECRST# 85 57 KROW3
C 21,60 SPI_CLK_R
60
21,60
EC_SPI_DI_C
SPI_SI_R
33R2J-2-GP 1 R2722 2
EC_SPI_DI_C
EC_SPI_DO_C
86
87
F_SCK
F_SDI&F_SDIO1
F_SDIO&F_SDIO0
PSL_OUT_GPIO71#
PSL_IN2_GPI06#
74
93
PSL_OUT#
PSL_IN2#
X02
1D05V_VTT R2721
VCC_POR# KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
58
59
KROW4
KROW5
C
91 73 PSL_IN1# 143R2J-GP 2 PECI 13 60 KROW6
65 CARD_WPAN_OUT# GPIO81/F_WP# PSL_IN1_GPI70# 5,22 H_PECI PECI KBSIN6/GPIOA6
1 2 EC_VTT 12 61 KROW7
VTT KBSIN7/GPIOA7
1
117 R2720
19 PM_PWRBTN#
112
GPIO20/TA2/IOX_DIN_DIO X02 0R0402-PAD C2716 NPCE885PA0DX-GP
19 AC_PRESENT GP/I/O84/IOX_SCLK/XORTR#
110 44 KBC_VCORF
SCD1U16V2KX-3GP
61 USB_PWR_EN#
2
GPO82/IOX_LDSH/TEST# VCORF
1
AGND
GND1
GND2
GND3
GND4
GND5
GND6
C2712
SC1U10V3KX-4GP-U Layout Note: X00
2
Need very close to EC
NPCE885PA0DX-GP R2766
X02
18
45
78
89
116
5
103
0R0402-PAD
D2702 2ECSWI#_KBC
Layout Note: 1
20 EC_SWI# 1
EC_AGND
20 EC_SWI#
Need very close to EC R2764
ECSWI#_KBC 0R0402-PAD X02
DY 3
22 EC_SCI# 1 2 ECSCI#_KBC
3D3V_AUX_KBC
R2765
0R0402-PAD
Layout Note: 2
83.00016.K11 R2723
1 2 Connect GND and AGND planes via either 3D3V_AUX_S5 BAS16-6-GP 0R0402-PAD X02
2nd = 83.00016.F11 1 2 ECSMI#_KBC
0R resistor or connect directly. 22 EC_SMI#
1
X02
1
R2737 ECRST# D2703
Ins 100KR2J-1-GP 20100712 V1.5 EC_AGND R2705 22 EC_SCI# 1
10KR2J-3-GP R2793
ECSCI#_KBC 0R2J-2-GP
DY 3
SC1U6D3V2KX-GP
2
1 2 BATLOW#_EC
19 BATLOW# DY
1
SERIES_ID C2715 2
83.00016.K11
E
1
B BAS16-6-GP
28,36,86 PURE_HW_SHUTDOWN# 2nd = 83.00016.F11
2
R2738 PROCHOT_EC Q2701 R2761
Vostro100KR2J-1-GP MMBT3906-4-GP DY 0R0402-PAD X02
C
D2704 1 2 PANEL_BLEN
G
17 L_BKLT_EN
Q2702 84.T3906.A11 22 EC_SMI# 1
2
2N7002BK-GP R2733
0R0402-PAD X02 2nd = 84.03906.F11
1
ECSMI#_KBC
DY 3
100KR2J-1-GP
R2732 S D H_PROCHOT#_EC
1 2 H_PROCHOT# 5,40
2
83.00016.K11
B X00
EC GPIO standard PH/PL B
1
84.07002.I31 BAS16-6-GP
2nd = 83.00016.F11
2
C2720
SC47P50V2JN-3GP
2nd = 84.2N702.W31
2
3D3V_AUX_KBC
3rd = 84.2N702.J31
C502 : check list 1.5 RN2701
BAT_SCL 3 2
BAT_SDA 4 1
3D3V_AUX_S5
Power Switch Logic(PSL) CLK_PCI_KBC CPU_THRM C2719 2 SRN4K7J-8-GP

DY1SCD1U10V2KX-5GP
2
3D3V_AUX_S5 BAT_IN# R2706 1 2 100KR2J-1-GP

R2734
KBC CLK
1
SYS_THRM C2721 2
3D3V_AUX_S5
330KR2J-L1-GP
C2722 R2740 DY1SCD1U10V2KX-5GP PCIE_WAKE#
1 2
EMI 22R2J-2-GP R2776
1 2
100KR2J-1-GP
DY
1
VGA_THRM R2708 1 2 10KR2J-3-GP

DY
2
SCD1U10V2KX-5GP ECRST# R2707 1 2 10KR2J-3-GP

1CLK_PCI_KBC_EMI 2
R2704
S
330KR2J-L1-GP X00
2
R2767 PSL_OUT# 1 2KBC_ON#_GATE G Q2703 EC_AGND BOOST_MODE# R2711 1 2 10KR2J-3-GP

0R0402-PAD
20KR2J-L2-GP DY
DY R2791
G
R2735 DMP2130L-7-GP
1
PSL_IN2# X02 1230

68 KBC_PWRBTN# 1 2 84.02130.031 0R2J-2-GP
X02 X02 1230 D
2nd = 84.00102.031 OVER_CURRENT_P8# R2713 1
DY 2 100KR2J-1-GP
3rd = 84.03413.A31
1
D
R2768
0R0402-PAD 4th = 84.02301.G31 3D3V_S0
1 2 PSL_IN1#
40 AC_IN#
C2723 FAN_TACH1 R2712 1 2 10KR2J-3-GP
X02 3D3V_AUX_KBC DY SC4D7P50V2CN-1GP
2
X00
X00
E51_RxD R2715 1 2 10KR2J-3-GP
DY
BLUETOOTH_EN R2714 1 2 10KR2J-3-GP
3D3V_AUX_KBC DY
3D3V_S5
A S5_ENABLE 1
R2709
10KR2J-3-GP
2 LID_CLOSE# R2774 1 2 100KR2J-1-GP A
D
Q2706
2N7002BK-GP
<Variant Name>
KBC_ON#_GATE G
84.07002.I31 RN2706
Wistron Corporation
2nd = 84.2N702.W31 RSMRST#_KBC 4
DY 1 Taipei Hsien 221, Taiwan, R.O.C.
S
S0_PWR_GOOD 3 2
3rd = 84.2N702.J31 SRN100KJ-6-GP
Title
KBC Nuvoton NPCE795
vinafix
SPI Shared Flash ROM A2
X02
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = Thermal
Fan controller G991 5V_S0
Thermal sensor NCT7718W 1

R2802
DY 2 FON# 1
U2802
FON# GND 8
5V_S0 0R2J-2-GP 2 VIN GND 7
FAN_VCC 3 6
VOUT GND
D 3D3V_S0 27 FAN1_DAC 4 VSET GND 5 D
1
SC10U6D3V5KX-1GP
*Layout* 10 mil
C2803 C2804
1
C2805
C2802 NCT3940S-A-GP SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP
For linear FAN
2
SCD1U10V2KX-5GP
74.03940.A71
2
2nd = 74.02793.A31
3rd = 74.00991.031
Layout notice : FAN1

Both DXN and DXP routing 10 mil R2807
trace width and 10 mil spacing. and route has to be away from the high noise area. X02 AFTP2803 1 5
27 FAN_TACH1 1 2 FAN_TACH1_C 3
Put the C2807 2200pF to close the NCT7718W
2
NCT7718_DXP 0R0402-PAD FAN_VCC

*Layout* 15 mil 1
U2801 4
SC2200P50V2KX-2GP
SCD1U16V2KX-3GP
1
2ND = 84.03904.P11
CH551H-30PT-GP
3
2
84.03904.L06
D2802
DY C2806
EC2801
1 VDD SCL 8 THM_SML1_CLK 20,86 HR-CON3-GP
SC470P50V2KX-3GP
C2810
R2808 DY 1 C2807 2 7 THM_SML1_DATA 20,86
2
D+ SDA
1
NTC-100K-8-GP Q2801 SC2200P50V2KX-2GP ALERT# C2809
3 6 DY
2
PMBS3904-1-GP D- ALERT# SC4D7U6D3V3KX-GP
4 5 DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
T_CRIT# GND
1
C2808
C2812
NCT7718_DXN Reserved for
2
2.System Sensor, Put on palm rest NCT7718W -GP DY DY signal quality
improvement.
20.F1716.003
2
C 83.R5003.C8F C
74.07718.0B9 AFTP2802 1FAN_TACH1_C 2nd = 83.R5003.G8H
2nd = 20.D0246.103
THERM_SYS_SHDN# 1 2 T_CRIT# 3rd = 83.R5003.H8H
R2813 0R0402-PAD
3D3V_S0
4th = 83.5R003.08F
AFTP2801 1FAN_VCC
X02
ALERT# R2815
R5
1 218K7R2F-GP
X02 1227
T_CRIT# R2814 1 22KR2F-3-GP
R7
VGA Thermal sensor P2800
86 P2800_VGA_DXP P2800_VGA_DXP
U2805
Layout notice : DY
1
Both DXN and DXP routing 10 mil DY 3D3V_S0_thermal 5 4 VGA_THRM_TDR 1R2818 2 0R2J-2-GP VGA_THRM 27
C2813 VCC TDR VGA_THRM_TDL
trace width and 10 mil spacing. 6 DXP TDL 3 1R2819 2 0R2J-2-GP
SC2200P50V2KX-2GP 7 DY 2 DY
2
DXN GND
1
8 OTZ ADJ 1
86 P2800_VGA_DXN P2800_VGA_DXN R2816
100KR2J-1-GP
P2800EB0-GP
DY
B B
74.02800.B71
2
1 2 3D3V_S0_thermal 3D3V_S0
3D3V_S0
R2817 0R0402-PAD X02-0311 Add R2816& R2817 to
option VGA_THRM
1
1
DY C2814 X00
and DY the circuit DY R2809
Q2802 100KR2J-1-GP
2
2N7002BK-GP
SCD1U10V2KX-5GP
2
27,36,86 PURE_HW _SHUTDOW N# D S THERM_SYS_SHDN#
84.07002.I31
G
2nd = 84.2N702.W31
1
C2811
SCD1U10V2KX-5GP DY 3rd = 84.2N702.J31
2
3D3V_S0 3D3V_S0 3D3V_S0
86.9 
1
R2820 DY U2804
470KR2F-GP R2801
1 DY 2 G709_SET 1 5 U2804_5 2 DY 150R2F-1-GP
1
SET VCC
1
24K3R2F-1-GP R2805
2 GND DY
2
THERM_SYS_SHDN# 1 DY 0R2J-2-GP
2 T8_G709 3 4 DY
R2812 OUT# HYST C2816
A <Variant Name> A
2
SCD1U10V2KX-5GP
G709T1UF-GP 3D3V_S0
74.00709.A7F U2804_4 2 DY 0R2J-2-GP
R2810
1
Wistron Corporation
2
R2811
DY 0R2J-2-GP
1
R(K)= 0.0012*T^2- 0.9308T+ Title
Thermal P2800/Fan Controllor P2793

96.147 Size Document Number Rev
A3

5
4 3 2
1
28 of 104
a f i x
Vin
5 4 3 2 1
SSID = AUDIO X01 1111

R2909
From PCH
SB_SPKR_R 1 2 HDA_SPKR 21
3D3V_S0 0R2J-2-GP
2
1D8V_S0
1
R2942 D2902
R2941 1 2 AUD_PC_BEEP 3 BAT54C-U-GP
10KR2F-2-GP AUD_HP1_JD# 82
83.00054.Q81
1
11KR2F-L-GP 2nd = 83.R2003.E81
R2913 3rd = 83.00054.X81
1
D AUD_SENSE_A 100KR2J-1-GP 4th = 83.BAT54.081 D
R2910 5V_S0 AUD_5V
R2923 X02
AUD_PC_BEEP X02 1230 KBC_BEEP_R 1 2 KBC_BEEP 27
2
1
R2911 0R0805-PAD
1 2 EXT_MIC_JD# 82 1 2
C2919 0R2J-2-GP From EC
DY SC1000P50V3JN-GP-U
Trace width>15 mils X020R0805-PAD
2
18KR2F-GP AUD_5V R2912 1 2
1
C2936 C2935 3D3V_S0 AUD_3D3V_1D5V
SC10U6D3V5MX-3GP
1
AUD_5V SCD1U10V2KX-5GP SCD1U10V2KX-5GP R2905
SC1U10V2KX-1GP
2
C2939
C2937
1 2
2
0R0402-PAD X02
SC1U10V2KX-1GP
U2901 X00
SC10U6D3V5MX-3GP
C2938
1
1
18 20 MIC_IN_L_C C2947 1 2 SC1U10V2KX-1GP MIC_IN_L MIC_IN_L 82
VA LINEIN_L
C2940
12 21 MIC_IN_R_C C2950 1 2 SC1U10V2KX-1GP MIC_IN_R
DY VA_HP LINEIN_R MIC_IN_R 82
1
36 1 AUD_SPK_L+ AUD_SPK_L+ 58
VP_L SPKR_L+ AUD_SPK_L- R2944 R2943
7 VP_R SPKR_L- 2 AUD_SPK_L- 58
4D3KR2F-GP 4D3KR2F-GP
VCOM 19 6 AUD_SPK_R+
SC10U6D3V5MX-3GP
VCOM SPKR_R+ AUD_SPK_R+ 58
5 AUD_SPK_R- AUD_SPK_R- 58
2
SPKR_R-
1
VHP_FILT- 11 VREFOUT_B
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
VHP_FILT VHP_FILT- PUMP_FLYP C2948 1
X00 17 VREF_FILT FLYP 8 2 SC2D2U10V3KX-1GP X00
X00 2 1 9 PUMP_FLYN
2
FLYN
2
C2946
C2945
C2944
3D3V_S0 SCD1U10V2KX-5GP C2941 28 C2951
C VL_IF VREFOUT_B SC1U10V2KX-1GP C
AUD_3D3V_1D5V 30 VL_HD VREFOUT_B 22
2 1 24 VREFOUT_C
1
SCD1U10V2KX-5GP C2942 VREFOUT_C
82 INT_MIC_L_R 2 1 INT_MIC_L_R_C 23 13 AUD_HP1_JACK_L R2916 1 249D9R2F-GP AUD_HP1_JACK_L2 82
SC1U10V2KX-1GP C2943 MICIN HPOUT_L AUD_HP1_JACK_R R2917 1
HPOUT_R 15 249D9R2F-GP AUD_HP1_JACK_R2 82
AUD_SENSE_A 25 SENSE_A
27 DMIC_SDA/GPIO0 HPREF 14
X02 1216 26 DMIC_SCL/GPIO1
R2945
INT_MIC_L_R1 2 VREFOUT_C 21 HDA_SDIN0 1 2 ACZ_SDATAIN0_R 33 16
82 INT_MIC_L_R R2915 33R2F-3-GP SDI AGND
21 HDA_CODEC_SDOUT 31 SDO
2K2R2J-2-GP X00 C2924 2 DY1SC22P50V2JN-4GP HDA_CODEC_BITCLK_R 10
GND
2
21 HDA_CODEC_BITCLK R29061 2 0R0402-PAD 32 BITCLK GND 37

C2952 21 HDA_CODEC_SYNC 34
SC1U10V2KX-1GP 21 HDA_CODEC_RST#
X02 35
SYNC
3
1
AUD_PC_BEEP RESET# PGND_L

29 PCBEEP PGND_R 4
CS4213D-CNZR-GP
71.04213.003
2 1
3D3V_S0
R2918 DY 10KR2J-3-GP
27 AMP_MUTE#
Depop sound
B B
3
D2901
BAS16-6-GP
POP
3D3V_S0
83.00016.K11
1
AUD_HP1_JACK_R2
1
2nd = 83.00016.F11 R2926 AUD_HP1_JACK_L2

POP 100KR2J-1-GP
R2925
E
2
AUD_PD#_C 2 1 AUD_PD#_C1 B
POP Q2901 POP
3
MMBT3906-4-GP Q2902
C
1KR2J-1-GP 84.T3906.A11 HP_MUTE 2 POP 1HP_MUTE_R R2928 2 POP 1 1KR2J-1-GP HP_MUTE_RC2 1 POPPMBS3904-1-GP
2nd = 84.03906.F11 R2927
3
1KR2J-1-GP
2
1
R2929 2 POP 1 1KR2J-1-GP HP_MUTE_RC1 1 POP
POP C2949 84.03904.L06 Q2903
SC10U6D3V5MX-3GP 2ND = 84.03904.P11 PMBS3904-1-GP
2
2
84.03904.L06
2ND = 84.03904.P11
A <Variant Name> A
Wistron Corporation
Title
Audio Codec CS4213D
A3 X02
vinafix
5
1
29 of 104
a f i x
Vin
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
30 of 104
a f i x
Vin
5 4 3 2 1
3D3V_S0
1
X02-20110414
EVDD10
LAN CHIP 3D3V_LAN_S5 DYR3102
10KR2J-3-GP
R3117 X02
1CLK_LAN_REQ#_EN 2
1 2
1
0R0603-PAD
R3101
1
C3106 10KR2J-3-GP
SC1U10V3ZY-6GP Q3101
D
DY PMBS3904-1-GP
D
60 mils
2
DVDD10
84.03904.L06
L3101 R3115 X02 R3113 2ND = 84.03904.P11
LANOUP_1.05S 1 2CTRL10A_R 1 2 DVDD10 2K49R2F-GP
IND-4D7UH-192-GP 0R0603-PAD 1 2 LANRSET
1
1
C3113 C3109 C3114 C3117 C3112 C3123 C3116
68.4R750.20C C3120 C3115 CLK_LAN_REQ#_R 2
DY 3
GIGAGIGAGIGA PCIE_CLK_LAN_REQ# 20
3D3V_LAN_S5
3D3V_LAN_S5
3D3V_LAN_S5
3D3V_LAN_S5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
2nd = 68.4R71G.10G
2
2
R3133
LANXOUT
SCD1U16V2ZY-2GP X5R 1 2
DY
DVDD10
DVDD10
LANXIN
3rd = 68.4R71E.10R
GPO
0R2J-2-GP
3D3V_LAN_S5 For Switch Regulator enable

RTL8105E-VD : 71.08105.B03 3D3V_LAN_S5
40 mils RTL8111F : 71.08111.N03 X00
2
48
47
46
45
44
43
42
41
40
39
38
37
1
1
C3118 C3121 C3119 U3101 R3105
49 0R0402-PAD
AVDD33
AVDD33
AVDD10
CKXTAL2
CKXTAL1
AVDD33
DVDD10
LED0
DVDD3
LED1/EESK
RSET
GPO/SMBALERT
GND
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
X02
1
AVDD33_REG LANOUP_1.05S
1
0R2J-2-GP
DY 2
R3106
59 LAN_MDI0P 1 MDIP0 REGOUT 36
2 35 AVDD33_REG
59 LAN_MDI0N MDIN0 VDDREG
C DVDD10 3 34 AVDD33_REG C
AVDD10 VDDREG ENSW REG
59 LAN_MDI1P 4 MDIP1 ENSWREG 33
R3104 5 32 EEDI/SDA
59 LAN_MDI1N MDIN1 EEDI/SDA
1 2 DVDD10 6 31
AVDD10 LED3/EEDO EECS
59 LAN_MDI2P 7 30 1 2
X02 0R0603-PAD C3101 C3111
59 LAN_MDI2N 8
MDIP2
MDIN2
EECS/SCL
DVDD10 29 DVDD10 R3107 10KR2J-3-GP
1
DVDD10 9 28 3D3V_S0
AVDD10 LANWAKE# PCIE_W AKE# 27
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
10 27 3D3V_LAN_S5
59 LAN_MDI3P MDIP3 DVDD33
11 26 ISOLATE# 2 1
59 LAN_MDI3N
2
3D3V_LAN_S5 3D3V_LAN_S5 MDIN3 ISOLATE# PLT_RST#_LAN 1KR2J-1-GP R3110

X5R 12 AVDD33 PERST# 25
1
1
DY
REFCLK_N
REFCLK_P
C3107
SMBDATA
R3109
CLKREQ#
SMBCLK
1
2
DVDD10
EVDD10
SCD1U10V2KX-5GP 15KR2J-1-GP
2
HSON
HSOP
RN3101
HSIN
HSIP
GND
2
SRN10KJ-5-GP
RTL8111F-CGT-GP
13
14
15
16
17
18
19
20
21
22
23
24
1 4
3
TPAD14-OP-GP TP3101 1 DVDD10
2 3 PLT_RST#_LAN
5,18,27,65,71,83 PLT_RST# SMBDATA_LAN
Q3104 CLK_LAN_REQ#_R
PMBS3904-1-GP 84.03904.L06 X01 1116
PCIE_TXP2
R3132 2nd = 84.03904.P11 PCIE_TXN2
1 2 CLK_PCIE_LAN
0R2J-2-GP DY CLK_PCIE_LAN# LANXOUT 1 2
3
B C3102 SC15P50V2JN-2-GP B
EVDD10 X3101
3D3V_S0 3D3V_LAN_S5 XTAL-25MHZ-155-GP
PCIE_RXP2_C
2
R3119 1 0R3J-0-U-GP PCIE_RXN2_C
DY 2 LANXIN 1 2
2
SCD1U10V2KX-4GP
C3131 C3103 SC15P50V2JN-2-GP
1
R3120 1 0R3J-0-U-GP
DY 2 R3116
3D3V_S5
84.02130.031 Q3103 RTL8111E-Stuff 82.30020.D41
2nd = 84.00102.031 DMP2130L-7-GP RTL8105E-DY 2nd = 82.30020.G71
3rd = 84.03413.A31 S
R3116 1 3rd = 82.30020.G61
D 2 10KR2J-3-GP SMBDATA_LAN
GIGA
D
1
PCIE_RXP2_C C3105 1 2 SCD1U10V2KX-5GP PCIE_RXP2 20

1
C3130 R3121 C3129 C3126 C3128 PCIE_RXN2_C C3104 1 2 SCD1U10V2KX-5GP PCIE_RXN2 20

G
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP 10KR2J-3-GP C3125

2
SC1U10V2KX-1GP PCIE_TXP2
GIGA PCIE_TXP2 20
2
PCIE_TXN2
PCIE_TXN2 20
2
1 2PM_LAN_ENABLE_R
2
R3118 20KR2J-L2-GP 3D3V_LAN_S5

CLK_PCIE_LAN 20
LAN_ENABLE_R_C
CLK_PCIE_LAN# 20
1 GIGA 2 GPO
27 PM_LAN_ENABLE R3103 1KR2J-1-GP
<Variant Name>
G
A A
Q3102
2N7002BK-GP 3D3V_LAN_S5
Wistron Corporation
2
S D PCIE_W AKE# 2
R3134 R3122 DY 110KR2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
100KR2J-1-GP Taipei Hsien 221, Taiwan, R.O.C.
84.07002.I31 EEDI/SDA Title
1 2
1
2nd = 84.2N702.W31 R3114 10KR2J-3-GP

LOM
3rd = 84.2N702.J31
A3
vinafix
5
1
31 of 104
a f i x
Vin
5 4 3 2 1
SSID = SDIO
XD_D7 1 TP3204 TPAD14-OP-GP
XD_D6/MS_BS XD_D6/MS_BS 74
XD_D5/SD_D2/MS_D5 XD_D5/SD_D2/MS_D5 74
20 CLK_PCH_48M
XD_D4/SD_D3/MS_D1 XD_D4/SD_D3/MS_D1 74
D D
XD_D3/SD_D4/MS_D4 1 TP3205 TPAD14-OP-GP
C3209 DY
1 2 RREF
SC100P50V2JN-3GP
R3201
24
23
22
21
20
19
1 2 U3201
6K2R2F-GP
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
3D3V_S0 1 18 XD_D2/SD_CMD
RREF SP10 XD_D2/SD_CMD 74
USB_PN5_R 2 17 CR_GPIO0 1 TP3201 TPAD14-OP-GP
USB_PP5_R DM GPIO0 XD_D1/SD_D5/MS_D0
43mA 3 DP SP9 16 XD_D1/SD_D5/MS_D0 74
4 15 XD_D0/SD_CLK/MS_D2
3V3_IN SP8 XD_W P/SD_D6/MS_D6 1
5 14
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
3D3V_CARD_S0 CARD_3V3 SP7 TP3206 TPAD14-OP-GP

V18 6 13 XD_W E#/SD_CD# XD_W E#/SD_CD# 74
V18 SP6
1
XD_CD#
C3204
C3203
250mA
SP1
SP2
SP3
SP4
SP5
DY 25
2
GND
SC1U6D3V2KX-GP
C3208
RTS5138-GR-GP
7
8
9
10
11
12
1
71.05138.003
2
C C
Close to chip
XD_ALE/SD_D7/MS_D3 XD_ALE/SD_D7/MS_D3 74
3D3V_CARD_S0 Vendor recommand XD_CLE/SD_D0/MS_D7 XD_CLE/SD_D0/MS_D7 74
XD_CE#/SD_D1 XD_CE#/SD_D1 74
XD_RE#/MS_INS# XD_RE#/MS_INS# 74
R3208 X02
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
XD_RDY/SD_W P/MS_CLK_R 1 2 XD_RDY/SD_W P/MS_CLK 74

1
1
C3206
C3207
XD_CD# 1 TP3203 TPAD14-OP-GP 0R0402-PAD

2
XD_D0/SD_CLK/MS_D2 R3209 2 1 33R2J-2-GP

XD_D0/SD_CLK/MS_D2_R 74
For EMI
Close U3201
B R3206 1 B
USB_PN5_R 2 0R0603-PAD USB_PN5 18
CLK_PCH_48M
1
R3210
10R2J-2-GP
DY USB_PP5_R R3207 1 2 0R0603-PAD USB_PP5 18

2
X02 1229
CLK_PCH_48M_R
changed R3206,R3207 to short pad,

removed TR3201 CMC footprint
SC10P50V2JN-4GP
1
C3210 DY
2
<Variant Name>
A A
Wistron Corporation
Title
Size
Card Reader-RTS5138
Document Number Rev
A3
5
4
vinafix 3 2
1
32 of 104
a f i x
Vin
A B C D E
4 4
3 3
(Blanking)
2 2
1 <Variant Name> 1
Wistron Corporation
Title
Reserved
A3
vinafix
A
B C D
E
33 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
34 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
35 of 104
a f i x
n = Reset.Suspend
5 4 3 2 1
ViSSID 27,42 IMVP_PW RGD

R3614
1 2
0R0402-PAD
SYS_PW ROK 1D05V_VTT 1
R3622
2 H_THERMTRIP# 5,22
1
2K2R2J-2-GP
C3612 DY
X02
E
SCD01U50V2KX-1GP
2
Q3603 1 R3601 2 H_PW RGD_R B DY Q3601
2N7002BK-GP 5,22 H_CPUPW RGD 1KR2J-1-GP MMBT2222A-3-GP
DY
1
84.02222.V11
C
PS_S3CNTRL G C3602 DY
SCD1U10V2KX-5GP
2nd = 84.02222.X11
2
D 84.07002.I31 D
2nd = 84.2N702.W31
83.00016.K11
S
3rd = 84.2N702.J31
2nd = 83.00016.F11
BAS16-6-GP
Power Sequence 2
2 3 PURE_HW _SHUTDOW N# 27,28,86
19,27 S0_PW R_GOOD 3 41 3V_5V_EN 1

D3601
1
200KR2J-L1-GP
SYS_PW ROK 19 BAS16-6-GP
1
1 2 S5_ENABLE 27
R3602
D3602 R3603 1KR2J-1-GP
DY
83.00016.K11
2
2nd = 83.00016.F11
ROSA Run Power 15V_S5

AO4468 MAX 9A
Rds(on) = 18.5mOhm
5V_S0
5V_S5 U3601 5V_S0
C 2 +5V_RUN Comsumption C
R3604 5 4
100KR2J-1-GP 6
D G
3
Peak current 6.628A
7
D
D
S
S 2 Design current 4.639A
8 1
1
D S
X02
1
AO4468-GP
1 2 5V_RUN_ENABLE 84.04468.037 C3603
3D3V_AUX_S5 R3605 0R0402-PAD 2nd = 84.02659.037 SC10U10V5ZY-1GP
2
1
3rd = 84.04178.037
C3608 4th = 84.04496.037
PS_S3CNTRL 37 SCD01U50V2KX-1GP 5th = 84.04800.D37
2
1 R3606 2 PS_S3CNTRL
100KR2J-1-GP
D G S
6
Rds(on) = 18.5mOhm
D2
G1
S1
Q3602 AO4468 MAX 11.6A

ME2N7002DKW -G-GP 3D3V_S0
D1
S2
G2
84.2N702.F3F 3D3V_S5 U3602 3D3V_S0

1
2nd = 84.2N702.A3F +3.3V_RUN Comsumption

S G D 5 4
Peak current 6.182A
3rd = 84.DMN66.03F 6
D G
3
Design current 4.467A
D S
7 D S 2
8 1
1
D S
B 19,27,37,47 PM_SLP_S3# X01 1109 B
AO4468-GP C3604
RUN_ENABLE 1 2 3.3V_RUN_ENABLE 84.04468.037 SC10U6D3V5KX-1GP
2
R3607 100KR2J-1-GP 2nd = 84.02659.037
1
3rd = 84.04178.037
C3605 4th = 84.04496.037
SCD01U50V2KX-1GP 5th = 84.04800.D37
2
change U3606 to 84.08062.037

1D5V_S3
from power team suggest 1D5V_S0
1D5V_S0
TPCA8062-H-GP MAX 28A
Rds(on) = 4.1~5.6m OHM +1.5V_RUN Comsumption
Peak current 10.667A
U3606 Design current 7.467A
8 D S 1
7 D S 2
6 D S 3
1
5 D G 4
X01 1109 C3609
<Variant Name>
A SC10U6D3V5KX-1GP A
2
1 2 1.5V_RUN_ENABLE TPCA8062-H-GP
R3630 100KR2J-1-GP
X01 1109 84.08062.037 Wistron Corporation
1

C3610 2nd = 84.00460.037 Taipei Hsien 221, Taiwan, R.O.C.
SCD047U25V2KX-GP
3rd = 84.00034.A37
2
Title
Power Plane Enable

A3
http://www.vinafix.vn vinafix Date: Tuesday, January 03, 2012 Sheet 36 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
Close to DIMM
Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK
S3 Power Reduction Circuit Processor VREF_DQ Implementation 0D75V_S0 1D5V_S0
R3707
0R2J-2-GP
1 DY 2
1
Q3708
2N7002BK-GP
R3703
22R2J-2-GP 2 DY
R3704
220R2J-L2-GP
D R3708 +V_SM_VREF_CNT 9 D
Q3702_D2
2
Q3701_D
M_VREF_DQ_DIMM0 1 2 +V_SM_VREF D S
R3705
X02 0R0402-PAD 100KR2J-1-GP
84.07002.I31
84.07002.I31
D
1
G
84.07002.I31 2nd = 84.2N702.W31 Q3702
D
Q3701 2N7002BK-GP 2nd = 84.2N702.W31
2nd = 84.2N702.W31 3rd = 84.2N702.J31 2N7002BK-GP
G 3rd = 84.2N702.J31
RUN_ENABLE 3rd = 84.2N702.J31 36 PS_S3CNTRL G DY
PS_S3CNTRL
S
S
0D75V_EN
Close to CPU
D
Q3704 S3 Power Reduction Circuit SM_DRAMPWROK

2N7002BK-GP
C G 1D5V_S3 C
36 PS_S3CNTRL
1
84.07002.I31 R3706
S
1KR2J-1-GP
2nd = 84.2N702.W31 1.05VTT_PW RGD 45,48
2
3rd = 84.2N702.J31 R3709
DY1 2
0R2J-2-GP
1 S3 Power Reduction Circuit
R3710 X02-0303 change 0R to short pad
0R0402-PAD SM_DRAMRST#
Q3703
X02 2N7002BK-GP
2
5 SM_DRAMRST# S D SM_DRAMRST#_D
1 R3718 2 DDR3_DRAMRST# 14,15
1KR2J-1-GP
1
19,27,36,47 PM_SLP_S3# 1
R3716
DY22R2J-2-GP
2 0D75V_EN 46 84.07002.I31 C3702
SC100P50V2JN-3GP
2nd = 84.2N702.W31
2
G
3rd = 84.2N702.J31
1
C3705 DRAMRST_CNTRL_PCH 20
DY SCD1U10V2KX-5GP
2
B B
C3703
Close to CPU 2 1DRAMRST_CNTRL_PCH
S3 Power Reduction Circuit SM_DRAMPWROK SCD047U16V2KX-1-GP
3D3V_S0
3D3V_S0
1
X00 1D5V_S0
R3713 CEKLT V1.0: PCH to 1K,CUP to 200R
200R2F-L-GP
1
U3701 R3702
2
1 5 200R2F-L-GP
19 PM_DRAM_PW RGD A VCC DY
0D75V_EN 2
2
B
3 4 VDDPW RGOOD_R 1R3719 2 VDDPW RGOOD 5
GND Y 910R2F-GP
1
U74LVC1G08G-AL5-R-GP-U
R3721
39R2J-L-GP
73.01G08.EHG DY
1
R3720
2nd = 73.7SZ08.EAH
2
Q3707_D 750R2F-GP
A
3rd = 73.7SZ08.DAH <Variant Name>
D
A
2
Q3707
4th = 73.01G08.L04 DY 2N7002BK-GP
R3717
19 PM_DRAM_PW RGD 1 DY 2 VDDPW RGOOD_R PS_S3CNTRL G 84.07002.I31 Wistron Corporation
0R2J-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2nd = 84.2N702.W31
Title
3rd = 84.2N702.J31
S
SM_DRAMPWROK must have a maximum of 15ns rise or fall time

over VDDQ * 0.55∮
∮ 200mV and the edge must be monotonic S3 Reduction Circuit
A3

5
4 3 2
1
37 of 104
a f i
in CONN x 5 4 3 2 1
VDCin
5V_S5
SSID = PWR.Support
1
PR3801 84.03904.L06 PD3802
DY
1
15KR2J-1-GP 3D3V_S5
DA3X101F0L-GP
2nd = 84.03904.P11 PR3802
83.3X101.011
2
10KR2J-3-GP 3D3V_S5
1
PSID_PROTECT 1 PMBS3904-1-GP
2nd = 83.00099.K11
3
PQ3802
1
PR3804
2
2
1
DY 2PSID_DISABLE#_R3rd = 83.00099.M11
PD3803
3
D PR3803 PSID_DISABLE#_R_C1 PR3806 D
100KR2J-1-GP DA3X101F0L-GP
2K2R2J-2-GP
10KR2J-3-GP 83.3X101.011
G
1
2nd = 83.00099.K11
2
PQ3801
3
FDV301N-NL-GP
PR3807 3rd = 83.00099.M11
D S PS_ID 1 2 PSID_EC 27
D
84.00301.A31 33R2J-2-GP
2nd = 84.27002.I31
PR3808
1
DY 2 X00 remove PR3812 PQ3803
33R2J-2-GP
+DC_IN
DCIN1
1 8
C 2 9 C
3 10
4 11 PS_ID_R +DC_IN AD+
5 12 PU3801
6 13 1 S D 8
S D
PC3805
PC3802
PC3803
7 14 2 7
SC1U25V5KX-1GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
1
S D
PC3804
PR3810
PC3806
240KR3-GP
X00 3 6
1
ACES-CONN14G-GP 1 2 PR3809 PS_ID_R2 PC3801 4 G D 5
SCD1U50V3KX-GP
DY DY
2
0R3J-0-U-GP AO4407AL-GP
2
20.F1498.007
2
Id= -10A
K
2nd = 20.D0276.107
1
PD3801 Qg= -22nC
3rd = 20.F2024.007 83.P6SBM.DAG P6SBMJ27APT-GP
PD3804
Rdson=14~30mohm
2nd = 83.P6SMB.JAG DY B240A-13-GP
84.04407.G37
A
AFTP3812 PS_ID_R
2
1
3rd = 83.P6SMB.CAG
2
AFTP3813
AFTP3814
1 +DC_IN
GND
PQ3805
R2
PR3811
2nd = 84.03604.A37
1 PQ3804 E
C AD_OFF_L B 47KR3J-L-GP
B R1 DY
R1
C AD_OFF_R
27 PW R_CHG_AD_OFF DY E
1
R2 PDTA124EU-1-GP
PDTC124EU-1-GP
B B
<Variant Name>
A A
Wistron Corporation
Title
DCIN Jack
A3
5
4
vinafix 3 2
1
38 of 104
a f i x
Vin SSID = PWR.Support
5 4 3 2 1
D Batt Connecter D
BATT1
10
1
BT+
K
2
1
AFTP3901 1BAT_ALERT 3
EC3904 EC3903 PD3902 4
SCD1U50V3KX-GP SC2200P50V2KX-2GP DY
SMF18AT1G-GP 5
2
6
A
7
8
SRN33J-7-GP 9
4 5 PBAT_SMBCLK1 11
27,40 BAT_SCL
3 6 PBAT_SMBDAT1
27,40 BAT_SDA
2 7 PBAT_PRES1#
27 BAT_IN#
1 8 ALP-CON9-4-GP-U
1 AFTP3906
PN3901
EC3901 EC3902
20.81507.009
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
DY DY
2nd = 20.81642.009
2
C C
3rd = 20.81684.009
AFTP3902 1 PBAT_PRES1#
AFTP3903 1 PBAT_SMBDAT1
AFTP3904 1 PBAT_SMBCLK1
AFTP3905 1 BT+
For actual location, need to be swap all pin

B B
Placement: Close to Batt Connector
BAT_SCL
BAT_IN#
BAT_SDA
X00
3
3
D3902 D3903 D3901
DA3X101F0L-GP DA3X101F0L-GP DA3X101F0L-GP
1
83.3X101.011 83.3X101.011 83.3X101.011 <Variant Name>

A A
2nd = 83.00099.K11 2nd = 83.00099.K11 2nd = 83.00099.K11 3D3V_AUX_KBC
3rd = 83.00099.M11 3rd = 83.00099.M11 3rd = 83.00099.M11

Wistron Corporation
Title
BATT CONN
A3
vinafix
5
4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = Charger
84.04407.G37
2ND = 84.03604.A37
D D
84.04407.G37 AD+_TO_SYS DCBATOUT BT+
PU4003
PU4002 2ND = 84.03604.A37 1 S D 8
D S S D
EE need pull high and net name AD+ 8
7 D S
1
2 1 2
2
3 S D
7
6
1
6 D S 3 PR4002 AD+ 4 G D 5
100KR2J-1-GP
PR4003
5 D G 4 D01R2512F-4-GP
GAP-CLOSE-PWR-3-GP
AO4407AL-GP
AO4407AL-GP
Id= -10A
2
2
1
10KR2J-3-GP
AD+_G_2
3D3V_AUX_S5
PG4002
PG4004
PG4005
PG4001
PG4006
Qg= -22nC
PR4004
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
Id= -10A PG4003 PR4005
2
5,27 H_PROCHOT#
10KR2F-2-GP
GAP-CLOSE-PWR-3-GP 470KR2J-2-GP
Qg= -22nC Rdson=14~13mohm
PR4001
PQ4008 PR4006
1
1
2N7002BK-GP Rdson=14~13mohm 0R2J-2-GP
2
DY PR4037 2
DY 1
DC_IN_D
100KR2J-1-GP
1
S D
AD+_G_1
PQ4002 1 2
2
3 4
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
D1 S1
84.07002.I31 PC4002
PWR_CHG_ACOK 2 5 SCD1U25V2KX-GP
G
G2 G1
2nd = 84.2N702.W31 PWR_DCBATOUT_CHG
PC4003
PC4004
1 6
SC1U25V3KX-1-GP
S2 D2
3rd = 84.2N702.J31
SC2200P50V2KX-2GP
ME2N7002DKW-G-GP
AD+ DY
SCD1U50V3KX-GP
PC4024
PWR_CHG_CMPOUT
SCD1U25V2ZY-1GP
84.2N702.F3F
PWR_CHG_ACN
PWR_CHG_ACP
PC4009
2nd = 84.2N702.A3F
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
EC4001
EC4002
3rd = 84.DMN66.03F
1
PC4008
PC4006
PC4026
PC4014
PC4025
PWR_CHG_CMPIN PR4008 PWR_CHG_REGN
CHG_AGND CHG_AGND DY DY
2
20R5J-GP PD4001
2
1
5
6
7
8
1 2 PWR_CHG_VCC PR4009 SD103AWS-1-GP
1
D
D
D
D
PR4007
AO4496-GP
PU4004
C X01 1108 CHG_AGND 0R3J-0-U-GP C
PR4029 316KR2F-GP 1 2 K A 21 84.04496.037
SCD047U25V2KX-GP
54K9R2F-L-GP PC4007
PC4011_1
1 2
1
PR4010 20R5J-GP PC4010 PU4005 SC1U25V3KX-1-GP
83.1R504.A8F 2ND = 84.04178.037
2
PC4011
SCD47U25V3KX-3-GP
ACP
ACN
PR4029_22
1
PWR_CHG_REGN
G
S
S
S
PQ4004 PWR_CHG_IOUT CHG_AGND 20 VCC 2nd = 83.1R004.H8F
1
1
2N7002BK-GP
4
3
2
1
PR4011 PR4030 3rd = 83.1R504.B8F
2
19K1R2F-GP 3D3V_AUX_KBC 100KR2J-1-GP PWR_CHG_ACDET 6 17 PWR_CHG_BTST
ACDET BTST
SCD01U50V2KX-1GP
49K9R2F-L-GP PR4031
S D 4th = 83.2R004.08F Charger Current=1.4~3.6A

1
68.5R610.20B
2
2
1
PC4012
PWR_CHG_CMPOUT 16
REGN
1
1
84.07002.I31 PR4013 2ND = 68.5R61A.10A
1
1
PR4012 PR4014 3
G
R4013 3K3R2F-2-GP 3K3R2F-2-GP PR4032 CMPOUT PWR_CHG_HIDRV PL4001

2nd = 84.2N702.W31 18
2
49K9R2F-L-GP 120KR2F-L-GP 3D3MR2J-GP HIDRV IND-5D6UH-52-GP BT+

3rd = 84.2N702.J31
DY DY 4 1
DY
2
2
CMPIN PWR_CHG_PHASE
AD_IA_HW 27 19 1 2BT+_R 1 2
2
2
PWR_CHG_CMPIN PHASE PC4013 PR4016
SC3300P50V3KX-1GP
SCD1U50V3KX-GP
CHG_AGND CHG_AGND D01R2512F-4-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4019
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV
27,39 BAT_SCL SCL LODRV
PC4015
PC4016
PC4017
PC4018
PG4007 GAP-CLOSE-PWR-3-GP
1
SCD1U25V2KX-GP
CHG_AGND
5
6
7
8
2
2 1 PWR_CHG_BAT_SDA 8 DY
27,39 BAT_SDA SDA
D
D
D
D
3D3V_AUX_S5
PG4009
PG4010
AO4496-GP
PU4001
PG4008 GAP-CLOSE-PWR-3-GP
2
PC4020
A00-0412 stuff PR4030& PR4032 13 PWR_CHG_SRP 1 PR4021 2
1
SRP
1
PWR_CHG_ILIM 10 10R2F-L-GP
ILIM
1
PR4017 12 PWR_CHG_SRN 1 PR4020 2
SRN
84.04496.037
G
S
S
S
100KR2J-1-GP 7D5R2F-GP DY
X00 2 1 PWR_CHG_IFAULT
11 NC#11
PWR_CHG_CMPIN DY
4
3
2
1
27 BOOST_MODE# 2ND = 84.04178.037
2
PR4018 CHG_AGND
0R2J-2-GP PR4022
1
B 0R2J-2-GP B
10KR2F-2-GP
3D3V_AUX_S5
SCD1U25V2KX-GP
PR4027 PR4023 5 7 PWR_CHG_IOUT 1 2
PR4035
ACOK# IOUT AD_IA 27

19K6R2F-GP 59KR2F-GP PWR_CHG_CSOP_1
DY
GND
GND
DY
SC220P50V2JN-3GP
PQ4003 3D3V_AUX_S5
1
PC4021
2N7002BK-GP
2
8K45R2F-2-GP
DYPR4026 BQ24727RGRR-GP
1 PR4024
21
14
PWR_CHG_CMPIN_R PQ4001 100KR2J-1-GP
D
1
2N7002A-7-GP
S D
74.24727.073
PC4022
CHG_AGND PG4011
2
1 2
DY
2
84.07002.I31 G PWR_CHG_CMPOUT CHG_AGND
SCD1U25V2KX-GP
GAP-CLOSE-PWR PWR_CHG_CSON_1
G
2nd = 84.2N702.W31 CHG_AGND DY

S
2
EE need check pull high
PC4023
CHG_AGND 3rd = 84.2N702.J31
1
AD_IA_HW2 27
2
CHG_AGND PWR_DCBATOUT_CHG
CHG_AGND
CHG_AGND
BT+_R
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
PWR_CHG_REGN 3D3V_AUX_S5
3D3V_AUX_S5 PWR_CHG_REGN
EC4003
EC4004
1
1
1
1
PR4025 PR4034
DY 100KR2J-1-GP 100KR2J-1-GP PR4019 DYPR4028
2
100KR2J-1-GP 100KR2J-1-GP
2
2
27 AC_IN#
PWR_CHG_ACOK X02 1228
SCD1U25V3KX-GP
1
PC4001
1
PR4033 PQ4006
A EC code only BQ24707 DY DY120KR2F-L-GP 2N7002BK-GP A
<Variant Name>
2
1
2
H_PROCHOT# AD_IA_HW AD_IA_HW2 DY PR4036 S D

120KR2F-L-GP
84.07002.I31
Wistron Corporation
65W 0 0
2

2nd = 84.2N702.W31
G
90W 1 0 PR4034 can dummy if you use external 10mW Title
3rd = 84.2N702.J31
AC_IN# CHARGER BQ24707
130W 0 1 Custom
vinafix
4 3 2 1
a f i x
Vin
A B C D E
SSID = PWR.Plane.Regulator_5v3p3v
PWR_5V_VCLK
PC4104 PC4102 PC4103
1
SC1KP50V2KX-1GP
SCD1U25V3KX-GP
SCD1U25V3KX-GP
1
1
2
3BST15V_2 2
3BST15V_1 2
3D3V_AUX_S5
1
PR4123
X02 1229 DY 0R2J-2-GP PD4103
4 DCBATOUT PWR_DCBATOUT_3D3V 83.0R203.081 PD4101 83.0R203.081 4
2nd = 83.00054.Y81 BAT54SPT-GP2nd = 83.00054.Y81
2
PG4102
1 2 PR4121 PR4124
PWR_5V_EN1 2 1 1 DY 2
3rd = 83.BAT54.P81 3rd = 83.BAT54.P81
1
GAP-CLOSE-PWR-3-GP 15V_S5 BAT54SPT-GP 5V_PWR
PG4103
0R2J-2-GP PG4105
2
1 2 0R0402-PAD GAP-CLOSE-PWR-3-GP
PR4122
GAP-CLOSE-PWR-3-GP 15V_PWR BOOST_10V
PG4104 0R0402-PAD 1 2
1 2
K
1
PR4127
1
PC4106
GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 2 PD4104 SC1U25V3KX-1-GP PC4108 PC4107
PG4106 1
3V_5V_EN 36 BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
DY
2
1 2
0R0402-PAD
A
GAP-CLOSE-PWR-3-GP
PU4101
Main source FDMS3604 (84.00033.037)
DCBATOUT
PWR_DCBATOUT_3D3V
PC4112 PC4113 PWR_DCBATOUT_5V 5V_PWR 5V_S5
PU4101 DCBATOUT PWR_DCBATOUT_5V PG4119
SC10U25V5KX-GP
SCD01U50V2KX-1GP
PC4109 PC4110 PC4111 2 1 2
ZZ MOS
1
3 PG4133
1
1
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC10U25V5KX-GP
1 4 PC4114 PC4115 PC4128 PC4129 PC4116 1 2 GAP-CLOSE-PWR-3-GP

84.00412.037 DY 10 PG4120
1
2ND = 84.08884.A37
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
D 9 GAP-CLOSE-PWR-3-GP 1 2
2
8
7
6
5
7 Design Current = 16A PG4131

D
D
D
D
Design Current=6.12A 8 6 1 2 GAP-CLOSE-PWR-3-GP
2
PU4104 25.1A<OCP< 29.3A PG4121
12
5
9.62A<OCP>11.37A SIS412DN-T1-GE3-GP PU4103 GAP-CLOSE-PWR-3-GP 1 2
PG4130
VIN
FDMS3600-02-RJK0215-COLAY-GP 1 2 GAP-CLOSE-PWR-3-GP
SCD1U25V3KX-GP PG4122
S
S
S
G
3D3V_S5 3D3V_PWR PC4117 PR4108 PR4109 PC4118

68.2R210.20B 84.00033.037 GAP-CLOSE-PWR-3-GP 1 2
1
2
3
4
3 3
PG4108 S G 2 1PWR_3D3V_VBST2_1
1 2 PWR_3D3V_VBST29 17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2 PG4132
SCD1U25V3KX-GP 1D5R3F-GP VBST2 VBST1 1D5R3F-GP 68.1R510.10J
1 2 GAP-CLOSE-PWR-3-GP
3D3V_PWR 2ND = 68.2R21B.10J PWR_3D3V_DRVH210 16 PWR_5V_DRVH1 2nd = 84.06920.037 2ND = 68.1R51A.10E 5V_PWR
1 2
PG4123
DRVH2 DRVH1 PL4101
GAP-CLOSE-PWR-3-GP PL4102 GAP-CLOSE-PWR-3-GP 1 2
PG4109 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 PG4128
IND-2D2UH-46-GP-U SW2 SW1 IND-1D5UH-34-GP
1 2 X01 1110 1 2 GAP-CLOSE-PWR-3-GP
1
PWR_3D3V_DRVL211 PWR_5V_DRVL1 PG4124

X01 1110 D 15
1
DRVL2 DRVL1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 1 2
8
7
6
5
PG4110 PR4110 DY PR4111 PG4129

D
D
D
D
PC4119 PG4116 2D2R5F-2-GP PU4105 PWR_5V_VO1 2D2R5F-2-GP PG4117 PC4120 PT4101 PT4104
1 2 14 DY 1 2 GAP-CLOSE-PWR-3-GP
1
1
PT4102 VO1 PG4125
SIS406DN-T1-GE3-GP
2
1
1
SCD1U10V2KX-4GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
ST220U6D3VDM-17GP
SE330U6D3VM-21-GP
GAP-CLOSE-PWR-3-GP PWR_3D3V_FB2 4 2 PWR_5V_FB1 GAP-CLOSE-PWR-3-GP
77.53371.16L 1 2
2
VFB2 VFB1
SE330U6D3VM-21-GP
PG4111 DY PG4149
1PWR_3D3V_SNUB
2
2nd = 77.93371.011 1 2
2
2
PG4126
1 S
2 S
3 S
1PWR_5V_SNUB
4 G
GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 6 20 PWR_5V_EN1 GAP-CLOSE-PWR-3-GP 1 2

PG4112 EN2 EN1 PG4151
1 2
S G X01 1110 X01 1110
PWR_3D3V_CS2 5 1 PWR_5V_CS1 PG4135
CS2 CS1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 1 2
3V_FEEDBACK
1
PG4113 PG4148
1 2
77.53371.16L DY PR4101 19 PWR_5V_VCLK PR4102 GAP-CLOSE-PWR-3-GP
PC4121 84.00406.037 91KR2F-GP VCLK 61K9R2F-GP
DY PC4123 80.22715.39L 1 2
PG4134
2nd = 77.93371.011
2
GAP-CLOSE-PWR-3-GP SC330P50V3KX-GP 2nd = 84.08878.A30 SC560P50V-GP

2nd = 77.22271.27L GAP-CLOSE-PWR-3-GP 1 2
2
PG4114 PWR_5V3D3V_PGOOD 7 21 PG4150
2
2
PGOOD GND
1 2 1 2 GAP-CLOSE-PWR-3-GP
VREG3
VREG5 PG4156
GAP-CLOSE-PWR-3-GP
PG4115
74.51225.073 GAP-CLOSE-PWR-3-GP
PG4147
1 2
1
1
1 2 TPS51225RUKR-GP 1 2 GAP-CLOSE-PWR-3-GP
3
13
PR4113 5V_PWR_2 PR4114 PG4152
1
GAP-CLOSE-PWR-3-GP PR4112 DY0R2J-2-GP 3D3V_PWR_2 0R2J-2-GP DY GAP-CLOSE-PWR-3-GP 1 2
PWR_5V3D3V_VREG3
6K65R2F-GP PG4101 PR4115

1 2 15KR2F-GP GAP-CLOSE-PWR-3-GP
2
1 2
1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R PG4155
PC4124 GAP-CLOSE-PWR-3-GP 1 2
2
DYSC18P50V2JN-1-GP PC4125 DY
SC18P50V2JN-1-GP GAP-CLOSE-PWR-3-GP
2
2
PG4157
1 2
1
1
3D3V_S5
2
PR4117
X02 1230 3D3V_PWR_2 3D3V_AUX_S5
X01 1108
PR4120 GAP-CLOSE-PWR-3-GP
2
1
10KR2F-2-GP PC4127 PC4126 9K76R2F-1-GP PG4153

1
SC4D7U6D3V5KX-3GP PR4116 1 2
SC4D7U6D3V5KX-3GP
PR4119 2 1 Close to VFB Pin (pin2)
2
2
100KR2J-1-GP GAP-CLOSE-PWR-3-GP
0R0402-PAD PG4154
1 2
2
Close to VFB Pin (pin5)

X02 1229 GAP-CLOSE-PWR-3-GP
PG4158
1 2
GAP-CLOSE-PWR-3-GP
I/P cap: CHIP CAP C 10U 25V K0805 X5R/78.10622.51L

Inductor: 2.2U PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B I/P cap:10U 25V K0805 X5R/ 78.10622.51L
O/P cap: CHIP CAP POL 330U6.3V M6.3*5.7 15mOhm / 77.53371.04L Inductor: 1.50UH PCMC104T-1R5 Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J
H/S: SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 O/P cap: 220U 6.3V PSLV0J227M 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
L/S: SI7716ADN-T1-GE3 / 13.5mOhm/16.5mOhm@4.5Vgs / 84.07716.037 O/P cap: CHIP CAP POL 330U6.3V M6.3*5.7 15mOhm / 77.53371.04L
H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037
1 1
<Variant Name>
Wistron Corporation
Title
3V/5V TPS51225
A2
vinafix
B C D E
a f i x
Vin
5 4 3 2 1
1D05V_VTT
SSID = CPU.Regulator 8 VR_SVID_ALERT#
PR4224
1
DY
75R2F-2-GP
2
PR4225 130R2F-1-GP
Note: 1 2
8 H_CPU_SVIDDAT Volterra's suggestion:
VT1318M PR4226 54D9R2F-L1-GP
VCC 26x22uF for 2-PHASE VCC
1 2
8 H_CPU_SVIDCLK
For P/N 74.01318.073, plz use 30 pcs of MLCC(22uF).
VCCAXG 23x22uF for 1-PHASE VCCAXG
For the next version(in September mid.), it can reduce the MLCC to 26 pcs. 48 D85V_PWRGD
27,36 IMVP_PWRGD
X02 1229 X02 1229
PR4201
PR4244
PR4204 825R2F-GP
PR4232
PR4205
PR4262
PR4265
PR4220
PR4208
PR4209
PR4210 475R2F-L1-GP
D
1D8V_S0 3D3V_S5
Boot Voltage PR4265 PR4204 D
X02 1229
1
5V_S5
0V 887ohm 825ohm
VR_SVID_ALERT#
21D5R2F-1-GP
0R0402-PAD
75KR2F-GP
698R2F-GP
887R2F-L-GP
0R0402-PAD
H_CPU_SVIDDAT
H_CPU_SVIDCLK
1
0R0402-PAD
191R2F-GP
20KR2F-L-GP
PR4231
1
PC4211 10R2F-L-GP
2
SC1U16V2KX-GP
PWR_VCORE_VR_ENABLE
PR4260 1V 215ohm 191ohm
2
866KR2F-GP
PWR_VCORE_R_OSC
PWR_VCORE_R_SEL0
PWR_VCORE_R_SEL1
2
PWR_VCORE_R_SEL6
PWR_VCORE_VR_READY2
PWR_VCORE_VR_READY1
PWR_VCORE_VR_TT#
PWR_VCORE_R_SEL4
1 2
PWR_VCORE_VIN_UVLO_R
PC4237 SCD1U10V2KX-5GP
1
PR4263 PC4214
100KR2F-L1-GP
SCD1U10V2KX-5GP
GND_1318
2
2
PR4223
0R2J-2-GP
1 2
GND_1318
49
48
47
46
45
44
43
42
41
40
39
38
37
PU4201
R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE
R_SEL0
R_SEL1
GND
R_OSC
1D8V_S0
PWR_VCORE_VDD3 1 36 PWR_VCORE_R_SEL2
43 PWR_VCORE_IPH1_2_L VDD3 R_SEL2 PWR_VCORE_R_SEL3
2 35
VDD R_SEL3 PWR_VCORE_R_REF
43 PWR_VCORE_IPH1_1_L 3 34
PWR_VCORE_VIN_UVLO VDD R_REF
4 33 PWR_AXG_IPH2_1_R 44
PWR_VCORE__PWM3 VIN_UVLO IPH2_2 PWR_VCORE_R_SEL5
5 32
PWR_VCORE__PWM2 PWM1_3 R_SEL5 PWR_AXG_PWM2_2
6 31
PR4217 43 PWR_VCORE__PWM2 PWR_VCORE__PWM1 PWM1_2 PWM2_2 PWR_AXG_PWM2_1 PR4229
7 30
PR4235 1K96R2F-1-GP 43 PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWM1_1 PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_PWM2_1 44 1K96R2F-1-GP
8 29
499R2F-2-GP 43 PWR_VCORE__TP_FAULT#1 TS_FAULT#1 TS_FAULT#2 PWR_AXG_IPH2_1 PWR_AXG_TS_FAULT#2 44
9 28 1 2 1 2
PWR_VCORE_IPH1_2 IPH1_3 IPH2_1 PWR_AXG_MRAMP2
1 2 1 2 10 27
PWR_VCORE_IPH1_1 IPH1_2 MRAMP2 PR4246
1 2 1 2 11 26
1
IPH1_1 SENSE2+
PR4257
PC4201
C PWR_VCORE_MRAMP1 1KR2F-3-GP C
SENSE1+
12 25
A2_OUT1
A3_OUT1
A3_OUT2
A2_OUT2
SENSE1-
MRAMP1 SENSE2-
A_ERR1
A_ERR2
PR4256 PR4216 PC4229 PC4228 PR4218 PR4212 DY
A2_IN1
A3_IN1
A3_IN2
A2_IN2
1
1
499R2F-2-GP 1K96R2F-1-GP PR4215 0R2J-2-GP 0R0402-PAD
DY
2
1
1
SC10P50V2JN-4GP
SC10P50V2JN-4GP
PR4261 PR4219 PR4258 15K8R2F-GP
15K4R2F-GP
SC10P50V2JN-4GP
DY DY 0R0402-PAD 0R2J-2-GP 0R2J-2-GP
DY DY
2
VT1318MFQX-1-GP
X02 1229
2
13
14
15
16
17
18
19
20
21
22
23
24
2
2
74.01318.A73
PWR_VCORE_A_ERR1
PWR_VCORE_A2_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A3_OUT1
PWR_AXG_A3_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A2_IN2
PWR_AXG_A_ERR2
X02 1229
PC4232 GND_1318
SC22P50V2JN-4GP PC4236
2 1 1 2
PC4239 SC56P50V2JN-2GP GND_1318 PR4252

PR4259
PC4238 PR4234 PWR_AXG_SENSE2_P 2 1 VCC_AXG_SENSE 9
2 1 VCORE_IN1_R0 2 1 1 2 VCORE_IN1_L0 1 2 0R0402-PAD
DY DY PWR_AXG_SENSE2_N 2 PR4254 1 VSS_AXG_SENSE 9
SC22P50V2JN-4GP 6K81R2F-1-GP SC220P50V3JN-GP 30K1R2F-L-GP 0R0402-PAD
PR4237 PR4236 PR4264
PR4251
1 2 1 2VCORE_IN1_R1 1 2 2 1 2 1 PWR_VCORE_SENSE_P
X02 1229
8 VCCSENSE
0R0402-PAD
2K05R2F-GP 18K2R2F-L-GP PR4233 PC4235 SC22P50V2JN-4GP PC4233 SC22P50V2JN-4GP
845R2F-GP 10KR2F-2-GP
X01 1110 X01 1110
X02 1229 1 2 1 2
PR4250
8 VSSSENSE 2 1 PWR_VCORE_SENSE_N PR4255
PC4218
0R0402-PAD PR4253 PC4234 PR4240
1 2 AXG_IN2_L1 1 2 1 2 AXG_IN2_R0 1 2 1 2
DY DY
30K1R2F-L-GP SC1KP50V2JN-2GP 6K81R2F-1-GP SC22P50V2JN-4GP 665R2F-2-GP
PR4249
PR4239
PR4238 PC4213
1 2 1 2AXG_IN2_R1 1 2
1 2VCORE_IPH1_R0 1 2 PR4245 10KR2F-2-GP
7K5R2F-1-GP 191R2F-GP
1 2
1K3R2F-1-GP X01 1110 X01 1110
PG4203 SC4700P25V2KX-3-GP
GAP-CLOSE-PWR
B B
GND_1318
PC4231
PR4243
1 2 AXG_IPH2_R0 1 2
SCD01U50V2KX-1GP 3K24R2F-GP
3D3V_S0
VCC_CORE
PR4222 PR4221
1 2 PWR_VCORE_MRAMP1 1 2 PWR_VCORE_VR_READY1
10KR2F-2-GP
60K4R2F-GP
PR4266
1 2 PWR_VCORE_VR_READY2
10KR2F-2-GP
VCC_GFXCORE
PR4228
1 2 PWR_AXG_MRAMP2
56K2R2F-2-GP
1D05V_VTT
PR4207
1 2 PWR_VCORE_VR_TT#
62R2J-GP
1
PC4219
SC47P50V2JN-3GP
2
A A
<Variant Name>
Wistron Corporation
Title
VT1318 CPU CORE(1/3)

A2
X01
http://www.vinafix.vn vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
5V_S5
PC4304
PC4305
PC4306
PC4307
PC4308
PC4309
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
1
PC4310
SCD1U10V2KX-5GP
2
1D8V_S0
D D
X02 1229
C1
C2
C3
C4
PU4301
PR4304
1
PC4302
VDDH
VDDH
VDDH
VDDH
SC4D7U6D3V3KX-GP 1 2PU4301_A1 A1 B4 PW R_CORE_BT1
42 PW R_VCORE__TP_FAULT#1 TS_FAULT# BST Layout Note:
2
0R0402-PAD Close to PU4301
1
A4 VCC
H4 PC4301 Design current = 36A
VX#H4 SCD22U10V3KX-2GP
H3
2
VX#H3
VX#H2 H2
PW R_VCORE_PU4301_VDD B1 H1 VCC_CORE
VDD VX#H1 PL4301
VX#F4 F4
F3 PW R_CORE_VX1 1 2
VX#F3
VX#F2 F2
B2 F1 VCC_CORE
42 PW R_VCORE_IPH1_1_L ISENSE VX#F1
VX#D4 D4
1D8V_S0 B3 D3 4 3
42 PW R_VCORE__PW M1 PWM VX#D3
VX#D2 D2
VX#D1 D1 IND-200NH-2-GP
PR4301
PC4303 68.CTX17.101
1
1 2 1 2 A2 PR4303
GND 2ND = 68.2415N.101
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100R5F-2-GP
10R2J-2-GP DY
SCD1U10V2KX-4GP
C VT1323SFCX-1-GP C
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
2
74.01323.A7Z
PG4301
1 2
GAP-CLOSE-PW R
GND_1323S_1
5V_S5
PC4311
PC4314
PC4312
PC4313
PC4320
PC4319
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
1
PC4318
SCD1U10V2KX-5GP
2
B 1D8V_S0 B
X02 1229
C1
C2
C3
C4
PU4302
PR4305
1
PC4315
VDDH
VDDH
VDDH
VDDH
SC4D7U6D3V3KX-GP 1 2 PU4302_A1 A1 B4 PW R_CORE_BT2

42 PW R_VCORE__TP_FAULT#1 TS_FAULT# BST Layout Note:
2
0R0402-PAD Close to PU4302

1
A4 VCC
H4 PC4316
VX#H4 SCD22U10V3KX-2GP
H3
2
VX#H3
VX#H2 H2
PW R_VCORE_PU4302_VDD B1 H1
VDD VX#H1
VX#F4 F4
F3 PW R_CORE_VX2
VX#F3
VX#F2 F2
42 PW R_VCORE_IPH1_2_L B2 ISENSE VX#F1 F1
VX#D4 D4
42 PW R_VCORE__PW M2 B3 PWM VX#D3 D3
1D8V_S0 D2
VX#D2
VX#D1 D1
PR4302
PC4317
1 2 1 2 A2 GND
<Variant Name>
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A 10R2J-2-GP A
SCD1U10V2KX-4GP
VT1323SFCX-1-GP
Wistron Corporation
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

PG4302
Title
1 2
GAP-CLOSE-PW R Size Document Number Rev
A3
GND_1323S_2
5
4
vinafix 3 2
1
43 of 104
a f i x
Vin
5 4 3 2 1
5V_S5
D D
PC4403
PC4404
PC4405
PC4406
PC4407
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
Layout Note:
1
PC4408
Close to PU4401
SCD1U10V2KX-5GP
2
1D8V_S0
X02 1229
C1
C2
C3
C4
PU4401
PR4403
1
PC4401
VDDH
VDDH
VDDH
VDDH
SC4D7U10V3KX-GP 1 2 PU4401_A1 A1 B4 PW R_AXG_BT3
42 PW R_AXG_TS_FAULT#2 TS_FAULT# BST
2
0R0402-PAD
1
A4 VCC
H4 PC4409
VX#H4 SCD22U10V3KX-2GP VCC_GFXCORE
H3
2
VX#H3
VX#H2 H2 PL4401
PW R_AXG_PU4401_VDD B1 H1
VDD VX#H1
VX#F4 F4 Design current = 22A
F3 PW R_AVG_VX1 1 2
VX#F3 IND-D1UH-26-GP
VX#F2 F2
C C
42 PW R_AXG_IPH2_1_R B2 ISENSE VX#F1 F1 68.R1010.10T
VX#D4 D4
1
1D8V_S0
42 PW R_AXG_PW M2_1 B3 PWM VX#D3 D3 2ND = 68.R1010.10X PR4402
VX#D2 D2
100R5F-2-GP
VX#D1 D1 DY
PR4401
PC4402
2
1 2 1 2 A2 GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z
PG4401 VCC_GFXCORE
1 2 X00
GAP-CLOSE-PW R
GND_1323S_3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
PC4415
PC4414
PC4413
PC4412
PC4411
PC4410
2
2
B B
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
PC4420
PC4419
PC4418
PC4417
PC4416
2
2
<Variant Name>
A A
Wistron Corporation
Title

A3
5
4
vinafix 3 2
1
44 of 104
a f i x
Vin
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p05v_pch/vccp_cpu 1D05_VTT_PW R 1D05V_VTT 1D05_VTT_PW R
PG4532 PG4520
1 2 1 2
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP

PG4513 PG4521
1 2 1 2
D
TPS51219 for 1D05V_PCH/VCCP_CPU GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG4514
1 2
PG4522
1 2
D

PG4515 PG4523
1 2 1 2
DCBATOUT PW R_DCBATOUT_1D05V GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG4516 PG4524
PD4501 1 2 1 2
SDMK0340L-7-F-GP
PG4501 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1 2 K DYA PG4517 PG4525
1 2 1 2
GAP-CLOSE-PW R-3-GP
PG4502 1 2 51219_EN GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
19,46,47,93 RUNPW ROK PG4518 PG4526
1 2
PR4501 1 2 1 2
GAP-CLOSE-PW R-3-GP 100KR2F-L1-GP
1
PG4503 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1 2 3D3V_S0 PC4501 PG4519 PG4527
SC1U6D3V2KX-L-1-GP DY PR4502 1 2 1 2
2
GAP-CLOSE-PW R-3-GP
PG4504 1 2 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1
1 2 PG4528 PG4529
PR4516 1KR2F-3-GP PW R_DCBATOUT_1D05V 1 2 1 2
GAP-CLOSE-PW R-3-GP 10KR2J-3-GP
PG4530 PG4531
2
C C
1 2 1 2
1
37,48 1.05VTT_PW RGD PC4502 PC4503 PC4512 GAP-CLOSE-PW R-3-GP
GAP-CLOSE-PW R-3-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V3KX-GP
X01 1110 D
2
5
6
7
8
X01 1110
D
D
D
D
PU4502
51219_MODE
3D3V_S5
Design Current = 18.26A
PR4505
PW R_VBST 1 2 PW R_LL_1 1 2PC4504
28.7A<OCP< 34A
2 1 PR4504 2D2R3J-2-GP
SIR172DP-T1-GE3-GP
G
S
S
S
10R2J-2-GP SCD1U25V3KX-GP
G S 84.00172.037
4
3
2
1
17
16
15
14
13
X01 1110 PU4501
2nd = 84.07698.037 1D05_VTT_PW R
GND
PGOOD
EN
MODE
BST
51219_VREF
PL4501
1
1 12 51219_SW 1 2
PR4506 VREF SW
18KR2F-GP 51219_REFIN 2 11 51219_DH COIL-D36UH-3-GP-U
REFIN DH 51219_DL
DY 3 GSNS DL 10
68.R3610.20S
4 VSNS V5 9 D
5
6
7
8
2nd = 68.R3610.20A PC4505
2
1
PC4506
COMP
D
D
D
D
1
PGND
PU4503 PT4501 PT4502
TRIP
GND
SCD1U10V2KX-4GP PR4524
SIR166DP-T1-GE3-GP
DY 2D2R5J-1-GP DY DY
SCD1U10V2KX-4GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
2
2
TPS51219RTER-GP 74.51219.073 84.00166.037
1
PR4507 PC4507
5
6
7
8
51219_GND_VCCP
B 20KR2F-L-GP B
DYSC2200P50V2KX-2GP
2
2nd = 84.00309.037
G
S
S
S
DY PC4508
2
G S
4
3
2
1
251219_COMP 5V_S5
2
51219_VSSP_GSNS 1
SCD1U10V2KX-4GP
1
PR4508
X01 1110 3D3R2F-GP
79.33719.L01
1
DY PC4524
151219_TRIP
PC4510 SC2200P50V2KX-YK-GP 2nd = 80.3371V.L01
1 2
51219_V5FILT
2
SC1KP50V2KX-1GP
1
PC4509
1
SC1U10V2KX-1GP
PC4511 2
2
SC1KP50V2KX-1GP DY PR4510
2
82K5R2F-GP
1
X02 0103
2
PR4509
10R2F-L-GP
2
51219_VCCP_VSNS 2 1
A PG4505 GAP-CLOSE-PW R-3-GP VCCIO_SENSE 8 <Variant Name> A
2 1
PG4506 GAP-CLOSE-PW R-3-GP VSSIO_SENSE 8
Wistron Corporation
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Inductor: 1.50UH PCMC104T Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J Taipei Hsien 221, Taiwan, R.O.C.
O/P cap: 330U2V EEFSX0D331ER 9mOhm 3Arms Panasonic/79.33719.L01 Title

H/S: SIR172DP / 10.3mohm/12.4mOhm@4.5Vgs/ 84.00172.037 TPS51219 1D05V_PCH/VCCP_CPU
L/S: SiR166DP / 0.32mohm/0.4mOhm@4.5Vgs/ 84.00166.037 Size Document Number Rev
A3
5
4
vinafix 3 2
1
45 of 104
a f i x
Vin
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
DCBATOUT +PW R_SRC_1D5V 1D5V_PW R 1D5V_S3

PG4603
1 2
PG4608
GAP-CLOSE-PW R-3-GP 1 2
D PG4604 D
1 2 GAP-CLOSE-PW R-3-GP
PG4609
PU4602 GAP-CLOSE-PW R-3-GP 1 2
PG4605
Main source FDMS3604 (84.00033.037) 1 2 GAP-CLOSE-PW R-3-GP
+PW R_SRC_1D5V PG4610
GAP-CLOSE-PW R-3-GP 1 2
PG4606
5V_S5 1 2 GAP-CLOSE-PW R-3-GP
PU4602 PG4611
PC4614
2 GAP-CLOSE-PW R-3-GP 1 2
ZZ MOS
SC1U10V3KX-3GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PG4625
PC4613
3
1
PC4601
PC4609
PC4611
PC4612
3D3V_S0 84.00172.037 1 4 1 2 GAP-CLOSE-PW R-3-GP
10 PG4612
1
BSZ115N03MSC 9 GAP-CLOSE-PW R-3-GP 1 2
2
Id=20A, Qg=9.8nC, 7
8 6 GAP-CLOSE-PW R-3-GP
2
1
Rdson=8.9 mohm 5 PG4613

PR4604 1 2
20KR2J-L2-GP
FDMS3600-02-RJK0215-COLAY-GP GAP-CLOSE-PW R-3-GP
PU4601 PG4614
2
PR4605_2
20 12 PC4619 Design Current = 16.04A 1 2
19,45,47,93 RUNPW ROK PGOOD V5IN SCD1U25V3KX-GP 84.00033.037
17 PR4605 25.2A<OCP< 29.8A GAP-CLOSE-PW R-3-GP
37 0D75V_EN VTTEN
15 PW R_1D5V_VBST1 2 1 2
2nd = 84.06920.037 PG4615
PW R_1D5V_EN 16
VBST 2D2R3J-2-GP 68.1R01C.10Q 1 2
EN/PSV
C
PW R_1D5V_VREF 6 PW R_1D5V_DRVH
2ND = 68.1R01B.10J 1D5V_PW R GAP-CLOSE-PW R-3-GP
C
VREF DRVH 14
1
PL4601 PG4616
PR4603 1 2
10KR2F-2-GP 13 PW R_1D5V_SW 1 2
SW
GAP-CLOSE-PW R-3-GP
COIL-1UH-51-GP-U PG4617
SCD1U10V2KX-5GP
SC4D7U6D3V5KX-3GP
2
1
PW R_1D5V_REFIN 8 11 PW R_1D5V_DRVL 1 2
PC4621
REFIN DRVL
1
PT4603
PC4620
1
1
PG4607
10 PR4612 GAP-CLOSE-PW R-3-GP
47KR2F-GP
DY DY
SCD1U50V3KX-GP
SCD1U10V2KX-4GP
PGND
1 PR4601 2
SE470UF2VDM-GP
PW R_1D5V_MODE 19 2D2R5F-2-GP PG4618
SCD01U16V2KX-3GP
GAP-CLOSE-PWR-3-GP
2
MODE
1
PC4603
EC4601
1 2
200KR2F-L-GP
2
1
1 PR4608 2
PW R_1D5V_TRIP 18 PW R_1D5V_VDDQS
PC4602
9 GAP-CLOSE-PW R-3-GP
2
TRIP VDDQS TPS51216_PHS_SET PG4619

80K6R2F-GP
PWR_1D5V_VDDQS
2
PR4602
PR4601_1
VTTIN 2 1 2
1
+0D75V_DDR_P
5K1R2F-2-GP
PW R_1D5V_VTTREF5
VTTREF
1
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3 PC4622 GAP-CLOSE-PW R-3-GP
VTT DY
1
PC4610 SC330P50V2KX-3GP
PR4606
79.47719.2BL PG4620
2
PC4616
PC4617
1
SCD22U6D3V2KX-1GP 1
PC4615
1 1 2
2
VTTS
21 GND DY 2ND = 77.24771.13L
2
2
VTTGND
7 PG4621
GND
1 2
X02 1223 X01 1110 TPS51216RUKR-GP
GAP-CLOSE-PW R-3-GP
74.51216.073 1D5V_PW R
PG4622
1 2
SC1U10V3KX-3GP
PC4604
1
B GAP-CLOSE-PW R-3-GP B
PG4623
1 2
2
GAP-CLOSE-PW R-3-GP
PG4624
1 2
+0D75V_DDR_P 0D75V_S0 GAP-CLOSE-PW R-3-GP
PG4601
2 1
GAP-CLOSE-PW R
X02 1229
PG4602
2 1
GAP-CLOSE-PW R PR4607
State S3 S5 VDDR VTTREF VTT 1 2 PW R_1D5V_EN
19,27 PM_SLP_S4#
S0 Hi Hi On On On 0R0402-PAD
1
DDR_VREF_S3 PC4606
PR4611
S3 Lo Hi On On Off(Hi-Z) DY SCD1U10V2KX-5GP
PW R_1D5V_VTTREF 1 2
2
S4/S5 Lo Lo Off Off Off
0R0603-PAD
MODE X02 1229

PR4608 Frequency Discharge Mode <Variant Name>
A A
200k ohm 400kHz
Tracking Discharge Wistron Corporation
100k ohm 300kHz
68k ohm 300kHz I/P cap:10U 25V K0805 X5R/ 78.10622.51L Taipei Hsien 221, Taiwan, R.O.C.
Non-tracking Discharge Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M Cyntec 3mohm/3.3mohm Isat =28Arms68.1R01C.10Q
47k ohm 400kHz Title
O/P cap: CHIP CAP 470UF 2V EEFSX0D471X 6mOhm 3.5Arm/Panasonic/79.47719.2BL
H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037 TPS51216_+1.5V_SUS
A3
X01
5
4
vinafix 3 2
1
46 of 104
a f i x
Vin
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
APL5930 for 1D8V_S0
D D
+1.8V_RUN
Design current = 1.086A
3D3V_S5
5V_S5
1D8V_PW R 1D8V_S0
C PC4703 C
PG4709
SC10U6D3V3MX-GP
1 2
1
PC4701 GAP-CLOSE-PW R-3-GP
SC1U10V3KX-3GP 1D8V_PW R
2
PU4701 PG4707
1 2
19,45,46,93 RUNPW ROK
VIN#5
6 VCNTL VOUT#4 4
PR4701 7 3 PG4708
1D8V_RUN_EN POK VOUT#3
19,27,36,37 PM_SLP_S3# 1 2 8 EN FB 2 1 2
0R2J-2-GP 9 VIN#9 GND 1
GAP-CLOSE-PW R-3-GP
PR4703 PC4704
SC4700P50V2KX-1GP
1
1
APL5930KAI-TRG-GP PC4705 PC4706
5912_1.8V_RUN_FB
16K5R2F-2-GP
SC68P50V2JN-1GP
PR4702
PC4702
DY DY 74.05930.03D DY
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
47KR2J-2-GP
2ND = 74.G9731.03D
2
2
2
2
1
PR4704
13K3R2F-L1-GP
B B
Vout=0.8V*(R1+R2)/R2
<Variant Name>
A A
Wistron Corporation
Title
APL5930 1D8V_S0
A3
5
4
vinafix 3 2
1
47 of 104
a f i x
Vin
5 4 3 2 1
APL5916 for VCCSA

1D05V_VTT
PG4812
1 2
GAP-CLOSE-PW R-3-GP
PG4811
D 1 2 D
GAP-CLOSE-PW R-3-GP
PG4810
1 2
PWR_VCCSA_VIN
GAP-CLOSE-PW R-3-GP
PG4801
5V_S5 1 2
GAP-CLOSE-PW R-3-GP
1
X00 PG4802
PR4801 1 2
3D3V_S0
0R2J-2-GP
GAP-CLOSE-PW R-3-GP
Iomax=6A
PG4809 OCP>9A
2
PW R_VCCSA_VCNTL 1 2
VCCSA=0.9V
1
1 PC4802 PC4803
GAP-CLOSE-PW R-3-GP
PC4801
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PR4802 SC1U6D3V2KX-GP
2
1KR2F-3-GP
2
2
6
PU4801 PG4803
1 2
VCNTL
7 5 0D85V_S0
42 D85V_PW RGD POK VIN VCCSA_PW R
X00 9 GAP-CLOSE-PW R-3-GP
C VIN C
PG4804
37,45 1.05VTT_PW RGD 1 PR4803 2 PW R_VCCSA_EN 8 EN VOUT 3 1 2
VOUT 4 R1
1
0R2J-2-GP GAP-CLOSE-PW R-3-GP
1
1
PR4804 PC4804 PG4805
1
PR4808 2 10KR2F-2-GP 1 2
GND
FB
SC100P50V2JN-3GP
47KR2F-GP DY DY PC4809 PC4805 PC4806
2
SC1U6D3V2KX-GP GAP-CLOSE-PW R-3-GP
2
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PW R_VCCSA_FB PT4801 PG4806
2
1
1 2
APL5916KAI-TRL-GP
R2
2
1
GAP-CLOSE-PW R-3-GP
DY
ST150U10VDM-4GP
1
PR4806 PG4807
PR4805 160KR2F-GP DY 1 2
74.05916.031 80K6R2F-GP
2ND = 74.00977.031 GAP-CLOSE-PW R-3-GP
2
PG4808
2
1 2
PWR_VCCSA_SEL1
GAP-CLOSE-PW R-3-GP
PQ4801
2N7002BK-GP
B Vout=0.8*(1+R1/R2) S
DY D
B
84.07002.I31
G
2nd = 84.2N702.W31
3rd = 84.2N702.J31
DY
PR4807
PW R_VCCSA_SEL0 1 2 VCCSA_SEL1 9
10KR2J-3-GP
1
DY PC4807
SCD1U10V2KX-4GP
<Variant Name>
A A
Wistron Corporation
Title
APL5916_VCCSA
A3
5
4
vinafix 3 2
1
48 of 104
a f i x
Vin
SSID = VIDEO SSID = Inverter
DCBATOUT_LCD
INVERTER POWER
1 R4907
2
100KR2J-1-GP
RN4901 DCBATOUT DCBATOUT_LCD
LCD1 BLON_OUT_C 1 8 BLON_OUT 27
31 LCD_TST_C 2 7 F4901 POLYSW -1D1A24V-GP-U
LCD_TST 27
NP1 3 6
1 30 LCD_BRIGHTNESS 4 5 1 2
L_BKLT_CTRL 17
2 29 SRN100J-4-GP
1
RN4903 BLON_OUT_C 3 28 69.50007.A31
SRN33J-5-GP-U LCD_BRIGHTNESS 4 27 C4905 DY C4906
LVDS_DDC_DATA SCD1U50V3KX-GP SC1KP50V2KX-1GP
17 LVDS_DDC_DATA_R 1 4 5 26 2nd = 69.50007.D31
2
17 LVDS_DDC_CLK_R 2 3 LVDS_DDC_CLK 6 25
17 LVDSA_CLK 7 24 3rd = 69.50007.A41
17 LVDSA_CLK# 8 23
17 LVDSA_DATA2 9 22 USB_CAMERA#
17 LVDSA_DATA2# 10 21 USB_CAMERA
17 LVDSA_DATA1 11 20 LCD_TST_C
12 19 LCDVDD
17 LVDSA_DATA1# 3D3V_CAMERA_S0
17 LVDSA_DATA0 13 18 3D3V_S0
17 LVDSA_DATA0# 14 17
15 16
NP2
SCD1U10V2KX-5GP
1
2
C4901
C4904
32 LCD_BRIGHTNESS
SC1U6D3V2KX-GP
LCD_TST
ETY-CONN30E-2-GP-U2
1
AFTP4906 1 USB_CAMERA#
SC33P50V2JN-3GP
AFTP4907 1 USB_CAMERA 20.F0891.030
SC33P50V2JN-3GP
1
1
EC4905
EC4906
2nd = 20.F0043.030 DY
2
USB_CAMERA USB_PP12 18 For EMI request
3D3V_S0 3D3V_CAMERA_S0
3
0818
68.00201.201 R4908
1 2
0R0603-PAD
TR4901
2nd = 68.02002.011 DLW 21HN121SQ2L-1GP
X02 SSID = VIDEO
SC33P50V2JN-3GP
1
1
EC4903 C4903
DY SC10U6D3V5KX-1GP
LCD POWER
2
2
USB_CAMERA# USB_PN12 18
3D3V_S5
LCDVDD
Close to LVDS connector Q4901
1 D D 6
2 D D 5
3D3V_S0 3 G S 4
X02 0103 R4912
15V_S5 1 2 330KR2J-L1-GP AO6402A-GP
remove R4903,R4904 co-lay position
FPVCC_CTL1
RN4902 84.06402.B3D
1
1 2
1 4 LVDS_DDC_DATA_R C4909 SCD1U25V2KX-GP R4916
2 3 LVDS_DDC_CLK_R 2nd = 84.P2703.03D150R3J-L-GP
2 DY 100KR2J-1-GP
1
3rd = 84.03456.D3D
Q4902
2
SRN2K2J-1-GP R4906
4 S1 D1 3 LCDVDD_1
84.2N702.F3F 5 G1 G2 2
2nd = 84.2N702.A3F
3rd = 84.DMN66.03F 6 D2 S2 1
Close to LVDS connector
ME2N7002DKW -G-GP
LVDSA_CLK 17 LVDS_VDD_EN
D4901 5V_S5 1 2
LCD_BRIGHTNESS R4917 100KR2J-1-GP
1
LVDSA_CLK# BAT54C-U-GP Q4903
LCD_TST_C 3 FPVCC_CTL3
3 LCDVCC_EN 1 R1
2
1
EC4907 EC4908 EC4901 EC4902 R2

DY DY PDTC144EU-1-GP
DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
2
2
84.00144.I11
SC33P50V2JN-3GP
SC33P50V2JN-3GP
27 LCD_TST_EN
83.00054.Q81 2nd = 84.05144.011

2nd = 83.00054.X81 <Variant Name>
3rd = 84.00044.B1K
3rd = 83.R2003.E81
4th = 83.BAT54.081 Wistron Corporation
For EMI request
Title
LCD Connector
A3
a f i x
Vin = VIDEO
5 4 3 2 1
SSID 3D3V_S0 5V_CRT_S0
JVGA_VS
JVGA_HS AFTP501 1 5V_CRT_S0
1
2
AFTP502 1 DDC_DATA_CON
3
4
AFTP503 1 DDC_CLK_CON
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
1
1
C5017
RN5012 RN5001 AFTP504 1 CRT_R
C5018
SRN2K2J-1-GP SRN2K2J-1-GP AFTP505 1 CRT_G
DY DY AFTP506 1 CRT_B
2
3D3V_S0 AFTP507 1 JVGA_HS
4
3
D AFTP508 1 JVGA_VS D
2
1
Q5001 DDC_DATA_CON
ME2N7002DKW -G-GP DDC_CLK_CON
4 S13 D1
DDC_DATA_CON
11/29 change CRT1 to 20.20927.015
1
1
5 G1 G2 2 84.2N702.F3F C5013
DY DY C5014
17 PCH_CRT_DDCDATA 2nd = 84.2N702.A3F SC22P50V2JN-4GP SC22P50V2JN-4GP
17 PCH_CRT_DDCCLK 6 1 3rd = 84.DMN66.03F
2
2
D2 S2
5V_CRT_S0_R
DDC_CLK_CON CRT1
9 VCC_CRT NC#4 4
NC#11 11
DDC_DATA_CON 12 16
DDC_CLK_CON DDCDATA_ID1 CHASSIS#16
15 DDCCLK_ID3 CHASSIS#17 17
CRT_R 1
CRT_G CRT_RED
2 CRT_GREEN GND 5
CRT_B 3 6
CRT_BLUE GND
GND 7
JVGA_VS 14 8
JVGA_HS VSYNC GND AFTP509
Layout Note: 13 HSYNC GND 10 1
C D-SUB-15-129-GP C
*Pi-filter & 150 Ohm pull-down
resistors should be as close 20.20948.015
as to CRT CONN.
2nd = 20.20945.015
* RGB signal will hit 75 Ohm
first, then pi-filter, finally
CRT CONN.
X01 1109
17 PCH_CRT_RED L5001 1 2 BLM15BB220SN-2GP CRT_R

68.00084.931 5V_CRT_S0_R 5V_CRT_S0 D5001 5V_S0
2nd = 68.00217.891 F5001

17 PCH_CRT_GREEN L5002 1 2 BLM15BB220SN-2GP CRT_G 1 2 2 1
68.00084.931
2nd = 68.00217.891 FUSE-1D1A6V-4GP-U CH551H-30PT-GP
17 PCH_CRT_BLUE L5003 1 2 BLM15BB220SN-2GP CRT_B 69.50007.691 83.R5003.C8F

68.00084.931 2nd = 69.50007.771 2nd = 83.R5003.G8H
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
4
3
2
1
C5007
C5008
C5009
3rd = 69.60040.011 3rd = 83.R5003.H8H
1
1
C5004
C5005
C5006
RN5003 2nd = 68.00217.891 4th = 83.5R003.08F

SRN150F-1-GP
DY DY DY
2
2
B B
5
6
7
8
5V_CRT_S0
5V_CRT_S0
D5002
5V_CRT_S0
14
10
2
CRT_R 3 DY
9 8
DY
1
Hsync & Vsync level shift DY C5012 83.3X101.011 1
SCD01U16V2KX-3GP U5001C
2nd = 83.00099.K11
2
7
DA3X101F0L-GP TC74VHCT125AFTQK2M-GP
73.74125.F0B 3rd = 83.00099.M11 D5003
14
U5001A 2 CLOSE TO
2nd = 73.74125.L13
HSYNC_5 CRT_G DY TRANSFORMER
17 CRT_HSYNC 3rd = 73.74125.L122 DY 3 3
1 5V_CRT_S0
TC74VHCT125AFTQK2M-GP 83.3X101.011
14
7
4
U5001B RN5011
JVGA_HS 2nd = 83.00099.K11 DA3X101F0L-GP
14
13
2 3
5 6 VSYNC_5 1 4 JVGA_VS
A 17 CRT_VSYNC DY DY 3rd = 83.00099.M11 D5004 <Variant Name> A
SRN0J-6-GP 2 12 11
TC74VHCT125AFTQK2M-GP DY
Wistron Corporation
7
CRT_B 3 DY U5001D 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

7
RN
1 TC74VHCT125AFTQK2M-GP Taipei Hsien 221, Taiwan, R.O.C.

RN5002 X02 1229 83.3X101.011
Title
1 4 2nd = 83.00099.K11 DA3X101F0L-GP
2 3
3rd = 83.00099.M11 CRT Connector
0R4P2R-PAD Size Document Number Rev
A3

5
http://www.vinafix.vn4 3 2
1
50 of 104
a f i x
Vin
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR HDMI CONN

X02 1229 HDMI_PLL_GND HDMI1
21 20
2
1 HDMI_DATA2_R_C_CON
HDMI_CLK_R_C R5101 R5106 Q5103
1 2 HDMI_CLK_R_C_CON HDMI_DATA1_R_C 1 2 HDMI_DATA1_R_C_CON R5123
2N7002BK-GP DY 0R2J-2-GP 2
0R0402-PAD 0R0402-PAD
3 HDMI_DATA2_R_C#_CON
4 HDMI_DATA1_R_C_CON
1
D D S 5 D
6 HDMI_DATA1_R_C#_CON
R5102 HDMI_DATA1_R_C# 1 R5105 2 HDMI_DATA1_R_C#_CON 5V_S0 7 HDMI_DATA0_R_C_CON
HDMI_CLK_R_C# 1 2 HDMI_CLK_R_C#_CON
0R0402-PAD 0R0402-PAD 84.07002.I31 8
HDMI_DATA0_R_C#_CON
9
G
changed R5101,R5102 to short pad, 2nd = 84.2N702.W31 10 HDMI_CLK_R_C_CON
removed TR5101 CMC footprint 11
removed TR5103 CMC footprint HDMI_CLK_R_C#_CON
3rd = 84.2N702.J31 12
1
13
R5113 14 5V_CRT_S0_R
DY 100KR2J-1-GP 15 DDC_CLK_HDMI
16 DDC_DATA_HDMI
17
2
HDMI_DATA0_R_C R5104 R5108
1 2HDMI_DATA0_R_C_CON HDMI_DATA2_R_C 1 2HDMI_DATA2_R_C_CON 18
19
SCD1U10V2KX-5GP
0R0402-PAD 0R0402-PAD
23 22
1
C5102
SKT-HDMI19P-63-GP-U
2
HDMI_DATA0_R_C# 1 R5103 2 HDMI_DATA0_R_C#_CON HDMI_DATA2_R_C# 1 R5107 2 HDMI_DATA2_R_C#_CON 22.10296.171
HPD_HDMI_CON
0R0402-PAD 0R0402-PAD 2nd = 22.10296.581
changed R5107,R5108 to short pad, 3rd = 22.10296.451
3D3V_S0
C C
3
Q5102
1 2HDMI_HPD_B 1 PMBS3904-1-GP
R5111 150KR2J-L1-GP 84.03904.L06
2ND = 84.03904.P11
2
1
R5110 HDMI_HPD_E 1 2 HDMI_PCH_DET 17
200KR2J-L1-GP
DY R5125 0R0402-PAD
1
R5112 X02
2
10KR2J-3-GP
C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C#
2
17 HDMI_CLK_R# C5104 SCD1U10V2KX-5GP HDMI_CLK_R_C
17 HDMI_CLK_R 1 2
C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C#

17 HDMI_DATA0_R# C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C
17 HDMI_DATA0_R 1 2

17 HDMI_DATA1_R 1 2

17 HDMI_DATA2_R 1 2
B B
8
7
6
5
8
7
6
5
RN5106 RN5107
SRN680J-GP SRN680J-GP
1
2
3
4
1
2
3
4
HDMI_PLL_GND
5V_CRT_S0_R
4
3
3D3V_S0
RN5101
SRN2K2J-1-GP
Q5104
1
2
ME2N7002DKW -G-GP
4 S13 D1
DDC_CLK_HDMI
5 G1 G2 2
17 PCH_HDMI_CLK
17 PCH_HDMI_DATA 6 D2 S2 1
84.2N702.F3F
A
2nd = 84.2N702.A3F <Variant Name>
A
3rd = 84.DMN66.03FDDC_DATA_HDMI
Wistron Corporation
Routing Guidelines:
Title
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK. HDMI Level Shifter/Connector
A3
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
52 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
LVDS_Switch
A3
vinafix
5
4 3 2
1
53 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
54 of 104
a f i x
Vin
5 4 3 2 1
SSID = User.Interface
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Size
ITP/Fan Connector
Document Number Rev
A3
vinafix
5
4 3 2
1
55 of 104
a f i x
Vin
SSID = SATA
5V_S0
SATA HDD Connector
3D3V_S0
HDD1
3D3V_S0 P1 V33 16 16
C5605
C5606
P2 17
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
V33 17
P3 V33
C5601
C5604
NP1 NP1
5V_S0 P7 V5 NP2 NP2
1
P8
2
V5
P9 V5
DY DY
2
AFTP5607 1HDD1_20 P13 S1
AFTP5608 V12 GND
1HDD1_21 P14 V12 GND S4
AFTP5609 1HDD1_22 P15 S7
V12 GND
GND P4
GND P5
21 SATA_TXP0 SCD01U16V2KX-3GP 2 1 C5602 SATA_TXP0_C S2 P6
SCD01U16V2KX-3GP A+ GND
Close to HDD1 21 SATA_TXN0 2 1 C5603 SATA_TXN0_C S3 A- GND P10
GND P12
C5615 1 2 SCD01U16V2KX-3GP SATA_RXP0_C S6
21 SATA_RXP0 C5616 B+
21 SATA_RXN0 1 2 SCD01U16V2KX-3GP SATA_RXN0_C S5 B- DAS/DSS P11
SKT-SATA7P-15P-80-GP
62.10065.H71
2nd = 62.10065.H81
ODD Connector SATA Zero Power ODD

ODD1 ODD_PW R_5V
X00 3D3V_S0
DY
18 SATA_ODD_DA# 1R5602 2 SATA_ODD_DA#_C P4 MD +5V P2 22 SATA_ODD_PW RGT
0R2J-2-GP SATA_ODD_PRSNT# P1 P3 RN5601
22 SATA_ODD_PRSNT# DP +5V SATA_ODD_PW RGT 4 1 U5601
S1 SATA_ODD_DA# 3 2 SY6288CCAC-GP ODD_PW R_5V
GND SATA_TXN4_C C5611 1 5V_S0
S4 GND A- S3 2 SCD01U16V2KX-3GP SATA_TXN4 21
S7 S2 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP SATA_TXP4 21 SRN100KJ-6-GP 4 5
GND A+ EN/EN# OCB ODD_PW R_5V
P5 GND 3 IN#3 OUT#6 6 100 mil
P6 GND 2 IN#2 OUT#7 7
8 S5 SATA_RXN4_C C5607 1 2SCD01U16V2KX-3GP SATA_RXN4 21 follow CKL1.5 1 8
GND B- GND OUT#8
1
9 S6 SATA_RXP4_C C5608 1 2SCD01U16V2KX-3GP SATA_RXP4 21 C5609
GND B+
1
1
SC10U6D3V5KX-1GP C5610
R5604 SC10U6D3V5KX-1GP
SUPPORT ZERO SATA 74.02001.079
2
10KR2J-3-GP
DY
2
SKT-SATA7P-6P-100-GP-U3
ODD 2nd = 74.06288.079
2
22.10300.211 3rd = 74.02311.079

2nd = 22.10300.201
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
Current limit
When the drive is powered off, the FET to the MD/DA pin is ON
Active High
3D3V_S0 3D3V_S0
typ =>2.5A
A00-0408 Add R5606 to pull high 3.3V_S0
2
R5605 R5606 Change pull high to 3.3V_S0

100KR2J-1-GP
DY 10KR2J-3-GP
A00-0415 Dummy R5606
1
SATA_ODD_DA#_C
ODD_PWRGT#
6
4
D2
G1
S1
Q5601 <Variant Name>

ME2N7002DKW -G-GP
D1
S2
G2
84.2N702.F3F
Wistron Corporation
1
2nd = 84.2N702.A3F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

3rd = 84.DMN66.03F Taipei Hsien 221, Taiwan, R.O.C.
Title
SATA_ODD_PW RGT SATA_ODD_DA#
HDD/ODD
Date:
X02
a f i x
Vin
5 4 3 2 1
SSID = ESATA
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
ESATA
A3
vinafix
5
4 3 2
1
57 of 104
a f i x
Vin
5 4 3 2 1
SSID = AUDIO
D Speaker Connector D
5
SPK1
1 ACES-CON4-4-GP
29 AUD_SPK_L-
29 AUD_SPK_L+ 2
29 AUD_SPK_R- 3
29 AUD_SPK_R+ 4
6
1
1
EC5801 EC5802 EC5803 EC5804
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
2
AFTP5805 1
20.F0765.004
2nd = 20.F1426.004
X02 1229
C C
change EC5801 EC5802 EC5803 AFTP5801 AUD_SPK_L-
1
EC5804 to 1000P cap for EMI request AFTP5802 1 AUD_SPK_L+
X02 1230 AFTP5803 1 AUD_SPK_R-
AFTP5804 1 AUD_SPK_R+
stuff EC5801 EC5802 EC5803
EC5804 for EMI request
B B
A <Variant Name> A
Wistron Corporation
Title
SPEAKER CONN
A3
vinafix
5
4 3 2
1
58 of 104
a f i
n = LOM x 5 4 3 2 1
ViSSID
MDO2+
MDO2-
5
ER5910 ER5911 U5901
LAN TransFormer 75R2J-1-GP

10/100
75R2J-1-GP
10/100
LAN_MDI0P
LAN_MDI0N
1
2
MCT LAN_MDI1P 4 Surge
LAN_MDI1N 6
MDO3+
D XF5901 MDO3- D
1
1CT:1CT MDO3+ ER5913 ER5912
31 LAN_MDI3P 2 23
75R2J-1-GP 75R2J-1-GP
MCT3 TVLST2304AD0-GP
1 24 10/100 10/100
31 LAN_MDI3N 3 22 MDO3- 83.02304.0AE
2
Giga Main: 68.IH106.30C MCT
2nd = 83.42236.0AE
Giga 2ND: 68.05009.30A 1CT:1CT MDO2+
31 LAN_MDI2P 5 20 3rd = 83.08902.0AE
10/100 Main: 68.HH085.301 4 21 MCT2 4th = 83.09904.AAE
MCT3
MCT2
MCT1
MCT0
6 19 MDO2-
31 LAN_MDI2N
1CT:1CT MDO1+
31 LAN_MDI1P 8 17
C5906
C5905
R5906
R5905
7 18 MCT1
1
9 16 MDO1-
31 LAN_MDI1N
4
3
XFOM RN5901
Surge Surge
SC1KP3KV8KX-GP-U
2
2
1CT:1CT MDO0+
31 LAN_MDI0P 11 14 GIGA SRN75J-2-GP-U Non-Surge Non-Surge
0R3J-0-U-GP
0R3J-0-U-GP
SC1KP3KV8KX-GP-U
2
2
10 15 MCT0
1
2
LOM_TCT
12 13 MDO0-
31 LAN_MDI0N
C C
1MCT1_C
1MCT0_C
XFORM-24P-19-GP
1
R5902 R5901
C5902 75R5F-1-GP 75R5F-1-GP
SCD1U10V2KX-5GP GD5901
2
2
MDO0+ 1 2 MDO0-
Surge
GT1206150ASMD-1-GP-U
1 MCT
GD5902
Surge
1
MDO1+ 1 2 MDO1- Non-Surge
C5901
Surge SC1KP3KV8KX-GP-U C5911
2
SC1KP2KV6KX-GP
GT1206150ASMD-1-GP-U
B B
0722 : change to gas tube
RJ45
RJ45
9 NP1
CHASSIS
MDO0+ 1
MDO0- 2
MDO1+ 3
MDO2+ 4
MDO2- 5
MDO1- 6
A MDO3+ 7 <Variant Name> A
MDO3- 8
MDO1+ 1 AFTP5901
CHASSIS
MDO2+ AFTP5902
10 NP2
MDO2-
1
1 AFTP5903 Wistron Corporation
RJ45-8P-88-GP MDO1- 1 AFTP5904 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
MDO3+ 1 AFTP5905 Taipei Hsien 221, Taiwan, R.O.C.
MDO3- 1 AFTP5906
22.10277.T41 MDO0+ 1 AFTP5907 Title
MDO0- 1 AFTP5908
2nd = 22.10177.J61 XFOM&RJ45
A3
vinafix
5
4 3 2
1
59 of 104
a f i x
Vin
5 4 3 2 1
SSID = Flash.ROM PCH
SPI
SPI Flash ROM(8M) for PCH

3D3V_S5 KBC
3D3V_S5
follow check list 1.5
1
D D
C6001 C6002
SC10U6D3V5KX-1GP DY SCD1U10V2KX-5GP
2
8
7
6
5
RN6001
SRN3K3J-1-GP
1
2
3
4
SPI_HOLD_0#
3D3V_S5
U6001
21,27 SPI_CS0#_R 1 8
SPI_SO S# VCC
21 SPI_SO_R 1 2 2 7
0R2J-2-GP 1 SPI_WP# DQ1 HOLD#/DQ3
2 R6003 R6001 3 6
DY 33R2J-2-GP 4
W#/VPP/DQ2 C
5
SPI_CLK_R 21,27
VSS DQ0 SPI_SI_R 21,27
27 EC_SPI_DI_C 33R2J-2-GP1 2 R6002
2
1
1
R6009 N25Q064A13ESE40F-GP
EC6002 DY 4K7R2J-2-GP EC6001
SC4D7P50V2CN-1GP DY DY DY SC10P50V2JN-4GP
2
2
72.25Q64.D01
1
EC6003
SC4D7P50V2CN-1GP
2nd = 72.25Q64.C01
3rd = 72.25Q64.B01
4th = 72.25640.D01
C C
SSID = RBATT
3D3V_AUX_S5
RTC_AUX_S5 Q6001
2
+RTC_VCC
3 RTC1
3
1 RTC_PWR 1 R6006
2 1
2
1KR2J-1-GP 2
C6003 CH715FPT-GP 4
SC1U6D3V2KX-GP
1
83.R0304.B81 ACES-CON2-31-GP
2nd = 83.R2004.C81 20.F1606.002

Width=20mils 2nd = 20.F1871.002
R6007 1 DY 2 100R2J-2-GP
RTC_PWR X00
VccRTC is now connected to VccDSW3_3
1
B B
G
R6008
10MR2J-L-GP
through the Schottky diode instead of the 3.3V Sus well.
S D RTC_DET# 22
2
Q6002
2N7002BK-GP
84.07002.I31
2nd = 84.2N702.W31
3rd = 84.2N702.J31
A A
<Variant Name>
Wistron Corporation
Title
Flash/RTC
A2
5
4
vinafix 3 2
1
Sheet 60 of 104
a f i x
Vin
5 4 3 2 1
SSID = USB
USB20_VCCA USB20_VCCA
5V_S5 U6102
100 mil USB2
1 GND OUT#8 8 5
2 IN#2 OUT#7 7 1
D 3 IN#3 OUT#6 6 D
1
4 5 C6103 C6104 TC6101 DY TC6103 USB_PN1_R 2
EN/EN# OCB
1
C6102 USB_PP1_R 3
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
SC100U6D3V6MX-GP
SC1U10V3ZY-6GP 4
2
SY6288DCAC-GP AFTP6102 1 6
2
SKT-USB6-16-GP
74.02000.B71 USB_OC#0_1 18
2nd = 74.06288.A79 22.10321.S01

2nd = 22.10341.831
27 USB_PW R_EN# LOW ACTIVE TYPE!!
AFTP6101 1 USB20_VCCA
AFTP6103 1 USB_PN1_R
AFTP6104 1 USB_PP1_R
USB20_VCCB
5V_S5 U6103
100 mil
1 GND OUT#8 8
C 2 7 C
IN#2 OUT#7 TC6102
3 IN#3 OUT#6 6
1
4 5 C6105 C6106
EN/EN# OCB
1
C6107 DY
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
SC1U10V3ZY-6GP
2
SY6288DCAC-GP
2
74.02000.B71 USB_OC#8_9 18
2nd = 74.06288.A79
LOW ACTIVE TYPE!!
27 USB_PW R_EN#
X02 1230
removed R6102,R6103 co-lay position
B B
TR6101
USB_PP1_R 4 3 USB_PP1 18
USB_PN1_R 1 2 USB_PN1 18
FILTER-310-GP-U U6105
USB_PN1_R 1 6 USB_PP1_R
69.10084.101 2
ESD I/O1
GND
ESD I/O4
VP 5 5V_S5
3 DY
ESD I/O2 ESD I/O3 4
2nd = 69.10166.001
IP4220CZ6-GP
<Variant Name>
A A
Wistron Corporation
Title
USB Power SW
5
4
vinafix 3 2
1
61 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
62 of 104
a f i x
Vin
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Variant Name> A
Wistron Corporation
Title
Bluetooth
A3
vinafix
5
4 3 2
1
63 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Size
RESERVED
Document Number Rev
A3 Enrico Caruso 14 MLK DIS
vinafix
X02
5
4 3 2
1
64 of 104
a f i x
Vin
5 4 3 2 1
SSID = Wireless Mini Card Connector(802.11a/b/g)
D 3D3V_S0 D
W LAN1
3D3V_S0 53
1D5V_S0 NP1 1D5V_S0
1 2
Decap
1
1
C6502 C6503 C6504 AFTP6505 1 W LAN_ACT 3 4
1
C6506 BT_ACT 5 6
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
DY C6505
DY 7 8
SCD1U10V2KX-5GP
20 CLK_PCIE_W LAN_REQ#
2
9 10
SC10U6D3V5KX-1GP
2
2
20 CLK_PCIE_W LAN# 11 12
20 CLK_PCIE_W LAN 13 14
15 16
DY
27 E51_RXD 1R6509 20R2J-2-GP E51_RX 17 18
27 E51_TXD 1R6508 20R2J-2-GP E51_TX 19 20 W IFI_RF_EN 27
DY 21 22 PLT_RST# 5,18,27,31,71,83
20 PCIE_RXN4 23 24 3D3V_S0
5V_S5 25 26
20 PCIE_RXP4
W LAN_ACT 27 28 1D5V_S0
29 30
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PCH_SMBCLK 14,15,20
1
C6501 C6508 20 PCIE_TXN4 31 32 PCH_SMBDATA 14,15,20

20 PCIE_TXP4 33 34
DY DY 35 36 USB_PN11_R
2
BT_ACT 1R6511 2 37 38 USB_PP11_R

0R2J-2-GP 3D3V_S0 39 40
41 42
43 44 CARD_W LAN_OUT# 27
C
27 BLUETOOTH_EN 1R6510 2 45 46 CARD_W PAN_OUT# 27
C
0R2J-2-GP 47 48 1D5V_S0
49 50
5V_S5 1R6503 2 +5V_MINI_DEBUG 51 52 3D3V_S0
DY 0R2J-2-GP NP2
54
TYCO-CONN52A-2-GP
20.F1743.052
2nd = 62.10043.A51
3rd = 62.10043.H01
R6506
1 2 0R0402-PAD USB_PP11_R
X02 1229
18 USB_PP11
R6505 0R0402-PAD USB_PN11_R
18 USB_PN11 1 2
B B
A <Variant Name> A
Wistron Corporation
Title
MINICARD(WLAN)/ITP CONN
A3
vinafix
5
4 3 2
1
65 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
66 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
67 of 104
a f i x
Vin
5 4 3 2 1
SSID = User.Interface R6811 X02

1 2 5V_S5
PLED1
FRONT POWER LED 0R0402-PAD
R6806
3
X02 Q6801
R2
LED_PW R FPOW ER_LED_A 2K A1
R6813 E 2 1
1 2 PW RLED#_C B
27 PW RLED# DY
R1
C 330R2J-3-GP LED-W -27-GP
0R0402-PAD
PDTA143ET-GP
83.01221.R70
84.00143.M11 2nd = 83.00110.R70 EC6801 SC220P50V2KX-3GP
LED_PW R 1 2
D
2nd = 84.02143.011 3rd = 83.01105.070 DY D
3rd = 84.00143.N11 EC6810 SC220P50V2KX-3GP
5V_S0
SATA_LED_R 1 DY2
Q6805 HDLED1 EC6807 SC220P50V2KX-3GP

R2
E R6812
W HITE_LED_BAT# 1 DY
2
3
21 SATA_LED# 1R6810 2 SATALED#_C B R1
15KR2J-1-GP C SATA_LED_R 2 1 HDD_LED_A 1A K2
EC6809 SC220P50V2KX-3GP
PDTA143ET-GP 330R2J-3-GP LED-W -27-GP AMBER_LED_BAT# 1 DY
2
SATA HDD LED(White) 84.00143.M11 83.01221.R70
2nd = 84.02143.011 2nd = 83.00110.R70
3rd = 84.00143.N11 3rd = 83.01105.070
R6804 X02
Battery LED2(WHITE_LED) 1 2
0R0402-PAD
Q6807
R6801 WHITE
C W HITE_LED_BAT# 2 1 BAT_W HITE#
R1
27 BATT_W HITE_LED# B DY 330R2J-3-GP
E
R2 5V_S5
C PDTC124EU-1-GP CHLED1 C
84.00124.H1K 3
1
R6805 X02
1 2 2
0R0402-PAD R6803
Q6808 499R2F-2-GP LED-OW -3-GP
C AMBER_LED_BAT# 2 1 BAT_AMBER#
27 CHG_AMBER_LED# B R1
DY
83.00326.G70
E
R2 2nd = 83.01222.K70
PDTC124EU-1-GP AMBER 3rd = 83.21355.A70
Battery LED1(AMBER_LED) 84.00124.H1K
Wireless LED
B Power button B
PW RBT1
6
1 2 KBC_PW RBTN#_C 4A 4B
27 KBC_PW RBTN# R6802 3A 3B
5V_S0 100R2J-2-GP 2A 2B
W LED1
AFTP6801 1 1A 1B
R6808
3
5
27 W LAN_LED# 2 1 W LAN_LED#_R 2K A1
ACES-CONN8G-GP-U
330R2J-3-GP LED-W -27-GP
AFTP6802
83.01221.R70 20.K0464.004 1
SCD1U25V2KX-GP
2nd = 83.00110.R70 2nd = 20.K0341.004

2
EC6806
DY
3rd = 83.01105.070
1
Place EC6806 near LED2

<Variant Name>
A A
Wistron Corporation
Title
LED Bard/Power Button

A3
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
D KB1 1 AFTP6901 D
31
1 KB_DET# KB_DET# 21 TouchPad Connector
2 KROW 7
3 KROW 6
4 KROW 4
5 KROW 2
6 KROW 5 5V_S0
7 KROW 1
8 KROW 3
9 KROW 0
10 KCOL5
1
11 KCOL4 C6901
12 KCOL7 5V_S0 SCD1U10V2KX-5GP
13 KCOL6
2
14 KCOL8
15 KCOL3
2
1
16 KCOL1
17 KCOL2 AFTP6929 1 5V_S0
18 KCOL0 RN6903 AFTP6931 1 TPDATA
19 KCOL12 SRN10KJ-5-GP AFTP6930 1 TPCLK
20 KCOL16
TPAD1
21 KCOL15
3
4
22 KCOL13 6
23 KCOL14 4A 4B
24 KCOL9 27 TPCLK 3A 3B
25 KCOL11 27 TPDATA 2A 2B
26 KCOL10 AFTP6927 1
C 27 CAP_LED_R 1A 1B C
28 5
29
1
30 DY DY ACES-CONN8G-GP-U
32 C6904 C6903
SC33P50V2JN-3GP SC33P50V2JN-3GP 20.K0464.004
2
ACES-CON30-10-GP
2nd = 20.K0341.004
20.K0592.030
2nd = 20.K0621.030
3rd = 20.K0565.030
CAP_LED_R 1 AFTP6957
GND 1 AFTP6972
B
SSID = User.Interface B
CAP LED CONTROL

5V_S5
Q6902
R2
R6905 E
1 2 Q6902_B
B
27 CAP_LED# R1
CAP_LED_Q CAP_LED_R
C 1 2
15KR2J-1-GP R6906 1KR2J-1-GP
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011 1 2
R6907 DY100R2J-2-GP
3rd = 84.00143.N11
A <Variant Name> A
KCOL0 1 AFTP6918 Wistron Corporation

KROW 7 1 AFTP6902 KCOL5 1 AFTP6910 KCOL12 1 AFTP6919 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
KROW 6 1 AFTP6903 KCOL4 1 AFTP6911 KCOL16 1 AFTP6920 Taipei Hsien 221, Taiwan, R.O.C.
KROW 4 1 AFTP6904 KCOL7 1 AFTP6912 KCOL15 1 AFTP6921
KROW 2 1 AFTP6905 KCOL6 1 AFTP6913 KCOL13 1 AFTP6922 Title
KROW [7..0] 27
KROW 5 AFTP6906 KCOL8 AFTP6914 KCOL14 AFTP6923
KROW 1
1
1 AFTP6907 KCOL3
1
1 AFTP6915 KCOL9
1
1 AFTP6924 Key Board/Touch Pad
KROW 3 1 AFTP6908 KCOL1 1 AFTP6916 KCOL11 1 AFTP6925 Size Document Number Rev
KCOL[16..0] 27
KROW 0 AFTP6909 KCOL2 AFTP6917 KCOL10 AFTP6926 A3
vinafix
1 1 1
5
4 3 2
1
69 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
<Variant Name>
A A
Wistron Corporation
Title
Hall Sensor
A3
vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
D D
Layout Note: PCH Debug Connector

Place near trace separated point
3D3V_S0
X00
LPC_AD[3..0] DB1
21,27 LPC_AD[3..0]
RN7101 1
LPC_AD0 8 1 LPC_LAD0_R 2
LPC_AD2 6
LPC 3 LPC_LAD2_R 4
LPC_FRAME#_R 6 LPC
SRN0J-7-GP 5,18,27,31,65,83 PLT_RST# 7
X00 8
R7103 1 2 0R2J-2-GP 9
21,27 LPC_FRAME# 18 CLK_PCI_LPC
10
LPC 11
12
MLX-CON10-7-GP
20.D0183.110
C C
B B
<Variant Name>
A A
Wistron Corporation
Title
Debug connector
A3
5
4
vinafix 3 2
1
71 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
72 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
73 of 104
a f i x
Vin
5 4 3 2 1
SSID = SDIO
3D3V_CARD_S0
CARD1
11 SD_VDD/MMC_VDD MS_DATA0 12 XD_D1/SD_D5/MS_D0 32

MS_DATA1 13 XD_D4/SD_D3/MS_D1 32
4 10 XD_D0/SD_CLK/MS_D2_R XD_D0/SD_CLK/MS_D2_R 32
MS_VCC MS_DATA2
MS_DATA3 7 XD_ALE/SD_D7/MS_D3 32
D 3D3V_CARD_S0 32 XD_W E#/SD_CD# 20 8 XD_RE#/MS_INS# 32 D

SD_CD MS_INS
32 XD_D4/SD_D3/MS_D1 3 SD_CD/DAT3/MMC_RSV MS_BS 15 XD_D6/MS_BS 32
MS_SCLK 5 XD_RDY/SD_W P/MS_CLK 32
XD_D0/SD_CLK/MS_D2_R 14
SC2D2U6D3V3KX-GP
32 XD_D0/SD_CLK/MS_D2_R SD_CLK/MMC_CLK
6
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
32 XD_D2/SD_CMD SD_CMD/MMC_CMD
C7404
C7405
GND 23
1
1
C7401
C7402
C7403
32 XD_CLE/SD_D0/MS_D7 18 SD_DAT0/MMC_DAT GND 24
19
DY DY DY 32 XD_CE#/SD_D1
32 XD_D5/SD_D2/MS_D5 1
SD_DAT1
21
2
2
SD_DAT2 SD_GND
32 XD_RDY/SD_W P/MS_CLK 22 SD_WP/SW MS_VSS 2
MS_VSS 16
NP1 NP1 SD_VSS/MMC_VSS1 9

NP2 NP2 SD_VSS/MMC_VSS2 17
CARD-PUSH-22P-GP
20.I0110.021
2nd = 20.I0133.001
X00
C C
XD_ALE/SD_D7/MS_D3
XD_D1/SD_D5/MS_D0
XD_CLE/SD_D0/MS_D7
XD_CE#/SD_D1
XD_D5/SD_D2/MS_D5
XD_D4/SD_D3/MS_D1
XD_D2/SD_CMD
XD_D0/SD_CLK/MS_D2_R
XD_W E#/SD_CD#
SC4D7P50V2BN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
XD_RDY/SD_W P/MS_CLK
EC7401
EC7402
EC7403
EC7404
EC7405
EC7406
EC7407
EC7408
EC7409
EC7410
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
1
1
DY DY DY DY DY DY DY DY DY DY
2
For EMI
B B
A <Variant Name> A
Wistron Corporation
Title
SD/XD/MS/MMC Card CONN

A3
vinafix
5
4 3 2
1
74 of 104
a f i x
Vin
5 4 3 2 1
SSID = ExpressCard
D D
C C
B B
<Variant Name>
A A
Wistron Corporation
Title
Express Card
A3
5 4
vinafix
3 2
1
75 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
76 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
77 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
78 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Free Fall Sensor

A3
vinafix
5
4 3 2
1
79 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
80 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
vinafix
5
4 3 2
1
81 of 104
a f i x
Vin = USB
5 4 3 2 1
SSID
X02 1230
removed R8203,R8204 co-lay position
IOBD1 is for USB board
D D
USB20_VCCB
IOBD1
TR8202
17
1
USB_PN9_R 4 3 USB_PN9 18 2
3
4
FILTER-310-GP-U 5
6
USB_PN9_R 7
69.10084.101 USB_PP9_R 8
9
2nd = 69.10166.001 USB_PN8_R 10
USB_PP8_R 11
12
13
14
15
X02 1230 16
removed R8201,R8202 co-lay position 18
C C
PTW O-CON16-1-GP
20.K0429.016
2nd = 20.K0460.016
TR8201
USB_PN8_R 4 3 USB_PN8 18
FILTER-310-GP-U
69.10084.101
2nd = 69.10166.001
B
SSID = Audio IOBD2 is for Audio board
B
IOBD2
17
29 INT_MIC_L_R 1
2
29 AUD_HP1_JACK_L2 3
29 AUD_HP1_JACK_R2 4
5
29 MIC_IN_L 6
29 MIC_IN_R 7
8
29 EXT_MIC_JD# 9
29 AUD_HP1_JD# 10
11
27 LID_CLOSE# 12
13
3D3V_S5 14
15
16
18
A MIC_IN_L 1 2 <Variant Name> A
SC10P50V2JN-4GP DY EC8201 PTW O-CON16-1-GP
MIC_IN_R 1 2
SC10P50V2JN-4GP DY EC8202 20.K0429.016
AUD_HP1_JACK_L2 1 2 Wistron Corporation
SC10P50V2JN-4GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
AUD_HP1_JACK_R2 1
DY EC8203 2nd = 20.K0460.016 Taipei Hsien 221, Taiwan, R.O.C.
2
SC10P50V2JN-4GP DY EC8204 Title
Size
IO Board Connector
Document Number Rev
A3 Enrico Caruso 14 MLK DIS
vinafix
X02
5
4 3 2
1
82 of 104
a f i x
Vin
5 4 3 2 1
1D05V_VGA_S0
3D3V_VGA_S0 3D3V_VGA_S0 C8334 C8336 C8337 C8335 C8338 C8339 C8346
Decap Decap
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
X02 1223
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
1
1
2N7002BK-GP
1
10KR2J-3-GP
10KR2J-3-GP
84.07002.I31 Q8301 X02 1223 R8303 VGA1A
OPS 1 OF 14
DY DY
DY
2
R8302 OPS OPS OPS
2nd = 84.2N702.W31 1/14 PCI_EXPRESS OPS OPS
D S
3rd = 84.2N702.J31
2
AB6
PEX_WAKE#
D D
AA22
VGA_RST# PEX_IOVDD
AC7 AB23
PEX_RST# PEX_IOVDD
AC24
R8308 1 VGA_PEG_CLKREQ# PEX_IOVDD
20R2J-2-GP AC6 AD25
20 PEG_CLKREQ#
DY
PEX_CLKREQ# PEX_IOVDD
AE26
X7R, Under GPU. X7R, Near GPU and power soruce.
PEX_IOVDD
20 CLK_PCIE_VGA AE8 AE27
PEX_REFCLK PEX_IOVDD
20 CLK_PCIE_VGA# AD8
PEX_REFCLK#
PEG_RXP0 SCD22U10V2KX-1GP 1 2 OPS C8301 PEG_C_RXP0 AC9
PEG_RXN0 SCD22U10V2KX-1GP PEG_C_RXN0 PEX_TX0 1D05V_VGA_S0
1 2 OPS C8302 AB9
PEX_TX0#
PEG_TXP0 AG6
PEG_TXN0 PEX_RX0
AG7 AA10
PEX_RX0# PEX_IOVDDQ
AA12
PEG_RXP1 SCD22U10V2KX-1GP PEG_C_RXP1 PEX_IOVDDQ
1 2 OPS C8303 AB10
PEX_TX1 PEX_IOVDDQ
AA13 C8345 C8342 C8343
PEG_RXN1 SCD22U10V2KX-1GP 1 2 OPS C8304 PEG_C_RXN1 AC10 AA16
PEX_TX1# PEX_IOVDDQ
AA18 Decap Decap
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
PEX_IOVDDQ
SCD1U10V2KX-5GP
PEG_TXP1 AF7 AA19 C8344 C8341 C8347
1
PEG_TXN1 PEX_RX1 PEX_IOVDDQ
AE7 AA20
1
PEX_RX1# PEX_IOVDDQ
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
AA21
1 2 OPS C8305 AD11 AB22 DY
2
PEG_RXN2 SCD22U10V2KX-1GP PEG_C_RXN2 PEX_TX2 PEX_IOVDDQ
1 2 OPS C8306 AC11 AC23 OPS OPS OPS
2
PEX_TX2# PEX_IOVDDQ OPS OPS
AD24
PEG_TXP2 PEX_IOVDDQ
AE9 AE25
PEG_TXN2 PEX_RX2 PEX_IOVDDQ
AF9 AF26
PEX_RX2# PEX_IOVDDQ
AF27
1 2 OPS C8308 AC12
PEX_TX3
PEG_RXN3 SCD22U10V2KX-1GP 1 2 OPS C8307 PEG_C_RXN3 AB12
PEX_TX3#
PEG_TXP3 AG9
PEG_TXN3 AG10
PEX_RX3 X7R, Under GPU.
PEX_RX3#
PEG_RXP4 SCD22U10V2KX-1GP 1 2 OPS C8309 PEG_C_RXP4 AB13
PEG_RXN4 SCD22U10V2KX-1GP PEG_C_RXN4 PEX_TX4
1 2 OPS C8310 AC13
PEX_TX4#
PEG_TXP4 AF10
PEG_TXN4 PEX_RX4
AE10
PEX_RX4#
PEG_RXP5 SCD22U10V2KX-1GP 1 2 OPS C8311 PEG_C_RXP5 AD14 210 mA
1 2 OPS C8312 AC14
PEX_TX5# PEX_PLL_HVDD
AA8
C AA9 3D3V_VGA_S0 C
PEG_TXP5 PEX_PLL_HVDD
AE12
PEG_TXN5 PEX_RX5 C8367 C8371 C8366
AF12
PEX_RX5#
AB8
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
1
PEG_RXP6 SCD22U10V2KX-1GP C8313 PEG_C_RXP6 PEX_SVDD_3V3
1 2 OPS AC15 OPS OPS DY
SCD1U10V2KX-5GP
PEG_RXN6 SCD22U10V2KX-1GP C8314 PEG_C_RXN6 PEX_TX6
1 2 OPS AB15
PEX_TX6#
2
PEG_TXP6 AG12
PEG_TXN6 PEX_RX6
AG13
PEX_RX6#
PEG_RXP7 SCD22U10V2KX-1GP 1 2 OPS C8316 PEG_C_RXP7 AB16
1 2 OPS C8315 AC16
PEX_TX7#
PEG_TXP7 AF13
PEG_TXN7 PEX_RX7
AE13
PEX_RX7#
AD17 NC
PEX_TX8
AC17 NC
PEX_TX8#
AE15 NC
PEX_RX8
AF15 NC
PEX_RX8#
AC18 NC F2
PEX_TX9 VDD_SENSE NVVDD_SENSE 92
AB18 NC
PEX_TX9#
AG15 NC F1
PEX_RX9 GND_SENSE NVGND_SENSE 92
AG16 NC
PEX_RX9#
4 PEG_TXP[0..7] PEG_RXP[0..7] 4
AB19 NC
PEX_TX10
4 PEG_TXN[0..7] PEG_RXN[0..7] 4 AC19 NC
PEX_TX10#
AF16 NC
PEX_RX10
AE16 NC
PEX_RX10#
AD20 NC
PEX_TX11
AC20 NC
PEX_TX11#
AE18 NC
PEX_RX11
AF18 NC
PEX_RX11#
AC21 NC
B PEX_TX12 R8305 B
AB21 NC
PEX_TX12# 200R2F-L-GP
PEX_TSTCLK_OUT
DY 1D05V_VGA_S0
AG18 NC AF22 1 2
PEX_RX12 PEX_TSTCLK_OUT PEX_TSTCLK_OUT#
AG19 NC AE22
PEX_RX12# PEX_TSTCLK_OUT#
AD23 NC
PEX_TX13
AE23 NC
PEX_TX13#
AF19
PEX_RX13 NC PEX_PLLVDD
AA14 150mA X02
AE19 NC AA15 VCC1R05VIDEO_PEX_PLLVDD 1 2
PEX_RX13# PEX_PLLVDD
L8302 0R0603-PAD
AF24 NC C8369 C8368 C8370
PEX_TX14
AE24 NC
1
PEX_TX14#
OPS OPS
SCD1U10V2KX-5GP
SC4D7U25V5KX-GP
AE21 DY
SC1U10V3KX-3GP
PEX_RX14 NC
AF21 NC R8304
2
PEX_RX14# TESTMODE
AD9 1 2
TESTMODE 10KR2J-3-GP
AG24
PEX_TX15 NC OPS
AG25 NC
PEX_TX15#
AG21 NC
PEX_RX15
AG22 NC
PEX_RX15#
GF119 GF117 R8306
AF25 PEX_TERMP 2 1
PEX_TERMP
2K49R2F-GP
N13M-NS-S-A1-GP
OPS
dGPU reset
R8307
DY
22 DGPU_HOLD_RST# 1 2
0R2J-2-GP VGA_RST# 86
A A
3D3V_VGA_S0
U8301
22 DGPU_HOLD_RST# 1 5
A VCC
5,18,27,31,65,71 PLT_RST# 2
B OPS
3 4 VGA_RST# X01 1110
2
GND Y
U74LVC1G08G-AL5-R-GP-U R8319 Wistron Corporation
DY 10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
73.01G08.EHG
1
2nd = 73.7SZ08.EAH Title
20100621 NV suggestion 3rd = 73.7SZ08.DAH GPU_PCIE(1/5)

4th = 73.01G08.L04 A2
5
4
vinafix 3 2
1
Sheet 83 of 104
a f i x
Vin
5 4 3 2 1
88,89 FBA_D[63..0] VGA1B 2 OF 14

2/14 FBA
FBA_D0 E18 GF119 F3
FBA_D0 NC FB_CLAMP
D FBA_D1 F18 D
FBA_D2 FBA_D1
E16 GF117
1
FBA_D3 FBA_D2
F17
FBA_D4 FBA_D3
D20
FBA_D5 FBA_D4
D21
FBA_D5 OPS R8411
FBA_D6 F20 10KR2J-3-GP
FBA_D7 FBA_D6
E21
2
FBA_D8 FBA_D7
E15
FBA_D9 FBA_D8
D15
FBA_D10 FBA_D9
F15
FBA_D11 FBA_D10
F13 1D5V_VGA_S0
FBA_D12 FBA_D11
C13
FBA_D13 FBA_D12 4 OF 14 VGA1D
B13
FBA_D14 FBA_D13
E13 12/14 FBVDDQ
FBA_D15 FBA_D14
FBA_D16
D13
FBA_D15 Decap Decap Decap Decap
B15 B26
FBA_D17 FBA_D16 FBVDDQ C8409 C8408 C8411 C8410 C8412 C8433 C8434 C8432
C16 C25
FBA_D18 FBA_D17 FBVDDQ
A13 E23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
A15 E26
1
B18 F14
A18 F21
A19 G13
2
C19
FBA_D23 FBVDDQ
G14 OPS OPS OPS OPS OPS OPS OPS OPS
FBA_D24 B24 G15
C23 G16
A25 G18
A24 G19
A21 G20
B21 G21
C20 H24
C21 H26
FBA_D33
R22
R24
FBA_D32
C27
FBVDDQ
J21
K21
Under GPU Near GPU
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD0 88 FBVDDQ
T22 C26 FBA_CMD1 1 TP8414 TPAD14-OP-GP L22
FBA_D35 FBA_D34 FBA_CMD1 FBVDDQ
R23 E24 L24
N25 F24 L26
N26 D27 M21
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD4 88,89 FBVDDQ
N23 D26 N21
N24 F25 R21
V23 F26 T21
V22 F23 V21
C T23 G22 W21 C
U22 G23
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD10 88,89
Y24 G24
AA24 F27
Y22 G25
AA23 G27
AD27 G26
AB25 M24
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD16 89
AD26 M23 FBA_CMD17 1 TP8415 TPAD14-OP-GP
FBA_D51 FBA_D50 FBA_CMD17
AC25 K24
AA27 K23
AA26 M27
W26 M26
Y25 M25
R26 K26
T25 K22
N27 J23
R27 J25
V26 J24
V27 K27
W27 K25
W25 J27
FBA_D63 FBA_CMD30 FBA_CMD30 88,89
J26 FBA_CMD31 1 TP8401 TPAD14-OP-GP 1D5V_VGA_S0
FBA_CMD31
D19
88 FBA_DQM0 FBA_DQM0 R8401
88 FBA_DQM1
D14
FBA_DQM1
OPS
C17 1 2 FB_CAL_PD_VDDQ D22
88 FBA_DQM2 FBA_DQM2 1D5V_VGA_S0 FB_CAL_PD_VDDQ
C22 40D2R2F-GP
88 FBA_DQM3 FBA_DQM3
P24
89 FBA_DQM4 FBA_DQM4 FB_CAL_PU_GND
W24 C24
89 FBA_DQM5 FBA_DQM5 FB_CAL_PU_GND
AA25
89 FBA_DQM6 FBA_DQM6 FBA_DEBUG0 R8424 1
U25 F22 DY 2 60D4R2F-GP
89 FBA_DQM7 FBA_DQM7 FBA_DEBUG0 FBA_DEBUG1 FB_CAL_TERM_GNDB25
J22 1 DY 2 60D4R2F-GP
FBA_DEBUG1 R8428 FB_CAL_TERM_GND
E19
88 FBA_DQS_WP0 FBA_DQS_WP0 N13M-NS-S-A1-GP
C15
88 FBA_DQS_WP1 FBA_DQS_WP1
88 FBA_DQS_WP2
B16
B22
FBA_DQS_WP2 FBA_CLK0
D24
D25
FBA_CLK0 88 OPS
88 FBA_DQS_WP3 FBA_DQS_WP3 FBA_CLK0# FBA_CLK0# 88
2
R25 N22
89 FBA_DQS_WP4 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 89
W23 M22 R8405 R8404
89 FBA_DQS_WP5 FBA_DQS_WP5 FBA_CLK1# FBA_CLK1# 89
AB26 42D2R2F-GP 51D1R2F-GP
B 89 FBA_DQS_WP6 FBA_DQS_WP6 B
89 FBA_DQS_WP7
T26
FBA_DQS_WP7 OPS OPS
1
F19 D18
88 FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK1
C14 C18
88 FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK1#
A16 D17
A22 D16
P25 T24
W22 U24
AB27 V24
T27 V25
30ohm@100MHZ(ESR=0.01ohm)
F16 1D05V_VGA_S0
FB_PLLAVDD
P22 L8401
FB_PLLAVDD
GF119 FB_DLLAVDD
H22 FB_PLLVDD_16mil 1 ( ( 2
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
BLM18KG300TN1D-GP
SCD1U10V2KX-5GP
GF117 FB_PLLAVDD
C8431 CHIP BEAD BLM18KG300TN1D MURATA
1
C8413 C8435 OPS

OPS OPS DY 68.00084.H41
2
2nd = 68.00376.041
TPAD14-OP-GP TP8416 1 D23
FB_VREF_PROBE
Near GPU.
N13M-NS-S-A1-GP
OPS
A A
Wistron Corporation
Title
GPU_Memory(2/5)
A2
5
4
vinafix 3 2
1
Sheet 84 of 104
a f i x
Vin
5 4 3 2 1
LVDS
VGA1J 10 OF 14
7 OF 14 7/14 IFPEF
D VGA1G D
4/14 IFPAB GF119
GF117
GF117 GF119 DVI-DL DVI-SL/HDMI DP
NC AC4 NC I2CY_SDA I2CY_SDA J3

IFPA_TXC# GF119 GF117 IFPE_AUX_I2CY_SDA#
NC AC3 NC I2CY_SCL I2CY_SCL J2
GF119 GF117 IFPA_TXC IFPE_AUX_I2CY_SCL
J7 NC
IFPEF_PLLVDD
AA6 NC
IFPAB_RSET
NC Y3 NC TXC TXC J1
IFPA_TXD0# IFPE_L3#
NC Y4 NC TXC TXC K1
IFPA_TXD0 IFPE_L3
K7 NC
IFPEF_PLLVDD
V7 NC K3
IFPAB_PLLVDD NC TXD0 TXD0 IFPE_L2#
NC AA2 NC K2
IFPA_TXD1# TXD0 TXD0 IFPE_L2
W7 NC NC AA3
IFPAB_PLLVDD IFPA_TXD1
K6 NC NC TXD1 TXD1 M3
IFPEF_RSET IFPE_L1#
NC TXD1 TXD1 M2
IFPE_L1
NC AA1
IFPA_TXD2#
NC AB1 M1
IFPA_TXD2 NC TXD2 TXD2 IFPE_L0#
NC N1
TXD2 TXD2 IFPE_L0
NC AA5
IFPA_TXD3#
NC IFPA_TXD3
AA4 IFPE
NC AB4 NC HPD_E HPD_E C2

IFPB_TXC# GPIO18
NC AB5
IFPB_TXC
GF119 GF117
GF119 GF117
W6 NC NC AB2
IFPA_IOVDD IFPB_TXD4#
NC AB3 H6 NC
IFPB_TXD4 IFPE_IOVDD
Y6 NC GF119
IFPB_IOVDD
J6 NC GF117
IFPF_IOVDD DVI-DL DVI-SL/HDMI DP
NC AD2
IFPB_TXD5#
NC AD3 NC I2CZ_SDA H4
IFPB_TXD5 IFPF_AUX_I2CZ_SDA#
NC I2CZ_SCL H3
IFPF_AUX_I2CZ_SCL
NC AD1
IFPB_TXD6#
NC AE1 NC TXC J5
IFPB_TXD6 IFPF_L3#
NC TXC J4
IFPF_L3
NC AD5 NC TXD3 TXD0 K5

IFPB_TXD7# IFPF_L2#
C NC AD4 NC TXD3 TXD0 K4 C
IFPB_TXD7 IFPF_L2
NC TXD4 TXD1 L4
IFPF IFPF_L1#
NC TXD4 TXD1 L3
IFPF_L1
NC TXD5 TXD2 M5
IFPF_L0#
NC B3 NC TXD5 TXD2 M4
GPIO14 IFPF_L0
IFPAB
N13M-NS-S-A1-GP
NC HPD_F F7
OPS GPIO19
N13M-NS-S-A1-GP
OPS
VGA1K 11 OF 14
3/14 DACA
GF119 GF117
GF117 GF119
DACA_VDD W5 NC NC B7
1
DACA_VDD I2CA_SCL
NC A7
R8503 DACA_VREF I2CA_SDA
TP8502 1 AE2 TSEN_VREF
DACA_VREF
0R0402-PAD
B TPAD14-OP-GP AF2 AE3 B
DACA_RSET NC NC DACA_HSYNC
X02 NC AE4
2
DACA_VSYNC
NC AG3
DACA_RED
NC AF4
DACA_GREEN
NC AF3
DACA_BLUE
VGA1H 8 OF 14
5/14 IFPC
IFPC
N13M-NS-S-A1-GP GF119 GF117
T6 NC GF117 GF119
IFPC_RSET
OPS DVI/HDMI DP
M7 NC NC I2CW_SDA IFPC_AUX_I2CW_SDA# N5
IFPC_PLLVDD
N7 NC NC I2CW_SCL N4
IFPC_PLLVDD IFPC_AUX_I2CW_SCL
NC TXC N3
IFPC_L3#
NC TXC N2
VGA1I 9 OF 14 IFPC_L3
6/14 IFPD NC TXD0 R3
IFPC_L2#
NC TXD0 R2
GF119 GF117 IFPC_L2
GF117 GF119
U6 NC NC TXD1 R1
IFPD_RSET IFPC_L1#
NC TXD1 T1
DVI/HDMI DP IFPC_L1
NC TXD2 T3
IFPC_L0#
T7 NC NC I2CX_SDA IFPD_AUX_I2CX_SDA# P4 NC TXD2 T2
IFPD_PLLVDD IFPC_L0
NC I2CX_SCL P3
IFPD_AUX_I2CX_SCL
R7 NC
IFPD_PLLVDD
NC TXC R5 P6 NC NC C3
IFPD_L3# IFPC_IOVDD GPIO15
NC TXC R4
IFPD_L3
T5 N13M-NS-S-A1-GP
NC TXD0 IFPD_L2#
NC TXD0 T4
A IFPD_L2 A
NC TXD1 U4 OPS
IFPD IFPD_L1#
NC TXD1 U3
IFPD_L1
NC TXD2 V4
IFPD_L0#
NC TXD2 V3
IFPD_L0
R6
IFPD_IOVDD GF119 NC GPIO17
D4 Wistron Corporation
NC GF117 Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DP/LVDS/CRT(3/5)
N13M-NS-S-A1-GP Size Document Number Rev
A2
http://www.vinafix.vn vinafix
OPS Date: Tuesday, January 03, 2012 Sheet 85 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
3D3V_VGA_S0
1.05V +/- 3%
150mA
(See NV DG)
3
4
1D05V_VGA_S0 PLLVDD_PWR
RN8606
SRN2K2J-1-GP
OPS
L8601
1 2 VGA1N 14 OF 14
2
1
8/14 MISC1
X02 0R0603-PAD D9 SMBC_Therm_NV
I2CS_SCL SMBD_Therm_NV
D8
I2CS_SDA
SC4D7U6D3V3KX-GP
1
1
SC10U6D3V3MX-GP
C8604 C8605 C8608 A9 GPU_LVDS_CLK1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8612 C8609 I2CC_SCL GPU_LVDS_DATA1
B9
I2CC_SDA
2
DY DY OPS VGA1M 13 OF 14
OPS OPS 28 P2800_VGA_DXN E12
THERMDN
GF117 GF119
9/14 XTAL_PLL NC C9
I2CB_SCL
28 P2800_VGA_DXP F12 NC C8
THERMDP I2CB_SDA
L6
CORE_PLLVDD
M6
SP_PLLVDD JTAG_TCK_VGA
20 JTAG_TCK_VGA AE5
NV_TMS JTAG_TCK
N6 GF119 TPAD14-OP-GP TP8603 1 AD6
D VID_PLLVDD NV_TDI JTAG_TMS D
TPAD14-OP-GP TP8604 1 AE6
NV_TDO JTAG_TDI
1 AF6
X7R, Under GPU. NC GF117 TPAD14-OP-GP TP865
JTAG_TRST# AG4
JTAG_TDO
JTAG_TRST# GPIO0
C6 NV_VID4 NV_VID4 92
B2 NV_VID3 NV_VID3 92
GPIO1
2
1
D6
VIDEO_CLK_XTAL_SS GPIO2
A10 C10 N12P_XTAL_OUTBUFF RN8602 C7
XTAL_SSIN XTAL_OUTBUFF GPIO3
OPS SRN10KJ-5-GP F9
GPIO4 NV_VID1
A3 NV_VID1 92
GPIO5 NV_VID2
C11 B10 A4 NV_VID2 92
XTAL_IN XTAL_OUT GPIO6
B6
3
4
N13M-NS-S-A1-GP GPIO7 NV_THERM_OVERT
A6
GPIO8
1
NV_THERM_ALERT
OPS GPIO9
F8
1
R8605 C5
GPIO10 NV_VID0
10KR2J-3-GP E7 NV_VID0 92
R8604 GPIO11 PWR_LEVEL
OPS GPIO12
D7
10KR2J-3-GP B4 NV_VID5 NV_VID5 92
2
27MHZ_OUT GPIO13
OPS
2
27MHZ_IN
GF117 GF119
C8611 NC D5
SC10P50V2JN-4GP GPIO16
X01 1116 NC GPIO20
E6
2 1 NC C4
GPIO21
OPS
2
R8607 N13M-NS-S-A1-GP
1
82.30034.641 X8601
0R0402-PAD
1MR2F-GP VGA1 X02 1230
2nd = 82.30034.651OPS XTAL-27MHZ-85-GP OPSR8606 X02
1
add R8608,Q8603;change Q8603.2 to OVER_CURRENT_P8
3rd = 82.30034.681
2
from AC_PRESENT for OC trigger IPCC fuction
1
2
C8610
X01 1116
2 1
SC10P50V2JN-4GP
27MHZ_OUT_R
3D3V_VGA_S0
GPIO12 3D3V_VGA_S0
OPS
OPS 1 R8608 2 OVER_CURRENT_P8#_R
1 - > normal mode
1 R8610 2 H_PROCHOT#_LL
100KR2J-1-GP
D G S 0 -> P8 mode DY 100KR2J-1-GP
D G S
I2CA=>CRT, I2CC=>LVDS. OPS
4
D2
G1
S1
Q8603
D2
G1
S1
ME2N7002DKW-G-GP Q8604 DY
3D3V_VGA_S0 ME2N7002DKW-G-GP
D1
S2
G2
84.2N702.F3F
D1
S2
G2
84.2N702.F3F
3
2nd = 84.2N702.A3F
3
1
S G D R8609 2nd = 84.2N702.A3F
3rd = 84.DMN66.03F OPS 10KR2J-3-GP S G D
3rd = 84.DMN66.03F
PWR_LEVEL
2
27 OVER_CURRENT_P8#
PWR_LEVEL
5 H_PROCHOT#_L
C C
PURE_HW_SHUTDOWN# 27,28,36
3D3V_VGA_S0
D
Q8602
2N7002BK-GP
R8641
RN8603
NV_THERM_OVERT
83 VGA_RST# 2
0R2J-2-GP
DY1VGA_RST#_R G 84.07002.I31
1 4
NV_THERM_ALERT 2 3 DY 2nd = 84.2N702.W31
3rd = 84.2N702.J31
S
SRN10KJ-5-GP
OPS NV_THERM_OVERT
3D3V_VGA_S0
Hynix:72.52G63.A0U (HT31P$AA)
Samsung:72.42164.D0U (JP0F2$AA)
3
4
RN8605
SRN4K7J-8-GP
OPS
Q8601 OPS
2
1
SMBC_Therm_NV 1 6 THM_SML1_CLK 20,28
2 5
THM_SML1_DATA 20,28
3 4
DMN66D0LDW-7-GP
84.DMN66.03F
SMBD_Therm_NV 2ND = 84.27002.E3F
B B
3D3V_VGA_S0
1
1
HYNIX
R8630
OPS R8632 R8634
DY 45K3R2F-L-GP 10KR2F-2-GP 10KR2F-2-GP
2
RAM_CFG[0] 2
RAM_CFG[1]
RAM_CFG[2]
1
3D3V_VGA_S0 SAMSUNG
OPS R8631
3D3V_VGA_S0
10KR2F-2-GP
DY R8633
34K8R2F-1-GP
R8635
10KR2F-2-GP
2
2
1
R8636
VGA1L N13M-NS-S-A1-GP 12 OF 14
DY 10KR2J-3-GP
10/14 MISC2
2
DY DY DY
2KR2F-3-GP
15KR2F-GP
10KR2F-2-GP
3D3V_VGA_S0
E10 R8624 R8625 R8626
VMON_IN0
F10 D12 ROM_CS#
VMON_IN1 ROM_CS#
2
B12 SUB_VENDOR
ROM_SI
A12 VGA_DEVICE
RAM_CFG[0] ROM_SO
D1 C12 SMB_ALT_ADDR
RAM_CFG[1] STRAP0 ROM_SCLK
D2
STRAP1
1
RAM_CFG[2] E4
RAM_CFG[3] STRAP2
PCIE_MAX_SPEED
E3
D3
STRAP3 OPS R8627 OPS R8617 OPS R8618
STRAP4
1
10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP

SAMSUNG R8638
GF119 DY
2
GF117
R8637 4K99R2F-L-GP
C1 10KR2F-2-GP
STRAP5 NC
D11
2
BUFRST#
STRAP_REF1_GND_J1 F6 D10 RAM_CFG[3]
MULTI_STRAP_REF0_GND PGOOD
GF119
PCIE_MAX_SPEED
GF117
1
F4
MULTI_STRAP_REF1_GND NC
E9
OPS R8639
CEC 10KR2F-2-GP
F5 NC
MULTI_STRAP_REF2_GND
1
HYNIX
2
R8640 R8623
A N13x GPUs do not support CEC.Leave the CEC pin as NC 10KR2F-2-GP
OPS 10KR2F-2-GP A
1
40K2R2F-GP
OPS
2
DY
2
R8613
Wistron Corporation
Title
vinafix
GPU_GPIO(4/5)
A1
Sheet 86 of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
VGA_CORE
Under GPU VGA1E 5 OF 14

11/14 NVVDD
VGA1F 6 OF 14 K10 VDD
13/14 GND K12 VDD
A2 M13 C8701 C8702 C8703 C8704 C8705 C8706 C8707 C8708 K14
GND GND VDD
AB17 GND GND M15 K16 VDD
1
AB20 M17 K18
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
GND GND VDD
AB24 GND GND N10 L11 VDD
D AC2 N12 L13 D
2
GND GND VDD
AC22 GND GND N14 OPS OPS OPS OPS OPS OPS OPS OPS L15 VDD
AC26 GND GND N16 L17 VDD
AC5 GND GND N18 M10 VDD
AC8 GND GND P11 M12 VDD
AD12 GND GND P13 M14 VDD
AD13 GND GND P15 M16 VDD
A26 GND GND P17 M18 VDD
AD15 GND GND P2 N11 VDD
AD18 GND GND P26 NEAR GPU Under GPU N15 VDD
AD21 GND GND R10 Decap Decap Decap P10 VDD
AD22 GND GND R12 P12 VDD
AE11 R14 C8731 C8730 C8719 C8718 C8717 C8716 C8715 C8714 C8713 C8712 C8711 C8710 C8709 P14
GND GND VDD
AE14 GND GND R16 P16 VDD
1
AE17 R18 P18
SC22U6D3V3MX-L-GP
SC47U6D3V5MX-1-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
GND GND VDD
AE20 GND GND T11 DY R11 VDD
AB11 T13 R13
2
GND GND VDD
AF1 GND GND T15 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS R15 VDD
AF11 GND GND T17 R17 VDD
AF14 GND GND U10 T10 VDD
AF8 GND GND U2 U11 VDD
AG2 GND GND U23 U13 VDD
AG26 GND GND U26 U15 VDD
C AB14 U5 U17 C
GND GND VDD
B1 GND GND V11 V10 VDD
B20 GND GND Y2 V18 VDD
B23 GND GND Y23
B27 GND GND Y26
B5 Y5 N13M-NS-S-A1-GP
GND GND
B8 GND
E11
E14
GND OPS
GND
E17 GND
E2 GND
E20 GND
E22 GND
E25 GND
E5 GND
E8 GND
H2 GND
H23 GND
H25 GND
H5 GND
K11 GND
K13 GND 3D3V_VGA_S0
K15 GND
K17 VGA1C 3 OF 14
GND
L10 GND 14/14 XVDD/VDD33
L12 GND
B B
L14 GND AD10 NC#AD10 VDD33 G10
L16 GND AD7 NC#AD7 VDD33 G12
L18 B19 G8 C8734 C8735 C8739 C8736 C8732 C8733
GND NC#B19 VDD33
L2 G9
SC4D7U6D3V3KX-GP
GND VDD33 OPS DY OPS OPS
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L23 OPS OPS
SC1U10V3KX-3GP
GND
L25 GND F11 3V3AUX
L5 AA7
2
GND GND
M11 GND GND AB7
N13M-NS-S-A1-GP
OPS CONFIGURABLE
POWER CHANNELS
* nc on substrate
G1
Under GPU NEAR GPU
NC#G1
G2 NC#G2
G3 NC#G3
G4 NC#G4
G5 NC#G5
G6 NC#G6
G7 NC#G7
V1 NC#V1
V2 NC#V2
A V5 NC#V5 A
V6 NC#V6
W1 NC#W1
Wistron Corporation
W2 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
NC#W2 Taipei Hsien 221, Taiwan, R.O.C.
W3 NC#W3
W4 NC#W4 Title
N13M-NS-S-A1-GP GPU_DPPWR/GND(5/5)
A3
vinafix
OPS Enrico Caruso 14 MLK DIS X02
5
1
87 of 104
a f i x
Vin
5 4 3 2 1
1D5V_VGA_S0
1D5V_VGA_S0
VRAM2
VRAM1 FBA_D[63..0] 84,89
FBA_D[63..0] 84,89 FBA_D23
K8 E3
FBA_D0 VDD DQL0 FBA_D16
K8 E3 K2 F7
VDD DQL0 FBA_D4 VDD DQL1 FBA_D20
K2 F7 N1 F2
N1 F2 R9 F8
R9 F8 B2 H3
B2 H3 D9 H8
D9 H8 G7 G2
G7 G2 R1 H7
VDD DQL6 FBA_D7 VDD DQL7
R1 H7 N9
VDD DQL7 VDD FBA_D31
N9 D7
VDD FBA_D11 DQU0 FBA_D25
D7 A8 C3
DQU0 FBA_D12 VDDQ DQU1 FBA_D30
A8 C3 A1 C8
D VDDQ DQU1 FBA_D10 VDDQ DQU2 FBA_D24 D
A1 C8 C1 C2
VDDQ DQU2 FBA_D13 VDDQ DQU3 FBA_D28
C1 C2 C9 A7
C9 A7 D2 A2
D2 A2 E9 B8
E9 B8 F1 A3
VDDQ DQU6 FBA_D14 VDDQ DQU7
F1 A3 H9
VDDQ DQU7 VDDQ
H9 H2 C7 FBA_DQS_WP3 84
VDDQ VDDQ DQSU
H2 C7 FBA_DQS_WP1 84 B7 FBA_DQS_RN3 84
VDDQ DQSU FBA_VREF_0 DQSU#
B7 FBA_DQS_RN1 84 H1
FBA_VREF_0 DQSU# VREFDQ
H1 M8 F3 FBA_DQS_WP2 84
VREFDQ VRAM_CH_A_ZQ_2 VREFCA DQSL
M8 F3 FBA_DQS_WP0 84 L8 G3 FBA_DQS_RN2 84
VRAM_CH_A_ZQ_1 VREFCA DQSL ZQ DQSL#
L8 G3 FBA_DQS_RN0 84
1
ZQ DQSL#
K1 FBA_CMD2 84
1
ODT
K1 FBA_CMD2 84 84,89 FBA_CMD9 N3
ODT R8802 A0
R8801 84,89 FBA_CMD9 N3 84,89 FBA_CMD11 P7
A0 243R2F-2-GP A1
243R2F-2-GP 84,89 FBA_CMD11 P7 84,89 FBA_CMD8 P3 L2 FBA_CMD0 84
A1 A2 CS#
84,89 FBA_CMD8 P3 L2 FBA_CMD0 84 OPS 84,89 FBA_CMD25 N2 T2 FBA_CMD5 84,89
2
A2 CS# A3 RESET#
OPS 84,89 FBA_CMD25 N2 T2 FBA_CMD5 84,89 84,89 FBA_CMD10 P8
2
A3 RESET# A4
84,89 FBA_CMD10 P8 84,89 FBA_CMD24 P2
A4 A5
84,89 FBA_CMD24 P2 84,89 FBA_CMD22 R8 T7 FBA_CMD4 84,89
A5 A6 NC#T7
84,89 FBA_CMD22 R8 T7 FBA_CMD4 84,89 84,89 FBA_CMD7 R2 L9
A6 NC#T7 A7 NC#L9
84,89 FBA_CMD7 R2 L9 84,89 FBA_CMD21 T8 L1
A7 NC#L9 A8 NC#L1
84,89 FBA_CMD21 T8 L1 84,89 FBA_CMD6 R3 J9
A8 NC#L1 A9 NC#J9
84,89 FBA_CMD6 R3 J9 84,89 FBA_CMD29 L7 J1
A9 NC#J9 A10/AP NC#J1
84,89 FBA_CMD29 L7 J1 84,89 FBA_CMD23 R7
A10/AP NC#J1 A11
84,89 FBA_CMD23 R7 84,89 FBA_CMD28 N7
A11 A12/BC#
84,89 FBA_CMD28 N7 84,89 FBA_CMD20 T3 J8
A12/BC# A13 VSS
84,89 FBA_CMD20 T3 J8 84,89 FBA_CMD14 M7 M1
A13 VSS NC#M7 VSS
84,89 FBA_CMD14 M7 M1 M9
NC#M7 VSS 1D5V_VGA_S0 VSS
M9 J2
VSS VSS
J2 84,89 FBA_CMD12 M2 P9
VSS BA0 VSS
MODE D 84,89 FBA_CMD12 M2 P9 84,89 FBA_CMD27 N8 G8
1
BA0 VSS BA1 VSS
84,89 FBA_CMD27 N8 G8 84,89 FBA_CMD26 M3 B3
BA1 VSS R8803 BA2 VSS
84,89 FBA_CMD26 M3 B3 T1
BA2 VSS 1K33R2F-GP VSS
R8807 1 T1 A9
OPS 2 162R2F-GP VSS VSS
VSS
A9 OPS 84 FBA_CLK0 J7
CK VSS
T9
J7 T9 K7 E1
2
84 FBA_CLK0 CK VSS 84 FBA_CLK0# CK# VSS
84 FBA_CLK0# K7 E1 P1
CK# VSS FBA_VREF_0 VSS
P1 84 FBA_CMD3 K9
VSS CKE
84 FBA_CMD3 K9 G1
1
CKE VSSQ
G1 F9
1
C VSSQ R8804 C8802 VSSQ C
F9 84 FBA_DQM3 D3 E8
VSSQ 1K33R2F-GP SCD01U50V2KX-1GP DMU VSSQ
84 FBA_DQM1 D3 E8 84 FBA_DQM2 E7 E2
DMU VSSQ DML VSSQ
E7 E2 OPS OPS D8
2
84 FBA_DQM0 DML VSSQ VSSQ
D8 D1
2
VSSQ VSSQ
D1 84,89 FBA_CMD13 L3 B9
VSSQ WE# VSSQ
84,89 FBA_CMD13 L3 B9 84,89 FBA_CMD15 K3 B1
WE# VSSQ CAS# VSSQ
84,89 FBA_CMD15 K3 B1 84,89 FBA_CMD30 J3 G9
CAS# VSSQ RAS# VSSQ
84,89 FBA_CMD30 J3 G9
RAS# VSSQ
H5TQ2G63BFR-11C-GP
H5TQ2G63BFR-11C-GP
OPS
OPS 72.52G63.A0U
72.52G63.A0U
1D5V_VGA_S0 DG requires 4x0.1uF and 8x1.0uF per

VRAM chip
Decap Decap C8805 C8806 C8807 C8808
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D5V_VGA_S0
1
FOR VRAM1
1
SCD1U10V2KX-5GP
1
1
1
C8801 C8803 Decap Decap Decap Decap
2
OPS OPS
2
2
2
OPS DY OPS OPS
Decap
1
1D5V_VGA_S0 C8809
CLOSE TO THE MEMORY OPS SC10U6D3V3MX-GP
2
20110725 for Vendor
CLOSE TO THE MEMORY
C8813 C8814 C8816
Decap Decap C8815
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
SC1U6D3V3KX-2GP
1
1
B C8810 C8811 B
Decap Decap Decap
FOR VRAM2 OPS OPS
2
OPS DY DY
X02 1229
removed C8815 follow NV suggestion
follow NV FAE suggest
FBA_CMD2 R8805 OPS 2 10KR2J-3-GP

ODT 1
FBA_CMD3 R8806 OPS 2 10KR2J-3-GP

CKE 1
FBA_CMD5 R8808 2 10KR2J-3-GP

RST 1 OPS
A A
Wistron Corporation
Title
GPU_VRAM1,2 (1/4)
A2
5
http://www.vinafix.vn 4
vinafix 3 2
1
Sheet 88 of 104
a f i x
Vin
5 4 3 2 1
1D5V_VGA_S0
1D5V_VGA_S0
VRAM4
VRAM3 FBA_D[63..0] 84,88
FBA_D[63..0] 84,88
K8 E3 FBA_D43
K8 E3 FBA_D33 VDD DQL0
VDD DQL0 K2 F7 FBA_D44
K2 F7 FBA_D39 VDD DQL1
VDD DQL1 N1 F2 FBA_D40
N1 F2 FBA_D35 VDD DQL2
VDD DQL2 R9 F8 FBA_D45
R9 F8 FBA_D36 VDD DQL3
VDD DQL3 B2 H3 FBA_D41
D B2 H3 FBA_D34 VDD DQL4 D
VDD DQL4 D9 H8 FBA_D46
D9 H8 FBA_D38 VDD DQL5
VDD DQL5 G7 G2 FBA_D42
G7 G2 FBA_D32 VDD DQL6
VDD DQL6 R1 H7 FBA_D47
R1 H7 FBA_D37 VDD DQL7
VDD DQL7 N9
N9 VDD FBA_D51
VDD FBA_D59 D7
D7 DQU0 FBA_D52
DQU0 FBA_D60 A8 C3
A8 C3 VDDQ DQU1 FBA_D50
VDDQ DQU1 FBA_D58 A1 C8
A1 C8 VDDQ DQU2 FBA_D53
VDDQ DQU2 FBA_D61 C1 C2
C1 C2 VDDQ DQU3 FBA_D49
VDDQ DQU3 FBA_D57 C9 A7
C9 A7 VDDQ DQU4 FBA_D55
VDDQ DQU4 FBA_D63 D2 A2
D2 A2 VDDQ DQU5 FBA_D48
VDDQ DQU5 FBA_D56 E9 B8
E9 B8 VDDQ DQU6 FBA_D54
VDDQ DQU6 FBA_D62 F1 A3
F1 A3 VDDQ DQU7
VDDQ DQU7 H9
H9 VDDQ
VDDQ H2 C7 FBA_DQS_WP6 84
H2 C7 FBA_DQS_WP7 84 VDDQ DQSU
VDDQ DQSU B7 FBA_DQS_RN6 84
B7 FBA_DQS_RN7 84 FBA_VREF_1 DQSU#
FBA_VREF_1 DQSU# H1
H1 VREFDQ
VREFDQ M8 F3 FBA_DQS_WP5 84
M8 F3 FBA_DQS_WP4 84 VRAM_CH_A_ZQ_4 VREFCA DQSL
VRAM_CH_A_ZQ_3 VREFCA DQSL L8 G3 FBA_DQS_RN5 84
L8 G3 FBA_DQS_RN4 84 ZQ DQSL#
ZQ DQSL#
ODT K1 FBA_CMD18 84
1
ODT K1 FBA_CMD18 84
1
84,88 FBA_CMD9 N3 A0
84,88 FBA_CMD9 N3 A0 84,88 FBA_CMD11 P7 A1
84,88 FBA_CMD11 P7 A1 R8904
R8901 84,88 FBA_CMD8 P3 A2 CS# L2 FBA_CMD16 84
84,88 FBA_CMD8 P3 A2 CS# L2 FBA_CMD16 84 243R2F-2-GP
243R2F-2-GP84,88 FBA_CMD25 84,88 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 84,88
N2 T2 FBA_CMD5 84,88
A3 RESET# OPS 84,88 FBA_CMD10 P8
2
OPS 84,88 FBA_CMD10 P8 A4
2
A4 84,88 FBA_CMD24 P2
84,88 FBA_CMD24 P2 A5
A5 84,88 FBA_CMD22 R8 T7 FBA_CMD4 84,88
84,88 FBA_CMD22 R8 T7 FBA_CMD4 84,88 A6 NC#T7
A6 NC#T7 84,88 FBA_CMD7 R2 L9
84,88 FBA_CMD7 R2 L9 A7 NC#L9
A7 NC#L9 84,88 FBA_CMD21 T8 L1
84,88 FBA_CMD21 T8 L1 A8 NC#L1
C A8 NC#L1 84,88 FBA_CMD6 R3 J9 C
84,88 FBA_CMD6 R3 J9 A9 NC#J9
A9 NC#J9 84,88 FBA_CMD29 L7 J1
84,88 FBA_CMD29 L7 J1 A10/AP NC#J1
A10/AP NC#J1 84,88 FBA_CMD23 R7
84,88 FBA_CMD23 R7 A11
A11 84,88 FBA_CMD28 N7
84,88 FBA_CMD28 N7 A12/BC#
A12/BC# 84,88 FBA_CMD20 T3 J8
84,88 FBA_CMD20 T3 J8 A13 VSS
A13 VSS 84,88 FBA_CMD14 M7 M1
84,88 FBA_CMD14 M7 M1 NC#M7 VSS
NC#M7 VSS M9
M9 VSS
VSS J2
J2 VSS
1D5V_VGA_S0 VSS 84,88 FBA_CMD12 M2 P9
84,88 FBA_CMD12 M2 P9 BA0 VSS
BA0 VSS 84,88 FBA_CMD27 N8 G8
84,88 FBA_CMD27 N8 G8 BA1 VSS
BA1 VSS 84,88 FBA_CMD26 M3 B3
84,88 FBA_CMD26 M3 B3 BA2 VSS
BA2 VSS
1
VSS T1
R8908 1 OPS T1
R8902 2 162R2F-GP VSS
VSS A9
VSS A9
1K33R2F-GP 84 FBA_CLK1 J7 CK VSS T9
84 FBA_CLK1 J7 CK VSS T9
84 FBA_CLK1# K7 E1
OPS 84 FBA_CLK1# K7 CK# VSS E1 CK# VSS
P1
P1 VSS
2
VSS 84 FBA_CMD19 K9
84 FBA_CMD19 K9 CKE
FBA_VREF_1 CKE G1
G1 VSSQ
VSSQ F9
F9 VSSQ
VSSQ
1
84 FBA_DQM6 D3 DMU VSSQ E8

84 FBA_DQM7 D3 DMU VSSQ E8
1
R8903 C8902 84 FBA_DQM5 E7 DML VSSQ E2

84 FBA_DQM4 E7 DML VSSQ E2
1K33R2F-GP SCD01U50V2KX-1GP VSSQ D8
VSSQ D8
D1
OPS OPS D1 VSSQ
2
VSSQ 84,88 FBA_CMD13 L3 B9

84,88 FBA_CMD13 L3 B9 W E# VSSQ
2
W E# VSSQ 84,88 FBA_CMD15 K3 B1

84,88 FBA_CMD15 K3 B1 CAS# VSSQ
CAS# VSSQ 84,88 FBA_CMD30 J3 G9
84,88 FBA_CMD30 J3 G9 RAS# VSSQ
RAS# VSSQ
H5TQ2G63BFR-11C-GP
H5TQ2G63BFR-11C-GP
B OPS OPS B
72.52G63.A0U 72.52G63.A0U
follow NV FAE suggest

1D5V_VGA_S0
FBA_CMD18 R8909 1 OPS 2 10KR2J-3-GP

C8905 C8906 C8907 C8908
ODT
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Decap Decap
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
FBA_CMD19 R8910 1 OPS 2 10KR2J-3-GP

CKE
FOR VRAM3
1
C8901 C8903 Decap Decap Decap Decap

OPS OPS
2
OPS OPS OPS OPS 1D5V_VGA_S0
C8909
SC4D7U6D3V3KX-GP
1D5V_VGA_S0
CLOSE TO THE MEMORY
1
Decap
2
C8913 C8915 C8916 OPS

SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Decap Decap
1
A C8910 C8911 Decap C8914 Decap Decap A
FOR VRAM4 OPS OPS DY

CLOSE TO THE MEMORY
2
OPS OPS OPS

Wistron Corporation
Title
GPU_VRAM3,4 (2/4)
vinafix
Custom
X02
http://www.vinafix.vn Date:
Enrico Caruso 14
Tuesday, January 03, 2012
MLK
Sheet 89
DIS
of 104
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3

5
4 3 2
1
90 of 104
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3

5
4 3 2
1
91 of 104
a f i x
Vin
5 4 3 2 1
D D
V-BOOT VID0 VID1 VID2 VID3 VID4 VID5 VID6
0.9000V 0 0 0 0 1 1 0
3D3V_S5
1
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
DY OPS OPS DY DY DY DY
PR9201
PR9202 PR9203 PR9204 PR9205 PR9206 PR9207
2
PWR_VGA_CORE_VID6 DCBATOUT PWR_DCBATOUT_VGA_CORE
NV_VID5 PR9215 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID5 PG9201
86 NV_VID5
NV_VID4 PR9216 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID4 1 2
86 NV_VID4
NV_VID3 PR9217 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID3 GAP-CLOSE-PWR-3-GP
86 NV_VID3
NV_VID2 PR9218 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID2
86 NV_VID2
NV_VID1 PR9241 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID1 PG9202
86 NV_VID1
NV_VID0 PR9242 1 OPS 2 0R2J-2-GP PWR_VGA_CORE_VID0 1 2
86 NV_VID0
GAP-CLOSE-PWR-3-GP
1
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
OPS OPS OPS OPS OPS PG9203
DY DY 1 2
PR9208 PR9209 PR9210 PR9211 PR9212 PR9213 PR9214 X01 1103 GAP-CLOSE-PWR-3-GP
2
2
PG9204
1 2
GAP-CLOSE-PWR-3-GP
5V_S5 PG9205
1 2
83.R5003.C8F GAP-CLOSE-PWR-3-GP
Please confirm with H/W for resistor pull high and pull GND 2nd = 83.R5003.G8H
3rd = 83.R5003.H8H PG9208
1
4th = 83.5R003.08F 1 2
PD9201 PR9220 GAP-CLOSE-PWR-3-GP
OPS10R2J-2-GP
93 DGPU_PWR_EN 2 DY1
2
CH551H-30PT-GP PWR_DCBATOUT_VGA_CORE
X01 1103
OPS
3D3V_VGA_S0 1 2 PWR_VGA_CORE_VR_ON
1
C PR9219 C
X01 1103 X01 1114
0R2J-2-GP PC9201 DY PC9213 PC9214 PC9216 PC9215
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD1U25V3KX-GP
1
PC9202
PWR_VGA_CORE_VCC
SC1U10V2KX-1GP
1
OPS Design Current = 25A
2
OPS OPS OPS OPS
OCP>31A
2
3D3V_S0
5
6
7
8
PU9202
D
D
D
D
GND_3211
1
VGA_CORE
SIR172DP-T1-GE3-GP
OPS
84.00172.037
32
31
30
29
28
27
26
25
OPS PR9221 PU9201 2ND = 84.07698.037
OPS 10KR2J-3-GP
EN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
G
S
S
S
GND_3211 2 1 PC9203
2
SC1KP50V2KX-1GP PR9240
4
3
2
1
0R2J-2-GP PC9211
PR9222
22,27,93 DGPU_PWROK
1
PWRGD VCC
24 OPS SCD22U25V3KX-GP PWR_VGA_CORE_UG 68.R2210.10N
1 DY 2 2 23 PWR_VGA_CORE_BOOT 1 OPS 2 PWR_VGA_CORE_BOOT_R 1 2
IMON BST PL9201
3 22 PWR_VGA_CORE_UG
66K5R2F-GP PWR_VGA_CORE_FBRTN CLKEN# DRVH PWR_VGA_CORE_SW PWR_VGA_CORE_SW
4
FBRTN SW
21 1 OPS 2
PWR_VGA_CORE_FB 5 20 5V_S0
PWR_VGA_CORE_COMP FB PVCC PWR_VGA_CORE_LG IND-D22UH-28-GP
6 19
SC100P50V2JN-3GP
COMP DRVL
SE470UF2VDM-GP
SE470UF2VDM-GP
PR9225 7 18
SC22P50V2JN-4GP
5V_S0 GPU PGND

OPS 1 OPS 2 PWR_VGA_CORE_ILIM 8 17
ILIM GND
1
5
6
7
8
5
6
7
8
1
PT9201
PT9202
33 OPS OPS OPS
CSCOMP
D
D
D
D
D
D
D
D
GND
1
PC9204 OPS 2K26R2F-1-GP PC9212 PU9203 PU9204 79.47719.2BL
CSREF
79.47719.2BL
RAMP
LLINE
CSFB
PC9206 X01 1110 SC2D2U10V3KX-1GP PG9206 PG9207
IREF
RPM
84.00166.037
2
2
SIR166DP-T1-GE3-GP
SIR166DP-T1-GE3-GP
OPS 2ND = 77.24771.13L
RT
2
PC9205 PWR_VGA_CORE_CSCOMP OPS OPS 2ND = 77.24771.13L

2ND = 84.00309.037
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1
1
OPS SC470P50V2KX-3GP OPS
9
10
11
12
13
14
15
16
G
S
S
S
G
S
S
S
1 2 1 2 1 2 ADP3211MNR2G-GP
PWR_VGA_CORE_FB_L
OPS 74.03211.033
4
3
2
1
4
3
2
1
PR9223 PR9224 GND_3211
2
1KR2F-3-GP 20KR2F-L-GP PWR_VGA_CORE_IREF
PWR_VGA_CORE_RPM
PWR_VGA_CORE_RT
PWR_VGA_CORE_CSCOMP
PWR_VGA_CORE_CSREF
PWR_VGA_CORE_FB_R
PWR_VGA_CORE_LLINE
PWR_VGA_CORE_CSFB
PWR_VGA_CORE_RAMP PWR_VGA_CORE_LG PWR_VGA_CORE_LG
84.00166.037
PR9228
1 OPS 2 PWR_VGA_CORE_CSCOMP_R
2ND = 84.00309.037
1
PR9229 PR9230
80K6R2F-GP
2
PR9235
PR9226 PR9227 OPS OPS OPS OPS PR9231 NTC-220K-2-GP
191KR2F-1-GP
300KR2F-L-GP
0R2J-2-GP OPS OPS 0R2J-2-GP 422KR2F-1-GP

PR9237 PR9238
2
2
1
1 OPS 2 1 OPS 2 1 OPS 2 PWR_VGA_CORE_L_L

PWR_VGA_CORE_RAMP_1
PR9236 196KR3F-2-GP X01 1110

174KR2F-GP
76K8R2D-GP
1
SC330P50V2KX-3GP
PR9233 OPS OPSPC9209 OPS PC9210
GND_3211 20KR2F-L-GP SC560P50V2KX-2GP
2
B B
2
PWR_DCBATOUT_VGA_CORE
1
1 OPS 2
PR9234 OPS
PR9232 20KR2F-L-GP
1KR2F-3-GP
2
1
OPS
PC9207
NVGND_SENSE
PWR_VGA_CORE_CSCOMP
NVVDD_SENSE
SC1KP50V2KX-1GP
2
OPS
1
GND_3211 PC9208
SC1KP50V2KX-1GP
2
83 NVGND_SENSE NVVDD_SENSE 83
GND_3211
OPS
1 2
Please confirm on H/W side whether have resistor pull high and pull GND by 100 ohm PR9239
0R2J-2-GP
GND_3211
A A
Wistron Corporation
Title
ADP3211_+VGA_CORE
Custom
Enrico Caruso 14 X01
vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
3D3V_S0 to 3D3V_VGA_S0 Transfer

3D3V_VGA_S0
DY
3D3V_S0 PR93011 20R2J-2-GP
DMP2130L-7-GP 84.02130.031
2nd = 84.00102.031
2
1
PR9316 PQ9302 D 3rd = 84.03413.A31
D
D 10KR2F-2-GP OPS PC9324 D
G
OPS 4th = 84.02301.G31 3D3V_VGA discharge
2
SCD1U10V2KX-5GP OPS
1
G
PR9319
1 2 PQ9302_G
10KR2F-2-GP
OPS
PR9319_1
X01 1108
1
6
4
PQ9303 PR9314
220R2J-L2-GP
D2
G1
S1
ME2N7002DKW-G-GP
84.2N702.F3F
2nd = 84.2N702.A3F OPS OPS
D1
S2
G2
2
3rd = 84.DMN66.03F
1
3
OPS PR9337
1 2 3.3V_RUN_VGA_1
19,45,46,47 RUNPWROK 100KR2J-1-GP
PR9321
3D3V_S0 1 DY 2
10KR2J-3-GP
DGPU_PWR_EN
22 DGPU_PWR_EN# NV do not need 1.8V

G
S D DGPU_PWR_EN 92
OPS
C C
PQ9304
2N7002BK-GP
2nd = 84.2N702.W31
3rd = 84.2N702.J31
84.07002.I31
DGPU_PWR_EN#
dGPU mode L
IGPU H
IGPU with BACO L
change low Rds(on) MOSFET

1D5V_VGA_S0 1D5V_S3
ZZ MOS 1D5V_VGA_S0
1D05V_VGA_S0
PU9305
AO4468, SO-8 8 D S 1
7 D S 2 0629 Modify: 3D3V_VGA_S0 should ramp-up before VGA_Core
Id=?A, Qg=9~12nC 6 D S 3 Add PC9332 10uF 0603.
1
Rdson=17.4~22m ohm 5 D G OPS PC9332 1D05V_VTT 1D05V_VGA_S0

4 VGA_Core should ramp-up before 1D5V_VGA_S0
1
OPS
1D5V_ENABLE_RC
PC9327
OPS 84.04468.037 SC10U6D3V3MX-GP PU9306
1D5V_VGA_S0 should ramp-up before 1D05V_VGA_S0
2
AO4468, SO-8 8 D S 1
SC10U6D3V3MX-GP
POWERPAK-8P-GP
2
2nd = 84.02659.037 7 D S 2 Decap 0629 Modify:

Id=?A, Qg=9~12nC 6 D S 3 Add PC9332 10uF 0603.
3rd = 84.04178.037
1
4th = 84.04496.037 Rdson=17.4~22m ohm 5 D G 4
DY PC9333
1D05V_ENABLE_RC
1
5th = 84.04800.D37 PC9329
B SC10U6D3V3MX-GP B
OPS AO4468-GP
2
84.04468.037
SC10U6D3V3MX-GP
2
PR9330 2nd = 84.02659.037
1 OPS 2 3rd = 84.04178.037
Discharge Circuit 4th = 84.04496.037
0R2J-2-GP 5th = 84.04800.D37
1
3D3V_AUX_S5 PC9326 OPS 1D5V_VGA_S0

OPS SCD01U50V2KX-1GP PR9334
2
1 2 1D5V_VGA_EN# 1 OPS 2
PR9332 100KR2J-1-GP
Discharge Circuit
1
D G S 0R2J-2-GP
1
OPS PR9336
83.R5003.C8F 470R2J-2-GP 3D3V_AUX_S5 PC9328 OPS 1D05V_VGA_S0
6
2nd = 83.R5003.G8H PQ9305 OPS SCD01U50V2KX-1GP
2
15V_S5
D2
G1
S1
3rd = 83.R5003.H8H ME2N7002DKW-G-GP 1 2 1D05V_VGA_EN#

DIS_1D5V_VGA_S02
4th = 83.5R003.08F PR9333 100KR2J-1-GP

84.2N702.F3F
1
2nd = 84.2N702.A3F OPS D G S
D1
S2
G2
PD9301 3rd = 84.DMN66.03F OPS PR9338

1
1D5V_VGA_EN# 83.R5003.C8F 470R2J-2-GP
4
92 DGPU_PWR_EN 2 DY1 S G D PR9331 2nd = 83.R5003.G8H PQ9306
15V_S5
100KR2J-1-GP
D2
G1
S1
3rd = 83.R5003.H8H ME2N7002DKW-G-GP
G
2
CH551H-30PT-GP OPS 4th = 83.5R003.08F 84.2N702.F3F
PR9326 OPS 2nd = 84.2N702.A3F OPS
D1
DIS_1D05V_VGA_S0
S2
G2
1
1 OPS 2 1D5V_VGA_EN PD9302 3rd = 84.DMN66.03F
2
22,27,92 DGPU_PWROK 1D05V_VGA_EN#
D S
0R2J-2-GP 1D5V_ENABLE 2 DY1 S G D PR9335
92 DGPU_PWR_EN 100KR2J-1-GP
G
CH551H-30PT-GP OPS
OPS
1
PQ9307 PR9327 1 1D05V_VGA_EN
OPS 21KR2J-1-GP
2N7002BK-GP 22,27,92 DGPU_PWROK
D S
1D05V_ENABLE
2nd = 84.2N702.W31
3rd = 84.2N702.J31
1
PC9330
84.07002.I31 SCD1U25V2KX-GP OPS
PQ9308
2N7002BK-GP
2
2nd = 84.2N702.W31
A
3rd = 84.2N702.J31 A
84.07002.I31
<Variant Name>
Wistron Corporation
Title
DISCRETE VGA POWER
A2 Enrico Caruso 14 MLK DIS X01
5
http://www.vinafix.vn 4
vinafix 3 2 1
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
<Variant Name>
A A
Wistron Corporation
Title
LVDS_Switch
A3
vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
D D
C C
(Blanking)
B B
<Variant Name>
A A
Wistron Corporation
Title
CRT_Switch
A3
vinafix
5 4 3 2 1
a f i x
Vin
5 4 3 2 1
SSID = SDIO
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
TOUCH PANEL
A3

5
4 3 2
1
96 of 104
a f i x
Vin
5 4 3 2 1
SSID = Mechanical
SPR1 DY SPR2
SPRING-62-GP SPRING-58-GP
34.4B312.002
1
H1 H3 H4 H5 H6 H7
HT85BE85R29-U-5-GP
H2
HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85B95X975R29-S-GP 34.39S07.003
HOLE256R115-GP
D D
1
1
SPR4 SPR5
For CPU BRACKET VGA Stand-Off PCH Stand-Off SPRING-13-GP-U SPRING-13-GP-U
SPR3 DY
SPRING-62-GP
H11
34.43E24.001 34.43E24.001
1
STF237R117H83-1-GP H12 H13
H8 H9 H10
STF217R113H162-GP STF237R117H83-1-GP 34.39S07.003
HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP
DIS
DY
1
1
1
1
C C
SSID = EMI
DCBATOUT
3D3V_S5
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9701
EC9702
EC9703
EC9704
EC9705
EC9706
EC9707
EC9708
EC9709
EC9710
EC9711
1
B B
EC9733
EC9734
EC9735
EC9736
EC9737
EC9732
1
1
DY
DY DY DY DY DY DY
2
2
5V_S5
PW R_DCBATOUT_VGA_CORE
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9714
EC9715
EC9717
EC9719
EC9721
EC9713
EC9716
EC9718
EC9720
EC9722
EC9712
1
EC9738
1
DY
2
5V_S0 1D5V_VGA_S0
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
A <Variant Name> A
EC9723
EC9724
EC9725
EC9727
EC9728
EC9729
EC9730
EC9731
EC9726
1
DY DY DY DY DY DY DY DY DY Wistron Corporation
2
Title
UNUSED PARTS/EMI Capacitors

A3

5
1
97 of 104
a f i x
Vin
5 4 3 2 1
Chief River Platform Power Sequence

(AC mode) Red Words: Controlled by EC GPIO
(DC mode) Red Words: Controlled by EC GPIO
+RTC_VCC t01 >9ms

+RTC_VCC
t01 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT
Within logic high level and disable if

3D3V_AUX_S5
D it is less than the logic low level.
3D3V_AUX_S5 D
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
Ta 5V_S5
V5REF_Sus must be powered up before PSL_OUT#(GPIO71) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 Ta 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) t05 >10ms 5V_S5
PCH to KBC GPIO00 V5REF_Sus must be powered up before
5V_S5 & 3D3V_S5 need meet 0.7V difference
PCH_SUSCLK_KBC t07 >5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
KBC GPO84 to PCH down after VccSus3_3, or before
5V_S5 & 3D3V_S5 need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<t08a<90ms +5VA_PCH_VCC5REFSUS Ta
KBC GPIO43 to PCH
PM_RSMRST#(RSMRST#_RST) t05 >10ms
In case of a non-Deep S4/S5 Platform
t07 >100ms PCH to KBC GPIO00
timing t42 should be added to t07 PCH_SUSCLK_KBC
Press Power Button which will make it 100mS minimum.
3D3V_AUX_KBC
Platform to KBC PSL_IN2
Sense the power button status KBC GPIO20 to PCH
AC KBC_PWRBTN#
PM_PWRBTN#
This signal has an internal
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the
input. AC PM_PWRBTN#
DC PM_PWRBTN#
After Power Button After Power Button
PCH to KBC GPIO44 PCH to KBC GPIO44
PM_SLP_S4# PM_SLP_S4#
t10 PCH to KBC GPIO01 t10 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO47 to LAN KBC GPIO47 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 1D5V_S3
C C
DDR_VREF_S3(0.75V) DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference 5V_S0 & 3D3V_S0 need meet 0.7V difference
5V_S0 5V_S0
Tb
V5REF must be powered up before 3D3V_S0 V5REF must be powered up before 3D3V_S0
Vcc3_3, or after Vcc3_3 within 0.7 Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3 after Vcc3_3, or before Vcc3_3
within 0.7 V.
+5VS_PCH_VCC5REF Tb within 0.7 V.
+5VS_PCH_VCC5REF Tb
1D5V_S0 1D5V_S0
1D8V_S0 1D8V_S0
0D75V_S0 0D75V_S0
1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK RUNPWROK
VCCP_CPU 1D05V_PCH
1D05_VTT_PWRGD VCCP_CPU
0D85V_S0 1D05_VTT_PWRGD
0D85V_S0
0D85V_S0 0D85V_S0
D85V_PWRGD D85V_PWRGD
SetVID ACK SetVID ACK

CPU SVID BUS 50us< t36 <2000us CPU SVID BUS 50us< t36 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
t37 t37
<5ms <5ms
IMVP_PWRGD IMVP_PWRGD
B B
PCH_CLOCK_OUT PCH_CLOCK_OUT
This signal represents the Power

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH This signal represents the Power
ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK(S0_PWR_GOOD) non-graphics power rails.
PWROK(S0_PWR_GOOD)
t18 t18
D85V_PWRGD >0us PCH to CPU D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms
t19 >1ms t19 >1ms
t20 >2ms t20 >2ms
1D8V_S0 1D8V_S0
5ms<t13 <650ms PCH to CPU 5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD) UNCOREPWRGOOD(H_CPUPWRGD)
SYS_PWROK t21+t22 >1ms+60us SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system 1ms< t25 <100ms PCH to all system
PLT_RST# PLT_RST#
t39 <200us t39 <200us
DMI DMI
N13M-GS Power-Up/Down Sequence
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
A
8209A_EN/DEM_VGA(Discrete only) A
VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)
1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms
1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms
First rail to power down VGA_CORE,1D05V_VGA_S0 <Variant Name>

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down Wistron Corporation
tPOWER-OFF <10ms Taipei Hsien 221, Taiwan, R.O.C.
Title
vinafix
Power Sequence
For power-down, reversing the ramp-up sequence is recommended. A1
5 4 3 2 1
a f i x
VinDV14 MLK Chief River POWER UP SEQUENCE DIAGRAM
5 4 3 2 1
5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3.1 -3.1 -3.1
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51216RUK
LL2
0D75V_S0
5V_AUX_S5 VTT
TPS51125 VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#

VIN PGOOD -2 Page46
5
Page41
4 5V_S5 3D3V_S5
DC BQ24707 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 BJT Page37
3D3V_AUX_KBC VDD VIN 1D8V_S0
-3.1 4 VOUT
Page40 ACOK 3D3V_S0
S5_ENABLE SWITCH
-4 Page37 PM_SLP_S3# RT8068
EN
RUNPWROK
AC_IN# GPIO34 PGD
GPIO70 1D5V_S0
Page47
C SWITCH C
Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE885P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Pather Point 12
GPIO77 PCH Sandy Bridge &
13 Ivy Bridge CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B V5IN VIN B
1D05_VTT
VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51219RTER A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD APL5916 RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery
8 VIN VCC_CORE
OUTPUT
SVID
SVID VCC_GFXCORE
A VR OUTPUT A
6 7 VT1318+1323
D85V_PWRGD IMVP_VR_ON 9 <Variant Name>
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
Power Up Sequence: -8 ~ 13 Title
Size Document Number

Power Sequence Diagram
Rev
A2
4
vinafix 3 2
Date: Friday, December 30, 2011
1
Sheet 99 of 104
a f i x
Vin
5 4 3 2 1
DCBATOUT
Adapter
TPS51219DSCR TPS51216RUKR ADP3211

D AO4407A D
Charger
BQ24707 1D05V_VTT
Battery +PBATT 1D5V_S3 0D75V_S0 VGA_CORE
AO4468 APL5916 TPCA8062 AO4468
1D05V_VGA_S0 0D85V_S0 1D5V_S0 1D5V_VGA_S0
C C
TPS51125ARGER
15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5
G547F2P81 AO4468 VT1318+1323 VT1323 AO4468

AO3403
RT8068
5V_USB2_S0 5V_S0 3D3V_S0

3D3V_LAN_S5
1D8V_S0
VCC_CORE VCC_GFXCORE
B B
ODD_PWR_5V G5285T11 RTS5138 DMP2130L
LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0
Power Shape
A <Variant Name> A
Regulator LDO Switch Wistron Corporation

Title
Size
Power Block Diagram
Document Number Rev
A3
vinafix
5
4 3 2
1
100 of 104
a f i x
Vin
A B C D E
PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
5V_S0
 
3D3V_S0 
SRN2K2J-1-GP SRN2K2J-1-GP

SMBCLK SMB_CLK
DIMM 1 SRN10KJ-5-GP
PCH_SMBCLK
1
SMBDATA SMB_DATA


 PCH_SMBDATA
SCL
SDA
PSDAT1 TPDATA TPDATA TPDATA
TouchPad Conn. 1
3D3V_S5 
PSCLK1 TPCLK TPCLK TPCLK
SMBus Address:A0 
2N7002SPT
 3D3V_AUX_KBC
SRN2K2J-8-GP 3D3V_S5
DIMM 2
 PCH_SMBCLK SCL

SML1CLK SML1_CLK
 PCH_SMBDATA SDA
 SRN4K7J-8-GP
SML1DATA  SML1_DATA To KBC SRN2K2J-1-GP
SMBus Address:A4
SML0CLK SML0_CLK GPIO17/SCL1

SRN100J-3-GP Battery Conn.
BAT_SCL BATA_SCL_1 CLK_SMB
SMBus address:16
SML0DATA SML0_DATA Minicard GPIO22/SDA1
 BAT_SDA
 BATA_SDA_1 DAT_SMB
3D3V_S5 3D3V_S0 PCH_SMBCLK

WLAN
SMB_CLK
PCH_SMBDATA
 SMB_DATA
BQ24707
SRN2K2J-8-GP
3D3V_S0
KBC SCL
SDA SMBus address:12

 SRN4K7J-8-GP
NPCE885P
SML1CLK
 SML1_CLK
 THM_SML1_CLK SCL Thermal
2 SML1DATA SML1_DATA THM_SML1_DATA 2
   SDL
2N7002SPT SMBus Address:98

PCH 3D3V_VGA_S0

3D3V_VGA_S0

VGA
GPIO73/SCL2 SML1_CLK SCL
SML1_CLK GPIO_VGA_04_CLK
 GPIO_4_SMBCLK GPIO74/SDA2 SML1_DATA SDA PCH
SML1_DATA GPIO_VGA_03_DATA GPIO_3_SMBDATA

SMBus Address:9E
3D3V_S0 5V_HDMI_S0
 
3D3V_S0
SRN2K2J-1-GP SRN1K5J-GP
3  3
SDVO_CTRLCLK PCH_HDMI_CLK DDC_CLK_HDMI


SDVO_CTRLDATA
 PCH_HDMI_DATA  DDC_DATA_HDMI
 HDMI CONN
2N7002DW-1-GP
3D3V_S0

SRN2K2J-1-GP
L_DDC_CLK LVDS_DDC_CLK_R LVDS_DDC_CLK CLK
L_DDC_DATA

 LVDS_DDC_DATA_R LVDS_DDC_DATA DATA LCD CONN
3D3V_S0 5V_S0
 
3D3V_S0
SRN2K2J-1-GP SRN10KJ-6-GP
4 4

CRT_DDC_CLK CRT_DDC_CLK  CRT_DDCCLK_CON

CRT_DDC_DATA CRT_DDC_DATA    CRT_DDCDATA_CON CRT CONN <Variant Name>
Wistron Corporation
2N7002DW-1-GP
Title
SMBUS Block Diagram

A2 Enrico Caruso 14 MLK DIS X02
B
vinafix C D
Date: Friday, December 30, 2011
E
Sheet 101 of 104
in a f i x A B C D E
VThermal Block Diagram Audio Block Diagram

1 1
3D3V_S5 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP SPKR_PORT_D_L-
SC2200P50V2KX-2GP
SPKR_PORT_D_R+ SPEAKER
Pather UMA
D- NCT7718_DXN
Place near CPU

Point Thermal PWM CORE
SML1_DATA THM_SML1_DATA Codec
  2N7002  NCT7718
SML1_CLK


THM_SML1_CLK

MMBT3904-3-GP
92HD79B1
GPIO58 SDA T8 HP1_PORT_B_L HP
HP1_PORT_B_R
PAGE20
GPIO75 SML1_DATA
SML1_CLK
3D3V_VGA_S0 SCL
T_CRIT# THERM_SYS_SHDN#
2N7002
S
D
PURE_HW_SHUTDOWN#
3D3V_S0
EN 3V/5V OUT
G
2
 Put under CPU(T8 HW shutdown) 2
PAGE27 GPIO74 PAGE85


KBC GPIO73

NPCE885P 2N7002
GPIO_VGA_04_CLK GPIO_4
VGA HP0_PORT_A_L MIC
GPIO_VGA_03_DATA GPIO_3 HP0_PORT_A_R
VREFOUT_A_OR_F IN
Thames
GPIO94 GPIO56
GPIO4
S3_Pro
FAN_TACH1
DMIC_CLK/GPIO1 Digital
FAN1_DAC
DMIC0/GPIO2
3 TACH MIC 3
FAN VGA_THRM TDR

PAGE28
P2800_VGA_DXP
5V VIN DXP THRMDA
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
VSET VOUT Thermal PORTC_L
VIN
Place near GPU(DISCRETE only). PORTC_R

Analog
FAN CONTROL P2800 VREFOUT_C MIC
P2793 MMBT3904-3-GP
PAGE28
PH
OTZ
4 4
<Variant Name>
Wistron Corporation
Title
Thermal/Audio Block Diagram

vinafix
Custom
A B C D E
a f i x
Vin
5 4 3 2 1
VERSION DATA PAGE Change Iteam VERSION DATA PAGE Change Iteam
11/03 92 change PU9201 pin24 from 5V_S0 to 5V_S5 to avoid 5V_S0 leakage issue 11/16 31 change C3102 C3103 to 15pF for vendor suggest
11/03 92 change PR9219 from 10K to 0ohm and DY PC9201 to adjust VGA_CORE sequence 11/16 86 change C8610 C8611 to 10pF for vendor suggest
X01
11/03 93 change PR9314 from 470 ohm to 220ohm to adjust 3D3V_VGA_S0 power down sequence 11/23 88 89 change R8807 R8908 from 80.6 ohm to 162 ohm for NV FAE suggest
D 11/08 40 change PC4010 from 78.47422.2QL to 78.47422.2BL to correct wistron Part number 11/24 83 change L8302 to 0 ohm for NV FAE suggest D
11/08 86 change VGA strap pin follow NV FAE suggest 12/16 20 reserve R2005 10K Pull High for PEG-CLKREQ#_L
11/08 42 change PR4120 from 10K to 9.76K to adjust 5V_S5 from 5.0V to 5.07V change R2945 to 2.2K,accuracy 'J' follow vendor suggestion to solve internal mic too low issue
12/16 29
change R3605 from 10K to 0 ohm,R3607 and R3630 from 10K to 100K, C3610 from 0.01 uF
11/09 36 12/22 88 DY C8815 C8816,stuff C8809 to avoid HDD interfere.
to 0.047 uF to adjust 3D3V_S0, 5V_S0 and 1D5V_S0 power sequence
12/23 22 DY R2202,stuff R2205 to pull low DGPU_HOLD_RST# to follow NV Design Guide
11/09 17 change RN1703 from 33 ohm to 22 ohm to solve CRT HSYNC and VSYNC rise and fail time issue
12/23 20 83 DY R2004,stuff R2005 to pull high PEG_CLKREQ# to 3D3V_S5,stuff R8302 to pull high
11/09 50 change L5001 L5002 L5003 to 68.00084.931 to solve CRT RGB rise and fall time fail issue VGA_PEG_CLKREQ#,stuff Q8301 follow NV suggestion
stuff EC4002,EC9709,EC9701,EC9705,EC9708,EC9702,EC9703,EC9704,EC9738,EC9710,EC4001, 12/27 28 exchange the name of AFTP2801 and AFTP2802 to stay same with UMA for AFTP request
11/09 40 38 97 EC9707,EC9713,EC9715,EC9716,EC9720,EC9718,EC9712,EC9714,PC4120,EC9717,EC9719,
EC9722,PC3801,EC9706,SPR1,SPR3,SPR4 for EMI request add 0.1uF caps EC4004(BT+_R to GND) and EC4003(PWR_DCBATOUT_CHG to GND) to
12/28 40 reduce EMI noise
11/09 27 change R2724 from 10K to 20K for PCB version change
C C
12/28 27 change R2724 from 20K to 33K for PCB version change
11/09 86 change ROM_SLK_D4 to SMB_ALT_ADDR follow NV Design Guide
12/29 88 remove C8815 to avoid HDD interfere follow NV suggestion
11/09 86 change ROM_SO_C4 to VGA_DEVICE follow NV Design Guide
changed R3206,R3207 to short pad,removed TR3201 CMC footprint;changed R5101,R5102,R5103,
11/09 86 change ROM_SI_D3 to SUB_VENDOR follow NV Design Guide 12/29 32 51 65 R5104,R5105,R5106,R5107,R5108 to short pad,removed TR5101,TR5102,TR5103,TR5104,CMC
X01 footprint;changed R6505,R6506 to short pad,removed TR6501 CMC footprint follow EMI suggestion
11/09 86 change STRAP0_STRAP3 to RAM_CFG[0]_RAM_CFG[3] follow NV Design Guide
5 14 15 change R504 R1404 R1405 R1503 R1504 R1807 R1906 R1910 R1912 R1913 R1924 R1929 R2306
11/09 86 change STRAP4 to PCIE_MAX_SPEED follow NV Design Gide R2307 R2308 R2402 R2403 R2404 R2720 R2723 R2733 R2761 R2764 R2765 R2766 R2767 R2768
18 19 23
X02 24 27 28 R2778 R2792 R2794 R2807 R2813 R2905 R2906 R3105 R3208 R3605 R3614 R3708 R3710 R5101
11/10 22 83 dummy R8319 R8307 R2205 stuff U8301 and add R2202 to pull high 29 31 32 R5102 R5103 R5104 R5105 R5106 R5107 R5108 R5125 R6505 R6506 R6510 R6511 R6804 R6805
DGPU_HOLD_RST# to 3D3V_S0 follow NV FAE suggest 12/29 R6811 R6813 R8503 R8607 / L8302 L8601 R2304 R2412 R3104 R3115 R3117 R3206 R3207 R4908
36 37 44
46 51 65 / R2301 R2911 R2912 / RN2010 RN2012 RN2014 RN2016 RN5002 / PR4212 PR4116 PR4121
68 83 86 PR4127 PR4252 PR4254 PR4251 PR4250 PR4261 PR4220 PR4232 PR4244 PR4304 PR4305 PR4403
11/10 21 seperate RN2203 to R2205 and R2206 for bom control
PR4611 PR4607 from 0ohm to short pad
11/11 41 change PR4102 from 51K to 61.9K to set 5V OCP
12/29 58 change EC5801 EC5802 EC5803 EC5804 to 1000P cap for EMI request
B 11/11 41 change PR4101 from 120K to 91K to set 3.3V OCP B
12/30 29 add 100K R2913 resistor in AUD_PC_BEEP let voltage can be discharged fast
11/11 42 change PR4236 from 1.78K to 2.05K for CPU Loadline adjustment
12/30 61 82 remove R6102,R6103;R8201,R8202;R8203,R8204 co-lay position;use CMC solution
11/11 42 change PR4264 from 20K to 18.2K for CPU Loadline adjustment
12/30 27 change R2735 from 10K to 20K to reduce inrush current of 3D3V_AUX_KBC
11/11 42 change PR4239 from 0 ohm to 191 ohm for GFX Loadline adjustment
12/30 41 change PC4126,PC4127 to 4.7u from 10u follow power team's suggestion
11/11 42 change PR4249 from 7.87K to 7.5K for GFX Loadline adjustment
remove TP2713,add R2713 for pull high OVER_CURRENT_P8# to 3D3V_AUX_KBC;add R8608,Q8603;
11/11 46 change PR4602 from 52.3K to 80.6K to Set 1.5V OCP 12/30 27 86 change Q8603.2 to OVER_CURRENT_P8# from AC_PRESENT for OC trigger IPCC function
11/11 92 change PR9238 from 133K to 196K and PR9225 from 3.83K to 2.26K for Loadline adjustment 12/30 58 stuff 1000pf EC5801 EC5802 EC580 EC5804 for EMI request
follow Nvidia SPEC
01/03 49 remove R4903,R4904 co-lay position;use CMC solution
11/11 45 dummy PR4506 and PR4507, Pop PR4505 and 3D3V_S0 change 3D3V_S5 for power team request
11/11 29 install R2909,R2910,D2902 as to audio chip will change to 4213D 01/03 45 change PR4510 to 82.5K from 69.8K to modify OCP follow power team's suggestion
<Core Design>
A 11/14 92 change PC9213 PC9214 PC9216 to 78.10622.51L for power team request A
11/15 29 change R2909 R2910 to 0 ohm for vendor request Wistron Corporation
11/15 61 82 stuff TR8201 TR8202 TR6101,dummy R6102 R6203 R8201 R8202 R8203 R8204 for EMI request Title
11/16 39 add test point AFTP3902 Change History

A3
5
4
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Date: W ednesday, January 04, 2012 Sheet
1
103 of 104
a f i x
Vin
5 4 3 2 1
VERSION DATA PAGE Change Iteam VERSION DATA PAGE Change Iteam
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
Change History
A3
vinafix
http://www.vinafix.vn Date: Tuesday, January 03, 2012 Sheet 104 of 104

Dell Inspiron 14 2420 3420 Schematics

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a f i x

Muxless Schematics Document D

Ivy Bridge & Sandy Bridge

Surge: For GO Rural config stuff.

vinafix Enrico Caruso 14 MLK DIS X02

##OnMainBoard Block Diagram SYSTEM DC/DC

Hynix:72.52G63.A0U (HT31P$AA) VRAM gDDR3 900MHz

Xtal=27MHz 83.84,85,86,87 INPUTS OUTPUTS

CODEC 24MHz KBC INPUTS OUTPUTS

MIC IN Fan Control G709

Name Schematics Notes Power Plane

CPU Core Rail

PCI EXPRESS* - GRAPHICS

A28 CLK_EXP_P CLK_EXP_P 20

R501 TPAD14-OP-GP TP501 1 SKTOCC#_R AN34 RN502

TPAD14-OP-GP TP502 1 H_CATERR# AL33

22,36 H_THERMTRIP# H_THERMTRIP# AN32 THERMTRIP#

JTAG & BPM

1K5R2F-2-GP AT31 XDP_BPM6 1 TP509 TPAD14-OP-GP

DDR SYSTEM MEMORY B

vinafix Enrico Caruso 14 MLK DIS X02

AJ26 AR35 CFG6 PCIE Port Bifurcation Straps

J15 RSVD#J15 RSVD_NCTF#AT2 AT2

vinafix Enrico Caruso 14 MLK DIS X02

Voltage Rail Voltage(V) Iccmax(A)

VCC_CORE(DC) 0.3~1.35 53 IVY-BRIDGE

PEG AND DDR

Y29 R805 R804

1. PH/PL resisors place close CPU

SSID = CPU VCC_GFXCORE

Voltage Rail Voltage(V) Iccmax(A)

DDR3 -1.5V RAILS

VCCSA Power Select

A19 H_SNB_IVB#_PW RCTRL 1 TP901 TPAD14-OP-GP Voltage(V) VID[0] VID[1]

A DDR_W R_VREFA <Variant Name> A

RN902 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Size Document Number Rev

vinafix Enrico Caruso 14 MLK DIS X02

AT35 VSS1 VSS81 AJ22

vinafix Enrico Caruso 14 MLK DIS X02

vinafix Enrico Caruso 14 MLK DIS X02

M_B_A12 A11 CKE1 SA1_DIM1

M_B_DQ10 DQ9 3D3V_S0

M_B_DQ19 DQ18 NC#2 1D5V_S3

M_B_DQ22 DQ21 VDD1

M_B_DQ52 DQ51 VSS

M_B_DQ53 DQ52 VSS

M_B_DQ56 DQ55 VSS

SSID = MEMORY DM1

M_A_DQ5 DQ4 DM6

M_A_DQ10 DQ9 3D3V_S0

M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP SC2D2U10V3KX-1GP

M_A_DQ31 DQ30 VDD10 1D5V_S3

M_A_DQ36 DQ35 VDD15

M_A_DQ42 DQ41 VSS

M_A_DQ43 DQ42 VSS

M_A_DQ63 DQ62 VSS

M_A_DQS#1 DQS0# VSS

SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

Digital Display Interface

AF43 LVDSB_DATA3 DDPC_3N BB47

50 PCH_CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43

X01 1109 RN1703 BB43