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Lecture 2 PDF
Lecture 2 PDF
Digital Electronics
Important Announcements
• Midterm Exam:
• Date: Tuesday, Oct 24 2017 – During the lecture hours
• Contents: Chapters 5 (as covered in the lecture) and 14 of
Sedra-Smith 7th ediRon
• HW set #1:
• Due date: Friday, October 6 2017 and during the lab
sessions. No extension or excepRon.
• Deliver to your TA, Leo Filippini, prior to the end of the lab
session
• Problems will be posted by the end of today.
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
MOS as a Switch
• MOS transistors are Voltage Controlled Current Sources
• For logic operaRons, a binary unit is required with:
• A “high” or 1 à Current flows
• A “low” or 0 à Current blocked
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
MOS as a Switch
• For an NMOS:
• VG=VDD à Small rDS à A “high” or logic 1
• VG=0 à open circuit à A “low” or logic 1
• For a PMOS:
• Everything is reversed.
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
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ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
Summary
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