1 2 3 4

+3.3V
+15V +15V
R1
D1
BAT54S/30V 1N4004
R2 10K TP38 D4 Barra Pino 1 x 4(A19mm) Macho(*)
+15VIN VIN_REF +3.3V
Debug

100pF/50V
33K/1% PGM_IN CN3

SMTPA130T/R
D3
+15V S3G R3 Q2 DEBUG_PIN1
TVS2 1
8K06/1% IRFR5505TR R8 DEBUG_PIN2
2

C1
PTC5 10R- 1/16W 3
R10 SIR+

D
A +15VIN 4 A
4,7R
300mA TP3
TP4
R36

TP49
G
Q4 1N4148 1N4148
2K2 BC847 D6 D7
S PGM
R37 R6 HDR 1X5 M P2.54(*)
G R12 CN4
D5 0R +3.3V TP1 TP2
D
BC847 2K2 10K Gravação
S3G Q7
Q1
R38 R7 BOOT
LML5203TR ON_OFF_CHARGE 1
10K U2RX
2
27K U2TX
3
4
O STM32F107 possui Debug pela Serial e o STM32F030 possui Debug pela I2C 5
R14 +3.3V
1.1 A

33K/1% R13 CTR_L3&DEBUG_SDA R136 0R(*) DEBUG_PIN1

RV1 Q5
BC847 100K +3.3V +3.3V CN9
R137
TP39 DEBUG_RX DEBUG_PIN1 Debug
BATERIA
Q6 R15 SIRENE_OUT&DEBUG_SCL 0R
BAT54S/30V

R60 1
100pF/50V

J1 D8 R16 TP27 BC847 R138 0R(*)

10K SIRENE_OUT&DEBUG_SCL DEBUG_PIN2 10K 2
S3G 8K06/1% SWDIO
2 3
TP41 SWCLK
4
C30

1 R139 NRST
D9

DEBUG_TX DEBUG_PIN2 5
2217S-02-WH2 6
0R

B TP12 TP29 B

+15V
Test point para teste do ETH_PPS PTC2 TP37

4
SIRENE_OUT&DEBUG_SCL
TP10 AUX_IN
+3.3V TVS1 TVS3

REF
GND
CTR_L3&DEBUG_SDA
R9 CD143A-SR0 0.3 A/60V
SMTPA130T/R

I/O
I/O
22R RF_MISO
10K

22R RF_MOSI

22R RF_SCK
L1

U2TX_RXBARR
U2RX_TXBARR
10uH CN6 LD14

2
3

Case
R40 10M VD

RF_NIRQ

USB B Type 180°

TP32

BOOT
BUZZER
VDD_1

PGM

DEBUG_TX
54 DEBUG_RX
1 R121
32,768KHz 33R VBUS
VDD_1 USB_D- R122 2 15K
D- CN7

SWCLK
X4 USB_D+ 3
100nF/50V

D+ Z1_IN
R123 4 1
C3 33R GND
TP36 2

57 R61
56 R62
55 R64

Case
Z2_IN
3
R124 R125 Z3_IN
4

64
63
62
61
60
59
58

53
52
51
50
49
C18 C19 15K 15K
R39 5
33pF/50V 33pF/50V Z4_IN
100R 6

VDD
VSS
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
7
AUX_IN
8
PGM_IN
9
10
SIR+
VDD_1 1 48 R134 0R VDD_3 11
VBAT VDD A_485_BARR
CTR_L1 2 47 R135 0R 12
Montado somente para o STM32F030 +3.3V PC13/TAMPER-RTC VSS B_485_BARR
BP1X2(*) 3 46 SWDIO 13
C PC14/OSC32_IN PA13 C
JP5 4 45 USB_D+
R131 PC15/OSC32_OUT PA12 TP31
U2TX_RXBARR ETH_MDIO 5 44 USB_D-
1 PD0/OSC_IN PA11
0R(*) R110 100R 6 43 U2RX Incluir test pint em todas as posições do conector
TP9 2 X3 PD1/OSC_OUT PA10 USB_D+ R53 0R(*) DIR_BARR
NRST 7 42 U2TX
33pF/50V

NRST PA9
BOOT CTR_L2 8 41 RF_GP0 JP1
PC0 PA8
TECLAS APRENDER R84 ETH_CLK50M ETH_MDC 9 40 Z1_IN
TP44
C51

8 MHz PC1 PC9 1

100nF/50V

R18 RF_nSEL 10 39 TP15 ZONA1

0R(*) PC2 PC8 2
100K C50 Z3&Z4 11 38
PC3 PC7
33pF/50V 12 37 LT_OUT BP1X2
C52

VSSA PC6
VDD_1 13 36 ON_OFF_CHARGE
VDDA PB15
CTR_L5 14 35
PA0-WKUP PB14 JP2
ETH_CLK50M 15 34 ETH_TXD1
PA1 PB13 Z2_IN
ETH_MDIO 16 33 ETH_TXD0 1
PA2 PB12 ZONA2
2
+15V BP1X2
PB10
PB11
VDD

VDD
VSS

VSS
PA3

PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2

R126 R127 R128 JP3

C23 U5
1R 1R 1R Z3_IN
C22 220pF/50V 3 6 U4 1
DRC VCC +3.3V ZONA3
100uF/25V + 4 7 TP35 2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

GND IPK STM32F107/LQFP64 +3.3V

5 8 L10 +3.3V
CII DRVC BP1X2
1 2
SWC SWE
ETH_TXEN
NRST_PHY

ETH_RXD0
ETH_RXD1

L4
BATERIA

ETH_CRS

220uH L11
VIN_REF
TECLAS

RF_SDN

MC34063A
CTR_L4

+ 10uH 10uH
VDD_2

JP4
Z1&Z2

R129
D10 3K3 Z4_IN
TPS2L60 C45 C24 C25 1
±1% ZONA4
R130 220uF/6,3V 33pF/50V 10pF/50V 2
VDD_2
0R(*)

D 2K05 VDD_3 D
BP1X2
0R

0R

±1%
0R

TP43

C8 C46
TP28

TP30

100nF/50V 100nF/50V
Title
R88

R132
R95

VDD_2 R133

Central ANM 24 NET

TECLAS APRENDER
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
U2RX_TXBARR FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 INTELBRAS S/A
00
(*) Não Montado Fone: (035) 3471-9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 1 of 6
FID FID File: Pag 1.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4
 1 2 3 4

CIRCUITO DE ZONAS CIRCUITO BARRAMENTO 485

+3.3V +3.3V

TP5
R17
BAT54S/30V 4K7 R52 2K2 Z1_IN
D13
Z1&Z2 R54 R55 TP6 +3.3V
10R 33K +3.3V
A R56 3K9 Z2_IN C33 A
C2 TVS4
100pF/50V SMTPA130T/R R57
100nF/50V
4K7
RS-485 A PTC3
U3 A_485_BARR
U2RX_TXBARR 1 8
RO VCC 60V/10 A
C39

TP47
2 6
RE DO/RI 2,2nF/50V
R58
DIR_BARR 3 7 120R
DE DO/RI
C40
+3.3V +3.3V U2TX_RXBARR 4 5 PTC4
DI GND 2,2nF/50V
B_485_BARR
TP7 DS75176B/DS75176BT
R63 60V/10 A
BAT54S/30V R59

TP48
4K7 R65 2K2 Z3_IN 4K7
D14
Z3&Z4 R66 R67 TP8

TVS-ESD 5V

TVS-ESD 5V
10R 33K
R69 3K9 Z4_IN
TVS5
C4

D12
SMTPA130T/R

D2
100pF/50V

B B

CIRCUITO DE CENTELHADORES

CENT1 CENT2 CENT3 CENT5 CENT4 CENT6 CENT7 CENT8

6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3
Z1_IN Z3_IN SIR+ A_485_BARR B_485_BARR PGM_IN
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8
9 9 9 9 9 9 9 9
10 10 10 10 10 10 10 10
C C
PONTA PONTA PONTA PONTA PONTA PONTA PONTA PONTA
GND_EARTH GND_EARTH GND_EARTH GND_EARTH GND_EARTH GND_EARTH GND_EARTH GND_EARTH

CENT9 CENT11 CENT17 CENT15 CENT16

6 6 6 6 6
5 5 5 5 5
4 4 4 4 4
3 3 3 3 3
Z2_IN Z4_IN AUX_IN
1 1 1 1 1
2 2 2 2 2
7 7 7 7 7
8 8 8 8 8
9 9 9 9 9
10 10 10 10 10
PONTA PONTA PONTA PONTA PONTA
GND_EARTH GND_EARTH GND_EARTH GND_EARTH GND_EARTH
Estes componentes representam os centelhadores que estão desenhados na placa como pequenas ranhuras de cobre.
Não fazem parte da lista de material.

D D

Title
Central ANM 24 NET
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 00
(*) Não Montado Fone: (035) 3471 - 9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 2 of 6
FID FID File: Pag 2.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4
 1 2 3 4

CIRCUITO MATRIZ DE TECLADO CIRCUITO MATRIZ CHARLIEPLEXING

+3.3v

TP17

R85 CTR_L1

LED_ETH_+
0R

LED_RF_-
TP18 LD1 LD2 LD9 LD10
A R90 R91 R92 R93 R97 R98 R99 R100 AZ AZ AZ AZ LEDS DO CADASTRO DE DISPOSITIVOS SEM FIO A
1K 1K 1K 1K 1K 1K 1K 1K CTR_L2
TP22 +3.3v
TP19 LD3 LD4 LD11 LD12 LD7 LD8
S16 S15 S14 S13 S12 S11 S10 S9 AZ AZ VD VM AZ AZ
TECLAS
CTR_L3&DEBUG_SDA

TP20 LD5 LD6

LED_ETH_-

LED_RF_+
D17 AZ AZ
BAT54S/30V
R101 R102 R103 R104 R105 R106 R107 R108 R111 CTR_L4
100K C34
1K 1K 1K 1K 1K 1K 1K 1K
100pF/50V LD16 LD17 LD18 LD19
AZ AZ AZ AZ
S1 S2 S3 S4 S5 S6 S7 S8 CTR_L5

TP46

B B

CIRCUITO BUZZER
+3.3v
TP26
+3.3v
+15V
TECLAS APRENDER
R78 BZ1
1K APRENDER CONTROLE APRENDER SENSOR TP40
CH1 CH2 2
R79
1 470R
D11
R112 BAT54S/30V TP52
10K 1 KHz
R109 C27 Q12
100pF/50V R81 BC847
10K BUZZER
R82 470R
10K

TP45
TECLAS FISICAS PARA CADASTRO E EXCLUSAO DE DISPOSITIVOS RF

C C

D D

Title
Central ANM 24 NET
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 00
(*) Não Montado Fone: (035) 3471-9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 3 of 6
FID FID File: Pag 3.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4
 1 2 3 4

A A

CIRCUITO AC

TP23
47R 1nF/50V
R96 C35
NTC1 +15VIN
F1 16R TR3 D18
5 6
TP24 R140 0R

39K - 1206
300V(*)
ES2D
PD1 +
R70

VR3
VR1 R114 C37
CN5 TP50 R71 0R 2 3 1nF - 1206

~ ~
+
300V 4K7 1000uF/16V
C5 + C38 + C36
1
2 C49 1 8

39K - 1206
10uF/400V

10uF/400V
3 100nF/305V(*)
1 4
300V(*)

AC & TERRA
R72 0R - R51
VDD_VIPER 4
VR4

VR2
300V 800V/MB8S
TP25 F2 R141 0R

150R - 1206
R116
B GND_IN TP51 B
D23 3
PTH 100kHz 12VA
S1M GND_IN
U2
1 16
GND DRAIN
2 15
GND DRAIN
3 14
N.C DRAIN
GND_IN
4 13
N.A DRAIN
D15 +15VIN
VDD_VIPER R76 5 12
VDD N.C
10R S1M 6 11
+ CONT N.C
R77
C6
FB 7 10 3K9
10uF/50V FB N.C
±1%
8 9 ISO4
BR N.C FB 4 1
33nF/50V

1nF/50V
GND_IN VIPER37L
C7 3 2
C26
FOD817BSD Z1
PTZ TE25/13V
R87 R94 GND_IN
0R(*) 4K7 C28
C C

2.2nF/250V

GND_IN
GND_IN

D D

Title
Central ANM 24 NET
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 INTELBRAS S/A
00
(*) Não Montado Fone: (035) 3471-9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 4 of 6
FID FID File: Pag 4.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4
 1 2 3 4

A A

R118 R117
RF_GPIO2
0R(*) LD15 0R(*)
R4 1K
R119 R120
LED_RF_+ LED_RF_-
VD
0R 0R

RF_SDN

56nH 0402

56nH 0402

10K - 0603
ANTENA
A1 L2 L2A L5 L5A
C29

R115
B 0402 0603 0603 B
5.1pF
L3 56nH 56nH 56nH
0603
C32 C48
L3A
0603
C31
56nH 270pF-0603 2,7pF/50V
0603
U1
X1
21
GND 3 4
1 20 Out Gnd
GND GPIO3
2 19 RF_GPIO2
SDN GPIO2
3 18
RXp XIN 1 2
4 17 In Gnd
RXn XOUT
5 16 RF_nSEL
+3.3V NC nSEL 30MHz
6 15 RF_MOSI
GND SDI
7 14 RF_MISO
VDD SDO
8 13 RF_SCK
VDD SCLK

2,2uF/10V
9 12 RF_NIRQ

100pF/50V

100nF/16V
GND nIRQ
10 11 RF_GP0
GPIO0 GPIO1
C42 C43 C44 SI4355
TP33 TP16

C C

D D

Title
Central ANM 24 NET
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 INTELBRAS S/A
00
(*) Não Montado Fone: (035) 3471-9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 5 of 6
FID FID File: Pag 5.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4
 1 2 3 4

A A

+3.3V
R11 R32
LED0
0R(*) LD13 0R(*)
R20

330R VD
R75 R113
LED_ETH_- LED_ETH_+
0R 0R

B B

TR1
RX- 8 9 TP_RD-
+3.3V

L6 CN2
600R BEAD RX+ 6 11 TP_RD+
2
+3.3V 5 13 1
6
TX- 3 14 TP_TD-
4
R5 R19 R21 R22 5
10K

10K

10K

10K
1K5

47R 47R 47R 47R 3

7
TX+ 1 16 TP_TD+
8
R23

R24

R25

R26

R27

U9
R43 RJ45 SMD 180°
ETH_TXEN 16 21 TX+ R44 R45
TXEN TXP HN16613CG 75R
ETH_TXD0 17 20 TX- 75R 75R
TXD0 TXN ±1%
C ETH_TXD1 18 23 RX+ ±1% ±1% C
TXD1 RXP
22 RX- PTC1
RXN
ETH_RXD0 R28 33R ±1% 8 SDVL4532SD140PT(*)
RXD0/MODE0
ETH_RXD1 R29 33R ±1% 7 3 LED0 C17
RXD1/MODE1 LED1/nINT/nPME/REGOFF C20 C21
R30 10K 10 2 R35 10K 1000pF/2000V
RXER/PHYAD0 LED2/nINT/nPME/nINTSEL 10uF/10V 100nF/16V
R31 TP42
ETH_CRS R33 33R ±1% 11 24
CRS_DV/MODE2 RBIAS
12,1kR - 1010218
ETH_MDC 13 19
MDC VDD1A
ETH_MDIO 12 1
MDIO VDD2A
9
VDDIO +3.3V
NRST_PHY R50 0R 15 6
nRST VDDCR
ETH_CLK50M R34 33R ±1% 14
nINT/REFCLK0
4
XTAL2
5 25
X2 XTAL1/CLKIN GND_EP
470pF/50V

100nF/16V

100nF/16V

100nF/16V

102_LAN8742A-CZ-TR
10uF/10V
1uF/6,3V

25MHz
C11

C12

C13

C14

C15
C9

C16 C10
33pF/50V 33pF/50V

D D

Title
Central ANM 24 NET
Size Number Revision
LEGENDA FIDUCIAIS PCB Rodovia BR 459 - 1325 - KM 124 Distrito Industrial 4780033/2
FID2 FID1 CEP 37.540-000 Santa Rita do Sapucaí A3 INTELBRAS S/A
00
(*) Não Montado Fone: (035) 3471-9840
Site: www.intelbras.com.br Date: 29/11/2018 29/11/2018 Sheet 6 of 6
FID FID File: Pag 6.SchDoc Drawn By: P&D - Layout de placas
1 2 3 4