SIMM, 4MB/8MB PROTECTABLE FLASH, CG, BOARD SCHEMATIC 768-008-11 REV A

4 3 2 1
REVISIONS
REV ECO DESCRIPTION BY/DATE CHK/DATE
EA . . TDW/14JUL99 .
EB . ADDED R15 TDW/13OCT99 .
A 5137 PRODUCTION RELEASE TDW/19OCT99 .

D BK[0..15] D
U1 U3
A1/BA0 24 25 BK0 A1/BA0 24 25 BK8
A0 D0 A0 D0
BA[3..19] A2/BA1 23 26 BK1 A2/BA1 23 26 BK9
A1 D1 A1 D1
A3/BA2 22 27 BK2 A3/BA2 22 27 BK10
A2 D2 A2 D2
BA3 21 28 BK3 BA3 21 28 BK11
A3 D3 A3 D3
BA4 20 32 BK4 BA4 20 32 BK12
A4 D4 A4 D4
BA5 19 33 BK5 BA5 19 33 BK13
A5 D5 A5 D5
BA6 18 34 BK6 BA6 18 34 BK14
A6 D6 A6 D6
BA7 17 35 BK7 BA7 17 35 BK15
A7 D7 A7 D7
BA8 16 BA8 16
A8 A8
BA9 15 BA9 15
A9 A9
BA10 14 BA10 14
A10 A10
BA11 13 BA11 13
A11 A11
BA12 8 BA12 8
A12 A12
BA13 7 BA13 7
A13 A13
BA14 6 BA14 6
A14 A14
BA15 5 BA15 5
A15 A15
BA16 4 BA16 4
A16 A16
BL[0..15] BA17 3 BA17 3
OPTIONAL A17 A17
BA18 2 BA18 2
A18 A18
BA19 1 BA19 1
A19 A19
R13 BA20 40 BA20 40
A20 A20
1 2 39 NC (A21) 39 NC (A21)
11 11
0 OHM NC (A22) NC (A22)
E2

A B
VBLK0/GND 9 VBLK0/GND 9
CE CE
RD\ / GND 37 PEG RD\ / GND 37
OE OE
FWR0B\ 38 FWR1B\ 38
WE WE
RESET\ 12 RESET\ 12
VCC RESET RESET
36 RY/BY 36 RY/BY
VIDEO BLOCK / (OTHER MEMORY)
P1 XXMx8FLASH XXMx8FLASH
1 2 BA21 5V,90nS 5V,90nS
(FWR0A\) 3 4 A1 (XM1)
VBLK1 (SRAM WE0\) 5 6 A2 (XM2) VCC VCC
C FWR0B\ (FWR0B\) 7 8 A3 (GAME SEL\)
R10 R9
C
BL0 (A25) 9 10 BL4 (SRAM CE\) U7 2 1 2 1
VCC BL1 (A24) 11 12 BL5 (VBIT SEL\) BN0 2 19 BL0
D1 Q1 10K 10K
BL2 (A23) 13 14 BL6 (WR0\) BN1 3 18 BL1
D2 Q2
BL3 (A22) 15 16 BL7 (WR1\) BN2 4 17 BL2
D3 Q3
U5 BA20 (A21) 17 18 BL8 (XM3) BN3 5 16 BL3
D4 Q4
4 2 R1 1K BA19 (A20) 19 20 BK7 (D7) BN4 6 15 BL4
TP
1Y 1A D5 Q5
3 R2 1K BA18 (A19) 21 22 BK6 (D6) BN5 7 14 BL5
1B D6 Q6
A3/BA2 7 5 A3 BA17 (A18) 23 24 BK5 (D5) BN6 8 13 BL6
2Y 2A D7 Q7
6 BA2 BA16 (A17) 25 26 BK4 (D4) BN7 9 12 BL7
2B D8 Q8
A2/BA1 9 11 A2 BA15 (A16) 27 28 BK3 (D3)
3Y 3A
10 BA1 BA14 (A15) 29 30 BK2 (D2) FLATCH2 11
3B CLK
A1/BA0 12 14 A1 BA13 (A14) 31 32 BK1 (D1) VCC/FLATCH2 1
4Y 4A OC
13 BA0 BA12 (A13) 33 34 BK0 (D0)
4B
BA11 (A12) 35 36 RD\ (RD\) 74AC574
15 R3 1K BA10 (A11) 37 38 BL9 (SRAM OE\)
G
1 BLOCKRW\ BA9 (A10) 39 40 BK15 (D15)
A/B
BA8 (A9) 41 42 BK14 (D14) U10
74AC257 BA7 (A8) 43 44 BK13 (D13) BN8 2 19 BL8
D1 Q1
BA6 (A7) 45 46 BK12 (D12) BN9 3 18 BL9
D2 Q2
A/B (A6) (D11)

DWG NO:
BA5 47 48 BK11 BN10 4 17 BL10
A = 960 ACCESS D3 Q3
BA4 (A5) 49 50 BK10 (D10) BN11 5 16 BL11
B = VIDEO MODE D4 Q4
BA3 (A4) 51 52 BK9 (D9) BN12 6 15 BL12
D5 Q5
BA2 (A3) 53 54 BK8 (D8) BN13 7 14 BL13
D6 Q6
BLOCKRW\ IS ACTIVE LOW WHEN BITBLITZ IS IN BA1 (A2) 55 56 BL10 (XM4) BN14 8 13 BL14 U2 U4

768 008 11
VIDEO BLOCK READ/ WRITE ENABLE D7 Q7
VCC BA0 (A1) 57 58 BL11 (FLH SEL\) BN15 9 12 BL15 A1/BA0 24 25 BN0 A1/BA0 24 25 BN8
D8 Q8 A0 D0 A0 D0
U6 BA22 59 60 GND (GND) A2/BA1 23 26 BN1 A2/BA1 23 26 BN9
A1 D1 A1 D1
VBLK0/GND 4 2 VBLK0 VBLK0 (FWR1A\) 61 62 BL12 (A31) FLATCH2 11 A3/BA2 22 27 BN2 A3/BA2 22 27 BN10
1Y 1A CLK A2 D2 A2 D2
3 R4 1K BL13 (SRAM WE1\) 63 64 BL14 (VOUT) VCC/FLATCH2 1 BA3 21 28 BN3 BA3 21 28 BN11
1B OC A3 D3 A3 D3
VBLK1/GND
7 5 VBLK1 FWR1B\ (FWR1B\) 65 66 BL15 (A30) BA4 20 32 BN4 BA4 20 32 BN12
2Y 2A GND to CPLD (A26) A4 D4 A4 D4
6 R5 1K 67 68 FLATCH2(A29) 74AC574 BA5 19 33 BN5 BA5 19 33 BN13
2B A5 D5 A5 D5
VCC/FLATCH2 9 11 R6 1K FLATCH1 (A27) 69 70 FLATCH1(A28) U8 BA6 18 34 BN6 BA6 18 34 BN14
3Y 3A A6 D6 A6 D6
10 FLATCH2 RESET\ RESET\ 71 72 BLKRW\ (XMB) BN0 18 2 BK0 BA7 17 35 BN7 BA7 17 35 BN15
3B B1 A1 A7 D7 A7 D7
RD\ / GND 12 14 RD\ BN1 17 3 BK1 BA8 16 BA8 16
4Y 4A B2 A2 A8 A8
13 R7 1K 72 PIN SIMM BN2 16 4 BK2 BA9 15 BA9 15
4B B3 A3 A9 A9
BN3 15 5 BK3 BA10 14 BA10 14
B4 A4 A10 A10
B G
15
1
R8
BLOCKRW\
1K BN4
BN5
14
13
B5 A5
6
7
BK4
BK5
BA11
BA12
13
8
A11
BA11
BA12
13
8
A11 B
A/B B6 A6 A12 A12
BN6 12 8 BK6 BA13 7 BA13 7
74AC257 B7 A7 A13 A13
BN7 11 9 BK7 BA14 6 BA14 6
B8 A8 A14 A14
BA15 5 BA15 5
A15 A15
19 VBLK1\ BA16 4 BA16 4
G A16 A16
1 RD\ BA17 3 BA17 3
74AC245 DIR A17 A17
BA18 2 BA18 2
A18 A18
BA19 1 BA19 1
A19 A19
BA20 40 BA20 40
U9 A20 A20
39 NC (A21) 39 NC (A21)
BN8 18 2 BK8 11 11
B1 A1 NC (A22) NC (A22)
BN9 17 3 BK9 E3
B2 A2

C D
OPTIONAL BN10 16 4 BK10 VBLK1/GND 9 VBLK1/GND 9
B3 A3 CE CE
BN11 15 5 BK11 RD\ / GND 37 PEG RD\ / GND 37
1

B4 A4 OE OE
J1 BN12 14 6 BK12 FWR0B\ 38 FWR1B\ 38
B5 A5 WE WE
BN13 13 7 BK13 RESET\ 12 RESET\ 12
1 R15 B6 A6 RESET RESET
BN14 12 8 BK14 36 36
2 0 OHM B7 A7 RY/BY RY/BY
BN15 11 9 BK15
B8 A8 XXMx8FLASH XXMx8FLASH
2 Pin
Right Angle Header
VBLK1\
2

19 5V,90nS 5V,90nS
G
1 RD\
74AC245 DIR VCC VCC
R11 R12
REF_J1 2 1 2 1
10K 10K
2 pin JUMPER
OPTIONAL
R14 0 OHM BN[0..15]
1 2

VCC
A ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO INTERNATIONAL GAME TECHNOLOGY A
THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
BK[0..15] = TO ON BOARD LATCHES OR TO 960 BUS FID1 FID2 FID3 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
1

C1 C2 C3 C4 C5 C6 C7 C8
TITLE
BL[0..15] = TO ON BOARD PIXEL MUX INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
BN[0..15] = EPROM DATA FROM B & C
FIDUCIAL FIDUCIAL FIDUCIAL
SCHEMATIC, PROTECTED
2

FOR PCB BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS

VSS REFERENCEONLY CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT FLASH CG SIMM
COVENANTS IT WILL NOT BE USED IN ANY MANNER DWG. SIZE DWG. NO. REV LTR
E1 DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. (form 6 99') C 768 008 11 A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
Tom Waxman 06OCT99 . . . . NONE 1 OF __
SHT __ 1
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17” UPRIGHT (821-307-01) 41