• Arquitetura de Computadores

Aula 01: Introdução

Mario F. Montenegro Campos

ICEx 4013 - mario@dcc.ufmg.br

O que é arquitetura de O que é este curso?

computadores? Entender as técnicas de projeto, arquitetura das máquinas
correntes, fatores da tecnologia, métodos de avaliação
que vão determinar a estrutura dos computadores do
próximo século
“os atributos de um sistema de computação na visão Paralelismo
do programador, i.e., a estrutura conceitual e o Tecnologia Linguagens de
comportamento funcional, … em oposição à Programação
Aplicações
implementação física.” Projeto da
Arquitetura de Computadores:
Interface
• Projeto do conjunto de instruções
Amdahl, Blaaw, and Brooks, 1964 • Organização
• Hardware

Sistemas
Operacionais História

Medidas e avaliação
 Pré-requisitos
Material do curso
• Conceitos em organização de computadores
– Organização de Computadores I
• Livro texto e papers
• Projeto de sistemas lógicos
– Introdução aos Sistemas Lógicos • Listas de exercícios

• Linguagens: C e assembler • Trabalhos de implementação de uma arquitetura

RISC
• Conceitos básicos de sistemas operacionais
• Projeto de final de curso, envolvendo um tópico
• Conceitos básicos de compiladores avançado

Programação
Cursos relacionados Hennessy and Patterson, Computer Architecture: A
Quantitative Approach, 4th Ed., Morgan Kaufman, 2006.
Programação
1 Fundamentals of Computer Design
Sistemas
ISL Paralela
Operacionais 2 Instruction Level Parallelism and Its Exploitation
3 Advanced Techniques for Exploiting Instruction-Level
Parallelism and Their Limits
SW Básico OC1
Sistemas 4 Multiprocessors and Thread-Level Parallelism
HW/SW
5 Memory Hierarchy Design
OC2 Arquitetura de 6 Storage Systems
Computadores
Appendix A: Pipelining: Basic and Intermediate Concepts
Graduação Pós-Graduação Appendix B: Instruction Set Principles and Examples
Appendix C: Introduction to Memory Hierarchy
 Tópicos a serem estudados
Livros de referência complementar I/O e armazenamento

Discos, WORM, Fitas RAID

• Patterson and Hennessy, Computer Organization and
Tecnologia emergentes
Design: the Hardware/Software Interface, Segunda edição, DRAM Interleaving
Morgan Kaufmann, 1997. Protocolos de barramento
• Sailer, P.M. and Kaeli, D.R., The DLX Instruction Set Coerência,
Architecture Handbook, Morgan Kaufmann, 1996. Hierarquia Cache L2 Bandwidth,
de memória Latência
• R. Lipsett, C. Schaefer, C. Ussery, VHDL: Hardware
Description Language and Design, Kluwer Academic
Publishers, 1989. Cache L1 Endereçamento,
VLSI Proteção,
• Peter J Ashenden, The Designer's Guide to VHDL, Morgan
Tratamento de exceção
Kaufmann, 1995. Arquitetura a nível de instrução

• manuais (SCI, SCSI, etc…) e papers Pipelining, resolução de hazards, Pipelining and paralelismo
superscalar, reordenamento, a nível de instrução
predição, especulação

Tópicos a serem estudados Metodologia de projeto de

arquiteturas de computadores
Memória
compartilhada, Avaliaç
Avaliação de sistemas
P M P M P M P M
°°° Troca de mensagens, existentes em busca
Complexidade de gargalos
S rede de interconexão Interfaces de redes do sistema
Benchmarks
switch entre processador Topologias, Implementaç
Implementação Avanços
e memória roteamento, da tecnológicos
Multiprocessadores, bandwith, pró
próxima geraç
geração
redes e interconexão latência,
reliability Workloads Simulaç
Simulação de novos
projetos e organizaç
organizações
 Metodologia de projeto de Evolução Tecnológica
arquiteturas de computadores Ano Componente Armazen. Linguagens O/S
(Idéia básica) 54
58
Tubes core (8 ms)
Transistor (10µs) Fortran
60 Algol, Cobol Batch
• Regra número 1: Nada vem de graça 64 Hybrid (1µs) thin films Lisp, APL, Basic
66 IC (100ns) (200ns) PL1, Simula,C
67 Multiprog.
• Regra número 2: Uma nova arquitetura ou uma nova idéia 71 LSI (10ns) 1k DRAM O.O. V.M.
Gerações
só é implementada após um estudo da sua viabilidade
Evoluções 73 (8-bit µP)
• Regra número 3: Nem sempre o melhor e o mais bem 75 (16-bit µP) 4k DRAM
78 VLSI (10ns) 16k DRAM Redes
desenvolvido vai ganhar o mercado
80 64k DRAM
– Microsoft Windows vs. Mac OS + OS2
84 (32-bit µP) 256k DRAM ADA
– 68000 vs. x86 Paralelismo 87 ULSI 1M DRAM
– Qualquer implementação nova tenta diminuir sua dependência com 89 GAs 4M DRAM C++
a sorte o máximo o possível (isso é um esforço multi-disciplinar) 92 (64-bit µP) 16M DRAM Fortran90

Evolução Tecnológica Evolução Tecnológica

Perspectiva da Intel Moore’s Law
Ano Processador # Xtors
1971 4004 2300
1972 8008 3500
1974 8080 6000
1978 8086/8088 29000
1982 80286 134K
1985 80386 275K
1989 80486 1.2M
1993 Pentium 3.1M
1995 Pentium Pro 5.5M
1997 Pentium II 7.5M
1999 Pentium III 9.5M
 Projeto de Novas Arquiteturas Projeto de Novas Arquiteturas
• Área de aplicação
– Special Purpose (e.g., DSP) / General Purpose • Requisitos do sistema operacional para aplicações
– Científico (intenso em FP) / Comercial (Mainframe) do tipo general purpose
– Tamanho do espaço de endereçamento (Address Space)
• Nível de compatibilidade de Software – Gerenciamento de memória e proteção
– Compatibilidade de código objeto/binário (custo HW vs. – Trocas de contexto
SW, x86) – Interrupções e Traps
– Linguagem de máquina (modificações no código • Padrões: inovação vs. competição
objeto/binário são possíveis no projeto da arquitetura) – IEEE 754 (Ponto flutuante)
– Linguagens de programação (por que não?) – Barramentos de I/O
– Redes
– Sistemas operacionais / Linguagens de programação ...

What is “Computer Architecture” Instruction Set Architecture (subset of Computer Arch.)

... the attributes of a [computing] system as seen by

Computer Architecture = the programmer, i.e. the conceptual structure and
Instruction Set Architecture + functional behavior, as distinct from the organization
of the data flows and controls the logic design, and
Machine Organization the physical implementation.
– Amdahl, Blaaw, and Brooks, 1964
-- Organization of Programmable SOFTWARE
Storage

-- Data Types & Data Structures:

Encodings & Representations

-- Instruction Set

-- Instruction Formats

-- Modes of Addressing and Accessing Data Items and Instructions

-- Exceptional Conditions

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 The Instruction Set: a Critical Interface Example ISAs (Instruction Set Architectures)

° Digital Alpha (v1, v3) 1992-97

° HP PA-RISC (v1.1, v2.0) 1986-96
software
° Sun Sparc (v8, v9) 1987-95
° SGI MIPS (MIPS I, II, III, IV, V) 1986-96
instruction set
° Intel (8086,80286,80386, 1978-96
80486,Pentium, MMX, ...)
hardware

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MIPS R3000 Instruction Set Architecture (Summary) Organization

° Instruction Categories Registers ° Capabilities & Performance Logic Designer's View

Characteristics of Principal
• Load/Store Functional Units ISA Level
R0 - R31
• Computational • (e.g., Registers, ALU, Shifters, Logic
• Jump and Branch Units, ...) FUs & Interconnect
• Floating Point ° Ways in which these components
- coprocessor are interconnected
PC
• Memory Management
• Special
HI ° Information flows between
LO components
° Logic and means by which such
3 Instruction Formats: all 32 bits wide information flow is controlled.
OP rs rt rd sa funct
° Choreography of FUs to
OP rs rt immediate realize the ISA
OP jump target ° Register Transfer Level (RTL)
Description
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Q: How many already familiar with MIPS ISA? cs 152 L1 Intro.38
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 Example Organization What is “Computer Architecture”?

° TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 Application

Operating
MBus Module System
SuperSPARC
Compiler Firmware
Floating-point Unit Instruction Set
Architecture
L2 Instr. Set Proc. I/O system
CC DRAM
Integer Unit $ MBus Controller Datapath & Control
Digital Design
L64852 MBus control Circuit Design
Inst Ref Data M-S Adapter Layout
Cache MMU Cache STDIO
SBus serial
Store SCSI kbd ° Coordination of many levels of abstraction
SBus mouse
Buffer Ethernet
DMA audio ° Under a rapidly changing set of forces
RTC
Bus Interface SBus Boot PROM
Floppy
° Design, Measurement, and Evaluation
Cards

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Technology Technology => dramatic change

DRAM chip capacity Microprocessor Logic Density
100000000

DRAM ° Processor
Year Size 10000000 • logic capacity: about 30% per year
R10000

1980 64 Kb Pentium
R4400 • clock rate: about 20% per year
1983 256 Kb 1000000
i80486

° Memory
Transistors

1986 1 Mb i80386

i80286
1989 4 Mb 100000
R3010 • DRAM capacity: about 60% per year (4x every 3 years)
1992 16 Mb i8086
SU MIPS
i80x86 • Memory speed: about 10% per year
M68K
10000
1996 64 Mb MIPS
Alpha • Cost per bit: improves about 25% per year
1999 256 Mb i4004

2002 1 Gb
1000
1970 1975 1980 1985 1990 1995 2000 2005 ° Disk
° In ~1985 the single-chip processor (32-bit) and the • capacity: about 60% per year
single-board computer emerged
• => workstations, personal computers, multiprocessors have
been riding this wave since

° In the 2002+ timeframe, these may well look like

mainframes compared single-chip computer
(maybe 2 chips)
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 Performance Trends Processor Performance (SPEC)

performance now improves - 50% per year (2x every 1.5 years)
300

250
Log of Performance
Supercomputers RISC
Mainframes
200
Minicomputers
150
Intel x86
RISC
100
introduction
Microprocessors 50 35%/yr

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995
Year
Year
1970 1975 1980 1985 1990 1995

Did RISC win the technology battle and lose the market war?
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Applications and Languages Measurement and Evaluation

Architecture is an iterative process
° CAD, CAM, CAE, . . . -- searching the space of possible designs
Design -- at all levels of computer systems
° Lotus, DOS, . . .
° Multimedia, . . . Analysis

° The Web, . . .
° JAVA, . . . Creativity
° ??? Cost /
Performance
Analysis

Good Ideas
Mediocre Ideas
Bad Ideas
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 Conceptual tool box?

Computer Architecture and Engineering ° Evaluation Techniques

Instruction Set Design
Interfaces
Compiler/System View
-“Building Architect”
° Levels of translation (e.g., Compilation)
Computer Organization ° Levels of Interpretation (e.g., Microprogramming)
° Hierarchy (e.g, registers, cache, mem,disk,tape)
Hardware Components
° Pipelining and Parallelism
Logic Designer’s View ° Static / Dynamic Scheduling
-“Construction Engineer” ° Indirection and Address Translation
° Synchronous and Asynchronous Control Transfer
° Timing, Clocking, and Latching
° CAD Programs, Hardware Description Languages, Simulation
° Physical Building Blocks (e.g., CLA)
° Understanding Technology Trends

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Levels of Representation (61C Review)

What are “Machine Structures”?
temp = v[k];
High Level Language v[k] = v[k+1]; Application (ex: browser)
Program Operating
v[k+1] = temp;
Compiler System
Compiler (WinXP)
Software Assembler
lw$15, 0($2) Instruction Set
Assembly Language lw$16, 4($2) Hardware Architecture
Program Processor Memory I/O system
sw $16, 0($2)
sw $15, 4($2) Datapath & Control
Assembler
Digital Design
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110 Circuit Design
Program 1100 0110 1010 1111 0101 1000 0000 1001 transistors
0101 1000 0000 1001 1100 0110 1010 1111

Machine Interpretation
* Coordination of many
Control Signal ALUOP[0:3] <= InstReg[9:11] & MASK
Specification levels (layers) of abstraction
°
°
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 Levels of Representation Anatomy: 5 components of
temp = v[k];
High Level Language
Program (e.g., C)
v[k] = v[k+1]; any computer
v[k+1] = temp;
Compiler lw $t0, 0($2)
lw $t1, 4($2)
Assembly Language sw $t1, 0($2)
Program (e.g.,MIPS) sw $t0, 4($2) Personal Computer
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program (MIPS) 1100 0110 1010 1111 0101 1000 0000 1001 Computer Keyboard,
0101 1000 0000 1001 1100 0110 1010 1111 Mouse
Processor Memory Devices
Machine
Interpretation Disk
Control Input (where
Hardware Architecture Description (“brain”) (where
(Logic, Logisim, etc.) programs, programs,
data data
Architecture Datapath live when live when
(“brawn”) Output not running)
Implementation running)

Logic Circuit Description Display,

(Logisim, etc.) Printer

Integrated Circuits
Overview of Physical
(2003 state-of-the-art)
Implementations • Primarily Crystalline Silicon
Bare Die • 1mm - 25mm on a side
The hardware out of which we make systems. • 2003 - feature size ~ 0.13µm = 0.13 x 10-6 m
• 100 - 400M transistors
• (25 - 100M “logic gates")
• Integrated Circuits (ICs)
– Combinational logic circuits, memory elements, analog interfaces. • 3 - 10 conductive layers
• Printed Circuits (PC) boards • “CMOS” (complementary metal oxide
– substrate for ICs and interconnection, distribution of CLK, Vdd, and GND semiconductor) - most common.
signals, heat dissipation.
• Power Supplies Chip in Package
– Converts line AC voltage to regulated DC low voltage levels.
• Chassis (rack, card case, ...)
– holds boards, power supply, provides physical interface to user or other • Package provides:
systems. – spreading of chip-level signal paths to board-level
• Connectors and Cables. – heat dissipation.
• Ceramic or plastic with gold wires.
 Technology Trends: Memory Capacity
Printed Circuit Boards (Single-Chip DRAM) size

1000000000
year size (Mbit)
100000000 19800.0625
10000000 1983 0.25
• fiberglass or ceramic 1000000
1986 1
• 1-20 conductive layers 1989 4
100000

• 1-20in on a side 1992 16

10000
• IC packages are soldered 1996 64
down. 1000
1998 128
1970 1975 1980 1985 1990 1995 2000

Year 2000 256

• Now 1.4X/yr, or 2X every 2 years. 2002 512
• 8000X since 1980!

Technology Trends: Technology Trends: Processor

Microprocessor Complexity Performance Intel P4 2000 MHz
900 (Fall 2001)

Performance measure
800 DEC Alpha
100000000
Itanium 2: 41 Million 1.54X/yr
700 21264/600
Athlon (K7): 22 Million
10000000 Alpha 21264: 15 million 600
DEC Alpha 5/500
Moore’s Law Pentium Pentium Pro: 5.5 million 500
i80486
PowerPC 620: 6.9 million 400
1000000
Alpha 21164: 9.3 million
DEC Alpha 5/300
i80386 Sparc Ultra: 5.2 million 300
100000
i80286
200 DEC Alpha 4/266

i8086
2X transistors/Chip 100 IBM POWER 100
10000 Every 1.5 years 0
i8080

i4004 87 88 89 90 91 92 93 94 95 96 97
1000 Called year
1970 1975 1980 1985 1990 1995 2000

Year
“Moore’s Law” We’ll talk about processor performance later on…
 Computer Technology - Dramatic Change Computer Technology - Dramatic Change
• Memory
– DRAM capacity: 2x / 2 years (since ‘96); • State-of-the-art PC when you graduate:
64x size improvement in last decade. (at least…)
• Processor – Processor clock speed: 5000 MegaHertz
– Speed 2x / 1.5 years (since ‘85); (5.0 GigaHertz)
100X performance in last decade. – Memory capacity: 4000 MegaBytes
• Disk (4.0 GigaBytes)
– Disk capacity: 2000 GigaBytes
– Capacity: 2x / 1 year (since ‘97)
(2.0 TeraBytes)
250X size in last decade.
– New units! Mega => Giga, Giga => Tera

(Tera => Peta, Peta => Exa, Exa => Zetta

Zetta => Yotta = 1024)

Levels of Organization Execution Cycle

Obtain instruction from program storage

Instruction
SPARCstation 20 Fetch

Instruction Determine required actions and instruction size

Decode
Computer
Workstation Design Target: Operand Locate and obtain operand data
25% of cost on Processor Processor Memory Devices
Fetch
25% of cost on Memory
(minimum memory size) Control Compute result value or status
Input Execute
Rest on I/O devices,
power supplies, box
Datapath Output Result Deposit results in storage for later use
Store

Next
Determine successor instruction
Instruction

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 The SPARCstation 20 The Underlying Interconnect
SPARCstation 20 SPARCstation 20

Memory Memory SIMMs Memory SIMM Bus

Controller SIMM Bus Controller

MBus Disk Standard I/O Bus:

MBus Slot 1 Processor/Mem Bus: SCSI Bus
SBus Slot 1 SBus Slot 3 Tape MBus
MBus Slot 0
SBus Slot 0 SBus Slot 2 Sun’s High Speed I/O Bus:
SCSI SBus
MSBI Bus MSBI
SEC SBus MACIO SEC MACIO

Low Speed I/O Bus:

Keyboard Floppy External Bus External Bus
& Mouse Disk

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Processor and Caches Memory

SPARCstation 20 SPARCstation 20

SIMM Slot 0

SIMM Slot 3

SIMM Slot 4

SIMM Slot 5

SIMM Slot 6

SIMM Slot 7
SIMM Slot 1

SIMM Slot 2
MBus Module Memory Memory SIMM Bus
Controller
Processor
MBus

MBus Slot 1 Registers Datapath

DRAM SIMM
MBus Slot 0
DRAM DRAM DRAM DRAM DRAM
Internal DRAM DRAM DRAM DRAM DRAM
Control
Cache

External Cache

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 Input and Output (I/O) Devices Standard I/O Devices
SPARCstation 20 SPARCstation 20
° SCSI Bus: Standard I/O
Devices
° SBus: High Speed I/O ° SCSI = Small Computer Systems Interface
Devices
° A standard interface (IBM, Apple, HP, Sun
° External Bus: Low Speed I/O Disk
... etc.) Disk

Device
SBus Slot 1 SBus Slot 3 Tape
° Computers and I/O devices communicate Tape
with each other
SBus Slot 0 SBus Slot 2

SBus SCSI
° The hard disk is one I/O device resides on SCSI
Bus
the SCSI Bus Bus
SEC MACIO

Keyboard Floppy External Bus

& Mouse Disk

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High Speed I/O Devices Slow Speed I/O Devices

SPARCstation 20 SPARCstation 20

° SBus is SUN’s own high speed I/O bus

° SS20 has four SBus slots where we can plug ° The are only four SBus slots in SS20--”seats”
in I/O devices are expensive

° Example: graphics accelerator, video adaptor, ° The speed of some I/O devices is limited by
... etc. human reaction time--very very slow by
computer standard
° High speed and low speed are relative terms ° Examples: Keyboard and mouse
° No reason to use up one of the expensive
SBus slot
SBus Slot 1 SBus Slot 3

SBus Slot 0 SBus Slot 2 Keyboard Floppy External Bus

SBus & Mouse Disk

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