La-E081p Rev1.0.pdf (Diagramas - Com.br)

A B C D E
COMPAL CONFIDENTIAL
1 MODEL NAME :CDM70 1
PCB NO : LA-E082P
BOM P/N :
BR14 KBL-U DSC

Kabylake U
2
2016-11-07 2
REV : 1.0 (A00)

@ : Nopop Component
EMC@ : EMI, ESD and RF Component
CXDP@ : XDP Component
CONN@ : Connector Component
3 3
MB PCB
Part Number Description
DAA000CR000 PCB 1SD LA-E082P REV0 MB DSC 1
Layout Dell logo
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2015
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
REV:X00 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
PWB: DKJP1 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-E082P
Date: Monday, December 12, 2016 Sheet 1 of 75
A B C D E
A B C D E
Breckenridge 14 DSC Block Diagram Reverse Type
Memory BUS (DDR4) DDR4-SO-DIMM X2

BANK 0, 1, 2, 3
PCIE[5][6][7][8] 2133 MHz
2GB dGPU Up to 2x8GB Modules P20~21
1
DDR3L PAGE 53~54 23X23PAGE 48~52 1
2-Lane eDP1.3 USB2.0[8]

EDP CONN LCD Touch
P29 P29
USB2.0[5]
HDMI 1.4 DDI[1] INTEL Camera
CONN P29 Trough eDP Cable
P23
SW2_DP1 USB2.0[1] SLGC55544BVTR USB2.0[1]_PS
To Type C USB POWER SHARE
P43
USB USB3.0 Conn
SW2_DP2 DP DeMUX DDI[2]
KABYLAKE_U MCP USB3.0[1] USB3 Repeater USB3.0
PS(Ext Port 1)
To M2 WiGig card PS8348B P43
P22 PS8713B P42
USB2.0[2]
USB3.0 Conn
VGA DP TO VGA SW2_DP3 USB3.0[3] (Ext Port 2) P44
CONN RTD2166 P24 To VGA
P24 USB2.0[3]
USB3.0 Conn
2
USB3.0[4] (Ext Port 3) P44 2
PCIE[4] PCIE[3] PAGE 6~19

PCIE[1] PCIE[9]
Card reader Intel Jacksonville M.2,3042 Key B M.2,3030 Key A

RTS5242 P34 WGI219LM P33 WWAN/LTE SATA[2]/PCIE[12][11]
WLAN+BT/WIGIG
SPI
P32 P32 INT.Speaker
W25Q128FVSIQ P33
USB2.0[4] USB2.0[7]
SD4.0 Transformer P8
ESPI
P34 P33 SW2_DP2 HD Audio I/F HDA Codec Universal Jack
USB3.0[2] 128M 4K sector
ALC3246 P33 P33
W25Q128FVSIQ
RJ45 P33 P8 Dig. MIC
128M 4K sector P29
reserve
Trough eDP Cable

TPM2.0
ATTPM20P-G1MA1-ABF
P37
SATA/PCIE REPEATER
PS8558x2
P38
3 3
KB/TP CONN
Expander IO SMSC KBC P45 LID SWITCH
P47
IT8010FN MEC5105 SATA/PCIE MUX
P35 P34-35 HD3SS3415
FAN CONN USH CONN
P35 P39 P38
Non-AR Type C CPU&PCH XDP Port

P14
DP1.2 4 lanes SATA HDD M.2 2280
SW2_DP1
Conn P41 SSD Conn P40 AUTOMATIC POWER
TX/RX HS Redriver Switch SWITCH(APS) P11
TUSB546 USB3.0[6]
P25
Free Fall sensor
P41
USB 3.0 + AM GPIO Smart Card TDA8034HN
Type C CONN. USB2.0 USH TPM1.2 USB2.0[10] DC/DC Interface
SMBUS P47
PD Solut i on BCM58102
CC USB2.0[9] RFID/NFC SPI
TPS65982D POWER ON/OFF
4
P28
Vbus P26-27 SW & LED P46
4
Fingerprint SPI
CONN
5V VR USH board P39 DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Charger TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Block diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E082P
A B C D E
5 4 3 2 1
POWER STATES
SSIC
For Breckenridge14/15 DSC
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB1-->Right 1 JUSB1-->Right
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Lef t
USB3.0-3 JUSB2-->Lef t 3 JUSB3-->Rear Lef t
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
D
USB3.0-4 JUSB3-->Rear Lef t 4 M2 3042(WWAN) D
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 Card Reader 5 Camera
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

USB3.0-6 PCIE-2 Type-C Port 6 NA
PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)

S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 M.2 3030(WIGIG) 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 9 Type-C Port
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 10 USH
Discrete Graphics x4
PCIE-7 SATA-0
PM TABLE PCIE-8 SATA-1
+5V_ALW
PCIE-9 LOM
+3.3V_ALW PCIE-10 NA
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
PCIE-11 SATA-1* NA M.2 2280 SSD
power (PCIex2 or SATA)
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 SATA HDD C
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

+1.0V_PRIM +VCC_CORE
+1.0V_PRIM_CORE +VCC_GT
+5V_ALW 2 +VCC_SA
State
+3.3V_ALW2 +1.0VS_VCCIO
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
S5 S4/AC doesn't exist OFF OFF OFF
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
SIO_SLP_SUS# CPU PWR

SIO_SLP_S4#
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
GT3 PWR
SY8210A
(PU200) Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0# TYPE-C Power
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER GPU PWR
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
D D
SIO_SLP_SUS#
SYX198D 3V3_MAIN_EN
(PU301) +1.0V_PRIM EM5209VF
(UV15) +1.0V_PEX_VDD
RUN_ON
CHARGER TPS62134C
ISL88738 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALW ON
(PU801) SY8288C
(PU102) TPS62134D SIO_SLP_SUS#
(PU402) +1.0V_PRIM_CORE
+5V_ALW2
DGPU_PWROK
GPU_GC6_FB_EN RUN_ON 3.3V_TS_EN
SYX196D EM5209 LP2301
(PU800) +1.35V_MEM_GFX (UZ4) +5V_RUN (QV8) +5V_TSP
BATTERY 3V3_MAIN_EN AUD_PWR_EN

RT8813A EM5209
(PU701) +GPU_CORE (@UZ5) +5V_RUN_AUDIO
USB_PWR_SHR_EN#
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR
USB_PWR_EN2#
+3.3V_ALW SY6288
(UI2) +USB_EX3_PWR
SIO_SLP_SUS# RUN_ON
AP3402KTTR AOZ1336
(PU501) (UZ8)
SIO_SLP_LAN#
ISL95857 ISL95857 ISL95857 AO6405
(PU602) (PU604) (PU603) (QV1) +3.3V_LAN
EM5209
(UZ2)
IMVP_VR_ON
AUX_EN_WOWL
IMVP_VR_ON
IMVP_VR_ON
EN_INVPWR
+3.3V_WLAN
@SIO_SLP_WLAN#
SIO_SLP_SUS#
+3.3V_ALW_PCH
B EM5209 @PCH_ALW_ON B
(UZ3)
RUN_ON 3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM
3.3V_WWAN_EN
EM5209 AUD_PWR_EN
(UZ4) +3.3V_WWAN EM5209
(@UZ5) +3.3V_RUN_AUDIO
ENVCC_PCH
G524B1T11U
(UV24) +LCDVDD DGPU_PWR_EN
LP2301A
(QV1) +3.3V_GFX_AON
TYPE-C EM5209VF 3V3_MAIN_EN

+3.3V_RUN_GFX
(UV15)
+TBTA_VBUS(5V~20V)
CV2_ON
TPS22967
(UZ18) +3.3V_CV2
USH/B
SIO_SLP_S4#
AP7175SP
(PU503) +2.5V_MEM
for DDR4
A
+5V_ALW A
AP2204 AP2112K
(UT8) (UT7) +3.3V_TBT_SX
+5V_TBT_VBUS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
5 4 3 2 1
5 4 3 2 1
1K 2.2K
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
R7 MEM_SMBCLK 202
DDR_XDP_WAN_SMBCLK
DMN66D0LDW-7
R8 MEM_SMBDATA 200 DIMMA
DDR_XDP_WAN_SMBDAT
DMN66D0LDW-7
499
202
D SKL-U D
+3.3V_ALW_PCH 200 DIMMB

499
R9 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
W2
V3 W3 53
51
XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
1
E11 D8 2.2K LNG2DMTR
4
+3.3V_TP
03 03 2.2K
02 C12 DAT_TP_SIO_I2C_CLK 9
02 E10 CLK_TP_SIO_I2C_DAT 8 TP
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
C C
01 B3 USH_SMBCLK M9
E5 USH_SMBDAT USH
01 L9
2.2K USH/B
00 D7 2.2K
00 E7
2.2K +3.3V_ALW +3.3V_TBT_FLASH
KBC 2.2K
C3 UPD1_SMBCLK UPD1_SMBCLK_Q B5
DMN66D0LDW-7 PD &
04
B4 UPD1_SMBDAT UPD1_SMBDAT_Q A5 FW reflash
04 DMN66D0LDW-7
MEC 5105
F7
05
B6
05
06 A12
B 1.8K B
06 N10
2.2K
+3.3V_ALW 1.8K
+3.3V_RUN_GFX
2.2K
EXPANDER_GPU_SMCLK
07 M4 DMN66D0LDW-7
M7 EXPANDER_GPU_SMDATA GPU
07
DMN66D0LDW-7
EXPANDER
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
A N2 PBAT_CHARGER_SMBCLK A
100 ohm 6
BATTERY
10 M3 PBAT_CHARGER_SMBDAT CONN
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
5 4 3 2 1
5 4 3 2 1
For 2LANE EDP,BR/SB12

+3.3V_RUN
UC1A CPU@ SKL-U
2 1 CPU_DP1_CTRL_CLK E55 C47

RC175 2.2K_0402_5% <23> CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <29>
2 1 CPU_DP1_CTRL_DATA <23> CPU_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <29>
RC178 2.2K_0402_5% <23> CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <29>
2 1 CPU_DP2_CTRL_CLK HDMI <23> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <29>
D RC176 2.2K_0402_5% <23> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 D
2 1 CPU_DP2_CTRL_DATA <23> CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47
RC177 2.2K_0402_5% <23> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47
<23> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3]
C50 E45
<22> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <29>
<22> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <29>
<22> CPU_DP2_N1 D52 DDI2_TXN[1] B52
PS8338(AR)/ <22> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
<22> CPU_DP2_N2 DDI2_TXN[2]
PS8348(NON AR) <22> CPU_DP2_P2
B50
D51 DDI2_TXP[2] DDI1_AUXN
G50
F50
CPU_DP1_AUXN
CPU_DP1_AUXP PAD~D @ T281
<22> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 PAD~D @ T282
<22> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <22>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <22>
DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2
<23> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
<23> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <23>
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <22> EDP_HPD 1 2
<22> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 RC1 100K_0402_5%
<22> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
N11 GPP_E17/EDP_HPD EDP_HPD <29>
GPP_E23 N12 GPP_E22/DDPD_CTRLCLK R12
T120@ PAD~D GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PANEL_BKLEN <29>
R11
RC2 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <29>
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <29,34>
1 OF 20
SKL-U_BGA1356
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C
SKL_ULT
UC1I CPU@
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7 TBT_FORCE_PWR
C33 CSI2_DP4 GPP_D4/FLASHTRIG PAD~D @ T19
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
SKL-U_BGA1356 9 OF 20
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (1/14)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
1.0
5 4 3 2 1
5 4 3 2 1
For DDR4
<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]
DDR4, Ballout for side by side(Non-Interleave) <20> DDR_A_D[0..63] <21> DDR_B_D[0..63]
<20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]

D D
<20> DDR_A_MA[0..16] SKL-U <21> DDR_B_MA[0..16]
UC1B CPU@ SKL-U UC1C CPU@
AU53 DDR_A_CLK#0
DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 PAD~D @ T3 DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] PAD~D @ T4 DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 PAD~D @ T5
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] PAD~D @ T6
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <20> DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 <21>
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 <20> DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BG0 <21>
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# <20> DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT#
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <20> DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1 DDR_B_ACT# <21>
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <21>
DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
C DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15 C
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BA0 <20> DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BA0 <21>
DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BA1 <20> DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BA1 <21>
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_A_DQS#2
DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS#3
DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#4 DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS3
DDR_B_D11 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3]
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#5 DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS5 DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS#7
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_B_DQS#0 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS7
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS0 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#2
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS1 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS#4 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS3
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS4 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT# DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_A_PARITY DDR_A_ALERT# <20> DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_ALERT#
DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PARITY <20> DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PARITY DDR_B_ALERT# <21>
DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR_DRAMRST# DDR_B_PARITY <21>
B DDR_B_D43 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +DDR_VREF_A_DQ +DDR_VREF_CA DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 DDR_DRAMRST# <20> B
AW25 AY68 AT21 AR18
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 PAD~D @ T132 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 DDR CH - B AU18
DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_VTT_CTRL <20> DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]
SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0402_1%
SM_RCOMP1 RC6 1 2 80.6_0402_1%
SM_RCOMP2 RC7 1 2 100_0402_1%
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
UC1E CPU@
SKL-U For BR/SB
2
SPI - FLASH
SMBUS, SMLINK
PCH_SPI_CLK AV2 MEM_SMBCLK 6 1
PCH_SPI_D1 AW3 SPI0_CLK R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14,20,21,41>
CXDP@ RC10 1 2 1K_0402_1% PCH_SPI_D0 AV3 SPI0_MISO GPP_C0/SMBCLK R8 MEM_SMBDATA QC2A
<14> PCH_SPI_DO_XDP SPI0_MOSI GPP_C1/SMBDATA
5
CXDP@ RC11 1 2 1K_0402_1% PCH_SPI_D2 AW2 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0 AU3 SPI0_IO3 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA SML0_SMBCLK <30> DDR_XDP_WAN_SMBDAT <14,20,21,41> D
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 SML0_SMBDATA <30> QC2B
<36> PCH_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_RUN
W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <34>
M2 GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <34> DDR_XDP_WAN_SMBDAT1 2
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# RC318 2.2K_0402_5%
J4 GPP_D2/SPI1_MISO DDR_XDP_WAN_SMBCLK1 2
V1 GPP_D3/SPI1_MOSI RC319 2.2K_0402_5%
V2 GPP_D21/SPI1_IO2
M1 GPP_D22/SPI1_IO3
LPC
GPP_D0/SPI1_CS# AY13 ESPI_IO0_R RC3661 2 15_0402_5%
GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <34,35> +3.3V_ALW_PCH
RC3671 2 15_0402_5%
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <34,35>
RC3681 2 15_0402_5% ESPI_IO2 <34,35>
G3 GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5%
<32> PCH_CL_CLK1 G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <34,35> MEM_SMBCLK 1 2
<32> PCH_CL_DATA1 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <34,35> RC12 1K_0402_5%
<32> PCH_CL_RST1# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <34> MEM_SMBDATA 1 2
2 1 10K_0402_5%
+3.3V_RUN LPC@ RC13 ESPI_CLK SML1_SMBCLK
RC14 1K_0402_5%
AW13 AW9 EMI@ RC16 1 2 15_0402_5% 1 2
<34> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 ESPI_CLK_5105 <34,35>
@ RC22 1 2 22_0402_5% RC15 1K_0402_5%
AY11 GPP_A10/CLKOUT_LPC1 AW11 SML1_SMBDATA 1 2
<34> ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <34>
RC17 1K_0402_5%
RC21 2 1 8.2K_0402_1% SML0_SMBCLK 1 2
+3.3V_1.8V_ESPI
SKL-U_BGA1356 5 OF 20 RC347 499_0402_1%
SML0_SMBDATA 1 2
RC348 499_0402_1%
+3.3V_LAN
C C
SOFTWARE TAA RF Request SML0_SMBCLK 1 2

@ RC19 499_0402_1%
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R ESPI_CLK_5105 1 2 SML0_SMBDATA 1 2
@RF@ CC316 33P_0402_50V8J @ RC20 499_0402_1%
33_0402_5%
33_0402_5%
1
+3.3V_RUN
@EMI@
@EMI@
RPC1
RC28
RC29
PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R SML0_SMBCLK 1 2

+3.3V_SPI <36> PCH_SPI_D1_R1 PCH_SPI_D0_R1 2 7 PCH_SPI_D0_0_R @RF@ CC318 33P_0402_50V8J CLKRUN# 1 2
2
<36> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R LPC@ RC27 8.2K_0402_5%

33P_0402_50V8J
33P_0402_50V8J
<36> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R SML1_SMBCLK 1 2

2 1 PCH_SPI_D2_R1
@EMI@
@EMI@
@RF@ CC319
1
1
CC7
CC8
@ RC31 1K_0402_5% @RF@ CC320 33P_0402_50V8J +3.3V_ALW_PCH

2
2 1 PCH_SPI_D3_R1
@ RC316 1K_0402_5%
PCH_SMB_ALERT# 1 2
Place close CPU side RC23 2.2K_0402_5%
03/02:follow Intel MOW_2015WW06 PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R
PCH_SPI_CLK_R1 @ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R
PCH_SPI_D0_R1 @ RC409 1 2 33_0402_5% PCH_SPI_D0_1_R TLS CONFIDENTIALITY
PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R
HIGH ENABLE
LOW(DEFAULT) DISABLE
WEAK INTERNAL 20K PD
B B
+3.3V_ALW_PCH
JSPI1 GPP_C5 1 2
+3.3V_SPI 22 ESPI@RC25 4.7K_0402_5%
21 GND2
CC9 2 1 PCH_SPI_CS#1_R1 20 GND1
1 2 PCH_SPI_CS#1 19 20
@RC32 0_0402_5%
PCH_SPI_D0_R1 19 EC interface
2 1 18
128Mb Flash ROM 0.1U_0201_10V6K 0_0402_5% RC33 @ PCH_SPI_D0 17 18
HIGH ESPI
UC5 2 1 PCH_SPI_D1_R1 16 17
PCH_SPI_CS#0_R1 @ RC37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 0_0402_5% RC34 @ PCH_SPI_D1 15 16 LOW(DEFAULT) LPC
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R 2 1 PCH_SPI_CLK_R1 14 15 WEAK INTERNAL 20k PD
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 IO1 IO3 6 PCH_SPI_CLK_0_R 0_0402_5% RC35 @ PCH_SPI_CLK 13 14
4 IO2 CLK 5 PCH_SPI_D0_0_R 2 1 PCH_SPI_CS#0_R1 12 13
GND IO0 0_0402_5% RC36 @ PCH_SPI_CS#0 11 12
W25Q128FVSIQ_SO8 2 1 PCH_SPI_D2_R1 10 11
0_0402_5% RC38 @ PCH_SPI_D2 9 10 +3.3V_ALW_PCH
+3.3V_SPI 2 1 PCH_SPI_D3_R1 8 9
0_0402_5% RC40 @ PCH_SPI_D3 7 8
@ CC10 6 7
+3.3V_SPI 6 GPP_B23
1 2 5 1 2
128Mb Flash ROM +3.3V_ALW_PCH
4 5 RC317 150K_0402_5%
0.1U_0201_10V6K 2 1 3 4
@ UC6 0_0402_5% RC41 @ 2 3
PCH_SPI_CS#1_R1 @ RC42 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 1 2
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 1 EXI BOOT STALL BYPASS
PCH_SPI_D2_R1 @ RC43 1 2 33_0402_5% PCH_SPI_D2_1_R 3 IO1 IO3 6 PCH_SPI_CLK_1_R
4 IO2 CLK 5 PCH_SPI_D0_1_R E-T_6705K-Y20N-00L HIGH ENABLED
GND IO0 CONN@ LOW(DEFAULT) DIABLED
A W25Q128FVSIQ_SO8 WEAK INTERNAL PD A
1.0
5 4 3 2 1
5 4 3 2 1
For BR DSC
UC1F CPU@ SKL-U
+3.3V_RUN
LPSS ISH
AN8
<31> MEDIACARD_IRQ# GPP_B15/GSPI0_CS#
2 1 HDD_FALL_INT ONE_DIMM# AP7 P2 MEM_INTERLEAVED
D RC370 10K_0402_5% AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 D
<36> TPM_PIRQ# GPP_B17/GSPI0_MISO GPP_D10 DGPU_HOLD_RST# <48>
2 1 3.3V_TS_EN NRB_BIT AR7 P4 AR_DET#
RC282 100K_0402_5% GPP_B18/GSPI0_MOSI GPP_D11 P1
HDD_FALL_INT AM5 GPP_D12 DGPU_PWR_EN <52>
<41> HDD_FALL_INT AN7 GPP_B19/GSPI1_CS# M4
SIO_EXT_SCI# <34> SIO_EXT_SCI# GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA
2 1 AP5 N3
<29> 3.3V_TS_EN BBS_BIT6 AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL +1.8V_RUN
RC237 10K_0402_5%
2 1 LPSS_UART2_RXD GPP_B22/GSPI1_MOSI N1
@ RC402 49.9K_0402_1% 2 1 GPP_C8 AB1 GPP_D7/ISH_I2C1_SDA N2 ISH_I2C2_SDA 1 2
2 1 LPSS_UART2_TXD Reserve @ RC405 100K_0402_5% AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL RC363 1K_0402_5%
<35> SBIOS_TX W4 GPP_C9/UART0_TXD AD11 ISH_I2C2_SDA ISH_I2C2_SCL 1 2
@ RC403 49.9K_0402_1%
AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SCL ISH_I2C2_SDA <32> WWAN RC362 1K_0402_5%
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <32>
LPSS_UART2_RXD AD1
LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD U1
9/24: Reserve for embedded locat i on,r ef er I nt el PDG 0. 9
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <32>
AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <32>
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <32> WLAN +3.3V_RUN
+3.3V_ALW_PCH GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <32>
U7 AC1
U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 RTD3_CIO_PWR_EN SIO_EXT_WAKE# <34>
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 PAD~D @ T18 LCD_CBL_DET# 1 2
2 1 SIO_EXT_WAKE# U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 HDD_EN LCD_CBL_DET# <29>
RC287 100K_0402_5%
<45> I2C1_SDA_TP U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# HDD_EN <41> DGPU_PWR_EN 1 2
RC283 10K_0402_5%
2 1 LPSS_UART2_RXD <45> I2C1_SCK_TP GPP_C19/I2C1_SCL AY8 CLKDET# RC386 10K_0402_5%
AH9 GPP_A18/ISH_GP0 BA8 PAD~D @ T258
RC330 49.9K_0402_1%
2 1 LPSS_UART2_TXD AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
RC331 49.9K_0402_1% GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7
AH11 GPP_A21/ISH_GP3 AY7 TPM_TYPE
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 LID_CL#_PCH
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 PAD~D @ T268
AF11 GPP_A12/BM_BUSY#/ISH_GP6
C AF12 GPP_F8/I2C4_SDA C
GPP_F9/I2C4_SCL GPP_A GROUP is +1.8V
DGPU_PWR_EN 1 2
SKL-U_BGA1356 6 OF 20 @ RC385 10K_0402_5%
Reserved TPM_TYPE 1 2
@ RC349 100_0402_1%
+3.3V_RUN
+3.3V_RUN
2 1 NRB_BIT
10K_0402_5%
@ RC186 4.7K_0402_5%
2
@ RC267
NO REBOOT STRAP
HIGH No REBOOT CONN@
1
JUART1
LOW(DEFAULT) REBOOT ENABLE ONE_DIMM# 1
Internal 20k PD LPSS_UART2_TXD 2 1
2
1
LPSS_UART2_RXD
10K_0402_5%
3
4 3
4
RC268
5
6 GND
2
GND
C
I
1
8
0
4
M
1
V
R
A
-
N
H
L
I
N
K
D
O
N
E
CVILU_CI1804M1VRA-NH
B +3.3V_ALW_PCH B
DIMM Detect
2 1 BBS_BIT6
@ RC184 8.2K_0402_5%
HIGH 1 DIMM
LOW 2 DIMM +3.3V_ALW_PCH
+3.3V_ALW_PCH
BOOT BIOS Dest i nat i on(Bi t 6
)
HIGH LPC
LOW(DEFAULT) SPI
2
2
Internal 20k PD RC400

@ RC371 10K_0402_5%
10K_0402_5%
1
1
AR_DET#
MEM_INTERLEAVED
1
1
10K_0402_5%
10K_0402_5% @RC401
RC372
2
AR_DET#
2
DIMM TYPE
HIGH NON AR
A HIGH Interleave A
LOW AR
LOW Non-Interleave
1.0
5 4 3 2 1
5 4 3 2 1
For Non AR,Breckenridge 14/15 DSC

UC1H CPU@ SKL-U
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN G8 USB3_PRX_DTX_N1 <42>
D H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <42> D
<31> PCIE_PRX_DTX_N1 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <42> -----> Ext USB3 Port 1 Charge
Card Reader RTS5242-----> <31> PCIE_PRX_DTX_P1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <42>
<31> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<31> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_PRX_DTX_N2 <32>
G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_PRX_DTX_P2 <32>
<25> USB3_PRX_DTX_N6 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_PTX_DRX_N2 <32> -----> M.2 3042(LTE)
Type-C Port -----> <25> USB3_PRX_DTX_P6 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <32>
<25> USB3_PTX_DRX_N6 C16 PCIE2_TXN/USB3_6_TXN J10
<25> USB3_PTX_DRX_P6 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_PRX_DTX_N3 <44>
H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_PRX_DTX_P3 <44>
<32> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_PTX_DRX_N3 <44> -----> Ext USB3 Port 2
<32> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_PTX_DRX_P3 <44>
M.2 3030(WLAN) ---> <32> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<32> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10 USB3_PRX_DTX_N4 <44>
G15 USB3_4_RXP C15 USB3_PRX_DTX_P4 <44> -----> Ext USB3 Port 3
<32> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15 USB3_PTX_DRX_N4 <44>
<32> PCIE_PRX_DTX_P4 B19 PCIE4_RXP USB3_4_TXP USB3_PTX_DRX_P4 <44>
M.2 3030(WiGig) ---> <32> PCIE_PTX_DRX_N4 A19 PCIE4_TXN AB9
<32> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10 USB20_N1 <43>
PEG_CRX_GTX_N0 F16 USB2P_1 USB20_P1 <43> -----> Ext USB Port 1 Charge(RIGHT)
PEG_CRX_GTX_P0 E16 PCIE5_RXN AD6
PEG_CTX_C_GRX_N0 2 0.22U_0402_16V7K PEG_CTX_GRX_N0 PCIE5_RXP USB2N_2 USB20_N2 <44>
CC34 1 C19 AD7
PEG_CTX_C_GRX_P0 CC35 1 2 0.22U_0402_16V7K PEG_CTX_GRX_P0 D19 PCIE5_TXN USB2P_2 USB20_P2 <44> -----> Ext USB Port 2(LEFT)
PCIE5_TXP AH3
PEG_CRX_GTX_N1 G18 USB2N_3 AJ3 USB20_N3 <44>
PEG_CRX_GTX_P1 F18 PCIE6_RXN USB2P_3 USB20_P3 <44> -----> Ext USB Port 3(REAR LEFT)
PEG_CTX_C_GRX_N1 CC36 1 2 0.22U_0402_16V7K PEG_CTX_GRX_N1 D20 PCIE6_RXP AD9
PEG_CTX_C_GRX_P1 2 0.22U_0402_16V7K PEG_CTX_GRX_P1 PCIE6_TXN USB2N_4 USB20_N4 <32>
CC37 1 C20 AD10
PCIE6_TXP USB2P_4 USB20_P4 <32> -----> M2 3042(WWAN)
PEG_CRX_GTX_N2 F20 AJ1
PEG_CRX_GTX_P2 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <29>
C Discrete Graphics---> PEG_CTX_C_GRX_N2 CC38 1 2 0.22U_0402_16V7K PEG_CTX_GRX_N2 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <29> -----> Camera C
PEG_CTX_C_GRX_P2 CC39 1 2 0.22U_0402_16V7K PEG_CTX_GRX_P2 A21 PCIE7_TXN/SATA0_TXN AF6
PCIE7_TXP/SATA0_TXP USB2N_6 AF7
PEG_CRX_GTX_N3 G21 USB2P_6
PEG_CRX_GTX_P3 F21 PCIE8_RXN/SATA1A_RXN AH1
PEG_CTX_C_GRX_N3 2 0.22U_0402_16V7K PEG_CTX_GRX_N3 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <32>
CC40 1 D21 AH2
PEG_CTX_C_GRX_P3 CC41 1 2 0.22U_0402_16V7K PEG_CTX_GRX_P3 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <32> -----> M.2 3030(BT)
PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <29>
<30> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <29> -----> LCD Touch
<30> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
10/100/1G LAN ---> PCIE9_TXN USB2N_9 USB20_N9 <26>
PCIE9_TXP USB2P_9 USB20_P9 <26> -----> Typce-C(Non AR)
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <37> USB2_ID @ RC337 1 2 0_0402_5%
D23 PCIE10_RXP USB2P_10 USB20_P10 <37> -----> USH
C23 PCIE10_TXN 2 1K_0402_5%
PCIE10_TXP USB2_COMP AG3 USB2_ID
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC338 1 USB2_ID <26>
2 1K_0402_5% 1 2 1K_0402_5%
SATAGP1 RC416
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <43>
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC1# <44>
<14> CPU_XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# <44> +3.3V_ALW_PCH
Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
<38> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 10K_8P4R_5%
<38> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 USB_OC3# 1 8
<38> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2280_DEVSLP <40,41> USB_OC0# 2 7
M2 2280 SSD ---> <38> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 SATAGP0 USB_OC1# 3 6
<38> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATAGP1 USB_OC2# 4 5
<38> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 M2280_PCIE_SATA#
B <38> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <38,39> RPC3 B
<38> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 SATALED#
GPP_E8/SATALED# SATALED# <32,40,46>
+3.3V_RUN
RPC4
M2280_PCIE_SATA# 4 5
SATAGP0 3 6
SATALED# 2 7
SATAGP1 1 8
10K_8P4R_5%
PEG_CRX_GTX_P[0..3]
<48> PEG_CRX_GTX_P[0..3]
PEG_CRX_GTX_N[0..3]
<48> PEG_CRX_GTX_N[0..3]
PEG_CTX_C_GRX_P[0..3]
<48> PEG_CTX_C_GRX_P[0..3]
PEG_CTX_C_GRX_N[0..3]
<48> PEG_CTX_C_GRX_N[0..3]
A A
1.0
5 4 3 2 1
5 4 3 2 1
For BR DSC
CC21
1 2 XTAL24_IN_R 1 2
RC417 33_0402_5%
15P_0402_50V8J
2
1M_0402_1%
3
4
RC46
UC1J CPU@ SKL_ULT
YC1
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
1
2
D42
<48> CLK_PCIE_N0 CLKOUT_PCIE_N0 XTAL24_IN
C42 CC22
<48> CLK_PCIE_P0 CLKREQ_PCIE#0_R CLKOUT_PCIE_P0 XTAL24_OUT
D GPU---> 0_0402_5% 2 1 RC373 @RF@ AR10 1 2 XTAL24_OUT_R 1 2 D
<48> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0#
+3.3V_RUN RC189 2 1 10K_0402_5% RC295 33_0402_5%
B42 For Skylake,YC1 24 MHz (50 Ohm ESR) 15P_0402_50V8J
<32> CLK_PCIE_N1 CLKOUT_PCIE_N1 CLK_ITPXDP_N For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
A42 F43 @ RC297 1 2 0_0402_5%
<32> CLK_PCIE_P1 CLKREQ_PCIE#1_R CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_ITPXDP_P CLK_ITPXDP_N_R <14>
WLAN---> 0_0402_5% 2 1 RC374 @RF@ AT7 E43 @ RC298 1 2 0_0402_5% 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
<32> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14>
+3.3V_RUN RC47 2 1 10K_0402_5%
D41 BA17 SUSCLK
<32> CLK_PCIE_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <32,40>
CC23
<32> CLK_PCIE_P2 CLKREQ_PCIE#2_R CLKOUT_PCIE_P2 XTAL24_IN PCH_RTCX1
WIGIG---> 0_0402_5% 2 1 RC375 @RF@ AT8 E37 1 2
<32> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT PCH_RTCX2
+3.3V_RUN RC50 2 1 10K_0402_5% E35
D40 XTAL24_OUT 12P_0402_50V8J
<40> CLK_PCIE_N3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
<40> CLK_PCIE_P3 CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5
1
0_0402_5% 2 1 RC376 @RF@ CLKREQ_PCIE#3_R AT10 RC52 2.7K_0402_1%
M.2 SDD---> <40> CLKREQ_PCIE#3 2 1 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 1 2
+3.3V_RUN RC59 For Skylake, pop RC52,depop RC324 RC54 YC2
B40 RTCX1 AM20 PCH_RTCX2 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52 32.768KHZ_12.5PF_9H03200042
<30> CLK_PCIE_N4 CLKOUT_PCIE_N4 RTCX2 10M_0402_5%
A40 546765_546765_2014WW48_Skylake_MOW_Rev_1_0 ESR MAX=50k ohm
<30> CLK_PCIE_P4
2
0_0402_5% 2 1 RC377 @RF@ CLKREQ_PCIE#4_R AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC56 1 2 20K_0402_5%
LAN---> <30> CLKREQ_PCIE#4 +RTC_CELL
1
RC51 2 1 10K_0402_5% GPP_B9/SRCCLKREQ4# SRTCRST# AM16 CC26
+3.3V_RUN RTCRST#
E40 CC24 1 2 1U_0402_6.3V6K 1 2 PCH_RTCX2_R 1 2
<31> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5 @ RC296 0_0402_5%
<31> CLK_PCIE_P5 1 RC378 @RF@ CLKREQ_PCIE#5_R CLKOUT_PCIE_P5 PCH_RTCRST# <34>
Card Reader ---> 0_0402_5% 2 AU7 12P_0402_50V8J
<31> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5# PCH_RTCRST#
+3.3V_RUN RC190 2 1 10K_0402_5% RC57 1 2 20K_0402_5%
CC25 1 2 1U_0402_6.3V6K
1 2 +3.3V_ALW_DSW
1 2 8/21 can change to 10K for merge to RP
PCH_PLTRST# @ RC62 1 2 0_0402_5%
PLTRST_LAN# <30> PCH_BATLOW# 1 2
+3.3V_LAN @ RC244 1 2 0_0402_5% SHORT PADS~D RC72 8.2K_0402_5%
PCH_PLTRST#_EC <35> @ CMOS1 AC_PRESENT 1 2
@ RC406 1 2 0_0402_5% RC243 10K_0402_5%
PLTRST_GPU# <48> CMOS1 must take care short & touch risk on layout placement
2 1 LAN_WAKE# +3.3V_ALW_PCH +RTC_CELL
@ RL70 10K_0402_5%
PCH_PLTRST# 1 2
+3.3V_ALW_DSW PLTRST_TPM# <36> 1 2
@ RC60 0_0402_5% INTRUDER#
5
C C
RC69 1M_0402_5%
1 PCH_PLTRST#_AND 1 2
P
2 1 B 4 PCH_PLTRST#_AND @ RC325 0_0402_5% +3.3V_ALW_PCH
2 O PCH_PLTRST#_AND <31,32,37,40>
RC323 10K_0402_5%
A
1
UC7 MPHYP_PWR_EN 1 2
2 1 PCH_PCIE_WAKE# TC7SH08FU_SSOP5~D @ RC65 @ RC387 10K_0402_5%
3
RC67 1K_0402_5% 100K_0402_5% VRALERT# 1 2
@ RC73 10K_0402_5%
1 2
2
+1.0V_VCCST @ RC344 10K_0402_5%
2 1 VCCST_PWRGD +3.3V_ALW
RC71 1K_0402_5%
SIO_SLP_LAN# 1 2
+3.3V_ALW_PCH @ RC68 10K_0402_5%
2 1 ME_SUS_PWR_ACK
@ RC74 10K_0402_5% SUSCLK 1 2
10/6 depop, prevent singal step. @ RC48 1K_0402_5%
2
@ RC411 10K_0402_5% UC1K CPU@ SKL-U
SYSTEM POWER MANAGEMENT

AT11 SIO_SLP_S0#
GPP_B12/SLP_S0# SIO_SLP_S0# <17,36,61>
AP15
PCH_PLTRST# GPD4/SLP_S3# SIO_SLP_S3# <34,35>
AN10 BA16
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,34,59,62>
PCH_RSMRST#_ANDAY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <34>
<14,45> PCH_RSMRST#_AND RSMRST# AN15 JAPS1
H_CPUPWRGD_R @ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <17,34,47,60,61,62> 1
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <34,47> +3.3V_ALW_PCH 1
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU
B65 BB17 SIO_SLP_S3# 2
<14,34,35> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_WLAN# <34,47> 2
AN16 +3.3V_ALW 3
B6 GPD6/SLP_A# SIO_SLP_A# <34> SIO_SLP_S5# 4 3
<14,34> SYS_PWROK SYS_PWROK SIO_SLP_S4# 4
BA20 BA15 5
<63> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,34> SIO_SLP_A# 6 5
H_CPUPWRGD VCCST_PWRGD <35> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT PCH_BATLOW# AC_PRESENT <34> 6
AU13 +3.3V_ALW 7
AR13 GPD0/BATLOW# 8 7
<34> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK PCH_RTCRST# 8
100P_0402_50V8J
ESD@ CC300
100P_0402_50V8J
ESD@ CC301
B AP11 9 B
<34> SUSACK# GPP_A15/SUSACK# AU11 10 9
PME#
GPP_A11/PME# PAD~D @ T115 10
1
BB15 AP16 INTRUDER# 11

<34,35> PCH_PCIE_WAKE# WAKE# INTRUDER# <35,46> POWER_SW#_MB 11
AM15 12
<30,34> LAN_WAKE# GPD2/LAN_WAKE# MPHYP_PWR_EN SYS_RESET# 12
AW17 AM10 13
2
<30> PM_LANPHY_ENABLE AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 14 13

<29> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# SIO_SLP_S0# 14
15
connect to VCCMPHYGTAON_1P0 enable pin 16 15
2 1 SKL-U_BGA1356 11 OF 20 17 16
RC311 10K_0402_5% SYS_RESET# 18 17
ESD Request:place near CPU side 19 18
GND
0.1U_0402_25V6
@ESD@
20
GND
1
CONN@
1 2 +3.3V_RUN ACES_50506-01841-P01
RC215 @ RC290 0_0402_5%
CC302
10K_0402_5%
POP NO Support Deep sleep 2
RC291 @
DE-POP Support Deep sleep +3.3V_RUN
XDP_DBRESET#
PCH_DPWROK 1 2 PCH_RSMRST#_AND <14> XDP_DBRESET#
5
@ RC215 0_0402_5% ESD Request:place near CPU side

1
+3.3V_RUN 1
P
B
1
SYS_RESET#_R 1 SYS_RESET#
0.01UF_0402_25V7K
100K_0402_1%
1 4 2
@ RC75 2 1 ME_RESET# 2 O RC224 1K_0402_5%
A
G
CC266
RC220
10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

2 1 74AHC1G09GW_TSSOP5
3
2 @ RC227 8.2K_0402_5%
2
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (6/14)
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCSTG
PCH_JTAG_TDI 1 2
RC81 51_0402_5%
PCH_JTAG_TDO 1 2
RC82 100_0402_5%
PCH_JTAG_TMS 1 2
UC1D CPU@ SKL-U RC130 51_0402_5%
CPU_XDP_TCLK 2 1 XDP_JTAGX
H_CATERR# D63 0_0402_5% RC328 @
A54 CATERR#
D <34> PECI_EC 1 2 H_PROCHOT#_R C65 PECI D
<34,63,66> H_PROCHOT# PROCHOT# JTA G
RC84 499_0402_1% H_THERMTRIP# C63
<20,21,35> H_THERMTRIP# A65 THERMTRIP# B61 CPU_XDP_TCLK
SKTOCC# PROC_TCK D60 CPU_XDP_TDI CPU_XDP_TCLK <14>
CPU MISC PROC_TDI CPU_XDP_TDI <14>
C55 A61 CPU_XDP_TDO
<14> XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
<14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 CPU_XDP_TRST# CPU_XDP_TMS <14>
T10 @ PAD~D XDP_OBS3_R BPM#[2] PROC_TRST# CPU_XDP_TRST# <14>
C56 1 2
T11 @ PAD~D BPM#[3] PCH_JTAG_TCK
B56 @ RC86 51_0402_5%
+1.0V_VCCST A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
<34> SIO_EXT_SMI# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
2 1 H_CATERR# <29> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
<34,45> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
@ RC79 49.9_0402_1%
2 1 H_THERMTRIP# <29> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_JTAGX 1 2
CPU_POPIRCOMP AT16 JTAGX +1.0V_VCCSTG
RC80 1K_0402_5% @ RC87 1K_0402_5%
PCH_POPIRCOMP AU16 PROC_POPIRCOMP
+1.0V_VCCSTG EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
2 1 H_PROCHOT# OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC83 1K_0402_5%
RC88
RC89
RC90
RC91
Service Mode Switch:
+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and
2
allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FP.T
2 1 TOUCHPAD_INTR#
RC414 10K_0402_5% +3.3V_ALW_PCH
2 1 CAM_MIC_CBL_DET#
RC413 10K_0402_5% ME_FW_EC 1 2 ME_FWP
2 1 CONTACTLESS_DET# @ RC221 0_0402_5%
2
RC278 10K_0402_5% PT,ST pop RC222 and SW1; MP pop RC221
2 1 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# don't move to RPC, @ RC222
C @ RC272 10K_0402_5% 1K_0402_5% C
2 1 AUD_PWR_EN
RC279 10K_0402_5%
1
2 1 IR_CAM_DET# @SW1
RC345 100K_0402_5% 1
<34> ME_FW_EC
2 1 HOST_SD_WP# 2 A
RC292 10K_0402_5% ME_FWP 3 B
2 1 FFS_INT2 4 C
RC404 10K_0402_5% 5 G1
G2
SS3-CMFTQR9_3P
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD.
2 1 SIO_EXT_SMI# (suspend power rail)
David_xie
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
2 1
RC288
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
<33> HDA_SYNC_R 1 2 33_0402_5% HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93
<33> HDA_BIT_CLK_R 1 2 33_0402_5% HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 SDIO/SDXC
<33> HDA_SDOUT_R ME_FWP RC223 1 2 1K_0402_5% BA21 HDA_SDO/I2S0_TXD
<33> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 GC6_EVENT# CAM_MIC_CBL_DET# <29>
RC95
<33> HDA_RST#_R FFS_INT2 J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 GC6_EVENT# <48>
<41> FFS_INT2 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 GPU_GC6_FB_EN
AY20 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET# GPU_GC6_FB_EN <48,52>
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 CONTACTLESS_DET# <37>
AK7 GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <31>
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 AUD_PWR_EN <33>
1 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
B RF@ CC27 AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
47P_0402_50V8J GPP_A16/SD_1P8_SEL
2
IR_CAM_DET# H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
<29> IR_CAM_DET# D7 GPP_D19/DMIC_CLK0 SD_RCOMP
<39,41> HDD_DET# GPP_D20/DMIC_DATA0
Close to RC93
KB_DET# D8 AF13
<45> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
<35,52,68> DGPU_PWROK GPP_D18/DMIC_DATA1
AW5
<33> SPKR GPP_B14/SPKR
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP# H_PROCHOT#
0.1U_0402_25V6
@ESD@ CC303
0.1U_0402_25V6
@ESD@ CC304
0.1U_0402_25V6
@ESD@ CC305
0.1U_0402_25V6
@ESD@ CC312
0.1U_0402_25V6
@ESD@ CC310
1
1
RF Request. Place near CPU side (Intel MOW)
2
HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_ALW_PCH +3.3V_ALW_PCH
2 1 SPKR 2 1 HDA_SDOUT
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.

@RF@ CC331
@RF@ CC332
@RF@ CC333
2 2 2
A TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
1.0
5 4 3 2 1
5 4 3 2 1
<14> CFG[0..19]
D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S CPU@ SKL-U
UC1T CPU@ SKL-U
RESERVED SIGNALS-1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6 E3
@ RC112 10K_0402_1% close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1% CFG4
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 C7 RSVD_AW48 RSVD_B11 A11
CFG5
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_C7 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
CFG8 F71 H11 F52
HIGH(DEFAULT) No stall(Normal Operat i on) CFG9 G69 CFG[8] 1 RSVD_H11 RSVD_F52
LOW stall CFG[9]
CC222
CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG12 H70 CFG[11] TP6 PAD~D @ T129 2 SKL-U_BGA1356 20 OF 20
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
RC109 1K_0402_5% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
F65 AW71
ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
B VSS_G65 RSVD_TP_AW70 PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
@ RC120 100K_0402_5%
For Skylake , RC120 depop

SKL-U_BGA1356 19 OF 20 For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
PROC_SELECT#:This pin is for compatibility

with future platforms. It should be unconnected
for KBL
A A
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
1 2 +1.0V_PRIM_XDP CXDP@
@ RC216 0_0603_1% CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
0_0402_5% +1.0V_PRIM_XDP
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 CC30
1 2 2 1
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17 UC8
CPU_XDP_PRDY# 5 OBSFN_A0 OBSFN_C0
0.1U_0201_10V6K
0.1U_0201_10V6K
6 CFG16 0.1U_0201_10V6K
<10> CPU_XDP_PRDY# OBSFN_A1 OBSFN_C1
@ CC28
@ CC29
1 1 7 8 14
CFG0 9 GND2 GND3 10 CFG8 VCC
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 OBSDATA_A1 OBSDATA_C1 14 1A 1B
D 2 2 CFG2 15 GND4 GND5 16 CFG10 D
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 1
19 OBSDATA_A3 OBSDATA_C3 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 GND6 GND7 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R XDP_OBS1 23 OBSFN_B0 OBSFN_D0 2A 2B
CXDP@ RC240 1 2 0_0402_5% 24 CFG18
<12> XDP_OBS1_R 25 OBSFN_B1 OBSFN_D1 26
Place near CFG4 27 GND8 GND9 28 CFG12 4
JXDP1 CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13 2OE
RC5 need to close to JCPU1 31 OBSDATA_B1 OBSDATA_D1 32 XDP_TMS 9 8 CPU_XDP_TMS <12>
CFG6 33 GND10 GND11 34 CFG14 3A 3B
@ RC123 1 2 1K_0402_5% CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
<11,34,35> VCCST_PWRGD 37 OBSDATA_B3 OBSDATA_D3 38 10
<11,45> PCH_RSMRST#_AND CXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 GND12 GND13 40 3OE
41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,34> SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 43 44
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD 46 ITP_PMODE
RESET_OUT#_R 47 HOOK2 RESET#/HOOK6 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 48 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 HOOK3 DBR#/HOOK7 <34> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5% 50
<11,34> SYS_PWROK 51 GND14 GND15 52 TDO_XDP 15
<8,20,21,41> DDR_XDP_WAN_SMBDAT 53 SDA TD0 54 TRST#_XDP GND PAD
<8,20,21,41> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 TCK1 TDI 58 XDP_TMS
<12> CPU_XDP_TCLK TCK0 TMS 74CBTLV3126BQ_DHVQFN14_2P5X3
59 60
GND16 GND17 PCH_SPI_DO2_XDP <8>
SAMTE_BSH-030-01-L-D-A CONN@
+1.0V_VCCSTG
+1.0VS_VCCIO +3.3V_ALW_PCH
CPU_XDP_TMS 1 2
1.5K_0402_5%
FIVR_EN_R
CXDP@ RC133
2 1 RC131 51_0402_5%
2
C RC132 150_0402_5% +3.3V_ALW_DSW CPU_XDP_TDI 1 2 C
+1.0V_VCCST RC134 51_0402_5%
1.5K_0402_5%
CPU_XDP_TDO 1 2
2
FIVR_EN
@ RC241
2 1 RC135 100_0402_5%
@ RC218 150_0402_5%
1
2 1 FIVR_EN CPU_XDP_TRST# 1 2
@ RC219 10K_0402_5% PCH_SPI_DO_XDP @ RC136 51_0402_5%
Place near JXDP1.48
1
CPU_XDP_TCLK 1 2
RESET_OUT#_R XDP_DBRESET# SIO_PWRBTN# RC139 51_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
CXDP@ CC32
0.1U_0402_25V6
1
@ CC33
CC269
@
1
+3.3V_RUN Place near JXDP1.41
2
XDP_TMS 1 2
2
PCH_JTAG_TMS <12>
2
2 1 XDP_DBRESET# TDI_XDP 1 2
@ RC229
PCH_JTAG_TDI <12>
RC137 3K_0402_5% 0_0402_5%
+1.0V_PRIM_XDP TDO_XDP 1 2
@ RC230 PCH_JTAG_TDO <12>
0_0402_5%
2 1 CPU_XDP_PREQ# Place near JXDP1.47

@ RC138 51_0402_5%
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

B B
0.1U_0402_25V6
@ESD@ CC306
0.1U_0402_25V6
@ESD@ CC307
0.1U_0402_25V6
@ESD@ CC308
1
1
2
2
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
A A
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ SKL-U BSC(Backside cap) : Place on secondary side, underneath the package
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
100_0402_1%
VCC_AM33 VCC_K37
2
AM35 K38
RC140
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
1
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <63>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <63>
T123@ PAD~D RSVD_AK32
1
B63 H_CPU_SVIDALRT#
100_0402_1%
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK VIDSCLK <63>
RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R 1 2
+1.0V_VCCSTG
AE62 @ RC143 0_0603_5%
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
C C
RF Request
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache) VIDSCLK 1 2
@RF@ CC321 33P_0402_50V8J
Place close CPU side
B B
+1.0V_VCCST
SVID ALERT
56_0402_1%
2
RC152
CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
1
2 1 H_CPU_SVIDALRT#
<63> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
2
100_0402_1%
CAD Note: Place the PU resistors close to CPU

RC157
RC208close to CPU 300 - 1500mils

1
A VIDSOUT A
<63> VIDSOUT
1.0
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
UC1M CPU@ SKL-U
D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71 Reserve for soldering
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GTUS
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGTX for SKYLAKE-U 2+3e
L68 VCCGT VCCGTX_AL60 AM48
VCCGT VCCGTX_AM48
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%
VCCGT VCCGTX_AM56
2
N63 AM58
RC161
N64 VCCGT VCCGTX_AM58 AU58

N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
1
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<63> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<63> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
B B
RC163
2
A A
1.0
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM +VCC_SFR_OC
+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM
UZ26
@ RC231 1 2 0_0402_5% VDDQ: 8.45A 1
+1.2V_MEM 2 1 2 VIN1
CZ102 1U_0402_6.3V6K VIN2
7 6 1 2
D PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS
VCCSTG_EN
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 2 4 5
@ RZ120 0_0402_5% ON GND
1 1 1 1
CC176
CC177
CC178
CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ SKL-U 1 2
CPU POWER 3 OF 4
5
0.1U_0402_10V7K
AU23 AK28 1
P
AU28 VDDQ_AU23 VCCIO AK30 <11,34,47,60,61,62> SIO_SLP_SUS# B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,34,59,62> SIO_SLP_S4# A
G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 @ UZ34
3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M BB32 AM30

1 1 1 TC7SH08FU_SSOP5~D
VDDQ_BB32 VCCIO
CC294
CC295
CC296 BB41 AM42 +VCC_SA

+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M
A18 G28
VCCST VCCSA J22
1 VCCSA
CC297
A22 J23
VCCSTG_A22 VCCSA J27
100_0402_1%
VCCSA
2
AL23 K23
2 VCCPLL_OC VCCSA K25
RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C PSC VCCPLL_K21 VCCSA K30 C
1
VCCSA
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <61> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <61>
1U_0402_6.3V6K
1
BSC H21
VSSSA_SENSE
CC195
H20
VCCSA_SENSE
1
100_0402_1%
100_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1 1 1 1
RC166
RC167
CC252
CC253
CC250
CC251
+VCC_SFR_OC
1U_0402_6.3V6K
1 1 2
+VCC_SA 2 2 2 2
CC199
RC168 100_0402_1%
2
+1.0V_VCCST
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2P_0402_50V8C
1 VSA_SEN- <63>
CC288
RF@ CC322
VSA_SEN+ <63>
CC202
S0 S0Ix S3
2 2
2
SIO_SLP_S0# HIGH LOW LOW
SIO_SLP_S3# HIGH HIGH LOW

RF Request
AND HIGH LOW LOW
B B
+1.0V_VCCST source +1.0V_VCCSTG source

+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0603_5%
pop option with UZ19
1
+1.0V_PRIM
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1
2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW 7 6 +1.0V_VCCST_C 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,34,59,62> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A
5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V
P
<11,36,61> SIO_SLP_S0# B 4 VCCSTG_EN
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <34,35,47,61> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3
A A
@ RZ320 1 2 0_0402_5%
1.0
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil +1.0V_MPHYGT

+1.0V_PRIM
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM
+3.3V_PGPPB 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil @ RC309 0_0603_5%
+3.3V_PGPPC +3.3V_PGPPE
@ CC205
@ CC206
+1.0V_APLLEBB
CC203
CC204
1U_0402_6.3V6K
1
@ CC265
+1.0V_MPHYAON UC1O CPU@ SKL-U close UC1.T16 and <400mil
2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 2
CPU POWER 4 OF 4
@ CC207
@ CC208
1 2 @ RC310 0_0603_5%
D @ RC299 0_0603_5% AB19 Must be +1.8V 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2 +3.3V_1.8V_PGPPG
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
close UC1.AF18 and <400mil VCCPGPPC
1 2 AF18 Y15 close UC1.AD15 and <400mil
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
1U_0402_6.3V6K
@ RC300 0_0402_5% AF19 T16 1
VCCPRIM_CORE VCCPGPPE
CC326
V20 AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF +3.3V_ALW_PCH
+1.0V_DTS V21 AD15
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
1 2 AL1 V19 2
@ RC301 0_0402_5% DCPDSW_1P0 VCCPRIM_3P3_V19
+1.8V_PRIM
1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
@ CC209
+1.0V_CLK1 L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
1 2 +1.0V_MPHYGT N15 close UC1.V19 and <120mil
VCCMPHYGT_1P0_N15 +RTC_CELL 2
1U_0402_6.3V6K
@ RC302 0_0402_5% N16 AK17 1
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
VCCMPHYGT_1P0_N17
CC212
+1.0V_CLK3 P15 AK19
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1 2 1 1 1 1
@ CC210
@ RC303 0_0402_5% K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC211
CC270
CC213
L15 close UC1.BB10 and <120mil
VCCAMPHYPLL_1P0
0.1U_0201_10V6K
A14 1
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0
CC214
K19
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
1 2
@ RC304 0_0402_5% AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18 RF Request
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C @ RC234 1 2 0_0402_5% AJ19 A10 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB C
+3.3V_VCCHDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM
1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <61> 1
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC216
AN13 CORE_VID1 <61>
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1 2 AF21 1 1 1
+3.3V_ALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K
@ RC235 0_0402_5% T19

1 VCCSRAM_1P0 Take care!!! Note1 on Page 19
@ CC217
RF@ CC323
RF@ CC324
RF@ CC325
T20
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0
AJ21 2 2 2
LPC@ RC211 1 2 0_0402_5% 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
+3.3V_1.8V_ESPI VCCPRIM_1P0_AK20
+1.8V_PRIM N18
PJP4 VCCAPLLEBB
1U_0402_6.3V6K
1 2
@ESPI@ RC212 0_0402_5%
CC218
PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_PGPPB
2
1 2
@ RC305 0_0402_5%
Must be +1.8V for eSPI I/F
+3.3V_PGPPC
1 2
@ RC306 0_0402_5% +1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK2 +1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
close UC1.K15, UC1.L15 and <100mil close UC1.AK17 and <120mil
+3.3V_PGPPD
@ RC1691 2 0_0603_5% 1 2 1 2
1 2 close UC1.K15 and <120mil @ RC170 0_0402_5% @ RC171 0_0402_5%
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
@ RC307 0_0402_5% close UC1.L19 and <100mil
1 1 1 1 1 1 1
B B
@ CC219
@ CC220
@ CC221
CC223
+3.3V_PGPPE
@ CC281
@ CC264
CC224
2 2 2
close UC1.K19 and <100mil 2 2 2 2
1 2
@ RC308 0_0402_5%
8/28 schematic review
LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402) +1.0V_PRIM +1.0V_MPHYGT
+3.3V_ALW_PCH +1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM +1.0V_CLK4
+1.0V_MPHYGT source 1
PJP3
2
+3.3V_VCCHDA PAD-OPEN1x3m
LC1 1 2 BLM15GA750SN1D_2P LC2 1 2 BLM15GA750SN1D_2P 1 2

0.1U_0201_10V6K
0.1U_0201_10V6K
@ RC173 0_0402_5%
47U_0805_6.3V6M
47U_0805_6.3V6M
47P_0402_50V8J
1 1 1 1 close UC1.N20 and <100mil 1

RF@ CC215
CC313
@ CC225
CC314
@ CC226
561280_561280_KBL_UY_PDG_Rev0p9 :MPHY has defeature

2 2 2 2 2
close UC1.AJ19 and <400mil close UC1.V15 and <100mil
+3.3V_ALW +3.3V_ALW_DSW
A 1 2 A
@ RC214 0_0402_5%
22U_0603_6.3V6M
@ CC279
22U_0603_6.3V6M
@ CC280
1 1
2 2
1.0
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

CPU@ CPU@
UC1P SKL-U UC1Q SKL-U CPU@ R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS VSS VSS
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS
SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20
A A
1.0
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_A_DQS#[0..7] +1.2V_MEM +1.2V_MEM
JDIMM1
<7> DDR_A_D[0..63]
1 2
<7> DDR_A_DQS[0..7] DDR_A_D1 VSS1 VSS2 DDR_A_D4
3 4
5 DQ5 DQ4 6
<7> DDR_A_MA[0..16] DDR_A_D0 VSS3 VSS4 DDR_A_D5
7 8
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D3
Layout Note: DDR_A_D6 17 VSS8 DQ6 18
DQ7 VSS9 DDR_A_D7
D
Place near JDIMM1 DDR_A_D2
19
21 VSS10 DQ2
20
22
+1.2V_MEM
D
23 DQ3 VSS11 24 DDR_A_D9
DDR_A_D13 25 VSS12 DQ12 26
1
DQ13 VSS13 DDR_A_D8
470_0402_1%
27 28
DDR_A_D12 29 VSS14 DQ8 30
DQ9 VSS15 DDR_A_DQS#1
RD11
31 32
+1.2V_MEM 33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
2
DDR_A_D15 37 VSS17 VSS18 38 DDR_A_D10
39 DQ15 DQ14 40
DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D11 1 2 DDR_DRAMRST#
DQ10 DQ11 <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
43 44 @ RD12 0_0402_5%
47 DQ21 DQ20 48
1
@ DDR_A_D37 49 VSS23 VSS24 50 DDR_A_D36
1
1
DQ17 DQ16
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD17
+ 51 52
2
2
DDR_A_D38 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D33 +1.2V_MEM
DDR_A_D34 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D40
1
1K_0402_1%
DDR_A_D44 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D41
DDR_A_D45 VSS34 DQ24
RD15
71 72
+1.2V_MEM +2.5V_MEM DQ25 VSS35
+DDR_VREF_A_CA +DDR_VREF_CA
2
73 74 DDR_A_DQS#5
75 VSS36 DQS3_c 76 DDR_A_DQS5
DM3_n/DBI3_n DQS3_t
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
77 78 1 2
DDR_A_D42 79 VSS37 VSS38 80 DDR_A_D47 RD17 2_0402_1%
1 1 1 1
1
DQ30 DQ31
0.022U_0402_16V7K
81 82
DDR_A_D46 VSS39 VSS40 DDR_A_D43
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD18
CD19
CD20
CD21
1K_0402_1%
83 84
1
85 DQ26 DQ27 86
2
1
2 2 2 2 VSS41 VSS42
RD16
CD31
87 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
2
93 CB1/NC CB0/NC 94
2
95 VSS45 VSS46 96
1
DQS8_c DM8_n/DBI_n/NC
24.9_0402_1%
97 98
DQS8_t VSS47
RD18
99 100
C VSS48 CB6/NC C
101 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
2
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7> 1
111 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT# CD29 @
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116 0.1U_0402_25V6
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7> 2
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
Layout Note: 123 A9 A7 124
DDR_A_MA8 VDD5 VDD6 DDR_A_MA5
Place near DDR_A_MA6
125
127 A8 A5
126
128 DDR_A_MA4 JDIMM1_EVENT# 1 2
JDIMM1.258 129 A6 A4 130 @ RD14 1K_0402_5%
H_THERMTRIP# <12,21,35>
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT#
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
<7> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1
139 140
<7> DDR_A_CLK#0 CK0_c CK1_c/NF
141 142
DDR_A_PARITY 143 VDD11 VDD12 144
145 PARITY A0 146
+0.6V_DDR_VTT BA1 A10/AP
VDD13 VDD14 DDR_A_BA0
CS0_n BA0 DDR_A_BA0 <7>
WE_n/A14 RAS_n/A16
VDD15 VDD16 DDR_A_MA15
0.1U_0402_10V6K
ODT0 CAS_n/A15
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 <7> DDR_A_CS#1 CS1_n A13 +DDR_VREF_A_CA

@ CD26
1 1
1
DDR_A_ODT1 VDD17 VDD18

CD22
CD23
CD24
CD25
161 162 T50 @ PAD~D

<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC +DDR_VREF_A_CA
163 164
2 2 PAD~D @ T51 165 VDD19 VREFCA 166 DIMM1_SA2
2
2 2 167 C1, CS3_n,NC SA2 168

171 DQ37 DQ36 172
175 DQ33 DQ32 176
DDR_A_D27 183 VSS60 DQ39 184
B B
185 DQ38 VSS61 186 DDR_A_D24
DDR_A_D29 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D20
DDR_A_D21 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D16
DDR_A_D17 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#2
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN DDR_A_D19
199
201
203
VSS68
DM5_n/DBI5_n
VSS69
DQS5_c
DQS5_t
VSS70
200
202
204
DDR_A_DQS2
DDR_A_D18 +1.2V_MEM
1
205 DQ46 DQ47 206

@ RD4 @ RD6 @ RD8 DDR_A_D22 207 VSS71 VSS72 208 DDR_A_D23 UD1
1
0_0402_5% 0_0402_5% 0_0402_5% @ 209 DQ42 DQ43 210 1 5 1 2

RD10 DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D53 NC VCC @ CD32 0.1U_0201_10V6K
213 DQ52 DQ53 214 2
0_0603_5%
2
DDR_A_D49 VSS75 VSS76 DDR_A_D52 <7> DDR_VTT_CTRL A

215 216 4
DIMM1_SA0 DQ49 DQ48 Y 0.6V_DDR_VTT_ON <59>
217 218 3
2
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_DQS#6 219 VSS77 VSS78 220 GND 1 2

DIMM1_SA2 DDR_A_DQS6 DQS6_c DM6_n/DBI6_n +3.3V_RUN
0.1U_0201_10V6K
SA0 SA1 SA2 221 222 74AUP1G07GW_TSSOP5 RD19 100K_0402_5%

DQS6_t VSS79 DDR_A_D54
2.2U_0402_6.3V6M
1 1 223 224
1
DDR_A_D50 VSS80 DQ54

CD28
@ @ @ 225 226
DIMM1 0 0 0 DQ55 VSS81 DDR_A_D55
CD27
RD5 RD7 RD9 227 228

DDR_A_D51 229 VSS82 DQ50 230
DIMM2 1 0 0 0_0402_5% 0_0402_5% 0_0402_5%
2 2 231 DQ51 VSS83 232 DDR_A_D61
DDR_A_D56 233 VSS84 DQ60 234
DIMM3 0 1 0
2
235 DQ61 VSS85 236 DDR_A_D60

DDR_A_D57 237 VSS86 DQ57 238
DIMM4 1 1 0 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
243 DM7_n/DBI7_n DQS7_t 244
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,21,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_WAN_SMBDAT <8,14,21,41>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM1_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A A
LCN_DAN05-Q0406-0103
CONN@
LINK DAN05-Q0406-0103 DONE
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
<7> DDR_B_DQS#[0..7]
For DDR4
+1.2V_MEM +1.2V_MEM
<7> DDR_B_D[0..63]
JDIMM2
<7> DDR_B_DQS[0..7]
1 2
DDR_B_D1 3 VSS1 VSS2 4 DDR_B_D5
<7> DDR_B_MA[0..16] DQ5 DQ4
5 6
9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D3
Layout Note: DDR_B_D6 21 VSS10 DQ2 22
DQ3 VSS11 DDR_B_D9
D
Place near JDIMM2 DDR_B_D13
23
25 VSS12 DQ12
24
26 D
27 DQ13 VSS13 28 DDR_B_D8
DDR_B_D12 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
35 DM1_n/DBI_n DQS1_t 36
+1.2V_MEM 39 DQ15 DQ14 40
43 DQ10 DQ11 44
DQ21 DQ20
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
47 48
51 DQ17 DQ16 52
1
@ DDR_B_DQS#4 53 VSS25 VSS26 54
1
1
DDR_B_DQS4 DQS2_c DM2_n/DBI2_n
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD49
+ 55 56
57 DQS2_t VSS27 58 DDR_B_D34
DDR_B_D39 59 VSS28 DQ22 60
2
2
61 DQ23 VSS29 62 DDR_B_D35
DDR_B_D38 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D40
DDR_B_D42 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D41
DDR_B_D43 71 VSS34 DQ24 72
DQ25 VSS35
+1.2V_MEM +2.5V_MEM
73 74 DDR_B_DQS#5
DDR_B_D44 VSS37 VSS38 DDR_B_D46
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
79 80
81 DQ30 DQ31 82
1 1 1 1
1

DQ26 DQ27
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
CD50
CD51
CD52
CD53
85 86
87 VSS41 VSS42 88 JDIMM2_EVENT# 1 2
2
2 2 2 2 CB5/NC CB4/NC H_THERMTRIP# <12,20,35>

89 90 @ RD27 1K_0402_5%
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
C VSS50 CB7/NC C
105 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR_DRAMRST#_R <20>
109 110
<7> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <7>
111 112
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
<7> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <7> 1
115 116
<7> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <7>
117 118 @ CD61
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
0.1U_0402_25V6
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA1 133 A3 A2 134 JDIMM2_EVENT#
135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<7> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <7>
139 140
<7> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <7>
141 142
Layout Note: DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
<7> DDR_B_PARITY DDR_B_BA1 PARITY A0 DDR_B_MA10
Place near <7> DDR_B_BA1
145
147 BA1 A10/AP
146
148
JDIMM2.258 VDD13 VDD14
CS0_n BA0
WE_n/A14 RAS_n/A16
VDD15 VDD16
ODT0 CAS_n/A15
CS1_n A13
VDD17 VDD18
<7> DDR_B_ODT1 ODT1 C0/CS2_n/NC
+0.6V_DDR_VTT
PAD~D @ T55 165 VDD19 VREFCA 166 DIMM2_SA2 +1.2V_MEM
+DDR_VREF_B_CA 167 C1, CS3_n,NC SA2 168
1
1K_0402_1%
169 170
171 DQ37 DQ36 172
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
173 174
RD28
175 DQ33 DQ32 176
1 1
1
DDR_B_DQS#2 VSS57 VSS58 +DDR_VREF_B_CA +DDR_VREF_B_DQ

CD54
CD55
CD56
0.1U_0402_10V6K
2.2U_0402_6.3V6M
177 178
2
DDR_B_DQS2 DQS4_c DM4_n/DBI4_n
@ CD58
1 1 179 180
DQS4_t VSS59 DDR_B_D18
CD57
181 182
2
2 2 DDR_B_D23 183 VSS60 DQ39 184 1 2

185 DQ38 VSS61 186 DDR_B_D19 RD30 2_0402_1%
2 2 DDR_B_D22 VSS62 DQ35
0.022U_0402_16V7K
B 187 188 B
DQ34 VSS63 DDR_B_D28
1K_0402_1%
189 190
1
DDR_B_D24 191 VSS64 DQ45 192
1
DQ44 VSS65 DDR_B_D29
RD29
CD62
193 194
DDR_B_D25 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_B_DQS#3
2
2
24.9_0402_1%
203 204
1
205 DQ46 DQ47 206
+3.3V_RUN DDR_B_D27 VSS71 VSS72 DDR_B_D30
RD31
207 208
209 DQ42 DQ43 210
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D53
1
@ 213 DQ52 DQ53 214
2
RD26 DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
1
@ 217 DQ49 DQ48 218

0_0603_5%
@ RD20 RD22 @ RD24 DDR_B_DQS#6 219 VSS77 VSS78 220
0_0402_5% 0_0402_5% DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
0_0402_5%
2
+3.3V_RUN_DIMM2 223 DQS6_t VSS79 224 DDR_B_D50

DDR_B_D55 225 VSS80 DQ54 226
2
227 DQ55 VSS81 228 DDR_B_D51

DIMM2_SA0 DDR_B_D54 VSS82 DQ50
2.2U_0402_6.3V6M
0.1U_0201_10V6K
1 229 230
1
DIMM2_SA1 231 DQ51 VSS83 232 DDR_B_D61

DIMM2_SA2 DDR_B_D56 VSS84 DQ60
CD59
CD60
233 234
SA0 SA1 SA2 235 DQ61 VSS85 236 DDR_B_D60
2
1
@ @ 2 DDR_B_D57 237 VSS86 DQ57 238

DIMM1 0 0 0 RD21 @ RD23 RD25 239 DQ56 VSS87 240 DDR_B_DQS#7
0_0402_5% 241 VSS88 DQS7_c 242 DDR_B_DQS7
DIMM2 1 0 0 0_0402_5% 0_0402_5%
* DIMM3 0 1 0
2
247 DQ62 DQ63 248

DIMM4 1 1 0 251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2 SCL SDA DIMM2_SA0 DDR_XDP_WAN_SMBDAT <8,14,20,41>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM2_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A LCN_DAN05-Q0406-0103 A
CONN@
LINK DAN05-Q0406-0103 DONE
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
5 4 3 2 1
A B C D E
+3.3V_RUN
For Breckenridge 12/14/15
2 1 SW 2_DP1_AUXN
RV70 100K_0402_5%
2 1 SW 2_DP2_AUXN
RV71 100K_0402_5%
2 1 SW 2_DP3_AUXN
RV72 100K_0402_5% +3.3V_RUN
1 1
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 1 SW 2_DP1_CADET
1 1 1 Priority: Type-C -> WiGig -> VGA
1
CV80
CV81
CV82
CV83
CV84
CV85
RV73 1M_0402_5%
2 1 SW 2_DP2_CADET
RV74 1M_0402_5%
2
2 1 SW 2_DP3_CADET 2 2 2 UV7
RV75 1M_0402_5%
2 1 SW 2_DP1_AUXP 1
RV76 100K_0402_5% 10 VDD33 55
2 1 SW 2_DP2_AUXP 34 VDD33 OUT1_D0p 54 SW2_DP1_P0 <25>
RV77 100K_0402_5% VDD33 OUT1_D0n SW2_DP1_N0 <25>
2 1 SW 2_DP3_AUXP CV86 1 2 0.1U_0201_10V6K CPU_DP2_P0_C 11 52
<6> CPU_DP2_P0 IN_D0p OUT1_D1p SW2_DP1_P1 <25>
RV78 100K_0402_5% CV87 1 2 0.1U_0201_10V6K CPU_DP2_N0_C 12 51
<6> CPU_DP2_N0 IN_D0n OUT1_D1n SW2_DP1_N1 <25>
<6> CPU_DP2_P1 CV88 1 2 0.1U_0201_10V6K CPU_DP2_P1_C 14 50 -----> TYPE C

CV89 1 2 0.1U_0201_10V6K CPU_DP2_N1_C 15 IN_D1p OUT1_D2p 49 SW2_DP1_P2 <25>
+3.3V_RUN <6> CPU_DP2_N1 IN_D1n OUT1_D2n SW2_DP1_N2 <25>
CV90 1 2 0.1U_0201_10V6K CPU_DP2_P2_C 16 47
<6> CPU_DP2_P2 IN_D2p OUT1_D3p SW2_DP1_P3 <25>
CV91 1 2 0.1U_0201_10V6K CPU_DP2_N2_C 17 46
<6> CPU_DP2_N2 IN_D2n OUT1_D3n SW2_DP1_N3 <25>
CV92 1 2 0.1U_0201_10V6K CPU_DP2_P3_C 19
<6> CPU_DP2_P3 IN_D3p
CV93 1 2 0.1U_0201_10V6K CPU_DP2_N3_C 20 44
<6> CPU_DP2_N3 IN_D3n OUT2_D0p SW2_DP2_P0 <32>
2
2
RV79 @
RV81 @
RV83 @
RV87 @
RV89 @
RV91 @
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ 43
CV94 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C 64 OUT2_D0n SW2_DP2_N0 <32>
<6> CPU_DP2_AUXP IN_AUXp
RV85
RV93
RV95
CV95 1 2 0.1U_0201_10V6K CPU_DP2_AUXN_C 63 41
<6> CPU_DP2_AUXN IN_AUXn OUT2_D1p SW2_DP2_P1 <32>
40
66 OUT2_D1n SW2_DP2_N1 <32>
<6> CPU_DP2_CTRL_CLK -----> WIGIG
1
1 65 IN_DDC_SCL 39
<6> CPU_DP2_CTRL_DATA IN_DDC_SDA OUT2_D2p SW2_DP2_P2 <32>
2 38 2
PS8348B_PI0 8 OUT2_D2n SW2_DP2_N2 <32>
@ T204 PAD~D IN_CA_DET
7 36
PS8348B_PI1 <6> CPU_DP2_HPD IN_HPD OUT2_D3p 35 SW2_DP2_P3 <32>
OUT2_D3n SW2_DP2_N3 <32>
PS8348B_SW 1 PS8348B_PI0 2
PS8348B_PI1 3 PI0 / SDA_CTL 33
PS8348B_SW 0 PI1 / SCL_CTL OUT3_D0p 32 SW2_DP3_P0 <24>
PS8348B_SW 1 4 OUT3_D0n SW2_DP3_N0 <24>
PS8348B_PEQ PS8348B_SW 0 5 SW1 30
SW0 OUT3_D1p 29 SW2_DP3_P1 <24>
PS8348B_CFG OUT3_D1n SW2_DP3_N1 <24>
28 -----> VGA
PS8348B_PC1 OUT3_D2p 27
OUT3_D2n
@ T223 PAD~D
25
PS8348B_CFG 21 OUT3_D3p 24
PS8348B_PC3 CFG OUT3_D3n
PS8348B_PC1 22 62
OUT1_AUXp_SCL SW2_DP1_AUXP <25,26>
PS8348B_PC2 23 OUT1_AUXn_SDA SW2_DP1_AUXN <25,26>
PC2 60 SW2_DP2_AUXP <32>
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
OUT2_AUXp_SCL
1
PS8348B_PC3 45 59
PC3 OUT2_AUXn_SDA SW2_DP2_AUXN <32>
@ RV80
@ RV82
@ RV84
@ RV86
RV88
@ RV90
@ RV92
RV94
RV96
58
OUT3_AUXp_SCL 57 SW2_DP3_AUXP <24>
@ @ PS8348B_PEQ 18 OUT3_AUXn_SDA SW2_DP3_AUXN <24>
2
PEQ 48 SW 2_DP1_CADET
13 OUT1_CA_DET 53
3 @ T224 PAD~D PD OUT1_HPD SW2_DP1_HPD <25,26> 3
37 SW 2_DP2_CADET
OUT2_CA_DET 42
OUT2_HPD SW2_DP2_HPD <32>
26 SW 2_DP3_CADET
9 OUT3_CA_DET 31
REXT OUT3_HPD SW2_DP3_HPD <24>
4.99K_0402_1%
1
2.2U_0402_6.3V6M
67 56
PAD(GND) CEXT
RV97
Internally t i ed t o VDD33/ 2, 3. 3V I / O; 1
CV96
PI0:Automat i c E Q di sabl e, I nt er nal pull do wn ~150K oh m
, 3. 3V I / O PS8348BQFN66GTR-A0_QFN66_5X10
PCx =
M:Portx output conf i gur at i on i s set byl i nk t raini gn PI0 = L: Automat i c E Q enabl e( def ault)
2
H: Automat i c E Q di sabl e 2
(default)
H:Portx output with f i xed 800 mV and 0dB
L:Portx output with f i xed 400 mV and 0dB
x=1, 2, 3
Internally pull down ~150K.3.3V I/O

For Control Switching Mode (CFG = L): Internally t i ed t o VDD33/ 2, 3. 3V I / O
[SW1,SW0 ]= [L,L], Port1 is selected (default) PEQ =
[SW1,SW0 ]= [L,H], Port2 is selected M:default, LEQ, compensate channel loss up to 11.5dB @ HBR2
[SW1,SW0 ]= [H,L], Port3 is selected H:HEQ, compensate channel loss up to 14.5dB @ HBR2
[SW1,SW0 ]= [H,H], Port3 is selected L:LLEQ, compensate channel loss up to 8.5dB @ HBR2
4 4
For Automat i c S witchi ng Mode ( CF G0= H):
[SW1,SW0 ]= [L,L], Port1 >Port2 >Port3 (default)
[SW1,SW0 ]= [L,H], Port1 >Port3 >Port2 DELL CONFIDENTIAL/PROPRIETARY
[SW1,SW0 ]= [H,L], Port3 >Port2 >Port1
[SW1,SW0 ]= [H,H], Port3 >Port1 >Port2 Compal Electronics, Inc.
[SW1,SW0 ]= [L,M], Port2 >Port1 >Port3 Title
[SW1,SW0 ]= [M,M], Port2 >Port3 >Port1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW2 PS8348B
LA-E082P
A B C D E
5 4 3 +5V_RUN 2 1
For 1.65G HDMI from CPU
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
1
CV41
EMI@ RV24 1 2 5.6_0402_5%
GND
OUT
HDMI_L_TX_P2 @
@EMI@ LV3
CV40
D D
2
2
1 2 HDMI_TX_P2 1 4 EMI@ 2
<6> CPU_DP1_P0
3
CV31 0.1U_0402_25V6 1 4 RV26
<6> CPU_DP1_N0
1 2 HDMI_TX_N2 2
2 3
3
200_0402_5% HDMI connector
CV32 0.1U_0402_25V6
1
HCM1012GH900BP_4P HDMI_L_TX_N2
1 2
EMI@ RV25 5.6_0402_5% JHDMI1 CONN@
HDMI_HPD 19
HP_DET
EMI@ RV27 1 2 5.6_0402_5% 18
HDMI_L_TX_P1 17 +5V
@EMI@ LV6 +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
SDA
2
1 2 HDMI_TX_P1 1 4 EMI@ HDMI_CTRL_CLK 15
<6> CPU_DP1_P1 1 4 SCL
CV33 0.1U_0402_25V6 RV29 14
2 1 HDMI_CEC 13 Reserved
200_0402_5% CEC
1 2 HDMI_TX_N1 2 3 10K_0402_5% @ RV19 HDMI_L_CLKN 12 20
<6> CPU_DP1_N1 2 3 CK- GND
CV34 0.1U_0402_25V6 11 21
1
HCM1012GH900BP_4P HDMI_L_TX_N1 HDMI_L_CLKP 10 CK_shield GND 22
1 2 HDMI_L_TX_N0 9 CK+ GND 23
EMI@ 5.6_0402_5% 8 D0- GND
RV28
HDMI_L_TX_P0 7 D0_shield
EMI@ RV30 1 2 5.6_0402_5% HDMI_L_TX_N1 6 D0+
HDMI_L_TX_P0 5 D1-
@EMI@ LV9 HDMI_L_TX_P1 4 D1_shield
D1+
2
1 2 HDMI_TX_P0 1 4 EMI@ HDMI_L_TX_N2 3
<6> CPU_DP1_P2 1 4 D2-
CV35 0.1U_0402_25V6 RV32 2
HDMI_L_TX_P2 1 D2_shield
200_0402_5% D2+
1 2 HDMI_TX_N0 2 3
<6> CPU_DP1_N2 2 3
CV36 0.1U_0402_25V6 CONCR_099BKAC19YBLCNF
1
HCM1012GH900BP_4P HDMI_L_TX_N0
1 2
EMI@ RV31 5.6_0402_5%
EMI@ LINK 099BKAC19YBLCNF DONE
RV33 1 2 5.6_0402_5%
HDMI_L_CLKP
HDMI_TX_P2 HDMI_OB
C @EMI@ LV12 RV10 1 2 470_0402_1%
C
2
2 1 HDMI_CLKP 1 4 EMI@ HDMI_TX_N2 RV11 1 2 470_0402_1%
<6> CPU_DP1_P3 0.1U_0402_25V6 1 4 HDMI_TX_P1
RV35 RV12 1 2 470_0402_1%
CV37 HDMI_TX_N1 RV13 1 2 470_0402_1%
200_0402_5%
2 1 HDMI_CLKN 2 3 HDMI_TX_P0 RV14 1 2 470_0402_1%
<6> CPU_DP1_N3 0.1U_0402_25V6 2 3 HDMI_TX_N0 1 2
CV38 RV15 470_0402_1%
1
HCM1012GH900BP_4P HDMI_L_CLKN HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
1 2
EMI@ RV34 5.6_0402_5%
1
D
RV18 1 2 10K_0402_5% 2 QV4
+3.3V_RUN
G L2N7002WT1G_SC-70-3
3
1M_0402_5%
2
RV20
2
G
1
3 1 HDMI_HPD 1 2
<6> CPU_DP1_HPD RV21 20K_0402_5%
S
QV5
L2N7002WT1G_SC-70-3
B B
+3.3V_RUN
QV3A +VHDMI_VCC
2
DMN65D8LDW-7_SOT363-6
1 6 HDMI_CTRL_CLK 1 2
<6> CPU_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
4 3 HDMI_CTRL_DATA 1 2
<6> CPU_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
5 4 3 2 1
5 4 3 2 1
For Breckenridge 12/14/15

For Realtek Solution
+3.3V_RUN +3.3V_RUN Place near UV6.4 Place near UV6.25 Place near UV6.26
+3.3V_RUN
+VCCK_12
60ohm/1A UV6 60ohm/1A
+3.3V_VGA +VDD_DAC_33
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_16V6K
+3.3V_RUN 1 2 1 20 2 1
+VCCK_12 AVC33 VDD_DAC_33 1 1 1
0.1U_0402_25V6
CV103
CV104
CV105
0.1U_0402_25V6
LV14 BLM15PX600SN1D_2P 4 BLM15PX600SN1D_2P LV30 1
D 14 AVCC_12 25 +VCCK_12 D
VCC_33 VCCK_12 1
CV100
CV106
2 1 ISPSCL 0.1U_0402_10V7K 1 2 CV111 SW2_DP3_AUXP_C 2 26 2 2 2
<22> SW2_DP3_AUXP AUX_P PVCC_33 +3.3V_RUN
@ RV106 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV112 SW2_DP3_AUXN_C 3 +CRT_VCC 2
2 1 ISPSDA <22> SW2_DP3_AUXN AUX_N 2
@ RV107 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV107 SW2_DP3_P0_C 5 17
<22> SW2_DP3_P0 SW2_DP3_N0_C LANE0_P HVSYNC_PWR VSYNC_CRT
0.1U_0402_10V7K 1 2 CV108 6 18
<22> SW2_DP3_N0 SW2_DP3_P1_C LANE0_N VSYNC HSYNC_CRT
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_10V7K 1 2 CV109 7 19
<22> SW2_DP3_P1 SW2_DP3_N1_C LANE1_P HSYNC
0.1U_0402_10V7K 1 2 CV110 8 1 1
<22> SW2_DP3_N1 LANE1_N
CV101
CV102
RV102
2 1 SW2_DP3_HPD
100K_0402_5% +3.3V_RUN
RV123
RV124
1
1
2 4.7K_0402_5%
2 4.7K_0402_5%
10
9 POL1/SPI_CEB
POL2
RTD2166 BLUE_P
21
22
BLUE_CRT
GREEN_CRT 2 2
11 GREEN_P
12 GPI1/SPI_CLK 23 RED_CRT
13 GPI2/SPI_SI RED_P
GPI3/SPI_SO
CLK_DDC2_CRT 15
DAT_DDC2_CRT 16 VGA_SCL
VGA_SDA 27
ISPSCL 30 LDO_RSTB 28
ISPSDA 29 SMB_SCL EXT_CLK_IN 31
SMB_SDA EXT1.2V_CTRL
SW2_DP3_HPD 32 24
<22> SW2_DP3_HPD HPD GND 33
EPAD_GND
RTD2166-CG_QFN32_4X4
C C
Operation Mode Table

POL1(P10)
0 1
0 X X
POL2
(P9) 1 ROM EEPROM
3
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
@ESD@ DV5
@ESD@ DV6
1
UV4
IN
AP2330W-7_SC59-3
GND
OUT
RED_CRT 1 2
EMI@ LV16 BLM15BB470SN1D_2P
3
B GREEN_CRT 1 2 +CRT_VCC B
BLUE_CRT 1 2
40mils
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1 1
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1
1 1 1 CV134
RV116
RV117
RV118
CV129
CV130
CV131
1U_0402_6.3V6K
2 JCRT1
2 2 2
CV126
CV127
CV128
@ @ @ 6
2
2
2 2 2 @ T87 PAD~D JCRT-11 11
RED 1
7
12
+CRT_VCC GREEN 2
8
HSYNC_CONN 13
BLUE 3
9
2
2.2K_0402_5%
2.2K_0402_5%
VSYNC_CONN 14
1K_0402_5%
1K_0402_5%
M_ID2# 4 G 16
RV119
RV120
RV121
RV122
10 G 17
15
5
@ @
1
1
DAT_DDC2_CRT
0.1U_0402_16V4Z
1 CCM_C070546HR015M29CZR
CLK_DDC2_CRT
CV135
CONN@
HSYNC_CRT 1 2
2
L
i
n
k
C
0
7
0
5
4
6
H
R
0
1
5
M
2
9
C
Z
R
d
o
n
e
EMI@ LV19 BLM15AG121SN1D_L0402_2P
VSYNC_CRT 1 2
EMI@ LV20 BLM15AG121SN1D_L0402_2P
22P_0402_50V8J
22P_0402_50V8J
A A
1 1
CV132
CV133
2 2 DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP to VGA & VGA Conn
1.0
LA-E082P
vinafix.com
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_UT9 +3.3V_CPS
For NON-AR port1

1 2
LT11 BLM15PX600SN1D_2P
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
TUSB546: Pop RT246,Depop CT122
1 1 1 1 PS8740:Depop RT246,Pop CT122
CT118
CT119
CT120
CT121
+3.3V_RUN_UT9
CT117
2 1
2.2U_0402_6.3V6M @ CT122
2
2 2 2 2
UT9
2
+3.3V_CPS_R1 MUX1_USB_EQ1
1K_0402_5%
@ RT145
D 1 2 1 35 D
@ RT246 0_0402_5% 6 VCC EQ1 38 MUX1_USB_EQ0
20 VCC EQ0
28 VCC 17 MUX1_I2C_EN
VCC I2C_EN
+3.3V_RUN_UT9
1
+3.3V_RUN 2 MUX1_DPEQ1
1 2 SW2_DP1_P0_C 9 DPEQ1 14 MUX1_DPEQ0 MUX1_I2C_EN
<22> SW2_DP1_P0 SW2_DP1_N0_C DP0p DPEQ0/A1
CT103 1 2 0.1U_0402_25V6 10
<22> SW2_DP1_N0 DP0n MUX1_SSEQ1
20K_0402_5%
1 2 CT104 0.1U_0402_25V6 3
1K_0402_5%
SSEQ1
1
SW2_DP1_P1_C MUX1_SSEQ0
@ RT301
1 2 12 11
@ RT397 0_0603_5% <22> SW2_DP1_P1 SW2_DP1_N1_C DP1p SSEQ0/A0
CT105 1 2 0.1U_0402_25V6 13
RT300
<22> SW2_DP1_N1 DP1n
CT106 0.1U_0402_25V6
1 2 SW2_DP1_P2_C 15 21 MUX1_FLIP_SEL
+3.3V_VDD_PIC <22> SW2_DP1_P2 SW2_DP1_N2_C DP2p FLIP/SCL MUX1_FLIP_SEL <26>
CT107 1 2 0.1U_0402_25V6 16
2
<22> SW2_DP1_N2 DP2n 22 MUX1_USB_SEL
CT108 0.1U_0402_25V6
1 2 SW2_DP1_P3_C 18 CTL0/SDA MUX1_USB_SEL <26>
1 2 <22> SW2_DP1_P3
CT109 1 2 0.1U_0402_25V6 SW2_DP1_N3_C 19 DP3p 23 MUX1_DP_SEL
0_0603_5% @ RT398 <22> SW2_DP1_N3 DP3n CTL1 MUX1_DP_SEL <26>
CT110 0.1U_0402_25V6
31 34 I2C Programming or Pin Strap Programming Select,Internally

<28> TBTA_RX1N 30 RX1n TX1n 33 TBTA_TX1N <28> 30k pull-up and 60k pull-down
<28> TBTA_RX1P RX1p TX1p TBTA_TX1P <28> I2C_EN =
39 37 0: Tie 1k to GND,Pin Strap(I2C disable)
<28> TBTA_RX2N 40 RX2n TX2p 36 TBTA_TX2P <28> R:Tie 20k to GND,TI Test Mode(I2C enabled)
<28> TBTA_RX2P RX2p TX2n TBTA_TX2N <28> F: Float,TI Test Mode(I2C enabled)
1:Tie 1k to VCC,I2C enabled
1 2 USB3_PTX_C_DRX_P6 8 5 USB3_PRX_C_DTX_P6 2 1
<10> USB3_PTX_DRX_P6 2 0.1U_0402_25V6 USB3_PTX_C_DRX_N6 SSTXp SSRXp USB3_PRX_C_DTX_N6 USB3_PRX_DTX_P6 <10>
CT113 1 7 4 CT111 2 1 0.1U_0402_25V6
<10> USB3_PTX_DRX_N6 SSTXn SSRXn USB3_PRX_DTX_N6 <10>
CT114 0.1U_0402_25V6 CT112 0.1U_0402_25V6
+3.3V_RUN_UT9
AUX1_SNOOP_EN#29 27 TUSB546A_SBU1_R 1 2
SNK_CAD/DCI_DAT SBU1 TUSB546A_SBU2_R TBTA_SBU1 <26,28>
1 2 32 26 @ RT132 1 2 0_0402_5%
C <22,26> SW2_DP1_HPD HPDIN/DCI_CLK SBU2 TBTA_SBU2 <26,28> C
@ RT380 0_0402_5% @ RT133 0_0402_5%
2 1 AUX1_SNOOP_EN# for pin control , connect to PD GPIO 24 SW2_DP1_AUXP_C 2 1
41 AUXp 25 SW2_DP1_AUXN_C 2 1 SW2_DP1_AUXP <22,26>
RT308 4.7K_0402_5% Check I2C or Pin control @ CT115 0.1U_0402_25V6
PAD AUXn SW2_DP1_AUXN <22,26>
@ CT116 0.1U_0402_25V6
TUSB546_QFN40_4X6
+3.3V_RUN_UT9
+3.3V_RUN_UT9 SW2_DP1_AUXN_C 1 2
+3.3V_RUN_UT9 +3.3V_RUN_UT9 100K_0402_5% RT131
2
SW2_DP1_AUXP_C 1
1K_0402_5%
@ RT143
2
2
2
1K_0402_5%
@ RT137
1K_0402_5%
@ RT247
100K_0402_5% RT130
1
1
MUX1_USB_EQ0
MUX1_SSEQ0 MUX1_DPEQ1
20K_0402_5%
1
1
1K_0402_5%
@ RT304
20K_0402_5%
20K_0402_5%
1
1
1K_0402_5%
@ RT302
1K_0402_5%
@ RT303
RT144
RT138
RT248
2
B B
2
Ser the USB receiver equalizer gain for upstream facing Select the DisplayPort receiver equalizer gain ,Internally Ser the USB receiver equalizer gain for downstream facing
SSTXP/N,Internally 30k pull-up and 60k pull-down 30k pull-up and 60k pull-down RX1 and RX2 when USB utilized,Internally 30k pull-up and
SSEQ = DPEQ = 60k pull-down
0: Tie 1k to GND 0: Tie 1k to GND USB_EQ =
R:Tie 20k to GND R:Tie 20k to GND 0: Tie 1k to GND
F: Float F: Float R:Tie 20k to GND
1:Tie 1k to VCC 1:Tie 1k to VCC F: Float
1:Tie 1k to VCC
+3.3V_RUN_UT9 +3.3V_RUN_UT9 +3.3V_RUN_UT9

1K_0402_5%
1K_0402_5%
@
2
2
1K_0402_5%
RT141
@ RT135
@ RT139
1
MUX1_SSEQ1 MUX1_DPEQ0 MUX1_USB_EQ1

20K_0402_5%
20K_0402_5%
20K_0402_5%
1
1
1K_0402_5%
@ RT305
1K_0402_5%
@ RT306
1K_0402_5%
@ RT307
@
RT136
RT142
A A
RT140
2
PROPRIETARY NOTE: Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP/USB3 Repeater SW TUSB546
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_VDD_PIC
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
For NON-AR port1
2
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
.1U_0402_16V7K
1
1
RT50
CT70
RT51
RT52
RT53
1
1 6 UPD1_SMBCLK_Q
<34> UPD1_SMBCLK
@ QT1A
2 DMN66D0LDW-7_SOT363-6
2
2
@ RT58 1 2 0_0402_5%
UT6
5
8 1 TBTA_ROM_CS#_PD_R
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD 4 3 UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <34> UPD1_SMBDAT
5 4
DI(IO0) GND @ QT1B
W25Q80DVSSIG_SO8 DMN66D0LDW-7_SOT363-6
@ RT59 1 2 0_0402_5%
D D
TBTA_ROM_CLK_PD_R 0_0402_5% 2 1 RT54 @ TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R 0_0402_5% 2 1 RT55 @ TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R 0_0402_5% 2 1 RT56 @ TBTA_ROM_DO_PD @ RT60 1 2 0_0402_5% UPD1_SMBUS_ALERT#
TBTA_ROM_CS#_PD_R TBTA_ROM_CS#_PD <34> UPD1_ALERT#
0_0402_5% 2 1 RT57 @
+3.3V_TBTA_FLASH
JDB1
1
1 2 TBTA_ROM_CLK_PD_R
2 3 TBTA_ROM_DI_PD_R
3 4 TBTA_ROM_DO_PD_R
7 4 5 TBTA_ROM_CS#_PD_R
8 GND 5 6 +5V_ALW
GND 6
PJP8 TI is 1x47uf+1x0.1uf
JXT_FP241AH-006GAAM 1 2
CONN@
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PAD-OPEN 1x3m +TBTA_Vbus_1
1 1 1 1
CT75
CT76
CT77
CT78
2 2 2 2
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
+VCC1V8A_TBTA_LDO
RT65 @ 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U_0402_16V6K
2.2U_0402_16V6K
2.2U_0402_16V6K
PJP7
1 1 1
TI is 3x1uf 1 2
+5V_ALW_PDA
CT71
CT72
CT73
DIV = R2/(R1+R2) Factory Device Description PAD-OPEN1x1m
1U_0402_16V6K
C 1 C
Configuration 2 2 2
CT74
1 2
DIV_min DIV_max @ RT63 0_0402_5%
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UFP only
5V @0.9A Sink capability with "Ask for Max/" for UT5
0.00 0.08 0 anything from 0.9 -3.0A +3.3V_TBTA_FLASH +3.3V_TBTA_FLASH F1
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
TBT Alternate Modes not supported I2C_ADDR
DisplayPort Alternate Modes not supported RT378 2 1 10K_0402_5% D1
TI VID supported I2C_SDA1 +TBTA_Vbus_1
RT379 2 1 10K_0402_5% D2
2
+3.3V_TBTA_FLASH C1 I2C_SCL1
UFP only I2C_IRQ1_N TI has 1x1uf
5V @0.9A Sink capability with "Ask for Max/" for 10K_0402_1% +3.3V_ALW
0.10 0.18 1 anything from 0.9 -3.0A RT76 @ RT66 2 1 3.3K_0402_5% UPD1_SMBDAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
TBT Alternate Modes not supported @ RT67 2 1 3.3K_0402_5% UPD1_SMBCLK_Q B5 I2C_SDA2 H11
1
1
and D pin configuration PD1_GPIO8 1 10K_0402_5% UPD1_SMBUS_ALERT# B6 I2C_SCL2 VBUS
CT82
@ RT68 2 J10
1U_0603_25V6K
TI VID supported I2C_IRQ2_N VBUS J11
1U_0402_16V6K
10U_0603_6.3V6M
1 1
1
MUX1_FLIP_SEL MUX1_FLIP_SEL_R VBUS
CT83
0_0402_5% 2 1 RT69 @ B2 K11
2
<25> MUX1_FLIP_SEL EN_PD_HV_1 EN_PD_HV_1_R GPIO0 VBUS
CT84
UFP only 0_0402_5% 2 1 RT70 @ C2
5V @3.0A Source capability <67> EN_PD_HV_1 GPIO1
0.20 0.28 43K_0402_1% RT71 2 1 1M_0402_5%
TBT Alternate Modes not supported 0_0402_5% 2 1 RT72 @ AC1_DISC#_R G11 GPIO2 2 2
DisplayPort Alternate Modes not supported <66,67> AC1_DISC# SW2_DP1_HPD_R GPIO3
0_0402_5% 2 1 RT73 @ C10
2
TI VID supported <22,25> SW2_DP1_HPD @ RT74 2 1 0_0402_5% OTG_ID E10 GPIO4 H2

@ RT75 2 1 0_0402_5% PD1_GPIO6 G10 GPIO5
UFP only GPIO6
0.30 0.38 3 5V @3.0A Source capability GPIO7
TBT Alternate Modes not supported GPIO8 G1
DisplayPort Alternate Modes -Sink, C and D pin configuration
SPI_CLK
SPI_MOSI
DRP TBTA_ROM_CS#_PD B3 SPI_MISO K6
SPI_SS_N C_USB_TP TBTA_TOP_P <28>
5V @0.9-3.0A Sink capability L6
5V @3.0A Source capability C_USB_TN TBTA_TOP_N <28>
0.40 0.48 L5
TBT Alternate Modes not supported UART_MOSI <10> USB20_P9 USB_RP_P
4 2 1 K5
DisplayPort Alternate Modes not supported UART_MOSI <10> USB20_N9 USB_RP_N
RT81 100K_0402_5%
TI VID supported 2 1 UART_MISO 2 1 E2 K7
Accepts data and power role swaps, but does not UART_MISO UART_TX C_USB_BP TBTA_BOT_P <28>
initiate. @ RT82 1M_0402_5% 0_0402_5% RT83 @ F2 L7 TBTA_BOT_N <28>
UART_RX C_USB_BN
@ RT84 2 1 0_0402_5% F4
@ T219 PAD~D SWD_DATA
DRP @ T220 PAD~D @ RT85 2 1 0_0402_5% G4 TI has 2x220pf
5V @0.9-3.0A Sink capability SWD_CLK TBTA_CC1 <28>
L9
5V @3.0A Source capability C_CC1 L10
0.50 0.58 5 TBT Alternate Modes not supported C_CC2 WHEN CONNECT BUSPOWERZ TO GND,
470P_0402_50V7K
470P_0402_50V7K
B TBTA_CC2 <28> B
DisplayPort Alternate Modes - Source, C, D, and E RT86 2 1 1M_0402_5% TBTA_MRESET E11
pin configurations. MRESET
CONNECT ALSO RPD_Gn to C_CCn 1 1
TI VID supported
CT85
CT86
Accepts power role swaps but will not initiate. K9 1 2
@ RT87 1 2 0_0402_5% TBTA_LSTX_R L4 RPD_G1 K10 @ RT104 1 2 0_0402_5%
Accepts data role swap to UFP and can initiate. TBTA_LSRX_R TBT_LSTX/R2P RPD_G2
@ RT88 1 2 0_0402_5% K4 @ RT105 0_0402_5% +3.3V_TBTA_FLASH 2 2
DRP TBT_LSRX/P2R
5V @0.9-3.0A Sink capability
5V @3.0A Source capability MUX1_FLIP_SEL/MUX1_USB_SEL control by: 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%
TBT Alternate Modes not supported GPIO: Pop RT69,RT90;Depop RT375,RT376 <25> MUX1_DP_SEL MUX1_USB_SEL @ RT89 1 TBTA_DEBUG4 DIG_AUD_P/DEBUG3 DEBUG_CTL1 TBTA_DBG_CTL2
0.60 0.68 6 2 0_0402_5% K3 D5 RT107 1 2 10K_0402_5%
DisplayPort Alternate Modes - Source, C, D, and E I2C:Depop RT69,RT90;pop RT375,RT376 <25> MUX1_USB_SEL @ RT90 DIG_AUD_N/DEBUG4 DEBUG_CTL2
0_0402_5%
pin configurations.
TI VID supported MUX1_FLIP_SEL
Accepts power role swaps but will not initiate. @ RT375 1 2 0_0402_5% UPD1_SMBCLK_Q 1 2 TBTA_DEBUG1 L2
MUX1_USB_SEL @ RT376 1 2 0_0402_5% UPD1_SMBDAT_Q @ RT92 1 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1
Accepts data role swap to DFP and can initiate. DEBUG2
@ RT93 0_0402_5%
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. K8 TBTA_SBU1_R 1 2
TBTA_AUXP_C C_SBU1 TBTA_SBU1 <25,28>
CT80 1 2 0.1U_0201_10V6K J1 @ RT108 0_0402_5%
<22,25> SW2_DP1_AUXP TBTA_AUXN_C AUX_P TBTA_SBU2_R
Route in pass through manner so AUX can be snooped by 546 CT81 1 2 0.1U_0201_10V6K J2 L8 1 2
<22,25> SW2_DP1_AUXN AUX_N C_SBU2 TBTA_SBU2 <25,28>
@ RT109 0_0402_5%
F10
BUSPOWER_N F11 PDA_RESET#_R0_0402_5% 2 1 @ RT110
+3.3V_TBTA_FLASH RESET_N
HRESET
TBTA_ROSC G2
+3.3V_TBTA_FLASH R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_1%
SS
2
@
0_0402_5%
RT100
TPS65982_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
TBTA_AUXN_C
RT98
2 1
RT95 100K_0402_5%
2
1
2 1 TBTA_AUXP_C
RT96 100K_0402_5% +VCC1V8D_TBTA_LDO 1 2
100K_0402_5%
@ RT97 0_0402_5%
0_0402_5%
1
1
RT101
RT103
@ CT87
RT99
0_0402_5% 0.22U_0402_16V7K
2 @
2
2
A A
Link TPS65982D (from SA00009W200 to SA00009W210) 08/04
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
[Type C]PD Controller TI
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-E082P 1.0

5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD +3.3V_VDD_PIC

2 1
+5V_TBT_VBUS UT7
1N4148WS-7-F_SOD323-2 1 5
DT2 VCC VOUT
D 2 1 2 D
100K_0402_5%
GND
1
@
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-7-F_SOD323-2 3 4
RT393
1 1 EN ADJ/NC
2.2U_0603_25V6K
0.1U_0402_25V6K
1
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2
2 2 RT111 100K_0402_5%
2
2
1
CT90
1U_0402_10V6K
2
+TBTA_Vbus_1
UT8
place near UT7
1
VCC
1U_0603_50V6K
DT3 1
1 2+5V_TBTA_VBUS_D3
VOUT
CT94
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD [Type C]PD Power
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-E082P 1.0

5 4 3 2 1
5 4 3 2 1
For NON AR Config
D D
RF Request
+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS +TBTA_VBUS
JUSBC1
A1 B12
GND_A1 GND_B12
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1P_C A2 B11
<25> TBTA_TX1P TX1+ RX1+ TBTA_RX1P <25>
CT96 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A3 B10
<25> TBTA_TX1N TX1- RX1- TBTA_RX1N <25>
2
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 1
2 1 A4 B9 1 2 ESD@ DT4
0.47U_0201_25V CT99 VBUS_A4 VBUS_B9 CT100 0.47U_0201_25V
TBTA_CC1 TBTA_SBU2 L30ESD24VC3-2_SOT23-3
A5 B8
<26> TBTA_CC1 CC1 SBU2 TBTA_SBU2 <25,26> 2 2
1 2 TBTA_TOP_P_R A6 B7 TBTA_BOT_N_R 1 2
<26> TBTA_TOP_P @EMI@ RT120 TBTA_TOP_N_R D+_A6 D-_B7 TBTA_BOT_P_R @EMI@ RT122
TBTA_BOT_N <26>
1 2 0_0402_5% A7 B6 1 2 0_0402_5%
Bottom
C <26> TBTA_TOP_N D-_A7 D+_B6 TBTA_BOT_P <26> C
@EMI@ RT121 0_0402_5% @EMI@ RT123 0_0402_5%
TOP
TBTA_SBU1 A8 B5 TBTA_CC2
<25,26> TBTA_SBU1 TBTA_CC2 <26>
1
SBU1 CC2
2 1 A9 B4 1 2
0.47U_0201_25V CT101 VBUS_A9 VBUS_B4 CT102 0.47U_0201_25V
A10 B3 TBTA_TX2N_C 0.22U_0201_6.3V6K 2 1 CT98
<25> TBTA_RX2N A11 RX2- TX2- B2 TBTA_TX2P_C TBTA_TX2N <25>
0.22U_0201_6.3V6K 2 1 CT97
<25> TBTA_RX2P RX2+ TX2+ TBTA_TX2P <25>
A12 B1
GND_A12 GND_B1
1 4
2 GND1 GND4 5
3 GND2 GND5 6
GND3 GND6
D
X
0
7
B
D
2
4
J
J
2
L
I
N
K
D
O
N
E
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
ESD@ DT5 ESD@ DT13

TBTA_TX1P_C 1 2 TBTA_RX1P 1 2
B ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2 B
ESD@ DT6 ESD@ DT14

TBTA_TX1N_C 1 2 TBTA_RX1N 1 2
ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2
ESD@ DT7 ESD@ DT15

TBTA_CC1 1 2 TBTA_SBU2 1 2
ESD@ DT8 ESD@ DT16

TBTA_SBU1 1 2 TBTA_CC2 1 2
ESD@ DT9 ESD@ DT17

TBTA_RX2N 1 2 TBTA_TX2P_C 1 2
ESD@ DT10 ESD@ DT18

TBTA_RX2P 1 2 TBTA_TX2N_C 1 2
ESD@ DT11 ESD@ DT19

TBTA_TOP_P_R 1 2 TBTA_BOT_P_R 1 2
ESD@ DT12 ESD@ DT20

A A
TBTA_TOP_N_R 1 2 TBTA_BOT_N_R 1 2
PROPRIETARY NOTE: Compal Electronics, Inc.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C
1.0
5 4 3 2 1
5 4 3 2 1
TOUCH_PANEL_INTR#:
LINK 50398-04041-001 DONE
JEDP1
1
1
+5V_TSP
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events
USB20_N8_R
4
EXC24CQ900U_4P
3
USB20_N8 <10>
For 2LANE EDP &5V_TSP
2
2 3 USB20_P8_R
3 4 1 2
For Breckenridge 14/15

4 5 USB20_P8 <10>
5 TOUCH_SCREEN_PD# <12> LV27 EMI@
6
6
AZC199-02SPR7G_SOT23-3
7
7 DMIC0 <33>
@ESD@
8
8 9
3
9 DMIC_CLK0 <33>
10 +3.3V_RUN
10 11
11 USB20_N5_R +3.3V_CAM
1
100P_0402_50V8J
@EMI@ CA5
100P_0402_50V8J
@EMI@ CA6
12 RF Request
12 USB20_P5_R
DV4
13
1
13
1
14 +5V_TSP
14 CAM_MIC_CBL_DET# <12>
15
15 16 Pin15: LOOP_BACK
D D
2
16 17
17 +BL_PWR_SRC
18
18 19 +3.3V_RUN
19 ESD depop locat i on
20
20 BIA_PWM
10K_0402_5%
21 EMI@ LV1 1 2
21
2
DISP_ON
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
22 BLM15PX221SN1D_2P
RV8
22 23
EMI Request 1 1
23 24
24 25
25 26 +LCDVDD 2 2
EDP_HPD <6>
1
26 27 TOUCH_SCREEN_DET#
27 28 EDP_HPD 1 2
28 29 @ RV7 100K_0402_5%
29 LCD_TST <34>
30
30 31 Reserve for EA
If touch panel, GPIO Low-> Touch Mic. EQ ;
31 +LCDVDD
TOUCH_SCREEN_DET# others the GPIO is High -> Non-Touch Mic.
32
32 33 EDP_AUXN_C CV1 2 1TOUCH_SCREEN_DET#
0.1U_0402_25V6
<12>
EQ
33 EDP_AUXP_C EDP_AUXN <6>
34 CV2 2 1 0.1U_0402_25V6
34 EDP_TXP0_C EDP_AUXP <6>
35 CV3 2 1 0.1U_0402_25V6
41 35 36 EDP_TXN0_C 2 1 0.1U_0402_25V6 EDP_TXP0 <6>
CV4
G1 36 EDP_TXP1_C EDP_TXN0 <6>
42 37 CV5 2 1 0.1U_0402_25V6
43 G2 37 38 EDP_TXN1_C 2 1 0.1U_0402_25V6 EDP_TXP1 <6>
CV6
G3 38 EDP_TXN1 <6>
44 39
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
ACES_50398-04041-001
CONN@
JIR1 +PWR_SRC
+BL_PWR_SRC +LCDVDD +3.3V_CAM +5V_TSP +3.3V_RUN 1
1 2 IR_CAM_DET# <12>
2
0.1U_0603_50V7K
0.1U_0201_10V6K
100P_0201_25V7K
RF@ CZ1
0.1U_0201_10V6K
100P_0201_25V7K
RF@ CA7
100P_0402_50V8J
RF@ CZ3
3 1
3 4
1 1 1 1 4
1
@ @ 5
5
CV11
CV12
CZ2
6
6 +PWR_SRC 2
7
2
2 2 2 2 GND 8
C GND C
ACES_50208-0060N-P01 RF Request
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10 CONN@
Link ACES_50208-0060N-P01 done
DV1 DV2
3 EDP_BIA_PWM 3
EDP_BIA_PWM <6> PANEL_BKLEN <6>
BIA_PWM 1 DISP_ON 1
2 BIA_PWM_EC 2
BIA_PWM_EC <34> PANEL_BKEN_EC <34>
1
4.7K_0402_5%
4.7K_0402_5%
1
RV1
RV2
+5V_RUN +5V_TSP +5V_RUN

2
QV8
2
47K_0402_5%
LP2301ALT1G_SOT23-3
2
1 3
RV6
S
RF Request
G
1
2
+LCDVDD +3.3V_CAM +BL_PWR_SRC
L2N7002WT1G_SC-70-3
1
D
QV7
2
<9> 3.3V_TS_EN
G
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
1 1 1 1 1 1 S
3
B B
2 2 2 2 2 2
LCDVDD POWER +LCDVDD +EDP_VDD

+3.3V_ALW
@
CV16 PJP12 UV24
WebCAM Backlight POWER +BL_PWR_SRC

2 1 1 2 1
VOUT 5
10U_0603_10V6M VIN
+PWR_SRC QV1 PAD-OPEN1x1m 2
GND
0.01UF_0402_25V7K
4
+3.3V_CAM +3.3V_RUN EN
@
6
D
CV17
4 5 3
S
QZ1 2 /OC
LP2301ALT1G_SOT23-3 1 G524B1T11U_SOT23-5
2
1000P_0402_50V7K
0.1U_0603_50V7K
DV3
G
270K_0402_5%
2
1 3 AO6405_TSOP6
D
CV13
3
2
2
RV4
<34> LCD_VCC_TEST_EN EN_LCDPWR

CV15
1
G
2
3
1
<6,34> ENVDD_PCH
2
100K_0402_5%
RV3
<11> 3.3V_CAM_EN# BL_PWR_SRC_ON BAT54CW_SOT323-3
QV2
1
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
A 1 A
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
EXC24CQ900U_4P
4 3 USB20_P5_R 2
G
<10> USB20_P5
2
1 2 USB20_N5_R
<10> USB20_N5 <34> EN_INVPWR
LZ1 EMI@ DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP CONN & Touch screen
1.0
5 4 3 2 1
5 4 3 2 1
Layout Not i ce : Pl ace bead as

+3.3V_LAN UL1 close UL4 as possible
2 1 TP_LAN_JTAG_TMS CLKREQ_PCIE#4 48 13 LAN_MDIP0 RL71 1 2 2.2_0603_5% LAN_MDIP0_L
<11> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 LAN_MDIN0_L
@ RL1 10K_0402_5% 36 14 RL72 1 2 2.2_0603_5%
TP_LAN_JTAG_TCK <11> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1
@ RL2 10K_0402_5% 44 17 LAN_MDIP1 RL73 1 2 2.2_0603_5% LAN_MDIP1_L
CLKREQ_PCIE#4 <11> CLK_PCIE_P4 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIN1_L
2 1 45 18 RL74 1 2 2.2_0603_5%
<11> CLK_PCIE_N4
PCIE
PCIE_PRX_C_DTX_P9 PE_CLKN MDI_MINUS1
MDI
@ RL4 4.7K_0402_5% 1 2
<10> PCIE_PRX_DTX_P9 LAN_MDIP2 LAN_MDIP2_L
CL1 0.1U_0402_25V6 38 20 RL75 1 2 2.2_0603_5%
1 2 PCIE_PRX_C_DTX_N9 39 PETp MDI_PLUS2 21 LAN_MDIN2 RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<10> PCIE_PRX_DTX_N9 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
+3.3V_LAN 1 2 PCIE_PTX_C_DRX_P9 41 23 LAN_MDIP3 RL77 1 2 2.2_0603_5% LAN_MDIP3_L
<10> PCIE_PTX_DRX_P9 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6 42 24 RL78 1 2 2.2_0603_5%
1 2 PCIE_PTX_C_DRX_N9 PERn MDI_MINUS3
<10> PCIE_PTX_DRX_N9
CL6 0.1U_0402_25V6
2
VCT_LAN_R1
10K_0402_5%
28 6 1 2
<8> SML0_SMBCLK
SMBUS
31 SMB_CLK SVR_EN_N 0_0402_5% @ RL3
D <8> SML0_SMBDATA SMB_DATA 1 +RSVD_VCC3P3_1 4.7K_0402_5% 1 2 RL6
RF Request D
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN +3.3V_LAN_OUT
2 5
1
1 2 <11,34> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<11> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
@ RL7 0_0402_5% SMBus Device Address 0xC8 4 1 2
VDD3P3_4 +3.3V_LAN
0_0603_5% @ RL8
10K_0402_5%
0.1U_0201_10V6K
22U_0805_6.3V6M
15 1
1
LOM_ACTLED_YEL# VDD3P3_15
@ RL9
26 19
LOM_SPD100LED_ORG# LED0 VDD3P3_19
CL7
CL28
@RF@ CL29
@RF@ CL30
27 29 Place CL28 close to UL1.5
LOM_SPD10LED_GRN# LED1 VDD3P3_29
LED
+0.9V_LAN
12P_0402_50V8J
82P_0402_50V8J
25 1 1
2
LED2 2
2 47 +3.3V_LAN
VDD0P9_47 46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37 2 2
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 JTAG_TDO 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
470P_0402_50V7K
XTALO_R
0.1U_0201_10V6K
1 2 XTALO 9 40 1
1
XTAL_OUT VDD0P9_40
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ RL34 0_0402_5% XTALI 10 22
1
XTAL_IN VDD0P9_22
CL18
CL19
1 1 1 1 16
1
VDD0P9_16
CL9
CL10
CL11
CL8
8 +0.9V_LAN
RJ45 LOM circuit
2
LAN_TEST_EN VDD0P9_8 2
CL12
RL11 30
1M_0402_5% TEST_EN
2
2 2 2 2 YL1 RES_BIAS 12 7 +REGCTL_PNP10 1 2

+3.3V_LAN:20mils
2
3 1 RBIAS CTRL0P9 4.7UH_BRC2012T4R7MD_20% LL1
OUT IN
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA
1
27P_0402_50V8J
VSS_EPAD
1K_0402_5%
3.01K_0402_1%
4 2 DCR=100mohm 1 @ JLOM1 CONN@
1
27P_0402_50V8J
GND GND
CL3
CL4
WGI219LM-QREF- A0_QFN48_6X6~D
1
CL14
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
RL12
RL13
Note: 25MHZ_18PF_7V25000034 1 2 10
CL13
RL14 150_0402_5% Yellow LED-

+1.0V_LAN will work at 0.95V to 1.15V
2
change to SA000081G0L, S IC A32 WGI219LM QREF A0 QFN 48P PHY 2 9
2
2
Yellow LED+
RJ45_MDIN3 8
8
RJ45_MDIP3 7
Place CL3, CL4 and LL1 close to UL1 7
RJ45_MDIN1 6
6
RJ45_MDIN2 5
5
C RJ45_MDIP2 C
4
4
RJ45_MDIP1 3
3
RJ45_MDIN0 2
2 15
RJ45_MDIP0 1 GND_2
vinafix
1 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND_1
RL19 150_0402_5% Green LED-
LED_100_ORG# 1 2 LED_100_ORG_R# 13
RL20 150_0402_5% Orange LED-
12
Green-Orange LED+
SANTA_130456-831
When LAN & WLAN are exist at the same time, WLAN will disable
TL1
2 1 1 24 Z2805
+3.3V_LAN CL16 0.1U_0201_10V6K TCT1 MCT1
LAN_MDIN3_L 2 23 RJ45_MDIN3
@ CL15 TD1+ MX1+
1 2 LAN_MDIP3_L 3 22 RJ45_MDIP3
TD1- MX1-
0.1U_0201_10V6K 2 1 4 21 Z2807
5
CL17 0.1U_0201_10V6K TCT2 MCT2

LOM_SPD100LED_ORG# 1 LAN_MDIN1_L 5 20 RJ45_MDIN1
P
B 4 TD2 MX2+
LOM_SPD10LED_GRN# 2 O LOM_CABLE_DETECT# <34> LAN_MDIP1_L 6 19 RJ45_MDIP1
G
A UL2 TD2- MX2-

B TC7SH08FU_SSOP5~D 2 1 7 18 Z2806 B
3
CL20 0.1U_0201_10V6K TCT3 MCT3

LAN_MDIN2_L 8 17 RJ45_MDIN2
TD3+ MX3+
LAN_MDIP2_L 9 16 RJ45_MDIP2
TD3- MX3-
QL1A 2 1 10 15 Z2808
DMN65D8LDW-7_SOT363-6 CL21 0.1U_0201_10V6K TCT4 MCT4
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL# LAN_MDIN0_L 11 14 RJ45_MDIN0
TD4+ MX4+
LAN_MDIP0_L 12 13 RJ45_MDIP0
+3.3V_LAN TD4- MX4-
2
SYS_LED_MASK# 350UH_IH-160
SYS_LED_MASK# <34,46>
1
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
RL29
1M_0402_5%
QL1B
2
LOM_SPD100LED_ORG#
4 3 LED_100_ORG#
+3.3V_LAN
5
1
SYS_LED_MASK#
RL30
RL15 2
RL16 2
RL17 2
RL18 2
1M_0402_5%
QL2A
GND
2
LOM_SPD10LED_GRN# 1 6 LED_10_GRN# 1 2 +GND_CHASSIS

EMI@ CL22 10P_1808_3KV8J
CHASSIS use 40mil trace if necessary
2
SYS_LED_MASK#
For WLAN can't recognize during enable
Unobtrusive mode(BITS152312)
QL2B
4 3
A A
5
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN Clarkvillie & RJ45
5 4 3 2 1
A B C D E
For PCIE Interface
1 1
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
RF Request +3.3V_MMI_AUX +3.3V_MMI_IN
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 2
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3V3AUX)
1 1 1 1
CR4
0_0603_5% R274 @
CR3
CR1
CR2
@RF@ CR27
@RF@ CR28
@RF@ CR25
@RF@ CR26
2 2 2 2
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1
+3.3V_MMI_AUX
2 2 2 2
2 1 MEDIACARD_IRQ# 7/18 Vender suggest.

RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12
<11,32,37,40> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18 +3.3V_RUN_CARD
2 18 1 2
<11> CLKREQ_PCIE#5 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5
<11> CLK_PCIE_P5 REFCLKP SD/MMCDAT1/RCLK-_R
6 15 SD/MMCDAT1/RCLK- 1 2
<11> CLK_PCIE_N5 REFCLKN SP1 SD/MMCDAT0/RCLK+_R
16 SD/MMCDAT0/RCLK+ @ RR9 1 2 0_0402_5%
CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P1 3 RTS5242 SP2 17 SD/MMCCLK @ RR10 1 2 0_0402_5% SD/MMCCLK_R
<10> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 HSIP SP3 SD/MMCCMD_R
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD @EMI@RR5 1 2 0_0402_5%
<10> PCIE_PTX_DRX_N1 PCIE_PRX_C_DTX_P1 HSIN SP4 SD/MMCDAT3_R
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 7 20 SD/MMCDAT3 @ RR6 1 2 0_0402_5%
<10> PCIE_PRX_DTX_P1 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N1 8 HSOP SP5 21 SD/MMCDAT2 @ RR7 1 2 0_0402_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N1
1
HSON SP6 29 SDWP @ RR8 0_0402_5%
SP7
32
2
2 <9> MEDIACARD_IRQ# WAKE# 2
31
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop locat i on
CR9 CR10 close to UR2.14
SD_LN1_P 23 SD_UHS2_D1N
10 SD_LN1_M
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 CR15 1 2
1 1
E-PAD
1
SDREG2
CR5
+RREF 9 28 1U_0402_6.3V6K
CR6
CR7
RREF GPIO SD_GPIO 2 1
+3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
3 3
QR1
L2N7002WT1G_SC-70-3
HOST_SD_W P# SDW P_Q SDW P STATUS
SDWP 1 3 SDWP_Q JSD1 CONN@
S
4
+3.3V_RUN_CARD VDD/VDD1
High High Write Protect(SD LOCK) +1.8V_RUN_CARD 14
SD/MMCCMD_R 2 VDD2
G
2
High SD/MMCCLK_R 5 CMD
Low Low Write Enable CLK
<12> HOST_SD_WP#
SD/MMCCD# 18
SDWP_Q 19 CARD DETECT
High High Write Protect(SD& FW LOCK) WRITE PROTEC
Low SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
Low High Write Protect(FW LOCK) SD/MMCDAT2_R 9 DAT1/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCDAT3_R 1 DAT2
SD_UHS2_D0P 11 CD/DAT3
SD_UHS2_D0N 12 D0+
SD_UHS2_D1P 16 DO-
SD_UHS2_D1N 15 D1+ 20
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D1- GND1 21
2 2
2
3 GND2 22
CR17
CR19
CR20
6 VSS1 GND3 23
CR18
10 VSS2 GND4 24
1
1 1 13 VSS3 GND5 25
17 VSS4 GND6 26
VSS5 GND7
T-SOL_156-2000302608_NR
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14

LINK SP070011U00 DONE
4 4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader RTS5242
A B C D E
5 4 3 2 1
+3.3V_WWAN NGFF slot B Key B for Brekenridge 14/15 DSC

+3.3V_WWAN
2 1 WWAN_PWR_EN
RZ43 47K_0402_5% JNGFF2 CONN@
100P_0402_50V8J
1 2
<34> SLOT2_CONFIG_3 1 2
RF@ CZ198
3 4
5 3 4 6 WWAN_PWR_EN
NGFF slot A Key A
1
USB20_P4_L 7 5 6 8 WWAN_RADIO_DIS#_R
USB20_N4_L 9 7 8 10 SLOT2_SATA_LED# 1 2
9 10 SATALED# <10,40,46>
11 @ RN101 0_0402_5%
2
11
+3.3V_WLAN
D D
12 JNGFF1 CONN@
13 12 14 1 2
<34> SLOT2_CONFIG_0 13 14 USB20_P7_L 1 2
15 16 3 4
<34> WWAN_WAKE# 15 16 HW_GPS_DISABLE#_R USB20_N7_L 3 4
2 1 17 18 5 6
@RF@ RZ326 0_0402_5% 19 17 18 20 7 5 6
USB3_PRX_L_DTX_N2 21 19 20 22 UIM_RESET 7
USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK
25 23 24 26 UIM_DATA
USB3_PTX_L_DRX_N2 27 25 26 28 8
USB3_PTX_L_DRX_P2 27 28 +SIM_PWR 8
29 30 9 10
31 29 30 32 ISH_I2C2_SCL_R 2 1 1 2 SW2_DP2_N3_C 11 9 10 12 SW2_DP2_AUXN_C 2 1
31 32 ISH_I2C2_SDA_R ISH_I2C2_SCL <9> <22> SW2_DP2_N3 SW2_DP2_P3_C 11 12 SW2_DP2_AUXP_C SW2_DP2_AUXN <22>
33 34 @ RZ76 2 1
0_0402_5% CV145 1 2 0.1U_0402_25V6 13 14 0.1U_0402_25V6 2 1CV150
33 34 ISH_I2C2_SDA <9> <22> SW2_DP2_P3 13 14 SW2_DP2_AUXP <22>
35 36 @ RZ77 0_0402_5% CV146 0.1U_0402_25V6 15 16 0.1U_0402_25V6 CV149
37 35 36 38 1 2 SW2_DP2_N2_C 17 15 16 18 SW2_DP2_N1_C 2 1
37 38 <22> SW2_DP2_N2 SW2_DP2_P2_C 17 18 SW2_DP2_P1_C0.1U_0402_25V6 SW2_DP2_N1 <22>
39 40 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9 CV148 1 2 0.1U_0402_25V6 19 20 2 1CV152
39 40 PCH_PLTRST#_AND <22> SW2_DP2_P2 19 20 SW2_DP2_P1 <22>
41 42 CV147 0.1U_0402_25V6 21 22 0.1U_0402_25V6 CV153
43 41 42 44 23 21 22 24 SW2_DP2_N0_C 2 1
43 44 PCIE_WAKE# <22> SW2_DP2_HPD 23 24 SW2_DP2_P0_C0.1U_0402_25V6 SW2_DP2_N0 <22>
45 46 25 26 2 1CV156
45 46 PCIE_PTX_C_DRX_P3 25 26 SW2_DP2_P0 <22>
47 48 @ RZ131 2 1 0_0402_5% CZ12 1 2 0.1U_0402_25V6 27 28 0.1U_0402_25V6 CV157
47 48 PORT80_DET# <34> <10> PCIE_PTX_DRX_P3 PCIE_PTX_C_DRX_N3 27 28
49 50 @ RZ132 2 1 0_0402_5% CZ13 1 2 0.1U_0402_25V6 29 30
49 50 WWAN_COEX3 HOST_DEBUG_TX WLAN_COEX3
<34,35> <10> PCIE_PTX_DRX_N3 29 30 PCH_CL_RST1# <8>
51 52 @RF@ RZ128 1 2 0_0201_5% 31 32
51 52 WWAN_COEX2 31 32 PCH_CL_DATA1 <8>
53 54 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX2 33 34
55 53 54 56 WWAN_COEX1 @RF@ RZ130 1 2 0_0201_5% WLAN_COEX1 WLAN <10> PCIE_PRX_DTX_P3 35 33 34 36 WLAN_COEX3 PCH_CL_CLK1 <8>
57 55 56 58 SIM_DET <10> PCIE_PRX_DTX_N3 37 35 36 38 WLAN_COEX2
PAD~D @ T225 59 57 58 60 39 37 38 40 WLAN_COEX1 RZ56 @
59 60 <11> CLK_PCIE_P1 39 40 WIGIG_32KHZ
61 62 41 42 0_0402_5% 2 1
<34> SLOT2_CONFIG_1 61 62 <11> CLK_PCIE_N1 41 42 PCH_PLTRST#_AND SUSCLK <11,40>
63 64 43 44
63 64 43 44 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,31,37,40>
65 66 45 46
65 66 <11> CLKREQ_PCIE#1 PCIE_WAKE# 45 46 WLAN_WIGIG60GHZ_DIS#_R
67 47 48
<34> SLOT2_CONFIG_2 67 <35,40> PCIE_WAKE# 47 48 ISH_UART0_RXD_R
49 50 2 1
PCIE_PTX_C_DRX_P4 49 50 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
CZ14 1 2 0.1U_0402_25V6 51 52 1 0_0402_5%
<10> PCIE_PTX_DRX_P4 PCIE_PTX_C_DRX_N4 51 52 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
69 68 CZ15 1 2 0.1U_0402_25V6 53 54 1 0_0402_5%
GND GND <10> PCIE_PTX_DRX_N4 53 54 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
55 56 1 0_0402_5%
55 56 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <9>
57 58 0_0402_5%
<10> PCIE_PRX_DTX_P4 59 57 58 60
WIGI <10> PCIE_PRX_DTX_N4 61 59 60 62 PCIE_WAKE# CLKREQ_PCIE#2 <11>
B
E
L
L
W
_
8
0
1
4
9
-
4
2
2
1
L
I
N
K
D
O
N
E
BELLW_80149-4221
63 61 62 64
<11> CLK_PCIE_P2 63 64
65 66 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9
<11> CLK_PCIE_N2 65 66
67
67
C C
69 68
GND GND
+3.3V_WWAN
RF Request
+3.3V_WWAN
BELLW_80148-4221
B
E
L
L
W
_
8
0
1
4
8
-
4
2
2
1
L
I
N
K
D
O
N
E
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
47P_0402_50V8J
100P_0402_50V8J
2000P_0402_50V7K
RF@
WWAN_RADIO_DIS#_R
22U_0603_6.3V6M
RF@ CZ24
100U_B2_6.3VM_R35M
RF@CZ26
1 1 2
RF@ CZ25
<34> WWAN_RADIO_DIS#
1
1
CZ20
1
CZ17
CZ18
CZ19
CZ21
+ DZ5
CZ23
RB751S40T1G_SOD523-2
2
1 2 HW_GPS_DISABLE#_R
<34> HW_GPS_DISABLE#
DZ6
1 2
@RF@ RI27 0_0402_5%
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
1 2
<10> USB3_PRX_DTX_P2
1 1 1
1
USB3_PRX_L_DTX_N2
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
4 3 1 2
<10> USB3_PRX_DTX_N2 @RF@ RI47 0_0402_5% 1 2 WLAN_WIGIG60GHZ_DIS#_R
2
<34> WLAN_WIGIG60GHZ_DIS# 2 2 2
HCM1012GH900BP_4P
1 2 DZ1
@RF@ RI28 0_0402_5% RB751S40T1G_SOD523-2
1 2
@RF@ RI29 0_0402_5%
LI17 RF@ LI8 RF@

2 1 USB3_PTX_C_DRX_P2 1 2 USB3_PTX_L_DRX_P2 1 2 USB20_P4_L Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
<10> USB3_PTX_DRX_P2 <10> USB20_P4
CI30 0.1U_0402_25V6
B B
2 1 USB3_PTX_C_DRX_N2 4 3 USB3_PTX_L_DRX_N2 4 3 USB20_N4_L 1 2 BT_RADIO_DIS#_R
<10> USB3_PTX_DRX_N2
CI29 0.1U_0402_25V6
<10> USB20_N4 <34> BT_RADIO_DIS# RF Request
DZ2 +3.3V_WLAN
HCM1012GH900BP_4P MCM1012B900F06BP_4P RB751S40T1G_SOD523-2
1 2
@RF@ RI30 0_0402_5% RF Request
1 2
SIM Card Push-Push
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
@RF@ RI48 0_0402_5%
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
1 2
1
+SIM_PWR @RF@ RI49 0_0402_5%
JSIM1 CONN@
2
4.7U_0402_6.3V6M
1 5 STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type M3042_PCIE#_SATA

UIM_RESET 2 VCC GND 6
1
UIM_CLK 3 RST VPP 7 UIM_DATA

CLK I/O
CZ37
4 8 0 GND GND GND GND SSD-SATA High MCM1012B900F06BP_4P

RFU1 RFU2
2
9 SIM_DET 4 3 USB20_P7_L
DTSW <10> USB20_P7
1 GND HIGH GND GND SSD-PCIE(2 lane) Low
10
11 GND 14 1 2 USB20_N7_L
GND GND <10> USB20_N7
12 15 8 HIGH GND GND GND W WAN Low
13 GND GND 16 LI9 RF@
GND GND
T
-
S
O
L
_
5
-
9
9
1
5
0
3
0
0
4
0
0
0
-
6
L
I
N
K
D
O
N
E
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Low

T-SOL_5-991503004000-6
15 HIGH HIGH HIGH HIGH NA Low @RF@ RI50

1 2
0_0402_5%
Power Rating TBD
Primary Power Aux Power
PWR Voltage
Rail Tolerance
Peak Normal Normal
+SIM_PWR
UIM_CLK +3.3V
@RF@ RZ335
1
47P_0402_50V8J
15K_0402_5%
@RF@ CZ38
A A
1
+SIM_PWR
2
UIM_DATA UIM_RESET
33P_0402_50V8J
33P_0402_50V8J
1
51_0402_5%
@RF@ RZ334
@RF@ CZ39
@RF@ CZ40
0.1U_0402_25V6
RF@ CZ41
1
1
2
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
RF Request NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
SPKR_R
100P_0402_50V8J
10K_0402_5%
1
1
BEEP_R
@ CA72
@ RA51
+5V_RUN_AUDIO
100P_0402_50V8J
10K_0402_5%
LA13
+5V_RUN_PVDD_Lplace close to pin41 place close to pin46
1
@ CA62
@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 2
HCB2012VF-601T20_2P
Internal Speakers Header
2
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1 1 600 Ohm/2A 1 1
2
CA45
CA47
CA60
CA46
CA48
CA59
40 mils trace keep 20 mil spacing CONN@
2
JSPK1
INT_SPK_L+ EMI@ LA6 1 2 BLM15PD800SN1D_2P INT_SPKR_L+ 1 2 2 2 2 2 2
INT_SPK_L- EMI@ LA7 1 2 BLM15PD800SN1D_2P INT_SPKR_L- 2 1
INT_SPK_R+ EMI@ LA8 1 2 BLM15PD800SN1D_2P INT_SPKR_R+ 3 2
INT_SPK_R- EMI@ LA9 1 2 BLM15PD800SN1D_2P INT_SPKR_R- 4 3
5 4 +3.3V_RUN_AUDIO
G1
L03ESDL5V0CC3-2_SOT23-3
D 6 D
3
G2 +5V_RUN_AUDIO
+3.3V_RUN_AUDIO_IO
@ESD@
@ESD@
ACES_50278-00401-001 2 1 LA5
LA12 BLM15PX600SN1D_2P +VDDA_AVDD1 1 2
place close to pin26
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
Link 50278-00401-001 DONE 1 RF Request
1
1
CA55
CA56
2 1 1
1
DA6
DA7
CA8
LA14 BLM15PX600SN1D_2P +5V_RUN_AUDIO
CA9
2
2
2
0.1U_0201_10V6K
10U_0603_10V6M
1
2
2
1
1
CA10
CA61
place close to pin9
+1.8V_RUN
2
2 +3.3V_RUN_AUDIO_DVDD
+1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
place close to pin40 1 2 1 1
Close to UA1 @ RA3 0_0603_5%
10U_0603_10V6M
0.1U_0201_10V6K
place close to pin1 1
1
2 2
CA58
CA57
2
2
41
46
26
40
36
1
9
UA1
Close to UA1 pin6
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
CPVDD
HDA_BIT_CLK_R DMIC_CLK0 11
I2C_SDA AUD_HP_OUT_L
@EMI@ RA17
12 31 +LINE1-VREFO-L RA57 1 2 4.7K_0402_5%

I2C_SCL LINE1-VREFO-L AUD_HP_OUT_R
10P_0402_50V8J
@EMI@CA54
30 +LINE1-VREFO-R RA58 1 2 4.7K_0402_5% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

1
LINE1-VREFO-R
33_0402_5%
10 29 +MIC2-VREFO
<12> HDA_SYNC_R HDA_BIT_CLK_R SYNC MIC2-VREFO
6 28 1 2
<12> HDA_BIT_CLK_R HDA_SDOUT_R 5 BIT-CLK VREF 35 CA35 2.2U_0402_6.3V6M
RF Request
Place RA9 close to codec
2
<12> HDA_SDOUT_R HDA_SDIN0_R SDATA-OUT CBN +1.8V_RUN_AUDIO +1.8V_RUN

1 2 8 37 2 1
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN CBP CA29 1U_0603_10V6K
Place CA29 close to Codec
2
100K_0402_5%1 2 RA52 4 20 @ RA53 1 2 0_0402_5%

+5V_ALW
EAPD/DC DET 5VSTB
10P_0402_50V8J
@EMI@ CA33
2 @ RA54 1 2 0_0402_5%
<29> DMIC0 DMIC_CLK0 1 GPIO0/DMIC-DATA12 +RTC_CELL
place close to UA1 pin3 2 DMIC_CLK_CODEC 3 34 1 2 1 2 RING2
<29> DMIC_CLK0
1
EMI@ RA14 22_0402_5% 47 GPIO1/DMIC-CLK CPVEE CA49 1U_0603_10V6K RA5 2.2K_0402_5%

PDB
RF@ CA69
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 48 +MIC2-VREFO 1 2 SLEEVE
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
33P_0402_50V8J
2 1 SLEEVE/RING2 please keep 40 mils trace width RA6 2.2K_0402_5%
2
C C
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
100K_0402_5% 2 1 RA44 27 1 1 1
1U_0603_10V6K 2 1 CA31 10U_0603_10V6M 2 1 CA51 39 LDO1-CAP 17 RING2 AUD_PC_BEEP 2 1 SPKR_R 1 2
LDO2-CAP MIC2-L/RING2 BEEP_R SPKR <12>
10U_0603_10V6M 2 1 CA52 7 18 SLEEVE CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
LDO3-CAP MIC2-R/SLEEVE BEEP <34>
10U_0603_10V6M CA53 19 1 2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
MIC-CAP 24 10U_0603_10V6M CA25 2 2 2
INT_SPK_L+ 42 LINE2-L 23
INT_SPK_L- 43 SPK-L+ LINE2-R 22 LINE1_L 1 2 HP_OUT_L
INT_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_R 10U_0603_10V6M 1 2 CA43 HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
INT_SPK_R+ 45 SPK-R- LINE1-R 16 AUD_PC_BEEP
10U_0603_10V6M CA44
SPK-R+ PCBEEP 32 HP_OUT_L 1 2 AUD_HP_OUT_L
AUD_SENSE_A 13 HP-OUT-L 33 HP_OUT_R 16.2_0402_1% 1 2 RA7 AUD_HP_OUT_R
+3.3V_RUN_AUDIO 1 2 AUD_SENSE_B 14 HP/LINE1 JD1 HP-OUT-R 16.2_0402_1% RA8
+3.3V_RUN_AUDIO MIC2/LINE2 JD2
RA61 100K_0402_1% 15 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
Place closely to Pin 14. AVSS2 49
100K_0402_1% 200K_0402_1%
1
THERMAL PAD
RA59
RF Request
+3.3V_RUN_AUDIO
2
0.1U_0402_25V6
1
@
CA41
RA60
2
2
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
AUD_HP_NB_SENSE
Add for solve 1 1
pop noise and
detect issue
2 2
B
CLASS-D POWER DOWN CONTROL CIRCUIT
vinafix Add this Filter to avoid other
components/chips be influenced
HP-Out-Lef t
HP-Out-Right Nokia-MIC
iPhone-MIC
B
1 2
@ RA48 0_0402_5%
place at AGND and DGND plane
680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
@ RA35
<34> AUD_NB_MUTE#
0_0402_5% Global Headset
RB751S40T1G_SOD523-2 PD#
1
@ RA36
2
1
PJP19
2
<12> HDA_RST#_R
1 2 2 Universal Jack
0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1
1 2 7
@ RA37 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L EMI@ LA15 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_L1 1 #4 G/M
#1 L Normal
Open
5
Only BR15U UMA use LA2,LA3,because 6L #5
AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R EMI@ LA16 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R
PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN 1 2 SINGA_2SJ3095-136111F
680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO
ESD@
@EMI@ CA2
@EMI@ CA3
ESD@
ESD@ ESD@ ESD@ CONN@
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A Link 2SJ3095-136111F DONE
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
Reserve for support D3 cold
1
CA1
CA4
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2
1
1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
A VIN1 VOUT1 A
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW VBIAS GND
5 10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K
+3.3V_RUN
6 9 @ PJP16
7 VIN2 VOUT2 8 +3.3V_RUN_AUDIO_UZ5 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
EM5209VF_SON14_2X3
GPAD PAD-OPEN1x1m
1 2
@ CZ128 0.1U_0201_10V6K Security Classification Compal Secret Data
Title
Issued Date 2016/01/01 Deciphered Date <Deciphered_Date>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec ALC3246
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E082P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+RTC_CELL
0_0402_5%
2 1
RE32 @
+RTC_CELL_VBAT eSPI
LPC
GPIO223
NA
SHD_IO0
GPIO224 GPIO227
NA *PRIM_PW RGD
SHD_IO1 SHD_IO2
GPIO016
NA
SHD_IO3
GPIO056
NA
SHD_CLK
GPIO055
PCH_RSMRST#
SHD_CS#
For BR DSC
UPD1_SMBDAT
0.1U_0201_10V6K
1 * For Version B IC 1 2
CE11
RE302 2.2K_0402_5%
GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 UPD1_SMBCLK 1 2
+3.3V_ALW_UE1
eSPI NA NA NA SIO_RCIN# NA RE303 2.2K_0402_5%
2 UPD1_ALERT#
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN# 1 2
+3.3V_ALW 1 2 1 1 RE91 100K_0402_5%
1
UPD2_ALERT#
CE13
CE14
CE23
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m RE92 100K_0402_5%
1
PBAT_CHARGER_SMBDAT 1 2
2
2 2
CE16
RE37 2.2K_0402_5%
PBAT_CHARGER_SMBCLK 1 2
2
UE1 RE43 2.2K_0402_5%
F2 TYPEC_ID
TYPEC_ID <35> EXPANDER_GPU_SMDAT 1 2
A2 GPIO033/RC_ID0 J10 PANEL_ID
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID PANEL_ID <35> RE524 2.2K_0402_5%
J13 EXPANDER_GPU_SMCLK
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <35> 1 2 D
B7 E7
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBCLK RE525 2.2K_0402_5%
2 1 D7
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2 RPE12

VREF_ADC
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 1 8
+3.3V_EC_PLL GPIO057/VCC_PWRGD HW_GPS_DISABLE# RUNPWROK <14>
CE19
CE20
@ CE17
F1 H5 2 7
VTR_PLL GPIO060/KBRST/48MHZ_OUT HW_GPS_DISABLE# <32> UPD2_SMBCLK
CE18
G11 3 6
GPIO104/UART0_TX HOST_DEBUG_TX <32,35> UPD2_SMBDAT
H1 G12 4 5
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FW_EC <12>
B13
GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <11>
G8 F10 2.2K_0804_8P4R_5%
M9 VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <26>
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 RPE9
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <35> SLOT2_CONFIG_1 1 8
GPIO026/TIN1 SIO_SLP_S4# <11,17,59,62> SLOT2_CONFIG_2
F8 M11 2 7
+3.3V_ALW_UE1 <35> PCH_DPWROK_EC RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <11> SLOT2_CONFIG_0
RF Request E8 H9 3 6
<35> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11,47> SLOT2_CONFIG_3
0.1U_0201_10V6K
1 M12 4 5
+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120
C2 L9
<32> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 BEEP <33>
CE15
F9 M10 100K_0804_8P4R_5%
<57,66> PBAT_PRES# GPIO175 GPIO151/ICT4 SLOT2_CONFIG_1 <32>
1 2 N4 N9 RPE11
2 <11,17,47,60,61,62> SIO_SLP_SUS# PCH_ALW_ON GPIO230 GPIO152/GPTP-OUT3 SLOT2_CONFIG_0 <32> USB_PWR_EN2#
RE349 43K_0402_1% M8 1 8
<47> PCH_ALW_ON GPIO231 USB_PWR_SHR_LFT_EN#
K8 C11 2 7
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <46> USB_PWR_EN1#
D10 3 6
GPIO157/LED1 BAT1_LED# <46> USB_PWR_SHR_VBUS_EN
E11 D11 4 5
<8> SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <46>
Close to pin H1 D8 E1
<8> SML1_SMBCLK WWAN_WAKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <29>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13 100K_0804_8P4R_5%
<32> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5 AC_DIS 1 2
<11> SUSACK# WLAN_WIGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_SMBDAT <37>
B3 @ RE83 100K_0402_5%
<32> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 EXPANDER_GPU_SMDAT USH_SMBCLK <37> HW_GPS_DISABLE#
K11 M7 1 2
2 2 <11,14> SIO_PWRBTN# VCCST_PWRGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 EXPANDER_GPU_SMCLK EXPANDER_GPU_SMDAT <35,48>
1 2 M4 RE12 100K_0402_5%
<11,14,35> VCCST_PWRGD RE308 @ 0_0402_5% N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT EXPANDER_GPU_SMCLK <35,48> WLAN_WIGIG60GHZ_DIS# 1 2
<35> LID_CL_NB# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <57,66>
E10 N2 RE8 100K_0402_5%
<45> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <57,66> WWAN_WAKE#
C12 N10 SLOT2_CONFIG_2 <32> 1 2
<45> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA SYS_LED_MASK#
A12 RE38 10K_0402_5%
JTAG_TDI GPIO140/SMB06_CLK/ICT5 RTCRST_ON_GPIO141 SYS_LED_MASK# <30,46> SYS_LED_MASK#
E9 B6 1 2
<35> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 RE21 10K_0402_5%
<35> JTAG_TDO JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 UPD1_SMBDAT THERMATRIP1# 1 2
<35> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <26>
C5 C3 RE301 10K_0402_5%
<35> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <26> PCIE_WAKE#_R
G13 1 2
PJP20 JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5% RE35 10K_0402_5%
GPIO200/ADC00 I_SYS_R I_BATT <66>
1 2 E3 J5 RE312 1 2 300_0402_5% GPIO126 1 2
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <35> FAN1_TACH LCD_TST D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6
I_SYS <63,66>
RE5 10K_0402_5%
1 <29> LCD_TST WWAN_RADIO_DIS# GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 BC_DAT_ECE1117
PAD-OPEN1x1m M2 G2 @ RE318 1 2 0_0402_5% 1 2
<32> WWAN_RADIO_DIS# GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 PCH_RSMRST#_GPIO204 TOUCHPAD_INTR# <12,45>
CE22 L10 H2 RE365 100K_0402_5%
C <35> FAN1_PWM GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_PWR_SHR_VBUS_EN WWAN_RADIO_DIS# C
0.1U_0201_10V6K L11 J2 1 2
2 <57> PS_ID SHD_CS# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_PWR_SHR_LFT_EN# USB_PWR_SHR_VBUS_EN <42,43>
M5 J3 RE10 100K_0402_5%
CE21 SHD_CLK J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_PWR_EN1# USB_PWR_SHR_LFT_EN# <43> BT_RADIO_DIS# 1 2
1 GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <44>
@ PJP21 0.1U_0201_10V6K <29> BIA_PWM_EC N1 D3 RE11 100K_0402_5%
TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 AUX_EN_WOWL <47> PORT80_DET#
1 2 D2 1 2
+3.3V_ALW GPIO002/PWM5 GPIO211/ADC09 LOM_CABLE_DETECT# <30>
Close to pin N5 N6 E2 RE512 100K_0402_5%
2 <57,66,67> ACAV_IN_NB GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PWR_EN2# BC_INT#_ECE1117 <45>
PAD-OPEN1x1m J9 G5
<29> PANEL_BKEN_EC VGA_ID GPIO015/PWM7 GPIO213/ADC11 UPD2_ALERT# USB_PWR_EN2# <44>
H11 F5
D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 PORT80_DET# LPC@
<11,47> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 PORT80_DET# <32> SHD_CLK RE374 1 SHD_CLK_R1 +RTC_CELL
<66> AC_DIS
H12 L1 2 24.9_0402_1%
GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <11,35>
G10 L3 VCI_IN1#
<37> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11,30> 1 2
MSCLK H10
<35> MSCLK RE507 100K_0402_5%
MSDATA G9 GPIO170/TFDP_CLK/UART1_TX H8 CV2_ON_R RE539 1SHD_IO0 <35>
2 100_0402_5% CV2_ON <37>
VCI_IN2#
<35> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ SHD_IO0 LPC@ RE366 1 1 2
+3.3V_ALW J7 2 24.9_0402_1% SHD_IO0_R1 LPC@ RE367 1 2 45.3_0402_1% SHD_IO0_R2
SHD_IO1 LPC@ RE368 1 RE508 100K_0402_5%
A4 GPIO223/SHD_IO0 L6 2 24.9_0402_1% SHD_IO1_R1 LPC@ RE369 1 2 45.3_0402_1% SHD_IO1_R2
POA_WAKE#
<33> AUD_NB_MUTE# EN_INVPWR GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SHD_IO2 LPC@ RE370 1 1 2
B2 L7 2 24.9_0402_1% SHD_IO2_R1 LPC@ RE371 1 2 45.3_0402_1% SHD_IO2_R2
LOM_CABLE_DETECT# <29> EN_INVPWR PRIM_PWRGD_GPIO024 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 LPC@ RE372 1 RE324 100K_0402_5%
2 1 C1 M6 2 24.9_0402_1% SHD_IO3_R1 LPC@ RE373 1 2 45.3_0402_1% SHD_IO3_R2
@ RE505 100K_0402_5% IMVP_VR_ON_EC N7 GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 Place near UE9
<35> IMVP_VR_ON_EC Place near UE1 +3.3V_ALW
2 1 USH_DET# K9 GPIO031/GPTP-OUT1 D6
<11,35> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <37>
@ RE526 10K_0402_5% N8 C7 SHD_IO2_R1
BCM5882_ALERT# <11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <35,66> 1 2
2 1 A5 RE59 close to UE2 at least 250mils
VCI_OUT ALWON <58> +PECI_VREF LPC@ RE376 1K_0402_5%
F13 D5 2 1 SHD_IO3_R1
GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <35> +1.0V_VCCST
E13 B5 0_0402_5% RE59 @
<57,67> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2# LPC@ RE377 1K_0402_5%
0.1U_0201_10V6K
C13 D4 SHD_CS#
<37> USH_DET# GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_WAKE# 1 2
GPIO126 E12 E4 POA_WAKE# <37> LPC@ RE98 4.7K_0402_5%
1
GPIO126/PVT_IO3 GPIO000/VCI_IN3#
CE25
RTCRST_ON_GPIO122 F11
F12 GPIO122/BCM0_DAT/PVT_IO1 C6
2
D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <47> +3.3V_ALW
RPE10 <45> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
CV2_ON_R D13 F3 @ CE54 1 2 10P_0402_50V8J LPC@ UE9
8 1 <45> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT SHD_CS#
IMVP_VR_ON_EC 8 1
7 2 SHD_IO3_R2 VCC CS# SHD_IO1_R2
PCH_ALW_ON <32> SLOT2_CONFIG_3
F4 7 2
6 3 GPIO041/SYS_SHDN# +PECI_VREF SHD_CLK_R1 HOLD#(IO3) DO(IO1) SHD_IO2_R2
RUN_ON_EC RE57 2 1 1K_0402_5% B1 J11 6 3
5 4 +3.3V_ALW2 SIO_EXT_SMI#_EC SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R SHD_IO0_R2 CLK WP#(IO2)
K7 K13 RE60 1 2 43_0402_5% 5 4
PECI_EC <12>
1
SIO_RCIN#_EC N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 M3042_PCIE#_SATA DI(IO0) GND

100K_0804_8P4R_5% GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N PAD~D @ T269 REM_DIODE1_N
100K_0402_5%
K6 A8 CE24 1 2 2200P_0402_50V7K W25Q80DVSSIG_SO8

<8> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_P REM_DIODE1_N <35>
RE58
TBT_RESET_N_EC_R H7 A7
1 2 <8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE2_N REM_DIODE1_P <35>
K1 A10 CE26 1 2 2200P_0402_50V7K
@ RE95 100K_0402_5% <35> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_P REM_DIODE2_N <35>
G7 A9
REM_DIODE2_P <35>
2
<8,35> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9

<8,35> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8
<8,35> ESPI_IO0 EXPANDER_GPU_SMDAT @ CE504 1 2 10P_0402_50V8J
L4 GPIO070/LAD0/ESPI_IO0 DP3_DN3A A11 REM_DIODE4_N CE27 1 2 2200P_0402_50V7K REM_DIODE4_N
B <8,35> ESPI_IO1 REM_DIODE4_N <35> B
+3.3V_ALW G6 GPIO071/LAD1/ESPI_IO1 DN4_DP4A B10 REM_DIODE4_P REM_DIODE4_P
<8,35> ESPI_IO2 REM_DIODE4_P <35> EXPANDER_GPU_SMCLK @ CE505 1 2 10P_0402_50V8J
L5 GPIO072/LAD2/ESPI_IO2 DP4_DN4A C10 +VR_CAP
100K_0402_5%
<8,35> ESPI_IO3 CLKRUN#_EC GPIO073/LAD3/ESPI_IO3 VIN VSET_5105

L2 C9
VSET_5105 <35>
2
SIO_EXT_SCI#_EC M1 GPIO067/CLKRUN# VSET B11

I_ADP <66>
RE63
SYS_PWROK G4 GPIO100/nEC_SCI VCP H3 THERMATRIP2#
VSS_ANALOG
THERMATRIP2# <35> I_BATT_R CE3 1 2 2200P_0402_50V7K
<11,14> SYS_PWROK L12 GPIO106/PWROK GPIO103/THERMTRIP2# B12 THERMATRIP1#
<6,29> ENVDD_PCH GPIO107/nSMI THERMTRIP1# H_PROCHOT#_R1 THERMATRIP1# <48>
VSS_ADC
H13 1 2 I_SYS_R
VSS_PLL
CE4 1 2 2200P_0402_50V7K
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# RE288 100_0402_5% H_PROCHOT# <12,63,66>
1
MEC_XTAL2_R A3 XTAL1
VSS1
VSS2
VSS3
XTAL2
JTAG_RST#
PCH_RSMRST# 1 2
MEC5105_WFBGA169_11X11
RE342 10K_0402_5%
A6
A13
E6
H4
1+VR_CAP J1
C4
G1
RE94
1U_0402_6.3V6K
SYS_PWROK 1 2
1
1 2
PCH_RTCRST# <11> RE56 10K_0402_5%
1U_0402_6.3V6K
75_0402_5% I_SYS_R
1
1 2
1
1
D
@SHORT PADS~D
JTAG1 @
100_0402_1%
+VSS_PLL
@
RE313 10K_0402_5%
1
RTCRST_ON_GPIO141 RTCRST_ON
@ RE65
1 2 2 QE12 LCD_TST 1 2
CE30
@ RE514 0_0402_5% G L2N7002WT1G_SC-70-3 RE20 100K_0402_5%
1
RTCRST_ON_GPIO122 1 2 S EN_INVPWR 1 2
2
3
@ RE515 0_0402_5% RE93
2
RE55 100K_0402_5%
CE31
PORT80_DET# 1 2
2
2
100K_0201_5%
@ RE513 100K_0402_5%
2
2
For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362
For MEC5105 Rev.B/C:Depop RE361,Pop RE360,RE362
For WDT issue fix options&assessment:Pop RE361, Depop RE362 +3.3V_RUN
SHD_IO2 @ RE360 1 2 0_0402_5% 1.8V_PRIM_PWRGD <62> +3.3V_ALW
2
+3.3V_ALW
10K_0402_5% DMN65D8LDW-7_SOT363-6
PRIM_PWRGD_GPIO024 @RE361 1 2 49.9K_0402_1%

For EMI request
RE67
VGA_ID 1 2
RE362 1 2 100K_0402_5% ESPI_CLK_5105 @ RE84 100K_0402_5%
+3.3V_ALW VGA_ID 1 2
100K_0402_5%
1
2
GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI) RUNPWROK RE85 100K_0402_5%
33_0402_5%
1
GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI)
@EMI@
RE68
MEC_XTAL2_R
RE350
PCH_RSMRST#_GPIO204 LPC@ RE363 1 2 0_0402_5%
3
PCH_RSMRST# <45>
1
QE2B
2
1
@ SHD_CS# 1 2
33P_0402_50V8J
RE290 @ESPI@ RE364 0_0402_5% RUN_ON# 5
32 KHz Clock
@EMI@
A A
0_0402_5% VGA_ID0
1
CE57
Discrete 0
2
2
YE1
QE2A
MEC_XTAL1 1 2 MEC_XTAL2 UMA 1

8/28 schematic review
2
<17,35,47,61> RUN_ON
10P_0402_50V8J
10P_0402_50V8J
32.768KHZ_9PF_X1A000141000200
1
1
CE28
CE29
2
LPC@ RE337 1 2 0_0402_5% CLKRUN#_EC Compal Electronics, Inc.

<8> CLKRUN# Title
SIO_EXT_SMI#_EC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
LPC@ RE338 1 2 0_0402_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
<12> SIO_EXT_SMI# LPC@ RE339 1 2 0_0402_5% SIO_RCIN#_EC
EC MEC5105
<8> SIO_RCIN# LPC@ RE341 1 2 0_0402_5% SIO_EXT_SCI#_EC Size Document Number Rev
<9> SIO_EXT_SCI# NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+1.8V_3.3V_ALW_VTR3
For BR DSC
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
1
<11> PCH_PLTRST#_EC A 4
3 Y PCH_PLTRST#_5105 <34>
GND
74AUP1G07GW_TSSOP5 +RTC_CELL
PCIE_WAKE# <32,40>
1
100K_0402_5%
RE31
@ CE10
1 2 2 1 1 2
<34> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,34>
0_0402_5% RE275 @ 0_0402_5% @ RE274
1U_0402_6.3V6K
2
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<34> POWER_SW_IN# POWER_SW#_MB <11,46>
RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
ESPI LPC
2.2U_0402_6.3V6M
1
PAGE
D D
CE12
2 1
2
0_0402_5% @ RE304
+3.3V_RUN
JESPI
1
2
1
2
3 ESPI_IO0 <8,34>
8 RC25_10K RC8_15ohm +3.3V_ALW
+3.3V_ALW
@ CE53
1 2
3
RC13/RC27_8.2K
+3.3V_ALW
100K_0402_5%
4 ESPI_IO1 <8,34> UE4
4
1
RE25
5 ESPI_IO2 <8,34> 0.1U_0402_25V6K
5
5
6 1 5
6 7 ESPI_IO3 <8,34> IMVP_VR_ON_EC 1 NC VCC
P
ESPI_CS# <8,34> <34> IMVP_VR_ON_EC
7 8 LPC@ RE375 1 20_0402_5% PCH_PLTRST#_EC B 4 IMVP_VR_ON 2
11 8 9 SIO_SLP_S3# 2 O A 4
RE26 <11,34,35> SIO_SLP_S3#
2
GND 9 LID_CL_NB# A Y VCCST_PWRGD <11,14,34>
G
12 10 2 1 UE3 3
GND 10 ESPI_CLK_5105 <8,34> <34> LID_CL_NB# LID_CL# <46> GND
.047U_0402_16V7K
TC7SH08FU_SSOP5~D
3
JXT_FP241AH-010GAAM
18 RC212_0ohm RC211_0ohm 10_0402_5% 74AUP1G07GW_TSSOP5
1
CONN@
CE8
RF Request
2
IMVP_VR_ON <63>
0603 0603 +3.3V_ALW

J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
1 2
0_0402_5% @ RE280
68P_0402_50V8J
1
RUN_ON_EC
RF@ CE61
2 1
<34> RUN_ON_EC RUN_ON <17,34,47,61>
0_0402_5% @ RE292
RE337,RE338
2
+3.3V_ALW
@ CE52
LPC 80Port Debug LPC ESPI
RE339,RE340, 1 2
31 0.1U_0402_25V6K
5
1 +3.3V_RUN +3.3V_RUN
RE341 1
P
B 4
2 O
2 +3.3V_RUN +3.3V_RUN A
G
UE5
0_ohm TC7SH08FU_SSOP5~D
3
3 LPC_LAD0 ESPI_IO0
4 LPC_LAD1 ESPI_IO1
+3.3V_ALW +3.3V_ALW
5 LPC_LAD2 ESPI_IO2
RE2 / RE3
+3.3V_ALW
1
C
6
7
LPC_LAD3
LPC_FRAME#
ESPI_IO3
ESPI_CS#
32 0_ohm RE343
240K_0402_5%
RE79
4.3K_0402_5%
RE300
130K_0402_5%
C
2
BOARD_ID PANEL_ID
<34> TYPEC_ID <34> BOARD_ID <34> PANEL_ID
8 PCH_PLTRST# NA
1
CE62 CE40 CE47
9 GND GND 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
2
10 LPC_CLOCK ESPI_CLK
RE343 CE62 REV RE79 CE40 REV RE300 CE47 PANEL SIZE
Single Port ACE w/o AR
* 240K 4700p 240K 4700p X00 240K 4700p 12"
130K 4700p Single Port ACE w/AR 130K 4700p X01 * 130K 4700p 14"
62K 4700p Dual Port ACE w/o AR 62K 4700p X02 33K 4700p 15"
WDT opt i on +3.3V_ALW
@ UE7 33K 4700p Dual Port ACE w/AR 33K 4700p X03 4.3K 4700p 17"
MEC5105 rev.B Pop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348 5 1
Dual Port ACE (w/AR +w/o AR)
1
VDD RESET PCH_DPWROK <11>
8.2K 4700p 8.2K 4700p X04
Depop RE362, RE536, RE537 @CE6 3 4
MR CT 4700p * 4.3K 4700p A00
2
Pop RE362, RE536, 4700p

1
2 @RE348
MEC5105 rev.C @CE5
Depop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348, RE537 10K_0402_5% RT9826-30GB
3300P_0402_50V7-K 1K 4700p 1K 4700p PANEL_ID rise t i mei s meas ur ed fr o m5 %~68 %.
2
1
1 2 1 2
<34> PCH_DPWROK_EC @ RE34 RE536 PD_ACE_DET# rise t i mei s meas ur ed fr o m5 %~68 %. BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %.
0_0402_5% 0_0402_5%
VSET_5105
GPIO223 is OD. When EC fetches
CT: 3300 pF ~ 10ms delay
2
VSET_5105 <34>
the code, set GPIO223 to Low. @ RE537
0.1U_0402_25V6
@RE530 1M_0402_5%
1
1.69K_0402_1%
2 1 10K_0402_5%
<34,35,66> ACAV_IN SHD_IO0 <34>
Reset Threshold Level 3.0V
1
1U_0402_6.3V6K
CE38
RE77
1
2
1
CE503
+3.3V_ALW
2
2
8
7
6
5
10K_8P4R_5%
49.9_0402_1%
RE71
5
RPE7
Rest=1.69K , Tp=97 degree
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
To prevent backdrive to PCH_DPWROK_EC
@ RE75
4 3 6 1
<34,35,66> ACAV_IN when AC is plugged before +3.3V_ALW ramps up.
1
2
3
4
RE72
RE73
RE74
B JDEG1 B
1 +EC_DEBUG_VCC
@QE13B @QE13A 1 2 JTAG_TDI Link 50271-0040N-001 DONE
2
DMN65D8LDW-7_SOT363-6 2 3 JTAG_TMS JTAG_TDI <34>
DMN65D8LDW-7_SOT363-6 JFAN1
3 4 JTAG_CLK JTAG_TMS <34> 1
4 5 JTAG_TDO JTAG_CLK <34> 1 2 FAN1_PWM
RE86
5 6 JTAG_TDO <34> 2 3 FAN1_TACH FAN1_PWM <34>
MSCLK 10K_0402_5%
6 7 1 2 +3.3V_RUN 3 4 FAN1_TACH <34>
MSDATA
In DC mode, ACAV_IN is LOW. This circuit doesn't af f ect PCH_ DP WR OK. 7 8 HOST_DEBUG_TX 4 +5V_RUN
In AC mode, 1. ACAV_IN is high. GPIO223 is tri-state. QE13B is ON. QE13A can prevent backdrive to PCH_DPWROK. 8 DEBUG_TX
10U_0603_6.3V6M
11 9 5
GND 9 GND1
1
2. EC fetches code and the drives GPIO223 to LOW to turn of f QE13B. When QE13Bi s off, un-pl ug/pl ug AC will not af fec t DS W_ DP WRO 12
GND 10
10
FAN1_PWM GND2
6
@ DE1
3. When WDT occurs, GPIO223 is tri-state (EC reset). ACAV_IN charges CE503. When AC is removed, ACAV_IN goes LOW immediately. 1 2 1 2
<9> SBIOS_TX
CE32
JXT_FP241AH-010GAAM @ RE306 RE48 10K_0402_5% ACES_50271-0040N-001
QE13B st ill kepps on acc or di ng t o RC di sc har gi ngr at e. PCH_ DP WR OKi s L O Wbecaus e ACAV_I Ni s L O W
. 0_0402_5% 1 2 FAN1_TACH CONN@
CONN@
2
RE51 10K_0402_5%
HOST_DEBUG_TX <32,34>
2
MSDATA <34>
1 2 MSCLK <34>
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
@ RE30 0_0402_5%
Control Byte Thermal diode mapping

0 1 0 0 A2 A1 A0 R/W
5085 Channel Locat i on
R/W = 0 = Write Place under CPU
R/W = 1 = Read Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
REM_DIODE1_P <34>
100P_0402_50V8J
DP2/DN2 WiGig (QE5)
1
C
+3.3V_ALW
@ CE35
1 2
1
SMBus address 0x40 DN2a/DP2a

0.1U_0402_25V6K
1U_0402_6.3V6K
DDR (QE7) B
1
E QE3
3
CE1
CE2
LMBT3904WT1G SC70-3
2
2
DP3/DN3 NA REM_DIODE1_N <34>
+3.3V_ALW
DP2/DN2 for WiGig on QE5, place QE5 close
DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
UE2
1
+3.3V_ALW
10K_0402_5%
10K_0402_5%
10K_0402_5%
18
VSTBY33
@ RE13
@ RE15
@ RE17
19
DP4/DN4 for Skin on
<34,48> EXPANDER_GPU_SMCLK SCL QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
1
10K_0402_5%
20 RE69
<34,48> EXPANDER_GPU_SMDAT SDL Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
16 1 2
+3.3V_ALW THERMATRIP2# <34>
2
GP7 VBUS2_ECOK <57,67> +1.0VS_VCCIO

RE6
1 15
2 A2 GP6 14 DCIN2_EN <57> REM_DIODE4_P <34> REM_DIODE2_P <34>
8.2K_0402_5%
LMBT3904WT1G SC70-3
A1 GP5 SATA_LED_EN <46> SIO_SLP_S3# <11,34,35>
1
LMBT3904WT1G SC70-3
CE36
100P_0402_50V8J
3 13 @ QE11
VBUS1_ECOK <67>
2
A0 GP4
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
12 E C
G
GP3 DCIN1_EN <67>
1
@ CE46
WRST# WRST# 4 11 C C B
2 2
2
WRST# GP2 DGPU_PWROK <12,52,68>
1
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
QE4
@CE39
A 10 1 3 1 2 2 2 B A
GPU_PWR_LEVEL <48>
2
EXPANDER_ALERT# GP1
1
1U_0402_6.3V6K
7 9 RE70 2.2K_0402_5% B B C E QE5

D
T267 @ PAD~D
3
INT GP0 USH_PWR_STATE# <37> +1.0V_VCCST
RE14
RE16
RE18
E E QE6 LMBT3904WT1G SC70-3
3
CE500
5 L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3

2
6 NC
2
8 NC 17 1 2 REM_DIODE2_N <34>
NC VSS <12,20,21> H_THERMTRIP# REM_DIODE4_N <34>
21 @ RE90 0_0402_5%
EPAD
MCP23008T-E-ML_QFN20_4X4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5105 Support
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
For NUVOTON TPM

+UZ12_TPM
place CZ50, CZ75 as close as UZ12.8
@ RZ89 1 2 0_0402_5%
+3.3V_RUN
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1
CZ75
CZ50
D 2 2 D
+3.3V_ALW_PCH +3.3V_M_TPM RF Request RF Request

PJP391
1 2 +3.3V_ALW +3.3V_M_TPM
PAD-OPEN1x1m
+3.3V_ALW
+3.3V_M_TPM
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
TPM_PIRQ# 1 1 1 1
1 2
0.1U_0201_10V6K
10U_0603_10V6M
RZ69 10K_0402_5%
1 1 place CZ51,CZ52 as close as UZ12.1 2 2 2 2
+3.3V_RUN
CZ51
CZ52
1
2 2
@ RZ362
10K_0402_5%
UZ12
1 +3.3V_M_TPM
2
1 2 29 VSB
<11,17,61> SIO_SLP_S0# 30 GPIO0/SDA/XOR_OUT 8 +UZ12_TPM
@ RZ112 0_0402_5%
1 2 TPM_LPM# 3 GPIO1/SCL VDD 14
@ RZ363 0_0402_5% 6 GPIO2/GPX VHIO 22
GPIO3/BADD VHIO
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
C RZ58 1 2 33_0402_5% PCH_SPI_D1_2_R 24 2 1 1 1
C
<8> PCH_SPI_D1_R1 RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 LAD0/MISO NC 7
<8> PCH_SPI_D0_R1 LAD1/MOSI NC
CZ53
CZ54
CZ55
18 10
<9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11
LAD3 NC 25 2 2 2
EMI@ RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC 26
<8> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% PCH_SPI_CS#2_R 20 LCKL/SCLK NC 31
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9
TPM_GPIO4 13 SERIRQ GND 16
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND
28 23 CZ53,CZ55 as close as UZ12.14
LPCPD# GND
1
10K_0402_5%
32 CZ54 as close as UZ12.22
GND
RZ62
4 33
5 PP PGND 12
TEST Reserved
2
JB2YX change to VB2YX 09/08
PCH_SPI_CLK_2_R
33_0402_5%
2
@EMI@
RZ63
B B
1
0.1U_0402_25V6
1
@EMI@
+3.3V_M_TPM
CZ56
2
S
PCH_SPI_CS#2_R 1 2 2
G LP2301ALT1G_SOT23-3
@ RZ113 100_0402_5% @ QZ9
D
1
TPM_LPM#
1
@ RZ111
RZ113 RZ111 POP 10K_0402_5%
1K 1K MMBT3906
2
100 10K LP2301A
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH & TPM
1.0
5 4 3 2 1
5 4 3 2 1
For ATMEL TPM
D D
+3.3V_ALW
1 2 USH_SMBCLK
RZ8 2.2K_0402_5%
1 2 USH_SMBDAT
RZ9 2.2K_0402_5%
1 2 USH_PWR_STATE#
RZ10 100K_0402_5%
USH CONN
C C
JUSH1
@ RZ85 1 2 0_0402_5% +PWR_SRC_R 1
+PWR_SRC 1
2
3 2
<34> CV2_ON 4 3
<34> POA_WAKE# 5 4
<34> EC_FPM_EN 6 5
7 6
8 7
<10> USB20_N10 9 8
<10> USB20_P10 10 9
11 10
<34> USH_SMBCLK 12 11
<34> USH_SMBDAT 13 12
<34> BCM5882_ALERT# 14 13
14
15
17 16
17
18
19
@ RZ114 1 2 0_0402_5% 21 20
<11,31,32,40> PCH_PLTRST#_AND 22 21
<35> USH_PWR_STATE# 23 22
<12> CONTACTLESS_DET# 24 23
25 24
@ RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<34> USH_DET# 26
@ DZ7 27
2 1 28 GND1
GND2
B RB751S40T1G_SOD523-2 B
CVILU_CF5026FD0RK-05-NH
CONN@
Link CVILU_CF5026FD0RK-05-NH
PCH_PLTRST#_AND Close to JUSH1
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
.047U_0402_16V7K
ESD@ CZ61
1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
CZ64
CZ66
CZ67
CZ68
For ESD solution 2 2 2 2
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW RF Request

RF Request
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
USH_SMBCLK 1 2 1 1 1 1
@RF@CZ62 68P_0402_50V8J
USH_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH & TPM
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
+3.3V_RUN
For Parade 2 Lane solution
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
vinafix
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@ RN51
1
1
@ RN25
@ RN26
@ RN27
@ RN28
RN49
RN50
RN42
RN43
RN44
PCIE/SATA Redriver for 2280
2
Brekenridge12 Need
2
2
RD1_A_DE0
RD1_B_EQ0 RD1_A_EQ0 Brekenridge14U UMA Need
RD1_A_DE1
RD1_B_EQ1 RD1_A_EQ1
D
RD1_B_DE0 Brekenridge14U DSC Need D
RD1_B_EQ2 RD1_A_EQ2
RD1_B_DE1
Brekenridge15U UMA Need
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@ RN52
@ RN53
@ RN54
@ RN179
@ RN176
@ RN174
Brekenridge15U DSC Need
1
1
@ RN39
@ RN41
RN38
RN40
Steamboat12 No need
2
2
2
Steamboat14 Need
Kirkwood12&13 Check
+3.3V_RUN
Programmable output de-emphasis level
0.1U_0201_10V6K
set t i ng for channel A.
0.01UF_0402_25V7K
1 1
A_DE0: internally pulled up at ~150K;
CN20
PWD Funtion
CN21
A_DE1 internally pulled down at ~150K
2 2
[A_DE1,A_DE0] == 0 Normal mode(default)
LL: -2dB
HL:
LH:
-7.5dB
-3.5dB (default)
PCIE/SATA Repeater 1 power down mode
HH: -6dB UN4
12
24 VDD_3.3
VDD_3.3
0.22U_0402_10V6K 1 2 CN22 PCIE_PTX_C_RD_DRX_P11 1 18
Programmable output de-emphasis level <10> PCIE_PTX_DRX_P11
0.22U_0402_10V6K 1 2 CN23 PCIE_PTX_C_RD_DRX_N11 2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_P11 <39>
C set t i ng for channel B
. <10> PCIE_PTX_DRX_N11 A_INN A_OUTN PCIE_PTX_RD_DRX_N11 <39> C
B_DE0: internally pulled up at ~150K;
1 2 CN26 PCIE_PRX_C_RD_DTX_P11 5 14
B_DE1 internally pulled down at ~150K <10> PCIE_PRX_DTX_P11
0.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_N11 B_OUTP B_INP PCIE_PRX_RD_DTX_P11 <39>
0.22U_0402_10V6K 1 2 CN27 4 15
<10> PCIE_PRX_DTX_N11 B_OUTN B_INN PCIE_PRX_RD_DTX_N11 <39>
[B_DE1,B_DE0] == RD1_A_EQ0 23 6 RD1_A_DE0
LL: -2dB RD1_A_EQ1 22 A_EQ0 A_DE0 8 RD1_A_DE1
RD1_A_EQ2 19 A_EQ1 A_DE1
HL: -7.5dB A_EQ2
LH: -3.5dB (default) +3.3V_RUN if signal is PCIE GEN3/SATA GEN3 maybe change C value RD1_B_EQ0 11 RD1_B_DE0
+3.3V_RUN or no need for DG0.9 SATA EXPRESS HDD 13
HH: -6dB RD1_B_EQ1 21 B_EQ0 B_DE0 9 RD1_B_DE1
RD1_B_EQ2 16 B_EQ1 B_DE1
10K_0402_5%
B_EQ2
1
100K_0402_5%
1
RN65
3
PWD RD1_REXT
RN171
7 10 RN30 1 2 4.99K_0402_1%
25 GND REXT 20 M2280_PCIE_SATA#
Equalizer control and program for channel A. EPAD MODE M2280_PCIE_SATA# <10,39>
A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K
2
2
IFDET_SATA_PCIE# RD2_A_EQ2_R 1 2 RD2_A_EQ2 PS8558BTQFN24GTR2-A_TQFN24_4X4

[A_EQ2,A_EQ1,A_EQ0] ==
6
3
LLL: For channel loss up to 17dB (default)
LHL: For channel loss up to 14dB

HLL: For channel loss up to 19dB M2280_PCIE_SATA# 2 IFDET_SATA_PCIE# 1 2 5 0 SATA
QN4A
QN4B
HHL: For channel loss up to 21dB RN192 0_0402_5%
LLH: For channel loss up to 18dB
1
4
M2280_PCIE_SATA# 1 2
LHH: For channel loss up to 10dB 1 PCIE
@ RN182 0_0402_5%
HLH: For channel loss up to 16dB
100K_0402_5%
1
HHH: For channel loss up to 20dB @
Equalizer control and program for channel B. RN183

B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K
2
+3.3V_RUN
[B_EQ2,B_EQ1,B_EQ0] ==
B
LLL: For channel loss up to 17dB (default) +3.3V_RUN +3.3V_RUN B
LHL: For channel loss up to 14dB
0.1U_0201_10V6K
HLL: For channel loss up to 19dB
0.01UF_0402_25V7K
1 1
10K_0402_5%
10K_0402_5%
CN30
CN31
HHL: For channel loss up to 21dB
1
LLH: For channel loss up to 18dB

RN64
RN63
LHH: For channel loss up to 10dB 2 2

HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB PCIE/SATA Repeater
2
RD2_A_EQ0_R 1 2 RD2_A_EQ0
RD2_A_EQ1_R 1 2 RD2_A_EQ1 RN225 0_0402_5%
6
RN224 0_0402_5%
UN5
3
12
IFDET_SATA_PCIE# 1 2 2 24 VDD_3.3
IFDET_SATA_PCIE# VDD_3.3
QN5A
RN186 0_0402_5% 1 2 5
2 CN32 PCIE_PTX_C_RD_DRX_P12
QN5B
RN189 0_0402_5% 0.22U_0402_10V6K 1 1 18

1
M2280_PCIE_SATA# <10> PCIE_PTX_DRX_P12 A_INP A_OUTP PCIE_PTX_RD_DRX_P12 <39>

1 2 0.22U_0402_10V6K 1 2 CN33 PCIE_PTX_C_RD_DRX_N12 2 17
<10> PCIE_PTX_DRX_N12
4
@ RN184 0_0402_5% M2280_PCIE_SATA# 1 2 A_INN A_OUTN PCIE_PTX_RD_DRX_N12 <39>

100K_0402_5%
@ RN187 0_0402_5%
1
PCIE_PRX_C_RD_DTX_P12
100K_0402_5%
@ 0.22U_0402_10V6K 1 2 CN36 5 14
<10> PCIE_PRX_DTX_P12 B_OUTP B_INP PCIE_PRX_RD_DTX_P12 <39>
1
+3.3V_RUN PCIE_PRX_C_RD_DTX_N12
RN185
@ 0.22U_0402_10V6K 1 2 CN37 4 15
+3.3V_RUN <10> PCIE_PRX_DTX_N12 B_OUTN B_INN PCIE_PRX_RD_DTX_N12 <39>
RN188
RD2_A_EQ0 23 6 RD2_A_DE0
RD2_A_EQ1 22 A_EQ0 A_DE0 8 RD2_A_DE1
2
RD2_A_EQ2 19 A_EQ1 A_DE1

if signal is PCIE GEN3/SATA GEN3 maybe change C value
2
A_EQ2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
or no need for DG0.9 SATA EXPRESS HDD

1
RD2_B_EQ0 11 RD2_B_DE0
@ RN55
@ RN56
@ RN57
@ RN58
10K_0402_5%
10K_0402_5%
10K_0402_5%
13
B_EQ0 B_DE0
1
RD2_B_EQ1 21 RD2_B_DE1
@ RN71
9
RD2_B_EQ2 16 B_EQ1 B_DE1
RN69
RN70
B_EQ2
3
2
7 PWD 10 RD2_REXT RN31 1 2 4.99K_0402_1%

2
25 GND REXT 20 M2280_PCIE_SATA#

RD2_A_DE0 EPAD MODE
RD2_A_DE1 PS8558BTQFN24GTR2-A_TQFN24_4X4
RD2_B_EQ0
RD2_B_DE0
A RD2_B_EQ1 A
RD2_B_DE1
RD2_B_EQ2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
@ RN60
@ RN62
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
RN59
RN61
@ RN72
@ RN73
@ RN74
2

2
SATA/PCIE REPEATER for M.2 2280
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-E082P 1.0

5 4 3 2 1
5 4 3 2 1
For Breckenridge 14/15 DSC
D D
NEED LINK TI hd3ss3415 as main

+3.3V_RUN
0.1U_0201_10V6K
0.01UF_0402_25V7K
1 1
CN52
CN53
2 2
UN8
9 37
C 19 VDD B0+ 36 PCIE_PRX_MUXA_DTX_P12 <41> C
26 VDD B0- 33 PCIE_PRX_MUXA_DTX_N12 <41>
34 VDD B1+ 32 PCIE_PTX_MUXA_DRX_P12 <41>
41 VDD B1- 28 PCIE_PTX_MUXA_DRX_N12 <41>
Spindle HDD(MUXA) VDD B2+ 27
1 B2- 24
<38> PCIE_PRX_RD_DTX_P12 2 A0+ B3+ 23
<38> PCIE_PRX_RD_DTX_N12 5 A0- B3-
<38> PCIE_PTX_RD_DRX_P12 6 A1+ 3
<38> PCIE_PTX_RD_DRX_N12 10 A1- C0+ 4 PCIE_PRX_MUXB_DTX_P12 <40>
<38> PCIE_PRX_RD_DTX_P11 11 A2+ C0- 7 PCIE_PRX_MUXB_DTX_N12 <40>
+3.3V_RUN
<38> PCIE_PRX_RD_DTX_N11 14 A2- C1+ 8 PCIE_PTX_MUXB_DRX_P12 <40>
<38> PCIE_PTX_RD_DRX_P11 15 A3+ C1- 12 PCIE_PTX_MUXB_DRX_N12 <40>
<38> PCIE_PTX_RD_DRX_N11 A3- C2+ 13 PCIE_PRX_MUXB_DTX_P11 <40> HDD_DET# 2 1
21 C2- 16 PCIE_PRX_MUXB_DTX_N11 <40> M2 2280(MUXB) 10K_0402_5% RN124
25 NC C3+ 17 PCIE_PTX_MUXB_DRX_P11 <40>
NC C3- PCIE_PTX_MUXB_DRX_N11 <40>
Co-lay with 2nd part 35 NC 18
39 NC GND 20
NC GND 22
GND 29
HDD_DET# 30 GND 38
GND 40
GND 42
GND 43
center pad
HD3SS3415RUAR_WQFN42_9X3P5
B B
IFDET_SATA#_PCIE HDD_SEL(HDD_DET#)
L SATA L Spindle HDD(MUXA)
H PCIE H M.2 2280(MUXB)
DN1
2 HDD_DET#
HDD_DET# <12,41>
1
<10,38> M2280_PCIE_SATA#
3
IFDET_SATA#_PCIE_D <40>
BAT54AW-7-F_SOT323-3
A A
PROPRIETARY NOTE:
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SATA/PCIE DEMUX
LA-E082P 1.0

5 4 3 2 1
5 4 3 2 1
For Breckenridge 14/15 DSC
RF Request +3.3V_HDD_M2
+3.3V_HDD_M2
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1 @ 1
1
68P_0402_50V8J
@RF@CN60
CN61
CN62
CN63
CN64
1
2
2 2
2 2280 SSD
NGFF slot C Key M

Place near HDD CONN
+3.3V_HDD_M2 2.8A
JNGFF3 PJP31
1 2 1 2
+3.3V_RUN
3 1 2 4
5 3 4 6 PAD-OPEN1x3m
7 5 6 8
9 7 8 10 NVME_LED# 1 2
11 9 10 12 SATALED# <10,32,46>
+3.3V_HDD_M2 @ RN100 0_0402_5%
13 11 12 14
15 13 14 16
1 2 M2280_DEVSLP 17 15 16 18
@ RN37 10K_0402_5% if signal is PCIE GEN3/SATA GEN3 maybe change C value 19 17 18 20
or no need for DG0.9 SATA EXPRESS HDD 21 19 20 22
C 23 21 22 24 C
25 23 24 26
27 25 26 28
2 1 PCIE_PRX_MUXB_C_DTX_N11 29 27 28 30
<39> PCIE_PRX_MUXB_DTX_N11 0_0402_5%2 1 RN82 @ PCIE_PRX_MUXB_C_DTX_P11 31 29 30 32
<39> PCIE_PRX_MUXB_DTX_P11 0_0402_5% RN81 @ 33 31 32 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_MUXB_C_DRX_N11 35 33 34 36
<39> PCIE_PTX_MUXB_DRX_N11 PCIE_PTX_MUXB_C_DRX_P11 37 35 36
CN70 2 1 0.22U_0402_10V6K 38
<39> PCIE_PTX_MUXB_DRX_P11 39 37 38 40 M2280_DEVSLP <10,41>
2 1 PCIE_PRX_MUXB_C_DTX_P12 41 39 40 42
<39> PCIE_PRX_MUXB_DTX_P12 0_0402_5%2 1 RN77 @ PCIE_PRX_MUXB_C_DTX_N12 43 41 42 44
<39> PCIE_PRX_MUXB_DTX_N12 0_0402_5% RN78 @ 45 43 44 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_MUXB_C_DRX_N12 47 45 46 48
<39> PCIE_PTX_MUXB_DRX_N12 PCIE_PTX_MUXB_C_DRX_P12 49 47 48
CN72 2 1 0.22U_0402_10V6K 50
<39> PCIE_PTX_MUXB_DRX_P12 51 49 50 52 PCH_PLTRST#_AND <11,31,32,37>
53 51 52 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
53 54 PCIE_WAKE# <32,35>
55 56
57 58
67 68 SUSCLK_R 1 2
69 67 68 70 @ RN99 SUSCLK <11,32>
0_0402_5%
<39> IFDET_SATA#_PCIE_D 71 69 70 72
73 71 72 74
75 73 74
75
77 76
B GND1 GND2 B
LCN_DAN05-67356-0103
CONN@
Link LCN_DAN05-67356-0103 DONE
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, M2 2280 Socket
1.0
5 4 3 2 1
5 4 3 2 1
For Breckenridge 14/15 DSC +5V_HDD
1
100K_0402_5%
@ RN1
+3.3V_RUN
2
1
100K_0402_5%
FFS_INT2_Q
RN2
3
2
QN1B
D D
5
4
6
QN1A
FFS_INT2 2
1
+3.3V_RUN
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
C C
1
Free Fall Sensor
CN1
CN2
CN3
2
2
LGA1
LNG2DM
10 5 INT1/IN2:Push-Pull,active high
9 VDD_IO RES
VDD 12
3 INT 1 11 FFS_INT2 HDD_FALL_INT <9>
4 SDO/SA0 INT 2 FFS_INT2 <12>
<8,14,20,21> DDR_XDP_WAN_SMBDAT SDA/SDI/SDO
1 6
<8,14,20,21> DDR_XDP_WAN_SMBCLK SCL/SPC GND 7
2 GND 8
CS GND
LNG2DMTR_LGA12_2X2
+3.3V_HDD
1 2 M2280_DEVSLP
@ RN3 10K_0402_5%
CONN@
B JSATA1 B
1
CN4 2 1 0.01UF_0402_25V7K PCIE_PTX_MUXA_C_DRX_P12 2 1
<39> PCIE_PTX_MUXA_DRX_P12 2 1 0.01UF_0402_25V7K PCIE_PTX_MUXA_C_DRX_N12 3 2
CN5
<39> PCIE_PTX_MUXA_DRX_N12 4 3
CN6 2 1 0.01UF_0402_25V7K PCIE_PRX_MUXA_C_DTX_N12 5 4
<39> PCIE_PRX_MUXA_DTX_N12 CN7 2 1 0.01UF_0402_25V7K PCIE_PRX_MUXA_C_DTX_P12 6 5
<39> PCIE_PRX_MUXA_DTX_P12 7 6
PJP34 8 7
1 2 +3.3V_HDD 9 8
+3.3V_RUN 9
10
PAD-OPEN1x2m 11 10
<10,40> M2280_DEVSLP 12 11
HDD& M2 2280 MUX
13 12
<12,39> HDD_DET# 14 13
+5V_HDD +3.3V_HDD 15 14
16 15
+5V_HDD 16
17
18 17
FFS_INT2_Q 18
1000P_0402_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
19
+5V_RUN +5V_HDD 20 19
20
1
+3.3V_RUN
CN8
CN9
CN11
@ PJP33 @ 21
G1
CN10
2 1 22
23 G2
+5V_HDD source
2
2
24 G3
PAD-OPEN1x1m G4
1
@ RN4 PJP32
10K_0402_5% 1 2 1.5A+5V_HDD ACES_59003-02006-002
+5V_ALW UZ23
PAD-OPEN1x1m
2
1 7
HDD_EN 2 VIN VOUT 8 +5V_HDD_UZ23 1 2 Link 59003-02006-002 DONE
A VIN VOUT CZ129 0.1U_0201_10V6K A
3 6 1 2
Place near HDD CONN
<9> HDD_EN ON CT CZ130 470P_0402_50V7K
1
<BOM
RN5Structure> 4
10K_0402_5%
VBIAS
GND
5
9
GND
2
AOZ1336_DFN8_2X2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDD CONN
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_USB_UI5 USB3 Redriver for charge

+3.3V_RUN
1 2 Brekenridge12 No need
@ RI79 0_0603_5%
+3.3V_USB_UI5 Brekenridge14U UMA Need
+3.3V_ALW_PCH
D D
1 2 Brekenridge14U DSC Need

0_0603_5% @ RI80
0.01UF_0402_25V7K
0.1U_0402_16V4Z
1 1 Brekenridge15U UMA Need
CI38
CI37
2 2 Brekenridge15U DSC Need
LInk CIS ok Steamboat12 Need
UI5
1
13 VDD
VDD Steamboat14 Need
USB1_A_EQ1 15 4 USB1_B_EQ1
USB1_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB1_B_DE0 Kirkwood12&13 Check
USB1_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB1_B_EQ0
USB1_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB1_B_DE1
A_DE1/NC B_DE1/NC
CI39 2 1 0.1U_0402_10V7K USB3_PTX_C_RD_DRX_P1 19 12 USB3_PTX_RD_DRX_P1
<10> USB3_PTX_DRX_P1 USB3_PTX_C_RD_DRX_N1 20 A_INp A_OUTp USB3_PTX_RD_DRX_N1 USB3_PTX_RD_DRX_P1 <43>
+3.3V_ALW_PCH CI40 2 1 0.1U_0402_10V7K 11
<10> USB3_PTX_DRX_N1 A_INn A_OUTn USB3_PTX_RD_DRX_N1 <43>
1 2 USB1_TEST USB3_PRX_RD_DTX_P1 9 22 USB3_PRX_C_RD_DTX_P1 CI41 2 1 0.1U_0402_10V7K

<43> USB3_PRX_RD_DTX_P1 USB3_PRX_RD_DTX_N1 B_INp B_OUTp USB3_PRX_C_RD_DTX_N1 CI42 USB3_PRX_DTX_P1 <10>
@ RI34 4.7K_0402_5% 8 23 2 1 0.1U_0402_10V7K
<43> USB3_PRX_RD_DTX_N1 B_INn B_OUTn USB3_PRX_DTX_N1 <10>
1 2 USB3_PD# 5
<34,43> USB_PWR_SHR_VBUS_EN @ RI81 7 PD# 10
0_0402_5%
USB1_TEST 14 REXT GND 21
TEST GND
4.99K_0402_1%
C 24 25 C
I2C_EN GPAD
2
2K_0402_5%
0_0402_5%
@
RI35
@ PS8713BTQFN24GTR2_TQFN24_4X4
RI37
RI36
CPN: SA00005OR30
1
MPN: PS8713BTQFN24GTR2-A2
PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4
+3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH

+3.3V_ALW_PCH +3.3V_ALW_PCH
2
2
2
@ RI57
@ RI38 @ RI40 @ RI42 @ RI44 @ RI51 @ RI53 @ RI55 4.7K_0402_5%
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
B B
1
1
1
USB1_A_EQ1 USB1_A_EQ0 USB1_B_EQ1 USB1_B_EQ0 USB1_A_DE1 USB1_A_DE0 USB1_B_DE1 USB1_B_DE0
1
1
1
1
@ RI43 @ RI45 @ RI52 @ RI54 @ RI56
@ RI39 @ RI41 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% @ RI58
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
2
2
2
2
Parade_PS8713B
A_EQ1 A_EQ0 B_EQ1 B_EQ0 Recommended EQ A_DE1 A_DE0 B_DE1 B_DE0 Recommended DE
0 0 0 0 loss up to 9.5dB 0 0 0 0 3.5dB de-emphasis

A A
0 1 0 1 loss up to 13dB 0 1 0 1 No de-emphasis
1 0 1 0 loss up to 4.5dB 1 0 1 0 2.7dB de-emphasis

1 1 1 1 loss up to 7.5dB 1 1 1 1 5dB de-emphasis
Both A_EQ&B_EQ have internal pull-down 150k Both A_DE&B_DE have internal pull-down 150k PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB3.0 Repeater
1.0
5 4 3 2 1
5 4 3 2 1
For w/ Repeater
+5V_USB_CHG_PWR
JUSB1
1
USB20_N1_R VBUS
150U_B2_6.3VM_R35M
2
USB20_P1_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
3
DI4 ESD@ @ 4 D+
USB3_PRX_RD_DTX_N11 1 USB3_PRX_RD_DTX_N1 1 1 1 USB3_PRX_RD_DTX_N1 GND
CI17
10 9 5
SSRX-
<42> USB3_PRX_RD_DTX_N1 USB3_PRX_RD_DTX_P1
CI32
CI14
+ 6 10
SSRX+ GND
2
D USB3_PRX_RD_DTX_P1 2 2 9 8 USB3_PRX_RD_DTX_P1 7 11 D
<42> USB3_PRX_RD_DTX_P1 2 2 USB3_PTX_C_DRX_N1 GND GND
ESD@ DI5
8 12
2
2 1 USB3_PTX_C_DRX_N1 4 4 USB3_PTX_C_DRX_N1 2 USB3_PTX_C_DRX_P1 SSTX- GND
7 7 9 13
<42> USB3_PTX_RD_DRX_N1 SSTX+ GND
CI13 0.1U_0402_25V6
USB3_PTX_C_DRX_P1 5 5 USB3_PTX_C_DRX_P1
1
2 1 6 6
<42> USB3_PTX_RD_DRX_P1 C-K_26230A-8K1A-02
CI16 0.1U_0402_25V6
1
3 3 CONN@
L05ESDL5V0NA-4_SLP2510P8-10-9
Link C-K_26230A-8K1A-02 DONE
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N1 1 2 USB20_N1_R
SW_USB20_P1 4 3 USB20_P1_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2
UI3
1 12
VIN VOUT
2
<10> USB20_N1 3 DM_OUT
<10> USB20_P1 DP_OUT 10 SW_USB20_P1
13 DP_IN 11 SW_USB20_N1
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<34,42> USB_PWR_SHR_VBUS_EN EN ILIM_L 16 2 1
RI14
ILIM_HI
6
CTL1
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
+5V_ALW SLGC55544CVTR_TQFN16_3X3
RI13 2 1 ILIM_SEL Link Seligro SA000097E10 Done

10K_0402_5% MAIN:SLGC55544CVTR
B +5V_ALW B
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, JUSB1+PS
1.0
5 4 3 2 1
5 4 3 2 1
For Breckenridge 14&15/Steamboat 14

DI1 ESD@
USB3_PRX_DTX_N3 1 1 USB3_PRX_DTX_N3
10 9 RF Request
<10> USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3 +USB_EX2_PWR +USB_EX2_PWR
<10> USB3_PRX_DTX_P3 JUSB2
2 1 USB3_PTX_C_DRX_N3 4 4 7 7 USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_P3 9
<10> USB3_PTX_DRX_N3 1 SSTX+
CI5 0.1U_0402_25V6
2 1 USB3_PTX_C_DRX_P3 5 5 6 USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_N3 8 VBUS
6
<10> USB3_PTX_DRX_P3 USB20_P2_R SSTX-
CI4 0.1U_0402_25V6 3
D+
0.1U_0201_10V6K
3 3 7
USB20_N2_R GND
100U_1206_6.3V6M
1 2 10
D- GND
1
USB3_PRX_DTX_P3
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ CI46
CI3
8 1 1 6 11
SSRX+ GND
CI1
4 12
USB3_PRX_DTX_N3 GND GND
L05ESDL5V0NA-4_SLP2510P8-10-9 5 13
2
D SSRX- GND D
2
2
2 2
ESD@ DI2
LOTES_AUSB0014-P003A
2
CONN@
LI3 EMI@
USB20_P2 USB20_P2_R
1
1 2
<10> USB20_P2
1
USB20_N2 4 3 USB20_N2_R Link LOTES_AUSB0014-P003A_9P DONE
<10> USB20_N2
EXC24CQ900U_4P
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<34> USB_PWR_EN1# EN
1 3 USB_OC1# <10>
OCB
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
12" not support

+USB_EX3_PWR
RF Request
+USB_EX3_PWR JUSB3 CONN@
DI6 ESD@ 1
USB3_PRX_DTX_N4 1 1 USB3_PRX_DTX_N4 USB20_N3_R VBUS
10 9 2
D-
USB3_PRX_DTX_P4 USB3_PRX_DTX_P4 D+
100U_1206_6.3V6M
0.1U_0201_10V6K
2 2 9 8 4
GND
StdA-SSRX-
CI10
2 1 4 7 10
StdA-SSRX+ GND
CI8
11
GND-DRAIN GND
12P_0402_50V8J
RF@ CI47
68P_0402_50V8J
RF@ CI48
5 12
2
StdA-SSTX- GND
2
13
StdA-SSTX+ GND
ESD@ DI3
3
2
C-K_26210B-8K1A-02
8 2 2
1
L05ESDL5V0NA-4_SLP2510P8-10-9
1
Link C-K_26210B-8K1A-02 DONE
B B
+USB_EX3_PWR
LI4 EMI@
USB20_P3 1 2 USB20_P3_R +5V_ALW
<10> USB20_P3
UI2
1
USB20_N3 4 3 USB20_N3_R 5 OUT
<10> USB20_N3 IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
EXC24CQ900U_4P 4
<34> USB_PWR_EN2# EN
@ CI11
1 3 USB_OC2# <10>
OCB
CI12
SY6288D20AAC_SOT23-5
2
2
vinafix
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT JUSB2&JUSB3
5 4 3 2 1
5 4 3 2 1
RF Request
KB_DET# 1 2
+3.3V_TP RF@ CZ84 68P_0402_50V8J
Touch Pad +3.3V_RUN +3.3V_TP BC_INT#_ECE1117 1
@RF@CZ85
2
68P_0402_50V8J
1
PJP35 RF@CZ83 BC_DAT_ECE1117 1 2
1 2 68P_0402_50V8J @RF@CZ86 68P_0402_50V8J
+3.3V_TP 2
PAD-OPEN1x1m BC_CLK_ECE1117 1 2
@RF@CZ87 68P_0402_50V8J
DAT_TP_SIO_R
4.7K_0402_5%
4.7K_0402_5%
1 2
1
D @RF@CZ88 68P_0402_50V8J D
RZ18
RZ19
CLK_TP_SIO_R 1 2
@RF@CZ89 68P_0402_50V8J
PS2
2
CVILU_CF5020FD0RK-05-NH
2 1 DAT_TP_SIO_R
<34> DAT_TP_SIO_I2C_CLK 22
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R 21 GND
<34> CLK_TP_SIO_I2C_DAT GND
@ RZ23 0_0402_5%
Keyboard
10P_0402_50V8J
10P_0402_50V8J
KB_DET# 20
<12> KB_DET# 20
1
19
I2C1_SDA_TP_R 19
CZ80
CZ81
2 1 18
0_0402_5% RZ346 @ 17 18
2
2 1 I2C1_SCK_TP_R 16 17
+5V_RUN 16
0_0402_5% RZ347 @ 15
+3.3V_ALW BC_INT#_ECE1117 15 +3.3V_TP +3.3V_ALW +5V_RUN
14
<34> BC_INT#_ECE1117 BC_DAT_ECE1117 13 14
<34> BC_DAT_ECE1117 12 13
BC_CLK_ECE1117 11 12
I2C From EC <34> BC_CLK_ECE1117 11
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10 1 1 1
10
@
9
+3.3V_TP DAT_TP_SIO_R 9
CZ90
CZ91
CZ92
8
+3.3V_TP +3.3V_TP CLK_TP_SIO_R 7 8
6 7 2 2 2
5 6
<12,34> TOUCHPAD_INTR# 5
10K_0402_5%
10K_0402_5%
4
4
1
@ @ I2C1_SDA_TP_R 3
3
1
I2C1_SCK_TP_R
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
2
2
RZ20
RZ21
1
C 1 Place close to JKBTP1 C
JKBTP1
2
2
2
CONN@
1 2 I2C1_SDA_TP_R
<9> I2C1_SDA_TP @ RZ26 0_0402_5%
1 2 I2C1_SCK_TP_R
<9> I2C1_SCK_TP @ RZ29 0_0402_5%
I2C From CPU Link HRS_TF49-20S-0P5SH done
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<34> PCH_RSMRST# B 4
O PCH_RSMRST#_AND <11,14>
2
<58> ALW_PWRGD_3V_5V A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Keyboard
1.0
5 4 3 2 1
5 4 3 2 1
Bat t er y LE D
HDD LED MUX
means EC can switch battery white led and HDD LED by hot key “ Fn+ H”
<35> SATA_LED_EN
BATT_WHITE#
5
1 2 BATT_WHITE#
D <34,46> BAT2_LED# D
RZ361 150_0402_5%
4 3 BAT2_LED#_R
<10,32,40> SATALED#
@ QZ2B
3
DMN65D8LDW-7_SOT363-6 R1=10K;R2=10K 1 2 BATT_YELLOW#
<34> BAT1_LED#
@ QZ3 RZ28 330_0402_5%
R2
DDTA114EUA-7-F_SOT323-3
2
Need LINK SB000002T00 Symbol
R1
+3.3V_ALW
1
2
1 6 BAT2_LED#_R
<34,46> BAT2_LED#
1 2
@ QZ2A @ RZ25 150_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_ALW
QZ7B LED3
DMN65D8LDW-7_SOT363-6 LTW-C193DC-C_WHITE
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
C <34> BREATH_LED# C
RZ32 330_0402_5%
Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<30,34> SYS_LED_MASK# B MASK_BASE_LEDS#

4
2 O
<35,46> LID_CL#
G
A UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH

LED board CONN
2 SW3 1
<11,35> POWER_SW#_MB
CONN@
+5V_ALW JLED1
4 3
1
SKRBAAE010_4P BATT_YELLOW# 2 1
BATT_WHITE# 3 2
4 3
5 4
B <35,46> LID_CL# B
6 5
+3.3V_ALW 6 7
GND1 8
GND2
CVILU_CF5006FD0R0-05-NH
Link CF5006FD0R0-05-NH DONE

LED Circuit Control Table
Fiducial Mark
@ FD1
1
SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D
@ FD4
CPU NGFF Standof f
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H12 @ H14 @ H15 @ H16 @ H17 @ H18 @ H20 @ H22 @ H23 @ H24 @ H25 @ H26 @ H28 @ H29 @ H32
H_3P8 H_3P8 H_3P8 H_3P8 H_1P1N H_1P1N H_3P2 H_3P2 H_2P3 H_3P0 H_2P5 H_4P0 H_4P0 H_2P3 H_4P0 H_2P5 H_4P0 H_4P0 H_2P5 H_2P5 H_2P2 H_2P3 H_2P5 H_2P5 H_2P6X3P6
FIDUCIAL MARK~D
1
A
EDP Standof f GPU Standof f Frame Standof f For JAE JSIM1 boss hole A
@ H34 @ H35 @ H36 @ H37 @ H38 @ CLIP1
H_3P2 H_3P2 H_3P3 H_3P3 H_3P8 @ H42 @ H43 CLIP_SH1506X616
H_0P7N H_0P9N
1
1
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN/+3.3V_LAN source +1.8V_RUN source

PJP41
1 2 +3.3V_WWAN
+3.3V_ALW
UZ2 PAD-OPEN1x3m 2.5A PJP42 0.013A

1 14 +3.3V_WWAN_UZ2 1 2 1 2
VIN1 VOUT1 +1.8V_PRIM +1.8V_RUN
2 13 CZ119 0.1U_0201_10V6K UZ8
VIN1 VOUT1 PAD-OPEN1x1m
3.3V_WWAN_EN 3 12 1 2 1 7
<34> 3.3V_WWAN_EN ON1 CT1 VIN VOUT +1.8V_RUN_UZ8
D
CZ109 470P_0402_50V7K 2 8 1 2 D
4 11 +3.3V_WWAN_UZ2 VIN VOUT CZ120 0.1U_0201_10V6K
+5V_ALW VBIAS GND RUN_ON_1.8V
1 2 3 6 1 2
5 10 1 2 <17,34,35,47,61> RUN_ON @ RZ345 ON CT
0_0402_5% CZ121 470P_0402_50V7K
<11,34> SIO_SLP_LAN# ON2 CT2 CZ110 470P_0402_50V7K 1
6 9 +5V_ALW 4
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 RF@ CZ124 VBIAS 5
VIN2 VOUT2 CZ111 0.1U_0201_10V6K 2200P_0402_50V7K GND 9
GND
1
1 2 3.3V_WWAN_EN 15 2
RZ40 100K_0402_5% GPAD PJP37 @ CZ197
EM5209VF_SON14_2X3 1 2 +3.3V_LAN 470P_0402_50V7K AOZ1336_DFN8_2X2
2
PAD-OPEN1x1m
1A RF Request
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+3.3V_ALW_PCH/+3.3V_RUN source
PJP38 0.63A
1 2 +3.3V_ALW_PCH
PAD-OPEN1x1m
+3.3V_ALW
UZ3
C 1 14 +3.3V_ALW_PCH_UZ3 1 2 C
2 VIN1 VOUT1 13 CZ112 0.1U_0201_10V6K
VIN1 VOUT1
@ RZ65 1 2 0_0402_5% 3 12 1 2
<34> PCH_ALW_ON ON1 CT1
@ RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K
<11,17,34,60,61,62> SIO_SLP_SUS#
+5V_ALW 4 11
VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2 CZ114 1000P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 PJP39
1 2 +3.3V_RUN
3.435A
+5V_RUN/+3.3V_WLAN source
B B
PJP40 2A
1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<17,34,35,47,61> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
1 2 4 11
<11,34> SIO_SLP_WLAN# VBIAS GND
@ RZ71 0_0402_5%
1 2 5 10 1 2
<34> AUX_EN_WOWL ON2 CT2
@ RZ70 0_0402_5% CZ118 470P_0402_50V7K
6 9 +3.3V_WLAN_UZ4 1 2
+3.3V_ALW VIN2 VOUT2
7 8 CZ122 0.1U_0201_10V6K
VIN2 VOUT2 PJP36
15 1 2 +3.3V_WLAN
GPAD
EM5209VF_SON14_2X3 PAD-OPEN1x2m
2A
1 2 AUX_EN_WOWL
RZ38 100K_0402_5%
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power control
5 4 3 2 1
5 4 3 2 1
UV1A
Part 1 of 6
PEG_CTX_C_GRX_P0 AG6 C6 GPU_GC6_FB_EN
PEG_CTX_C_GRX_N0 PEX_RX0 GPIO0 GPU_GC6_FB_EN <12,52>
AG7 B2
PEG_CTX_C_GRX_P[0..3] PEG_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
<10> PEG_CTX_C_GRX_P[0..3] PEG_CTX_C_GRX_N1 PEX_RX1 GPIO2
AE7 C7
PEG_CTX_C_GRX_N[0..3] PEG_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9
<10> PEG_CTX_C_GRX_N[0..3] PEG_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3
PEG_CRX_GTX_P[0..3] PEG_CTX_C_GRX_P3 PEX_RX2_N GPIO5 GC6_EVENT#_D 3V3_MAIN_EN <52,68> GC6_EVENT#_D
AG9 A4 2 1 GC6_EVENT# <12>
<10> PEG_CRX_GTX_P[0..3] PEG_CTX_C_GRX_N3 AG10 PEX_RX3 GPIO6 B6
PEG_CRX_GTX_N[0..3] AF10 PEX_RX3_N GPIO7 A6 THERMATRIP_GPU# DV10
<10> PEG_CRX_GTX_N[0..3] NC OVERT
AE10 F8 RB751S40T1G_SOD523-2
AE12 NC GPIO9 C5 FBVREF_ALTV
AF12 NC GPIO10 E7 GPU_PWM_VID
NC GPIO11 GPU_HOT# GPU_PWM_VID <68>
AG12 D7
AG13 NC GPIO12 B4 NVVDD_PSI <68>
GPIO
D NC GPIO13 D
AF13 B3
PEG_CRX_GTX_P0 CV201 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_P0 AE13 NC GPIO14 C3
PEG_CRX_GTX_N0 CV202 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_N0 AE15 NC GPIO15 D5 1 2
AF15 NC GPIO16 D4 @ RV211 0_0402_5%
PEG_CRX_GTX_P1 CV203 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_P1 AG15 NC GPIO17 C2
PEG_CRX_GTX_N1 CV204 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_N1 AG16 NC GPIO18 F7
NC GPIO19 THERMATRIP_GPU#
D
AF16 E6 3 1
PEG_CRX_GTX_P2 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_P2 NC GPIO20 GPU_PEX_RST_HOLD# THERMATRIP1# <34>
CV205 AE16 C4
PEG_CRX_GTX_N2 CV206 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_N2 AE18 NC GPIO21 QV11
AF18 NC AB6 L2N7002WT1G_SC-70-3
G
2
PEG_CRX_GTX_P3 CV207 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_P3 AG18 NC PEX_WAKE_NC
PEG_CRX_GTX_N3 CV208 2 1 0.22U_0402_16V7K PEG_CRX_C_GTX_N3 AG19 NC DGPU_PEX_RST#
AF19 NC
AE19 NC +3.3V_RUN_GFX
AE21 NC AG3
AF21 NC NC AF4 GPU_SMBCLK_R 1 2
AG21 NC NC AF3 RV218 1.8K_0402_5%
AG22 NC NC GPU_SMBDAT_R 1 2
+3.3V_GFX_AON NC RV219 1.8K_0402_5%
PEG_CRX_C_GTX_P0
10K_0402_5%
<52,69> VRAM_EN AC9 AE3

PEX_TX0 NC
1
DACs
PEG_CRX_C_GTX_N0
RV201
AB9 AE4
PEG_CRX_C_GTX_P1 AB10 PEX_TX0_N NC
PEG_CRX_C_GTX_N1 AC10 PEX_TX1
PEG_CRX_C_GTX_P2 PEX_TX1_N +3.3V_GFX_AON
PCI EXPRESS
AD11
PEX_TX2
2
QV10 PEG_CRX_C_GTX_N2 AC11 W5

G
PEG_CRX_C_GTX_P3 AC12 PEX_TX2_N NC AE2 THERMATRIP_GPU# 2 1

1 3 GFXCLK_REQ_Q# PEG_CRX_C_GTX_N3 AB12 PEX_TX3 TSEN_VREF AF2 RV222 10K_0402_5%
<11> CLKREQ_PCIE#0 PEX_TX3_N NC NVVDD_PSI
AB13 1 2
D
AC13 NC RV220 10K_0402_5%

L2N7002WT1G_SC-70-3 AD14 NC GPU_HOT# 1 2
1 2 AC14 NC RV221 100K_0402_5%
@ RV200 0_0402_5% AC15 NC 3V3_MAIN_EN 2 1
AB15 NC RV223 10K_0402_5%
AB16 NC B7 1 2 GPU_PEX_RST_HOLD# 2 1
C AC16 NC I2CA_SCL A7 RV212 1 2 1.8K_0402_5% RV224 10K_0402_5% C
AD17 NC I2CA_SDA RV213 1.8K_0402_5% GC6_EVENT#_D 2 1
AC17 NC C9 1 2 RV225 10K_0402_5%
AC18 NC I2CB_SCL C8 RV214 1 2 1.8K_0402_5% SYS_PEX_RST_MON# 2 1
NC I2CB_SDA
I2C
AB18 RV215 1.8K_0402_5% @ RV226 10K_0402_5%
AB19 NC A9 1 2
AC19 NC I2CC_SCL B9 RV216 1 2 1.8K_0402_5%
AD20 NC I2CC_SDA RV217 1.8K_0402_5% FBVREF_ALTV 1 2
AC20 NC D9 GPU_SMBCLK_R RV227 100K_0402_5%
NC I2CS_SCL GPU_SMBDAT_R
Place close to ball GPU_GC6_FB_EN
AC21 D8 2 1
AB21 NC I2CS_SDA RV299 10K_0402_5%
AD23 NC LV10
AE23 NC 2 1
NC +1.0V_PEX_VDD
0.1U_0402_10V7K
22U_0603_6.3V6M
AF24 PBY160808T-300Y-N_2P
AE24 NC L6 +CORE_PLLVDD
NC PLLVDD 1
CV210
AG24 M6
NC SP_PLLVDD
CV211
AG25
NC N6
AE8
<11> CLK_PCIE_P0 CLK_PCIE_N0 PEX_REFCLK
AD8 LV8
<11> CLK_PCIE_N0 GFXCLK_REQ_Q# PEX_REFCLK_N
AC6 +PLLVDD 2 1
PEX_CLKREQ_N +1.0V_PEX_VDD
0.1U_0402_10V7K
4.7U_0603_6.3V6K
22U_0603_6.3V6M
PBY160808T-181Y-N_2P
1 2 PEX_TSTCLK_OUT AF22
CLK
PEX_TSTCLK_OUT 1 1 1
@ RV207 200_0402_1% PEX_TSTCLK_OUT# AE22 C11 GPU_CLK_27M_IN
PEX_TSTCLK_OUT_N XTAL_IN GPU_CLK_27M_OUT
CV212
CV213
CV214
B10
XTAL_OUT
DGPU_PEX_RST# 1 2 DGPU_PEX_RST_R# AC7 A10 XTALSSIN 1 2 2 2 2
@ RV208 2 1 0_0402_5% AF25 PEX_RST_N XTAL_SSIN C10 XTALOUTBUFFRV228 1 2 10K_0402_5%
RV209 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF RV229 10K_0402_5%
GM108-ES-S-A1_FCBGA595
B B
0.1U_0402_10V7K
+3.3V_ALW
1 @
CV209
RV202
10K_0402_5%
2 1 YV1
2 27MHZ_12PF_X1E000021042600
GPU_CLK_27M_IN 1 3 GPU_CLK_27M_OUT_R 1 2 GPU_CLK_27M_OUT
IN OUT
5
RV230 910_0402_5%
18P_0402_50V8J
18P_0402_50V8J
1 2 4
P
<9> DGPU_HOLD_RST# B SYS_PEX_RST_MON#_R GND GND

4 1 2 1 1
2 O @ RV204 0_0402_5% SYS_PEX_RST_MON# <49>
CV215
CV216
<11> PLTRST_GPU# A
G
1
10K_0402_5%
RV203
UV14
3
2 2
S
P
_
P
L
L
V
D
Dl
a
n
di
V
I
D
_
P
Lb
L
V
D
Dd
P
o
w
e
r
TC7SH08FU_SSOP5~D
P
L
L
V
D
D
F
i
l
t
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r
i
n
g
r
a
i
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F
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C
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C
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C
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n
+3.3V_ALW
0.1U_0402_10V7K
1 2
04
1
u
F
4
0
230
1
p
e
r11 1
0
.
1
u
F
48 5
0
25
11
1
1
0_0402_5%
@
@ @ RV231 0_0402_5%
CV311
RV206
.
7
u
F
0
6
08o
2
2a
u
F
0
0o
QV12B
GPU_SMBCLK_R 4 3 EXPANDER_GPU_SMCLK
2 EXPANDER_GPU_SMCLK <34,35>
2
2
u
F 8.
0 02
5h
B
eE
dR
3
0.
h
mo
2
DGPU_PEX_RST#
(0
S0
=
0
0
h
m
)
B
e
a
d=
1
mm
1
1 2
5
@ RV232 0_0402_5%
5
4
2
(
E
S
R3
0
o
h
)
UV25 1 2 +3.3V_RUN_GFX
2
SYS_PEX_RST_MON# 1 @ RV233 0_0402_5%

P
B DGPU_PEX_RST#
0
6
0
4 DMN66D0LDW-7_SOT363-6
GPU_PEX_RST_HOLD# 2 Y GPU_SMBDAT_R 1 6 EXPANDER_GPU_SMDAT
A EXPANDER_GPU_SMDAT <34,35>
G
1
10K_0402_5%
A A
RV205
TC7SH08FU_SSOP5 QV12A
3
1 2
@ RV234 0_0402_5%
2
GPU_PWR_LEVEL
1 2 GPU_HOT#
<35> GPU_PWR_LEVEL @ RV210 0_0402_5%
LOW Low Performace Compal Electronics, Inc.
HIGH High Performace TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
N15S PCIE,I2C,DAC,GPIO
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
UV1C UV1E
Part 3 of 6 F11 A2 Part 5 of 6 K11

AC3 NC AD10 A26 GND_001 GND_057 K13
AC4 NC NC AD7 AB11 GND_002 GND_058 K15
Y4 NC NC B19 AB14 GND_003 GND_059 K17
Y3 NC FBA_CMD32 V5 AB17 GND_004 GND_060 L10
AA3 NC NC V6 AB20 GND_005 GND_061 L12
AA2 NC NC G1 AB24 GND_006 GND_062 L14
AB1 NC NC G2 AC2 GND_007 GND_063 L16
NC NC GND_008 GND_064
NC
AA1 G3 AC22 L18
AA4 NC NC G4 AC26 GND_009 GND_065 L2
AA5 NC NC G5 AC5 GND_010 GND_066 L23
D NC NC G6 AC8 GND_011 GND_067 L25 D
NC G7 AD12 GND_012 GND_068 L5
AB5 NC V1 AD13 GND_013 GND_069 M11
AB4 NC NC V2 AD15 GND_014 GND_070 M13
AB3 NC NC W1 AD16 GND_015 GND_071 M15
AB2 NC NC W2 AD18 GND_016 GND_072 M17
AD3 NC NC W3 AD19 GND_017 GND_073 N10
I
2
C
S
S
l
a
v
e
A
d
d
r
e
s
s
AD2 NC NC W4 AD21 GND_018 GND_074 N12

AE1 NC NC AD22 GND_019 GND_075 N14
AD1 NC AE11 GND_020 GND_076 N16
S
M
B
U
S
_
A
L
T
_
A
D
D
R
D
e
s
c
r
i
p
t
i
o
n
AD4 NC AE14 GND_021 GND_077 N18

AD5 NC D11 AE17 GND_022 GND_078 P11
NC BUFRST_N AE20 GND_023 GND_079 P13
0
0
x
9
E
(
D
e
f
a
u
l
t
)
D10 1 2 AF1 GND_024 GND_080 P15

NC GND_025 GND_081
GND
T2 @ RV251 10K_0402_5% AF11 P17
T3 NC E9 SYS_PEX_RST_MON# AF14 GND_026 GND_082 P2
1
0
x
9
C
(
M
u
l
t
i
-
G
P
U
u
s
a
g
e
)
T1 NC GPIO8 SYS_PEX_RST_MON# <48> AF17 GND_027 GND_083 P23

R1 NC E10 AF20 GND_028 GND_084 P26
NC NC GND_029 GND_085
GENERAL
R2 AF23 P5
LVDS/TMDS
R3 NC F10 AF5 GND_030 GND_086 R10
V
G
A
_
D
E
V
I
C
E
S
e
t
t
i
n
g
N2 NC NC AF8 GND_031 GND_087 R12

N3 NC AG2 GND_032 GND_088 R14
NC D1 STRAP0 AG26 GND_033 GND_089 R16
V
G
A
_
D
E
V
I
C
E
D
e
s
c
r
i
p
t
i
o
n
STRAP0 D2 STRAP1 B1 GND_034 GND_090 R18

V3 STRAP1 E4 STRAP2 B11 GND_035 GND_091 T11
V4 NC STRAP2 E3 STRAP3 B14 GND_036 GND_092 T13
0
N
o
n
-
P
r
i
m
a
r
y
3
D
A
c
c
e
l
e
r
a
t
i
o
n
D
e
v
i
c
e
(
C
l
a
s
s
C
o
d
e
3
0
2
h
)
U3 NC STRAP3 D3 STRAP4 B17 GND_037 GND_093 T15
U4 NC STRAP4 C1 B20 GND_038 GND_094 T17
T4 NC NC B23 GND_039 GND_095 U10
1
P
r
i
m
a
r
y
D
i
s
p
l
a
y
o
r
V
G
A
D
e
v
i
c
e
(
C
l
a
s
s
C
o
d
e
3
0
0
h
)
T5 NC B27 GND_040 GND_096 U12

R4 NC F6 MULTI_STRAP_REF0_GND 1 2 B5 GND_041 GND_097 U14
R5 NC MULTI_STRAP_REF0_GND F4 MULTI_STRAP_REF1_GND RV252 1 2 40.2K_0402_1% B8 GND_042 GND_098 U16
C NC NC F5 MULTI_STRAP_REF2_GND @ RV253 1 2 40.2K_0402_1% E11 GND_043 GND_099 U18 C
R
e
s
i
s
t
a
n
c
e
M
a
p
p
i
n
g
t
o
H
e
x
V
a
l
u
e
s
NC @ RV254 40.2K_0402_1% E14 GND_044 GND_100 U2

N1 E17 GND_045 GND_101 U23
M1 NC E2 GND_046 GND_102 U26
R
e
s
i
s
t
o
r
V
a
l
u
e
P
u
l
l
-
u
p
t
o
V
D
D
3
3
P
u
l
l
-
d
o
w
n
t
o
G
N
D
M2 NC F12 E20 GND_047 GND_103 U5

M3 NC THERMDP E22 GND_048 GND_104 V11
K2 NC E12 E25 GND_049 GND_105 V13
4
.
9
9
K
1
0
0
0
0
0
0
0
K3 NC THERMDN E5 GND_050 GND_106 V15

K1 NC E8 GND_051 GND_107 V17
J1 NC H2 GND_052 GND_108 Y2
1
0
K
1
0
0
1
0
0
0
1
NC H23 GND_053 GND_109 Y23

H25 GND_054 GND_110 Y26
M4 F2 H5 GND_055 GND_111 Y5
1
5
K
1
0
1
0
0
0
1
0
M5 NC VDD_SENSE GPU_VDD_SENSE <68> GND_056 GND_112

L3 NC
L4 NC
2
0
K
1
0
1
1
0
0
1
1
NC
NC AA7
K5 GND AB7
2
4
.
9
K
1
1
0
0
0
1
0
0
J4 NC F1 GND
NC GND_SENSE GPU_VSS_SENSE <68>
3
0
.
1
K
1
1
0
1
0
1
0
1
J5
N4 NC
TEST
3
4
.
8
K
1
1
1
0
0
1
1
0
N5 NC
NC
P3 AD9 GPU_TESTMODE RV255 1 2 10K_0402_5%
4
5
.
3
K
1
1
1
1
0
1
1
1
P4 NC TESTMODE AE5 GPU_JTAG_TCK

NC JTAG_TCK AE6 GPU_JTAG_TDI
JTAG_TDI AF6 GPU_JTAG_TDO +3.3V_GFX_AON
J2 JTAG_TDO AD6 GPU_JTAG_TMS
B J3 NC JTAG_TMS AG4 GPU_JTAG_TRST# RV256 1 2 10K_0402_5% B
NC JTAG_TRST_N @ RPV1
GPU_JTAG_TDO 5 4
H3 GPU_JTAG_TDI 6 3
H4 NC GPU_JTAG_TCK 7 2
NC SERIAL GPU_JTAG_TMS 8 1
D12
ROM_CS_N B12 ROM_SI_GPU 10K_8P4R_5%
ROM_SI A12 ROM_SO_GPU
ROM_SO C12 ROM_SCLK_GPU
Decive ID change to 0x1056 ROM_SCLK
+3.3V_GFX_AON +3.3V_RUN_GFX
49.9K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
34.8K_0402_1%
8.45K_0402_1%
Strap Pin Name Logical Strapping Bit 3 Logical Strapping Bit 2 Logical Strapping Bit 1 Logical Strapping Bit 0 Note VENDER STRAP Part Number Note(ROM_SI)
2
2
8.45K_0402_1%
2
@ RV249
RV235
@ RV237
RV239
RV241
@ RV245
@ RV247
RV243
ROM_SCLK SOR3_EXPOSED->0 SOR2_EXPOSED->0 SOR1_EXPOSED->0 SOR0_EXPOSED->0 ROM_SCLK pull-down RV246 4.99k to GND Hynix 0x7 H5TC4G63CFR-N0C RV248 45.3k PD
@ @
1
@ ROM_SI RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] ROM_SI pull-down RV248 24.9k to GND Micron 0x6 MT41J256M16LY-091G:N RV248 34.8k PD
1
STRAP0
STRAP1 ROM_SO DEVID_SEL->0(default) PCIE_CFG->0(defual) SMB_ALT_ADDR->0(default) VGA_DEVICE->0 ROM_SO pull-down RV250 4.99k to GND Samsung 0x1 K4W4G1646E-BC1A RV248 10k PD
STRAP2
STRAP3
STRAP4 STRAP0 Keep pull up to 3V3_AON and pull-down to GND footprint and stuff 50k ohm pull up STRAP0 pull up RV235 50k to +3.3V_GFX_AON
ROM_SCLK_GPU
A ROM_SI_GPU A
ROM_SO_GPU
2K_0402_1%
STRAP1
2
2K_0402_1%
2K_0402_1%
2K_0402_1%
2K_0402_1%
10K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
STRAP2
2
STRAP3 Reserve
RV236
RV250
RV238
RV240
RV242
RV244
RV246
RV248
STRAP4
DEVID_SEL/PCIE_CFG defaul set 0, need refer Platform Update Notification for the latest configuration
1
@ @ @ @ @
1
N15S DP, STRAP, GND
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
UV1D PLACE BETWEEN GPU

Part 4 of 6 PLACE NEAR BALLS PLACE NEAR GPU AND POWER SUPPLY +1.0V_PEX_VDD
+1.35V_MEM_GFX
P
E
X
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I
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D
D
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P
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b
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d
I=2000mA B26 AA10
FBVDDQ_01 PEX_IOVDDQ_1
1U_0402_6.3V6K
4.7U_0603_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
C25 AA12
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13
PLACE NEAR GPU PLACE UNDER GPU FBVDDQ_03 PEX_IOVDDQ_3 1 1 1 1
C
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c
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t
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r0
T
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P
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a
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E26 AA16
CV225
CV226
CV227
CV228
F14 AA18
22U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
u
F
0
4
2308
1111
F21 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
1 1 1 1 1 1 1 1 FBVDDQ_07 PEX_IOVDDQ_7
4
.
7
u
Fu
000
6
0
G14 AA21
CV217
CV218
CV219
CV220
CV221
CV222
CV223
CV224
G15 AB22
1
02
F
8
55
G16 AC23
2 2 2 2 2 2 2 2 G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
D FBVDDQ_11 PEX_IOVDDQ_11 D
2
u
F
0
G19 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_AON
J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
N21 FBVDDQ_22 PEX_IOVDD_6
R21 FBVDDQ_23
T21 FBVDDQ_24 +3.3V_GFX_AON
V21 FBVDDQ_25
W21 FBVDDQ_26 PLACE UNDER GPU PLACE NEAR GPU
G+
C3
6.
2V
._
0G
GX
1_
0A
/O
GN
1
2
p
i
n
c
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n
n
e
c
t
t
o
FBVDDQ_27
D
D
R
3b
C
P
Ud
s
i
dc
e
F
B
V
D
D
/
F
B
V
D
D
Q
G10
3V3_AON
F
G12
3V3_AON
C
o
m
i
n
e
D
e
o
u
p
l
i
n
g
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
G8
VDD33_3 G9
VDD33_4 1 1 1
C
a
p
a
c
i
t
o
r00008
T
y
p
e
P
o
p
u
l
a
t
i
o
n
CV229
CV230
CV231
0
.
1
u
FFFF
0
4
23350
22211
V7
W7 NC 2 2 2
NC
1
.
0
uu0
0
6
AA6
W6 NC D22 1 2
NC FB_CAL_PD_VDDQ +1.35V_MEM_GFX
4
.
712
0
6
Y6 RV257 40.2_0402_1% +3.3V_RUN_GFX

NC
uF
0
8
C24 1 2
FB_CAL_PU_GND RV258 42.2_0402_1%
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
2
u
0
5
M7 B25 1 2 1 1 1 1
C N7 NC FB_CAL_TERM_GND RV259 51.1_0402_1% C
NC
CV232
CV233
CV234
CV235
T6
P6 NC
NC 2 2 2 2
PLACE NEAR BGA

T7
IFPD_PLLVDD_2 +3.3V_GFX_AON
R7
U6 NC
P
o
w
e
r
S
u
p
p
l
y
R
a
i
l
N
1
6
S
-
G
M
R
IFPD_RSET
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
R6 AA8
NC PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD_2 1 1 1
CV236
CV237
CV238
AB8
(
V
)
(
A
)
PEX_SVDD_3V3
2 2 2
J7
G
P
U
_
C
o
r
e
----
2
1
NC
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
G
P
U
_
F
B
I
O
1
.
5
/
1
.
3
5
1
.
4
J6 NC PEX_PLLVDD_2
NC
PLACE UNDER GPU PLACE NEAR GPU

P
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X
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I
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V
D
D
/
Q
1
.
0
+1.0V_PEX_VDD
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
P
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X
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P
L
L
V
D
D
1
.
0
GM108-ES-S-A1_FCBGA595 1 1 1
CV239
CV240
CV241
F
B
A
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P
L
L
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A
V
D
D
1
.
0
2 2 2
F
B
A
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L
L
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D
D
1
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0
B B
P
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0
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111
0
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20
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0
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211
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6
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vinafix
N15S Power
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
Caps on Power Side

1UX4 4.7UX10 under GPU
4.7UX5 22UX1 47UX2 330UX2 near GPU
D D
UV1F
+GPU_CORE
Part 6 of 6 +GPU_CORE
K10 V18
K12 VDD_001 VDD_041 V16
K14 VDD_002 VDD_040 V14
K16 VDD_003 VDD_039 V12
K18 VDD_004 VDD_038 V10
L11 VDD_005 VDD_037 U17
POWER
L13 VDD_006 VDD_036 U15
L15 VDD_007 VDD_035 U13
L17 VDD_008 VDD_034 U11
M10 VDD_009 VDD_033 T18
M12 VDD_010 VDD_032 T16
M14 VDD_011 VDD_031 T14
M16 VDD_012 VDD_030 T12
M18 VDD_013 VDD_029 T10
N11 VDD_014 VDD_028 R17
N13 VDD_015 VDD_027 R15
N15 VDD_016 VDD_026 R13
N17 VDD_017 VDD_025 R11
P10 VDD_018 VDD_024 P18
P12 VDD_019 VDD_023 P16
VDD_020 VDD_022 P14
VDD_021
C C
B B
A A
N15S Power GFX Core
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
FBA_D[0..31] FBA_D[32..63]
FBA_D[0..31] <53> FBA_D[32..63] <54> FBA_ODT_L FBA_CMD2 RV264 1 2
DDR3L CMD Mapping Table UV1B FBA_RN[0..3]
FBA_RN[0..3] <53>
FBA_RN[4..7]
FBA_RN[4..7] <54> FBA_ODT_H FBA_CMD18
10K_0402_5%
RV265 1 2
FBA_DQM[0..3] FBA_DQM[4..7] 10K_0402_5%
FBA_DQM[0..3] <53> FBA_DQM[4..7] <54> FBA_CKE_L FBA_CMD3 RV266 1 2
Part 2 of 6 FBA_WP[0..3] FBA_WP[4..7] 10K_0402_5%
CMD0 CS0# CMD32 FBA_WP[0..3] <53> FBA_WP[4..7] <54> FBA_CKE_H FBA_CMD19
CMD1 CMD33 RV267 1 2
FBA_D0 E18 C27 10K_0402_5%
CMD2 ODT CMD34 FBA_D1 FBA_D00 FBA_CMD0 FBA_CMD1 FBA_CMD0 <53>
CMD3 CKE CMD35 F18 C26
FBA_D2 E16 FBA_D01 FBA_CMD1 E24 FBA_CMD2 T110 PAD~D@
CMD4 A14 CMD36 A14 FBA_D3 FBA_D02 FBA_CMD2 FBA_CMD3 FBA_CMD2 <53>
CMD5 RST CMD37 RST F17 F24
FBA_D4 D20 FBA_D03 FBA_CMD3 D27 FBA_CMD3 <53>
CMD6 A9 CMD38 A9 FBA_D5 FBA_D04 FBA_CMD4 FBA_CMD4 <53,54> FBA_CMD5
FBA_RST
CMD7 A7 CMD39 A7 D21 D26
D FBA_D6 F20 FBA_D05 FBA_CMD5 F25 FBA_CMD5 <53,54> D
CMD8 A2 CMD40 A2 FBA_D7 FBA_D06 FBA_CMD6 FBA_CMD6 <53,54>
10K_0402_5%
CMD9 A0 CMD41 A0 E21 F26
FBA_D07 FBA_CMD7 FBA_CMD7 <53,54>
1
FBA_D8 E15 F23
CMD10 A4 CMD42 A4 FBA_D9 FBA_D08 FBA_CMD8 FBA_CMD8 <53,54>
RV263
CMD11 A1 CMD43 A1 D15 G22
FBA_D10 F15 FBA_D09 FBA_CMD9 G23 FBA_CMD9 <53,54>
CMD12 BA0 CMD44 BA0 FBA_D11 FBA_D10 FBA_CMD10 FBA_CMD10 <53,54>
CMD13 WE# CMD45 WE# F13 G24
FBA_D12 C13 FBA_D11 FBA_CMD11 F27 FBA_CMD11 <53,54>
CMD14 A15 CMD46 A15
2
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_CMD12 <53,54>
CMD15 CAS# CMD47 CAS# FBA_D14 FBA_D13 FBA_CMD13 FBA_CMD13 <53,54> +3.3V_RUN +3.3V_GFX_AON
CMD16 CMD48 CS0# E13 G27
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CMD14 <53,54> +5V_RUN
CMD17 CMD49 QV14
FBA_D16 B15 FBA_D15 FBA_CMD15 M24 FBA_CMD15 <53,54>
CMD18 CMD50 ODT LP2301ALT1G_SOT23-3
FBA_D17 C16 FBA_D16 FBA_CMD16 M23 FBA_CMD17 FBA_CMD16 <54>
CMD19 CMD51 CKE FBA_D17 FBA_CMD17 T111 PAD~D@
1
FBA_D18 FBA_CMD18
100K_0402_5%
D
CMD20 A13 CMD52 A13 A13 K24 3 1
FBA_D19 FBA_D18 FBA_CMD18 FBA_CMD19 FBA_CMD18 <54>
RV268
CMD21 A8 CMD53 A8 A15 K23
FBA_D20 FBA_D19 FBA_CMD19 FBA_CMD19 <54>
0.1U_0402_25V6
CMD22 A6 CMD54 A6 B18 M27
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_CMD20 <53,54>
CMD23 A11 CMD55 A11
G
2
FBA_D21 FBA_CMD21 FBA_CMD21 <53,54>
1
FBA_D22
CV252
CMD24 A5 CMD56 A5 A19 M25
2
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_CMD22 <53,54>
CMD25 A3 CMD57 A3 FBA_D24 FBA_D23 FBA_CMD23 FBA_CMD23 <53,54> DGPU_PWR_EN#
CMD26 BA2 CMD58 BA2 B24 K22
2
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_CMD24 <53,54>
CMD27 BA1 CMD59 BA1 FBA_D26 FBA_D25 FBA_CMD25 FBA_CMD25 <53,54>
L2N7002WT1G_SC-70-3
CMD28 A12 CMD60 A12 A25 J25
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_CMD26 <53,54>
CMD29 A10 CMD61 A10 FBA_D27 FBA_CMD27 FBA_CMD27 <53,54>
1
FBA_D28 D
CMD30 RAS# CMD62 RAS# A21 K27
FBA_D29 FBA_D28 FBA_CMD28 FBA_CMD28 <53,54>
QV13
CMD31 CMD63 B21 K25 2
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_CMD29 <53,54> <9> DGPU_PWR_EN G
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 FBA_CMD31 FBA_CMD30 <53,54>
S
3
FBA_D32 R22 FBA_D31 FBA_CMD31 T112 PAD~D@
FBA_D33 R24 FBA_D32 D19 FBA_DQM0
FBA_D33 FBA_DQM0
INTERFACE A
FBA_D34 T22 D14 FBA_DQM1
FBA_D35 R23 FBA_D34 FBA_DQM1 C17 FBA_DQM2
FBA_D36 N25 FBA_D35 FBA_DQM2 C22 FBA_DQM3
FBA_D37 N26 FBA_D36 FBA_DQM3 P24 FBA_DQM4
MEMORY
C FBA_D38 N23 FBA_D37 FBA_DQM4 W24 FBA_DQM5 C
FBA_D39 N24 FBA_D38 FBA_DQM5 AA25 FBA_DQM6
FBA_D40 V23 FBA_D39 FBA_DQM6 U25 FBA_DQM7 +1.0V_PEX_VDD
FBA_D41 V22 FBA_D40 FBA_DQM7
FBA_D42 T23 FBA_D41 F19 FBA_RN0
FBA_D42 FBA_DQS_RN0
1
FBA_D43 U22 C14 FBA_RN1
FBA_D44 Y24 FBA_D43 FBA_DQS_RN1 A16 FBA_RN2 PJP44
FBA_D45 AA24 FBA_D44 FBA_DQS_RN2 A22 FBA_RN3 +1.0V_PRIM
FBA_D45 FBA_DQS_RN3 PAD-OPEN1x1m
FBA_D46 Y22 P25 FBA_RN4
FBA_D47 AA23 FBA_D46 FBA_DQS_RN4 W22 FBA_RN5 UV15
FBA_D48 AD27 FBA_D47 FBA_DQS_RN5 AB27 FBA_RN6 1 14 +1.05V_PEX_VDD_UV15 1 2
2
FBA_D49 AB25 FBA_D48 FBA_DQS_RN6 T27 FBA_RN7 2 VIN1 VOUT1 13 CV246 0.1U_0402_10V7K
+1.0V_PEX_VDD FBA_D50 AD26 FBA_D49 FBA_DQS_RN7 VIN1 VOUT1
FBA_D51 AC25 FBA_D50 E19 FBA_WP0 1 2 3V3_MAIN_EN_R 3 12 1 2
LV26 PLACE UNDER GPU FBA_D52 AA27 FBA_D51 FBA_DQS_WP0 C15 FBA_WP1 <48,68> 3V3_MAIN_EN @ RV269 0_0402_5% ON1 CT1 CV247 4700P_0402_25V7K
1 2 +FB_PLLAVDD FBA_D53 AA26 FBA_D52 FBA_DQS_WP1 B16 FBA_WP2 4 11
FBA_D53 FBA_DQS_WP2 +5V_ALW
0.1U_0402_10V7K
0.1U_0402_10V7K
PBY160808T-300Y-N_2P
FBA_D55 FBA_D54 FBA_DQS_WP3 FBA_WP4
22U_0603_6.3V6M
1 1 Y25 R25 5 10 1 2
FBA_D56 FBA_D55 FBA_DQS_WP4 FBA_WP5 ON2 CT2
@
1 R26 W23 CV248 470P_0402_50V7K

FBA_D57 FBA_D56 FBA_DQS_WP5 FBA_WP6
CV242
CV243
CV244
T25 AB26 6 9 PJP43

FBA_D58 N27 FBA_D57 FBA_DQS_WP6 T26 FBA_WP7 7 VIN2 VOUT2 8 +3.3V_RUN_GFX_UV15 1 2
2 2 FBA_D59 FBA_D58 FBA_DQS_WP7 VIN2 VOUT2 +3.3V_RUN_GFX
R27
2 FBA_D60 V26 FBA_D59 15
FBA_D61 V27 FBA_D60 GPAD PAD-OPEN1x1m
FBA_D62 FBA_D61 +3.3V_RUN
0.1U_0402_10V7K
W27 EM5209VF_SON14_2X3
FBA_D62
2
FBA_D63 W25
FBA_D63
0.1U_0402_10V7K
CV249
D24
F16 FBA_CLK0 D25 CLKA0 <53>
PLACE CLOSE to GPU 1
1
P22 FB_PLLAVDD_1 FBA_CLK0_N CLKA0# <53>
FB_PLLAVDD_2
CV245
N22
D23 FBA_CLK1 M22 CLKA1 <54>
2 @T95 PAD~D FB_VREF_PROBE FBA_CLK1_N CLKA1# <54>
B D18 B
I=35mA FBA_WCK01
H22 C18
FB_DLLAVDD FBA_WCK01_N D17
RV260
2 1 FB_CLAMP_GPU
10K_0402_5%
F3
FB_CLAMP
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
D16
T24
U24
+1.35V_MEM_GFX
2 1 F22 FBA_WCK45_N V24
+1.35V_MEM_GFX FBA_CMD34 FBA_WCK67
@ RV261 2 1 60.4_0402_1% J22 V25
@ RV262 60.4_0402_1% FBA_CMD35 FBA_WCK67_N
F
B
x
_b
P
L
L
_
A
V
D
D
a
n
d
F
B
_
D
L
L
_
A
V
D
D
C
o
m
i
n
e
d
C
a
p
a
c
i
t
o
r
T
y
p
e
P
o
p
u
l
a
t
i
o
n
0
.
1
u
F
0
4
0
2
2 1
2
2
u
F
0
8
0
5
B
e
a
d0
3
01
o
h
mm
DV8
1
DGPU_PWROK
(
E
S
R
=0
.
0
o
h
)
3
<12,35,68> DGPU_PWROK
6
0
3
1
2 VRAM_EN <48,69>
<12,48> GPU_GC6_FB_EN
1
200K_0402_5%
@
RV270
BAT54CW_SOT323-3
A A
2
N15S Memory
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 16 bits 256x16 DDR3L
FBA_D[0..31]
FBA_D[0..31] <52>
FBA_WP[0..3]
FBA_WP[0..3] <52>
FBA_DQM[0..3]
FBA_DQM[0..3] <52>
FBA_RN[0..3]
FBA_RN[0..3] <52>
D D
UV17 UV18
+FBA_VREF_CA0 M8 E3 FBA_D11 +FBA_VREF_CA0 M8 E3 FBA_D1
+FBA_VREF_CA0 +FBA_VREF_DQ0 VREFCA DQL0 FBA_D13 +FBA_VREF_DQ0 VREFCA DQL0 FBA_D4
+FBA_VREF_DQ0
H1 F7 H1 F7
VREFDQ DQL1 F2 FBA_D10 VREFDQ DQL1 F2 FBA_D3
FBA_CMD9 N3 DQL2 F8 FBA_D15 FBA_CMD9 N3 DQL2 F8 FBA_D6
<52,54> FBA_CMD9 FBA_CMD11 P7 A0 DQL3 H3 FBA_D9 FBA_CMD11 P7 A0 DQL3 H3 FBA_D0
<52,54> FBA_CMD8 FBA_CMD25 N2 A2 DQL5 G2 FBA_D8 FBA_CMD25 N2 A2 DQL5 G2 FBA_D2
ADDRESS
ADDRESS
<52,54> FBA_CMD10 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
<52,54> FBA_CMD24 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
<52,54> FBA_CMD22 FBA_CMD7 R2 A6 D7 FBA_D17 FBA_CMD7 R2 A6 D7 FBA_D25
<52,54> FBA_CMD7 FBA_CMD21 T8 A7 DQU0 C3 FBA_D21 FBA_CMD21 T8 A7 DQU0 C3 FBA_D29
<52,54> FBA_CMD21 FBA_CMD6 R3 A8 DQU1 C8 FBA_D18 FBA_CMD6 R3 A8 DQU1 C8 FBA_D26
<52,54> FBA_CMD6 FBA_CMD29 L7 A9 DQU2 C2 FBA_D20 FBA_CMD29 L7 A9 DQU2 C2 FBA_D28
<52,54> FBA_CMD29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D19 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D27
<52,54> FBA_CMD23 FBA_CMD28 N7 A11 DQU4 A2 FBA_D22 FBA_CMD28 N7 A11 DQU4 A2 FBA_D30
<52,54> FBA_CMD28 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D16 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D24
<52,54> FBA_CMD20 FBA_CMD4 T7 A13 DQU6 A3 FBA_D23 FBA_CMD4 T7 A13 DQU6 A3 FBA_D31
<52,54> FBA_CMD4 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
<52,54> FBA_CMD14 NC NC
C C
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2
<52,54> FBA_CMD12 FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
<52,54> FBA_CMD27 FBA_CMD26 M3 BA1 VDD G7 FBA_CMD26 M3 BA1 VDD G7
<52,54> FBA_CMD26 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9
<52> CLKA0 CLKA0# K7 CK VDD R1 CLKA0# K7 CK VDD R1
<52> CLKA0# FBA_CMD3 K9 CK VDD R9 FBA_CMD3 K9 CK VDD R9
POWER
POWER
RV300 <52> FBA_CMD3 CKE VDD CKE VDD
1 2 +1.35V_MEM_GFX +1.35V_MEM_GFX
162_0402_1% FBA_CMD2 K1 A1 FBA_CMD2 K1 A1
<52> FBA_CMD2 FBA_CMD0 L2 ODT VDDQ A8 FBA_CMD0 L2 ODT VDDQ A8
<52> FBA_CMD0 FBA_CMD30 J3 CS VDDQ FBA_CMD30 CS VDDQ
80.6_0402_1%
80.6_0402_1%
@ @ C1 20130610 J3 C1
<52,54> FBA_CMD30 RAS VDDQ RAS VDDQ
1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
<52,54> FBA_CMD15 FBA_CMD13 L3 CAS VDDQ 10U reserve FBA_CMD13 CAS VDDQ
RV281
RV282
D2 L3 D2
<52,54> FBA_CMD13 WE VDDQ WE VDDQ
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
E9 E9
VDDQ VDDQ
@ CV277
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1
Control & DQM
Control & DQM

VDDQ CV284 FBA_WP0 VDDQ
CV283
CV281
CV280
CV279
@ CV278
F3 H2 F3 H2 1 1 1 1 1 1 1
2
FBA_WP2 DQSL VDDQ DQSL VDDQ
CV282
CV290
CV289
CV288
CV287
CV286
CV285
C7 H9 C7 H9
CLKA0_C DQSU VDDQ DQSU VDDQ
2 2 2 2 2 2 2
FBA_DQM1 2 2 2 2 2 2 2
0.01UF_0402_25V7K
@ E7 A9 E7 A9
FBA_DQM2 D3 DML VSS B3 D3 DML VSS B3
1 DMU VSS DMU VSS
CV309
E1 E1
VSS G8 VSS G8
FBA_RN1 G3 VSS J2 FBA_RN0 G3 VSS J2
2 FBA_RN2 B7 DQSL VSS J8 PLACE UNDER DRAM FBA_RN3 B7 DQSL VSS J8
DQSU VSS M1 PLACE CLOSE DRAM DQSU VSS M1 PLACE UNDER DRAM 20130610
VSS M9 VSS M9
VSS P1 VSS P1 10U reserve
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
<52,54> FBA_CMD5 RESET VSS T1 RESET VSS T1
FBA_ZQ0 L8 VSS T9 FBA_ZQ1 L8 VSS T9 PLACE CLOSE DRAM
ZQ VSS ZQ VSS
GND
GND
243_0402_1%
243_0402_1%
1
1
B
J1 B1 J1 B1 B
NC VSSQ NC VSSQ
RV285
RV294
L1 B9 L1 B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
SA00006E800 Link done

D
D
R
3D
pQt
e
r
M
e
m
o
r
ye
F
B
V
D
D
/
Q
D
e
c
o
u
p
l
i
n
g
F
B
Vp
Di
/
C
o
m
b
i
n
d
C
a.
a
cFFu
o
r4
T
y
p
e
P
o
p
u
l
a
t
i
o
n
01
1
uu0
0
0
230
240
.
01
0
6
0
F
0
8
5
+1.35V_MEM_GFX +1.35V_MEM_GFX
1.33K_0402_1%
1.33K_0402_1%
1
1
RV288
RV286
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
A BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, A
2
+FBA_VREF_CA0 +FBA_VREF_DQ0 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1.33K_0402_1%
0.01UF_0402_25V7K
1.33K_0402_1%
0.01UF_0402_25V7K
1
1 1
RV289
CV274
RV287
CV273
2 2
2
Title
MARX-VRAM_A Lower
Size Document Number Rev
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 16 bits 256x16 DDR3L
FBA_D[32..63]
FBA_D[32..63] <52>
FBA_WP[4..7]
FBA_WP[4..7] <52>
FBA_DQM[4..7]
FBA_DQM[4..7] <52>
vinafix
FBA_RN[4..7]
FBA_RN[4..7] <52>
D D
UV19 UV20
+FBA_VREF_CA1 M8 E3 FBA_D52 +FBA_VREF_CA1 M8 E3 FBA_D35
+FBA_VREF_DQ1 H1 VREFCA DQL0 F7 FBA_D49 +FBA_VREF_DQ1 H1 VREFCA DQL0 F7 FBA_D37
VREFDQ DQL1 F2 FBA_D53 VREFDQ DQL1 F2 FBA_D34
FBA_CMD9 N3 DQL2 F8 FBA_D50 FBA_CMD9 N3 DQL2 F8 FBA_D39
<52,53> FBA_CMD8 FBA_CMD25 N2 A2 DQL5 G2 FBA_D55 FBA_CMD25 N2 A2 DQL5 G2 FBA_D32
ADDRESS
ADDRESS
<52,53> FBA_CMD10 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
<52,53> FBA_CMD24 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
<52,53> FBA_CMD22 FBA_CMD7 R2 A6 D7 FBA_D44 FBA_CMD7 R2 A6 D7 FBA_D56
<52,53> FBA_CMD7 FBA_CMD21 T8 A7 DQU0 C3 FBA_D40 FBA_CMD21 T8 A7 DQU0 C3 FBA_D60
<52,53> FBA_CMD21 FBA_CMD6 R3 A8 DQU1 C8 FBA_D46 FBA_CMD6 R3 A8 DQU1 C8 FBA_D58
<52,53> FBA_CMD6 FBA_CMD29 L7 A9 DQU2 C2 FBA_D41 FBA_CMD29 L7 A9 DQU2 C2 FBA_D61
<52,53> FBA_CMD29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D45 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D57
<52,53> FBA_CMD23 FBA_CMD28 N7 A11 DQU4 A2 FBA_D43 FBA_CMD28 N7 A11 DQU4 A2 FBA_D63
<52,53> FBA_CMD28 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D47 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D59
<52,53> FBA_CMD20 FBA_CMD4 T7 A13 DQU6 A3 FBA_D42 FBA_CMD4 T7 A13 DQU6 A3 FBA_D62
<52,53> FBA_CMD4 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
<52,53> FBA_CMD14 NC NC
C C
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2
<52,53> FBA_CMD12 FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
<52,53> FBA_CMD27 FBA_CMD26 M3 BA1 VDD G7 FBA_CMD26 M3 BA1 VDD G7
<52,53> FBA_CMD26 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
<52> CLKA1 CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
<52> CLKA1# FBA_CMD19 K9 CK VDD R9 FBA_CMD19 K9 CK VDD R9
POWER
POWER
RV301 <52> FBA_CMD19 CKE VDD CKE VDD
1 2 +1.35V_MEM_GFX
162_0402_1% FBA_CMD18 K1 A1 +1.35V_MEM_GFX FBA_CMD18 K1 A1
<52> FBA_CMD18 FBA_CMD16 L2 ODT VDDQ A8 FBA_CMD16 L2 ODT VDDQ A8
<52> FBA_CMD16 FBA_CMD30 CS VDDQ FBA_CMD30 CS VDDQ
80.6_0402_1%
80.6_0402_1%
@ @ J3 C1 J3 C1
<52,53> FBA_CMD30 RAS VDDQ RAS VDDQ
1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
<52,53> FBA_CMD15 FBA_CMD13 CAS VDDQ 20130610 FBA_CMD13 CAS VDDQ
RV290
RV291
L3 D2 L3 D2
<52,53> FBA_CMD13 WE VDDQ E9 10U reserve WE VDDQ E9
VDDQ 0.1U_0402_10V7K VDDQ
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
Control & DQM
Control & DQM

VDDQ VDDQ
@ CV293
@ CV294
F3 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2
FBA_WP5 DQSL VDDQ DQSL VDDQ

CV300
CV299
CV298
CV297
CV296
CV295
CV306
CV305
CV303
CV302
CV301
C7 H9 C7 H9
CLKA1_C DQSU VDDQ DQSU VDDQ
CV304
FBA_DQM6 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.01UF_0402_25V7K
@ E7 A9 E7 A9
FBA_DQM5 D3 DML VSS B3 D3 DML VSS B3
1 DMU VSS DMU VSS
CV310
E1 E1
VSS G8 VSS G8
FBA_RN6 G3 VSS J2 FBA_RN4 G3 VSS J2
2 FBA_RN5 B7 DQSL VSS J8 FBA_RN7 B7 DQSL VSS J8
DQSU VSS M1 PLACE UNDER DRAM DQSU VSS M1 PLACE UNDER DRAM 20130610
VSS M9 VSS M9
VSS P1 PLACE CLOSE DRAM VSS P1 10U reserve
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
<52,53> FBA_CMD5 RESET VSS T1 RESET VSS T1 PLACE CLOSE DRAM
FBA_ZQ2 L8 VSS T9 FBA_ZQ3 L8 VSS T9
ZQ VSS ZQ VSS
GND
GND
243_0402_1%
243_0402_1%
1
1
B
J1 B1 J1 B1 B
NC VSSQ NC VSSQ
RV292
RV293
L1 B9 L1 B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

20130606
+1.35V_MEM_GFX +1.35V_MEM_GFX
reduce 1 ???
1.33K_0402_1%
1.33K_0402_1%
1
1
RV297
RV295
2
+FBA_VREF_CA1 +FBA_VREF_DQ1
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1.33K_0402_1%
0.01UF_0402_25V7K
1.33K_0402_1%
0.01UF_0402_25V7K
A BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, A

1
1 1 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
RV298
CV276
RV296
CV275
2 2
2
Title
MARX-VRAM_A Lower
Size Document Number Rev
1.0
LA-E082P
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
7
VCCCLK1~6 SIO_SLP_SUS#
VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
SIO_SLP_S5#
+1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
3 VCCDSW_3P3
SLP_A#
SIO_SLP_A#
CPU
+3.3V_SPI 5 +3.3V_ALW_PCH SIO_SLP_LAN#
11
+VCC_CORE VCCHDA SLP_LAN#
D VCCST_PWRGD VCCSPI D
12 VCCST_PWRGD VCC VCCPRIM_3P3

VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
VCCIO +1.8V_PRIM SYS_PWROK
H_CPUPWRGD 6 16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.2V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.6V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 6 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL 17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
+PWR_SRC
+1.0V_PRIM_CORE SIO_SLP_SUS# +3.3V_ALW
6 TLV62130
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
6 +1.8V_PRIM
TLV62130
+5V_RUN
C 3.3V_TS_EN C
+5V_TSP LP2301ALT1G GPP_B21
+PWR_SRC
6
+3.3V_RUN
+1.0V_PRIM SYX198
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
+5V_ALW +5V_ALW2
EC 5105 SYX198
+5V_ALW
+5V_RUN +5V_HDD 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SYX198
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
B PCH_RSMRST# 5 B
+PWR_SRC 7 SIO_SLP_SUS#
+3.3V_ALW
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO PCH_DPWROK

4 EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
RESET_OUT#
11 +3.3V_WLAN EM5209VF AUX_EN_WOWL 16
Pop option
+3.3V_SPI
5 SIO_SLP_SUS#
10 SIO_SLP_S4#
SIO_SLP_S5#
9
SIO_SLP_LAN#
MCP 23008
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
RT8207MZ VTT
DDR
+0.6V_DDR_VTT
PCH_PWROK
12
0.6V_DDR_VTT_ON
A
SM BUS 14 A

Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Re v
1.0
LA-E082P
Date : Monday, December 12, 2016 Sheet 55 of 75
5 4 3 2 1
5 4 3 2 1
D D
1
C C
B B
A A
Title
Stack-up
LA-E082P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
EMC@ PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
@ JRTC1
1 3
+COINCELL 2 1 G 4
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
EMC@ PD1 EMC@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C
@ PBATT1
1 2 +PBATT
PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <34,66>
6 6 3
PBAT_CHARGER_SMBCLK <34,66> PBAT_PRES# <34,66>
1
6 7 5 4
EMC@ PC1
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
@ PR3
2
GND 1 2
0_0402_5%
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 PS_ID
S
PS_ID <34>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 EMC@
1
PESD5V0U2BT_SOT23-3 C
2 PQ3 PR7
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
5A_100V 15UA_0.88V_TO227-3
2
DC_IN+ Source 1
3
+DC_IN +3.3V_VDD_DCIN +DC_IN
S1 S2 +SDC_IN
PU2
PQ9 +DC_IN_SS PQ4
1U_0603_50V6K
2 1
AON7409_DFN8-5 AON7409_DFN8-5 3 VIN
+SDC_IN VOUT
PC11
EMC@ PL4 1 1
PC4 0.022U_0603_50V7K
FBMJ4516HS720NT_2P 2 2 1
1
1 2 3 5 5 3 GND 2
PQ5 AO3409_SOT23
PR11 499K_0402_1%
PR10 11/11
1
300K_0402_1% AP2204RA-3.3TRG1_SOT89-3
1
PC10
499K_0402_1%
4
1
3
B S B
2.2U_0402_10V6M
0.022U_0603_50V7K
2
2
G
2
2
PC6
PR12
4.7K_0805_5%
10U_0805_25V6K
1000P_0603_50V7K
2
1
1
D
@ PJPDC1 +3.3V_VDD_DCIN
100K_0402_5%
0.1U_0603_25V7K
1
1
7
PC8
PR15
2
1
GND 6
EMC@ PC5
PC7
@ PR13
100K_0402_5%
2
GND -DCIN_JACK
PR14
5
2
5 4
2
2
1
1
4 +DCIN_JACK
3
@EMC@
49.9K_0402_1%
2
3 2 PR16 PR17
2 1 100K_0402_5%
6
1
1
CVILU_CI0805M1HRC-NH
2
2
PQ1A
PR18 2 2 1
L2N7002WT1G_SC70-3
PC9 49.9K_0402_1%
+3.3V_VDD_DCIN
1
2 1 D
@ PR19
2
1
PQ7
2 1 2 0_0402_5%
0.1U_0402_10V7K G
S @ PR20
3
@ PR21 PU1 0_0402_5% VBUS2_ECOK <35,67>

L2N7002WT1G_SC70-3
5
0_0402_5% MC74VHC1G08DFT2G_SC70-5
1
3
<34,66,67> ACAV_IN_NB 1 2 1 @ PR23 D
P
B
PQ6
4 2 1 2
1 2 2 O
PQ1B
G
G
A 0_0402_5% PR24 5 2 1
S AC_DISC# <34,67>
3
@ PR22 100K_0402_5%
3
0_0402_5% @ PR25
4
0_0402_5%
PQ8
@ PR26 L2N7002WT1G_SC70-3
0_0402_5%
S
1 2 3 1
<35> DCIN2_EN
G
2 2
1
A A
100K_0402_5%
1
PR28
0_0402_5%
@ PR29
PR27
2
100K_0402_5%
1
+3.3V_VDD_DCIN
+3.3V_ALW Compal Electronics, Inc.
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1
LA-E082P
5 4 3 2 1
A B C D E
@ PR119
0_0402_5%
PGOOD_3V 1 2
ALW_PWRGD_3V_5V <45>
PGOOD_5V 1 2
1 @ PR120 1
0_0402_5%
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
+PWR_SRC
@
PJP100 @ PR100 PC102
1
3V_VIN BST_3V BST_3V_R
499K_0402_1%
1 2 1 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
1
PU100
2
10U_0805_25V6K
10U_0805_25V6K
100P_0402_50V8J
100P_0402_50V8J
RF@ PC100
RF@ PC103
BS
IN
IN
IN
IN
1
1
LX_3V
PC105
PC104
6 20 PL100
LX LX 1.5UH_9A_20%_7X7X3_M
2
2
7 19 LX_3V 1 2
GND LX +3.3V_ALWP
8 SY8288BRAC_QFN20_3X3 18
GND GND
RF@ PR106
680P_0603_50V7K 4.7_1206_5%
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2
1
@ PR104
PC106
PC107
PC108
PC109
PC129
PC110
10 16 0_0402_5%
NC NC 1 2 +3.3V_RTC_LDO 3VALWP
OUT
2
EN2
EN1
21
NC
@ PR105
FF
GND 0_0402_5% TDC 6.8 A
1 3V_SN 2
PR107
Peak Current 9.7 A
11
12
13
14
15
100K_0402_5%
RF@ PC112
2 2
+3.3V_ALW
1 2 3.3V LDO 150mA~300mA OCP Current 9 A f i x by I C
1
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0603_6.3V6K
2
PGOOD_3V
@
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 3V_FB_R 1 2 JUMP_43X118
+PWR_SRC
@
PJP103
+5V_ALWP 1 2 +5V_ALW
1 2
@
PJP101 @ PR111 PC114

1 2 5V_VIN BST_5V 1 2 BST_5V_R 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K

0_0603_5%
5
1
100P_0402_50V8J
100P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
RF@ PC115
RF@ PC116
PU102
1
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 1.5UH_9A_20%_7X7X3_M
7 19 LX_5V 1 2
3 GND LX +5V_ALWP 3
4.7_1206_5%
8 SY8288CRAC_QFN20_3X3 18
GND GND
1
@EMC@
PR112
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
PC119
1
9 17 1 2
PC120
PC121
PC122
PC123
PC130
PC124
PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6K
5V_SN
OUT
LDO
2
EN2
EN1
21
FF
GND
680P_0603_50V7K
1
11
12
13
14
15
@EMC@
PC125
PR113
100K_0402_5%
+5V_ALW2
2
@ PD100 1 2
+3.3V_ALW
ENLDO_3V5V
RB520SM-30T2R_EMD2-2
3V5V_EN
2 1 5V LDO 150mA~300mA
1
PGOOD_5V
PC126
4.7U_0603_6.3V6K
@ PR114
5VALWP
2
1 2
<34> ALWON
TDC 6.5 A
0_0402_5%
Peak Current 9.3 A
3V5V_EN
OCP Current 9 A f i x by I C
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR116
PC128
PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 5V_FB_R 1 2
2
2
4 4
EN1 and EN2 dont't floating
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
A B C D E
5 4 3 2 1
D D
vinafix
+PWR_SRC
@PJP202
1 2 +1.2V_DDR_B+
PU200
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 1x2m~D
2200P_0402_50V7K
0.1U_0402_25V6
1
10 19 RF@ PR202 RF@ PC204

PC200
PC201
PC202
PC203
+3.3V_ALW
IN OT 4.7_1206_5% 680P_0603_50V7K
13 18 @ PR203 PC205 1 2 +1.2V_DDR_SNB 1 2
2
BYP PG
1U_0402_6.3V6K
+1.2V_DDR_VCC 14 12
0_0603_5%
+1.2V_DDR_BST
1
0.1U_0603_16V7K
2+1.2V_DDR_BST_R
1 2
+1.2V_DDRP
@EMC@
@EMC@
VCC BS
1
PC206
C PL201 C
4 11 +1.2V_DDR_LX 1 2
VTTGND LX
1
2.2U_0402_6.3V6M
330P_0402_50V7K
1UH_11A_20%_7X7X3_M
2
+1.2V_DDR_FB
PC207
9 16
PGND FB
1
PC208
102K_0402_1%
2
+1.2V_DDRP
PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2200P_0402_50V7K
22U_0603_6.3V6M
R1
100P_0402_50V8J
7 1 2
VLDOIN
1
PC210
PC211
PC212
PC213
PC223
PC214
PC216 @EMC@
PC217 @EMC@
2
2
ILMT_DDR 17 6
@ PR205 ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A
1
+1.2V_DDR_VTTREF
100K_0402_1%
2 3
1
when this pin is pull S3 VTTREF
PR206
low, floating or pull
22U_0603_6.3V6M
SY8210AQVC_QFN19_4X3
EN_1.2V
high
1
1U_0402_10V6K
PC218
+1.2V_DDR OCP set 8A
2
2
PC219
EN_0.6V
@ PR207
2
0_0402_5%
1
@ PR208
0_0402_5%
2 1
B <11,17,34,62> SIO_SLP_S4# B
0.1U_0402_10V7K
1M_0402_5%
1
1
@ PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@ PJP200 @ PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
@ PR210 1 2 1 2
0_0402_5%
<20> 0.6V_DDR_VTT_ON
2 1
0.1U_0402_10V7K
1M_0402_5%
1
@ PC222
+1.2V_DDR 0.6Volt +/- 5%

PR212
TDC 6.2A TDC 1.05A

2
Mode S3 S5 VOUT VTT Peak Current 8.9A Peak Current 1.5A

Normal H H on on
2
Stadby L H on off OCP Current 10.6A OCP Current 2A (fix)

Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
D D
@ PR312
0_0402_5%
1 2
SIO_SLP_SUS# <11,17,34,47,61,62>
+1VALW P_EN
1
1M_0402_1%
PR302 @ PJP302
+1VALWP 1 2 +1.0V_PRIM
2
1 2
JUMP_43X118
RF@ PR303 RF@ PC302

4.7_1206_5% 680P_0603_50V7K
2 +1VALW P_SNB 1
+PWR_SRC @ PJP301
+1VALW P_B+
PU301
1 2
1 2 8 1 PC304 @ PR304
100P_0402_50V8J
100P_0402_50V8J
IN EN 0.1U_0603_25V7K 0_0603_5%
10U_0603_25V6M
10U_0603_25V6M
PAD-OPEN 1x2m~D 6 +1VALW P_BST 1 2+1VALW P_BST_C
1 2 PL301
BS
1
1
PC305 0.68UH_7.9A_20%_5X5X3_M
PC306
9 10 +1VALW P_LX 1 2 +1VALWP
RF@ PC301
RF@ PC303
C C
GND LX
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
330P_0402_50V7K
1
1
4 +1VALW P_FB
FB
PC307
PC308
PC309
PC310
PC311
21.5K_0402_1%
1
+1VALW P_ILMT 3 7
+3.3V_ALW
2
ILMT BYP
PR306
4.7U_0603_6.3V6K
+3.3V_ALW 2 5
PG LDO
1
PC312
+1VALWP_LDO
1K_0402_5%
SYX196DQNC_QFN10_3X3
PR308
2
1
2
PR307
2
4.7U_0603_6.3V6K
2
1
+1VALW P_ILMT
PC313
1
1
PR311
2
31.6K_0402_1%
@ PR310
0_0402_5%
2
+1.0V_PRIM
2
TDC 5.4A
Peak Current 10.5 A
OCP 12.6A
B OCP Current 9 A Fix by IC B
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A
Title
+1VALWP
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-E082P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
1
@ PR425
0_0402_5% @ PR404 0 X X 0(LPM)
<11,17,36,61> SIO_SLP_S0# 1 2 0_0402_5%
@ PJP401
TPS62134C 1 0 0 0.80
2
JUMP_43X79 1 0 1 0.95
@ PR402 1 2
0_0402_5% +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
1 2
<17,34,35,47> RUN_ON
LPM_1VS_VCCIO
1 1 1 1.05
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
PC402
PR403
D 1M_0402_1% D
2
@
13
14
15
16
17
PU401
Vin=3~17V
+1.0VS_VCCIO
EN
PGND
PGND
TP
LPM
@ PJP403
TDC 2.2 A
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP Peak Current 3.1 A
PL402 OCP Current 4.2 A Fix by IC
10U_0603_10V6M
10U_0603_10V6M
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
TYP MAX
1
LX_1VS_VCCIO
+3.3V_ALW 11 2 1 2
+1VS_VCCIOP
PC403
PC404
PVIN SW
Choke DCR 48.0mohm
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
TPS62134CRGT_QFN16_3X3
1
10 3
PC406
PC407
PC422
AVIN SW
2
100P_0402_50V8J
0.1U_0402_25V6
1
1
VID0_VCCIO 9 4
PC408
RF@ PC409
VID0 PG RF@
1SNUB_1VS_VCCIO
1
PR405
AGND
4.7_0603_5%
VID1
FBS
@ PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_VCCIO
SS_1VS_VCCIO
VID1_VCCIO RF@ +1VS_VCCIOP
VID1_VCCIO PC401
0_0402_5%
1
680P_0402_50V7K
2
1
PR421
PR415 @ PR416
470P_0402_50V7K
10K_0402_1% 10K_0402_1%
2
1
1
@ PR422
0_0402_5%
C C
2
FB_1VS_VCCIO 1 2
PR427
PC410
VCCIO_SENSE <17>
2
0_0402_5%
@ @ PR412
2
1 2
VSSIO_SENSE <17>
0_0402_5%
"R" for SILERGY

+3.3V_ALW
1
@ PR426 @ PR410
0_0402_5% 0_0402_5%
1
<11,17,36,61> SIO_SLP_S0#
2
@ PJP402
@ PR406 LPM_1.0V_PRIM_COREP JUMP_43X79
EN_1.0V_PRIM_COREP
0_0402_5% 1 2
<11,17,34,47,60,62> SIO_SLP_SUS# 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6
1
1
PC411
PR407
1M_0402_1%
2
@
2
13
14
15
16
17
PU402
B Vin=3~17V B
EN
PGND
PGND
TP
LPM
@ PJP404
VIN_1V_PRIM
+5V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW PL404
10U_0603_10V6M
10U_0603_10V6M
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
1
LX_1V_PRIM
11 2 1 2
+1.0V_PRIM_COREP
PC412
PC413
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
TPS62134DRGT_QFN16_3X3
1
10 3
PC424
PC415
PC416
AVIN SW
Rup
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
2200P_0402_50V7K
0.1U_0402_25V6
1
9 4
PC417
0 X X 0.7(LPM)
@EMC@ PC418
VID0 PG RF@
PR417 PR418 PR409 TPS62134D 1 0 0 0.85
2
AGND
10K_0402_1% 10K_0402_1% 4.7_0603_5%

1SNUB_1V_PRIM
VID0_PRIM_CORE
VID1
FBS
@EMC@
SS
1 0 1 0.90
2
VID0_PRIM_CORE
1 1 0 0.95
8
VID1_PRIM_CORE
1 1 1 1.00
1
RF@
VID1_PRIM_CORE
@ PR408 PC419
@ PR419 @ PR420 0_0402_5% 680P_0402_50V7K
SS_1V_PRIM
10K_0402_1% 10K_0402_1% 1 2
<18> CORE_VID0
2
@ PR411
+1.0V_PRIM_CORE
0_0402_5%
FB_PRIM_CORE
TDC 1.8 A
1 2 1 2
<18> CORE_VID1 Peak Current 2.6 A
@ PR423 OCP Current 4.2 A Fix by IC
470P_0402_50V7K
0_0402_5%
1M_0402_1%
TYP MAX
1
1
PR428
A A
@ PR424 Choke DCR 48.0mohm
PC420
100K_0402_1%
2
@
2
"R" for SILERGY
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
0.1
LA-E082P
5 4 3 2 1
5 4 3 2 1
PC502
22U_0603_6.3V6M @ PJP502
1 2 1 2
+1.8VALWP +1.8V_PRIM
PAD-OPEN1x1m
@ PJP501
1 2 VIN_1.8VALW
+3.3V_ALW Imax= 2A, Ipeak= 3A
PAD-OPEN1x1m
FB=0.6V
D D
PU501
PR517 PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
100K_0402_5% IN LX +1.8VALWP
1
5 2
68P_0402_50V8J
<34> 1.8V_PRIM_PWRGD PG GND RF@
1SNUB_1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
1
6 1 PR502
PC503
1
1
FB EN 4.7_0603_5%
PC501
PC504
PR501
2
RT8097ALGE_SOT23-6
2
20K_0402_1%
1 2 EN_1.8VALW
<11,17,34,47,60,61> SIO_SLP_SUS# Rup
2
RF@
@ PR504 PC506
1
0_0402_5% 680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% 0.1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.7 A
Note: Peak Current 1A
2
When design Vin=5V, please stuff snubber OCP Current 3.5A f i x by I C
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
C C
B B
+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
OCP is 1.1~1.5A
@ PU503
PJP505
AP7361C-FGE-7_U-DFN3030-8_3X3 @ PJP506
1 2 +2.5V_VIN 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT
+2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2 PAD-OPEN1x1m
1
4.7U_0603_6.3V6K 7 NC PR515
2
NC 3 21.5K_0402_1% PC515
6 ADJ/NC 0.01UF_0402_25V7K
2
NC
1
4
EN_2.5V GND PC516
1 2 5
<11,17,34,59> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
@ PR513
1
0_0402_5%
@ PC513
PR514 PR516
2
1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%

A A
2
Title
+1.8VALWP/+2.5VSP
0.1
LA-E082P
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST VCC_SA
TDC 4A
Peak Current 4.5A
0.1U_0402_25V6
OCP current 5.4A
1
45.3_0402_1%
100_0402_1%
75_0402_1%
PC602
1 2
+5V_ALW Choke DCR 13 m ohm
PR605
PR601
PR604
@ PR602
Local sense put on HW site
2
0_0402_5% @ PJP603
0.22U_0603_25V7K
@ 1 2CPU_B+
1U_0603_10V6K
1 2
D 1 2 @ PR603 VCCSA_B+ CPU_B+ D
<15> VIDSCLK
1
49.9_0402_1% PR618 0_0402_5%
PC603
PC604
PAD-OPEN1x1m
<15> VIDALERT_N 1 2
@ 0_0402_5% PR625
2
<15> VIDSOUT 1 2
10_0402_1% PR626
PR678 VCCSA_B+
VIDALERT_N_B
<12,34,66> H_PROCHOT#
VIDSOUT_B
VIDSCLK_B
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
PR608
VR_HOT#_CPU
10U_0805_25V6K
10U_0805_25V6K
PH601 PR610 78.7K_0402_1%
470K_0402_5% 10K_0402_1% 1 2
1 2 NTC_GT_R1 2 PR613 1.91K_0402_1% PR612
PROG1_CPU
PROG2_CPU
1
2VR_READY_CPU
PC612
PC608
84.5K_0402_1% 1 PR611
+3.3V_RUN
VCC_CPU
VIN_CPU
1 2 1 2 48.7K_0402_1%
PR631 PC613 <11> PCH_PWROK 1 2
2
27.4K_0402_1% 330P_0402_50V7K @ PR614 0_0402_5%
1 2 1 2EN_CPU
<35> IMVP_VR_ON
PC614 PR617 @ PR616 0_0402_5%
2200P_0402_50V7K 3.92K_0402_1%
1 2 1 2
40
39
38
37
36
35
34
33
32
31
PU602 SA_UGATE
PC616 PR619 2.2_0603_5%
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
68P_0402_50V8J @ PR620 1 2
1 2 PC617 PR621 0_0402_5%
BST_C_SA
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA PU614
<34,66> I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2778_DFN8_2X2~D PQ501
<16> VCC_GT_SENSE NTC_GT IMON_B FCCM_C ISUMN_R_VSA
PR622 3 28 AON7934_DFN3X3A-8-10
D1
D1
D1
G1
@ PC618 1.91K_0402_1% COMP_GT 4 NTC_B ISUMN_C 27 PC611 1 8 PL614
FB_GT COMP_B ISUMP_C UGATE PHASE
0.082U_0402_16V7K
1 2 1 2 5 26 0.22U_0603_16V7K 0.47UH_MMD05CZR47M_12A_20%
RTN_GT FB_B RTN_C FB_VSA 2BST_SA 2 9 SA_SW
@ PC620
6 25 1 7 10 2 1
RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA
1
330P_0402_50V7K 7 24 COMP_VSA
PC621 PR623 ISUMN_R_GT 8 ISUMP_B COMP_C 23 IMON_VSA PWM_SA 3 6
ISUMN_B IMON_C PWM VCC
2
C C
PC619 1200P_0402_50V7K 2K_0402_1% 9 22
G2
S2
S2
S2
2
ISEN1_B PWM_A PWM_IA <64>
1
SA_LGATE
4.7_1206_5%
@EMC@ PR627
1 2 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_IA <64> GND LGATE
1
PR606 @
TP
ISUMN_A
ISUMP_A
PR624
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
IMON_A
0.01UF_0402_25V7K 41 0_0402_5%
+5V_ALW
NTC_A
RTN_A
AGND 3.65K_0603_1%
1
FB_A
<16> VSS_GT_SENSE
9
PR679 @
2
PWM_VSA 0_0402_5%
ISUMP_VSA 2
+5V_ALW
1SA_SNUB
ISUMN_VSA
11
12
13
14
15
16
17
18
19
20
ISL95857AHRTZTS27_TQFN40_5X5~D
2
1
680P_0603_50V7K
1U_0402_10V6K
FCCM_VSA
<64> ISUMP_GT
IMON_IA
FB_IA
<64> FCCM_GT
NTC_IA
COMP_IA
4.42K_0402_1%
PC685
@EMC@ PC622
2
1
PR628
PC625
330P_0402_50V7K
2
1 2
0.047U_0402_25V7K
PR629
2
0.033U_0402_16V7K
95.3K_0402_1%
1
1
33P_0402_50V8J
2.49K_0402_1%
PC624
PC626
1 2
PR630
PH603
1
1
2200P_0402_50V7K
4700P_0402_25V7K
10K_0402_5%
11K_0402_1%
PR632 PC627 470K_0402_5%

2
2
1
2200P_0402_50V7K
PH602
PR633
PC628
1K_0402_1% 1 2 1 2
1 2 1 2
2
PR647 27.4K_0402_1% PR635 1 2
PR638 1 2 10K_0402_1%
2.61K_0402_1%
2
1
365_0402_1%
PC630
340_0402_1% PR636 665_0402_1%
2
1
PC629
PC631
1 2
PR642
<64> ISUMN_GT PR639
2200P_0402_50V7K
PR640
3.6K_0402_1% 1 2 1 2
2
1 2 1 2
.1U_0402_16V7K
0.033U_0402_16V7K
PC632 PR641
2
1
2
1K_0402_1%
11K_0402_1%
PC636 1000P_0402_50V7K 1K_0402_1%
3300P_0402_25V7K
68P_0402_50V8J
PC641
PR643
1
1
PR644
PC633
1 2
PC637
2
10KB_0402_5%
1
B PC639 PR645 PR646 PC640 B
PH604
2200P_0402_50V7K 316_0402_1% 1 2 1 2
330P_0402_50V7K
1 2 1 2
2
316_0402_1% 2200P_0402_50V7K
PR648
2
1 2 PR649
1
130K_0402_1%
1 2
1
1.5K_0402_1% PC642 ISUMN_VSA
1200P_0402_50V7K 2K_0402_1%
680P_0402_50V7K 2K_0402_1%
PC643
PR651
0.033U_0402_16V7K 1.62K_0402_1% PC644
1
1
1 2 .1U_0402_16V7K
2
.1U_0402_16V7K
@ PR652
1 2
2
1
PR650
PC645
2
1 2
PC646
0.047U_0402_25V7K
2
VSA_SEN- <17>
PC647
@ PC601
1 2
2
1
PC649
0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
PR656
11K_0402_1%
<15> VCCSENSE
2
PC650
1 2
@ PC652
PR657
1
@ PC651 PH605 @ 330P_0402_50V7K
1 2 4.42K_0402_1% 10KB_0402_5% 1 2
0.082U_0402_16V7K
1 2 1 2
@ PC653
330P_0402_50V7K
1
VSA_SEN+ <17>
ISUMN_IA <64>
2
PC654
A A
1 2
ISUMP_IA <64>
0.01UF_0402_25V7K
<15> VSSSENSE
Local sense put on HW site
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL VCCSA_ISL95857
5 4 3 2 1
5 4 3 2 1
D
@ +PWR_SRC VCC_core D
PJP601
TDC 21A
1 2
Peak Current 32A
CPU_B+ PAD-OPEN 4x4m OCP current 38.4A
@EMC@ PL602
9A Z80 10M 1812_2P Choke DCR 0.9 +-7%m ohm
1 2
100U_D_20VM_R55M
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
PC606
+
1
1
PC656
PC657
PC658
PC663
@EMC@ PC659
@EMC@ PC660
2
2
VCC_GT
TDC 18A
Peak Current 31A
PU610
PL610
0.15UH_MMD06CZER15MG_37A_20%
OCP current 37.2A
PC655 9
PGND2
Choke DCR 0.9 +-7%m ohm
0.22U_0603_16V7K 8
<63> PWM_IA BST_C_IA PWM
1 2BST_IA
7 4 IA_SW 4 1
BOOT VSW
PGND1
3 +VCC_CORE
1 2BST_R_IA 6 2 3 2
BOOT_R VDD
4.7_1206_5%
@EMC@ PR663
PR660 5 1
VIN SKIP#
1
2.2_0603_5% @ PJP602
1FCCM_R_IA
1
1 2
C PR661 GPU_B+ CPU_B+ C
10P_0402_50V8K
CSD97396Q4M_VSON8_3P5X4P5
1
1
5.11K_0402_1%
3.65K_0603_1% PAD-OPEN 1x2m~D

1
1U_0402_10V6K
PC686
PR662
PC680
+5V_ALW
2
1
1000P_0402_50V7K
2
2
PC661
2
<63>
<63>
ISUMP_IA
ISUMN_IA
@ PR659
2
IA_SNUB
0_0402_5%
2
GPU_B+
680P_0603_50V7K
1
@EMC@ PC662
1
5.11K_0402_1%
<63>
PR681
FCCM_IA
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@
2
1
PC665
PC664
PC672
PC673
2
2
PL612
PU612
0.15UH_MMD06CZER15MG_37A_20%
PC671 9
B 0.22U_0603_16V7K 8 PGND2 B
<63> PWM1_GT
1 7 PWM
2BST_GT 4 GT_SW1 4 1
BST_C_GT BOOT VSW
PGND1
3 +VCC_GT
1 2BST_R_GT
6 2 3 2
5 BOOT_R VDD
4.7_1206_5%
@EMC@ PR676
PR672 1
2GT1P
VIN SKIP#
1
2.2_0603_5%
FCCM_R_GT
10P_0402_50V8K
CSD97396Q4M_VSON8_3P5X4P5
1
5.11K_0402_1%
PR674
1U_0402_10V6K
PC688
PR680
PC679
+5V_ALW
3.65K_0603_1%
2
1
1000P_0402_50V7K
PC677
2
<63>
ISUMN_GT
GT_SNUB1
@ PR671
2
0_0402_5%
2
<63>
680P_0603_50V7K
FCCM_GT
<63>
1
ISUMP_GT
5.11K_0402_1%
1
@ PR682
@EMC@ PC678
2
2
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL VCC_CORE/GT_ISL95857
5 4 3 2 1
4
+VCC_CORE
A
A
+330u_D2*2 pcs
22U_0603 * 33 pcs +1U_0201*35 pcs
VCC_CORE Place on CPU
2 1 2 1 2 1
1
+
330U_D2_2.5VM_R9M
PC1099 PC1083 PC1076
PC1127
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
1
+
330U_D2_2.5VM_R9M
PC1095 PC1030 PC1081 PC1078
PC1062
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
@ PC1170 PC1094 PC1031 PC1080 PC1077

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
@ PC1171 PC1096 PC1032 PC1082 PC1079

2 1 2 1 2 1 2 1 2 1
RF@ PC1172 PC1090 PC1033 PC1067 PC1001

100P_0603_50V8 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
@ PC1173 PC1093 PC1034 PC1072 PC1002

2 1 2 1 2 1 2 1 2 1
RF@ PC1174 PC1091 PC1035 PC1069 PC1003

100P_0603_50V8 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1097 PC1036 PC1074 PC1004

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
B
B
vinafix
PC1092 PC1037 PC1070 PC1005
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1098 PC1038 PC1061 PC1006

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1050 PC1039 PC1071 PC1007

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1051 PC1084 PC1066 PC1008

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1052 PC1086 PC1073 PC1009

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC1054 PC1088 PC1075 PC1011

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
22U_0603 * 12 pcs + 1U_0201*7 pcs
VCC_SA Place on CPU
PC1126 PC1087 PC1064 PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1164 PC1089 PC1065 PC1013

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
C
C
2 1
PC1125
1U_0201_6.3V6M
+VCC_GT
+VCC_SA
2 1 2 1 2 1
+330u_D2*2 pcs
22U_0603 * 26 pcs +1U_0201*12 pcs
VCC_GT Place on CPU (U22)
2
1
+
330U_D2_2.5VM_R9M
PC1040 PC1133 PC1014
PC1128
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+
330U_D2_2.5VM_R9M
PC1041 PC1137 PC1015
PC1063
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2 1 2 1 RF@ PC1181 PC1042 PC1129 PC1016

100P_0603_50V8 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
PC1153 PC1057 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 RF@ PC1180 PC1043 PC1132 PC1017
100P_0603_50V8 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1147 PC1058 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1177 PC1044 PC1136 PC1018
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1148 PC1059 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1179 PC1045 PC1134 PC1019
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1149 PC1060 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1176 PC1046 PC1135 PC1020
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Date:
Size
Title
PC1150 PC1139 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1178 PC1047 PC1138 PC1021
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Monday, December 12, 2016
Document Number
PC1151 PC1140 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1175 PC1048 PC1027 PC1022
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1152 PC1141 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
PROCESSOR DECOUPLING
2 1 PC1049 PC1028 PC1023

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
LA-E082P
PC1142 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC1055 PC1130 PC1024
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1143 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC1056 PC1029 PC1025
E
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Sheet
PC1144 2 1 2 1
22U_0603_6.3V6M
2 1 PC1131 PC1026
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1145
65
22U_0603_6.3V6M
2 1
of
PC1146
22U_0603_6.3V6M
71
R ev
0.1
1
A B C D
+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901
0.01_1206_1% EMC@ PL901
1UH_6.6A_20%_5X5X3_M
1 4 2 1
2 3 +PWR_SRC
2200P_0402_50V7K
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
0.1U_0402_25V6
15U_B2_25VM_R100M
15U_B2_25VM_R100M
15U_B2_25VM_R100M
1 1 1
@EMC@ PC902
@EMC@ PC903
1
1
PC911
PC904
PC905
PC906
PC909
PC910
PC951
@ PJP901 + + +
1 2
2
1 PAD-OPEN 4x4m @ 2 @ 2 @ 2 1
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
1
1
PC913
PC914
PC915
PC916
PC917
PC918
PC919
PC920
2
2
1
1
PR909 PR910
3.3_0402_1% 3.3_0402_1%
2
CSIN_ISL88738
PC925
CSIP_ISL88738
4.7U_0402_6.3V6M
2200P_0402_50V7K
1 2
0.1U_0402_25V6
1U_0402_25V6K
1U_0402_25V6K
1
@EMC@ PC928
@EMC@ PC929
1
1
PC926
PC927
2
2
2
2
PC930
+SDC_IN @ PR943
PD901 0_0603_5% 0.22U_0603_25V7K
1
2 1 2 1 ADP_ISL88738
+PWR_SRC
2
SDMK0340L-7-F_SOD323-2~D
1
PR914
PD903
PR944 3.3_0603_1%
2 1
+VBUS_DC_SS 442K_0402_1%
1
2 2
2
RB520SM-30T2R_EMD2-2
ACIN_ISL88738
CSIP_ISL88738
CSIN_ISL88738
BOOT1_ISL88738
UG1_ISL88738
LX1_ISL88738
LG1_ISL88738
0.1U_0402_25V6
PD904
1
2 1
+DC_IN_SS
1
PC1286
PR945 PR915
SDMK0340L-7-F_SOD323-2~D 100K_0402_5% 4.7_0402_5%
2
1 2 VDD_ISL88738
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
ISL88738HRTZ-T TQFN 32P PWM PQ905 PQ904
PC931 1U_0603_25V6 CSD87351Q5D_SON8-7 CSD87351Q5D_SON8-7
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
1
PC932
+VCHGR PQ906
1
1 2 DCIN_ISL88738 1U_0402_6.3V6K
VDDP_ISL88738 2UG2_ISL88738 PR917 AON7409_DFN8-5
DCIN VDDP
2 1
1 2
VDD_ISL88738 18 7 LG2_ISL88738
PL902 0.005_1206_1% 1
2
+PBATT
2.2UH_PCMB103T-2R2MS_13A_20%
VDD LGATE2
2
7 7 1 4 3 5
PC933 PR918 @ 6 1 6 LX2_ISL88738
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 5 5 2 3
100K_0402_1%
1 4
4
OTGEN/CMIN UGATE2 PC934 PR921 SW1_ISL88738 SW2_ISL88738
1
ACAV_IN1 1@ PR920 SDA_ISL88738

20_0402_5% 21 4 BOOT2_ISL88738 2 1 2 1
10U_0805_25V6K
10U_0805_25V6K
<34,57> PBAT_CHARGER_SMBDAT SDA BOOT2
1
4.7_1206_5%
4.7_1206_5%
1
SCL_ISL88738 VSYS_ISL88738
EMC@ PR923
EMC@ PR924
PQ909 1@ PR922 20_0402_5% 22 3 0.22U_0603_25V7K 4.7_0603_5%
4700P_0402_25V7K
<34,57> PBAT_CHARGER_SMBCLK
8
SCL VSYS
1
1
D
PC935
PC936
L2N7002WT1G_SC70-3 PR925
OTGPG/CMOUT
2
2 PROCHOT#_ISL8873823 CSOP_ISL88738
PC937
2 154K_0402_1% 1@ PR926 0_0402_5% 2
<12,34,63> H_PROCHOT# PROCHOT# CSOP
AMON/BMON
<34> AC_DIS G
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
CSON_ISL88738
BATGONE
S <67> PROCHOT#_ISL88738
24 1
3
1
ACOK CSON @
BGATE_ISL88738
BGATE
CMOP
PROG
PSYS
VBAT
@ PR928 0_0402_5% @ PR929 0_0402_5%

1 2 ACOK_ISL88738 1 2
680P_0603_50V7K
680P_0603_50V7K
PR927 +PWR_SRC
2
1M_0402_1% @ PR930 PC938

25
26
27
28
29
30
31
BGATE_ISL88738 32
EMC@ PC940
EMC@ PC941
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 2
VBAT1_ISL88738
105K_0402_1%
<34,57> PBAT_PRES# 100K_0402_1%
2
1
3
1 2 BATGONE_ISL88738 @ PC939 0.1U_0402_25V6 3
PR932
0_0402_5%
PR933
100K_0402_1%
1 2
+3.3V_ALW PR951
2
@ 0_0402_5%
1 2
<67> CMOUT
@ PR949
COMP_ISL88738
2
1 2
499_0402_1%
1
PR934
560P_0402_50V7K
PC942 1U_0402_25V6K
0_0402_5%
0.1U_0402_25V6
1
1
PC943
1 2
12.7K_0402_1%
1
PC947
@ PR936
PR948
2
2
0_0402_5%
PC945 PR937 2.2_0402_1%

2
1
0_0402_5%
@ 4.7U_0402_6.3V6M
0.01UF_0402_25V7K
2
1
1
PC944
@ PR947
1 2
2
PR938 2.2_0402_1% LM393_P

2
PR935
@ PR950
2
1 2 0_0402_5%
I_SYS <34,63> 1 2
@ PC946 1U_0402_25V6K
PD905
I_BATT
I_ADP
PR939 BAT54CW-7-F SOT-323 PC949

@ 0_0402_5% 0.1U_0402_10V7K
<26,67> AC1_DISC#
1 2 3 1 2
MC74VHC1G08DFT2G_SC70-5
I_BATT <34> PR941 1 PU903
5
I_ADP <34> +PBATT @ 0_0402_5%
1 2 2 1
@ PR946
0_0402_5%
P
<34,57,67> ACAV_IN_NB B <34,35> ACAV_IN
2 1 4 1 2
ACAV_IN1
1 2 2 Y
Close to EC ADP_I pin A
1
PR940
2
4
100_0402_5% @ PR942 PR953 4
3
@ PC950 0_0402_5% 100K_0402_1%
0.1U_0402_25V6
1
2
For IT8010 voltage
leakage issue
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title
CHARGE
0.1
A B C D
5 4 3 2 1
PD1202
5A_100V 15UA_0.88V_TO227-3
2
1
3
DCIN_AC_Detector
@ PC1201
0.01U_0402_25V7K~D S4 S5
1 2
PQ1213 +VBUS_DC_SS PQ1202
AON7409_DFN8-5 AON7409_DFN8-5
+3.3V_VDD_DCIN PD1801
1 1
+DC_IN 3 +3.3V_VDD_DCIN +AC_IN 2 2
+SDC_IN
1500P_0402_50V7K
+3.3V_VDD_DCIN
D 3 5 5 3 D
1
1
PQ1203 AO3409_SOT23
PR1207 499K_0402_1%
LM393_P
2200P 50V K X7R 0603

PR1251 PR1202
AO3409_SOT23
499K_0402_1%
+3.3V_VDD_PIC 2 300K_0402_1% 300K_0402_1%
4
1
1
3
3
S S
BAT54CW-7-F SOT-323
PQ1215
PC1202
PR1205
2
2
PR1203 +3.3V_VDD_PIC 2
G G
2
2
1.8M_0402_1%
2
1
1
D D
1 2 +3.3V_VDD_PIC
PC1203
1
1
PR1206 PR1252
1
1K_0402_1% 100K_0402_5% PR1209
PR1253
LM393_P
240K_0402_1%
100K_0402_5%
1
1
102K_0402_1%
100K_0402_5%
6 2
1
PR1201
2
1
PR1214
PR1208
49.9K_0402_1%
2
PR1213
PR1212
PU1201A 100K_0402_5%
3
49.9K_0402_1%
PQ1214A
2
LM393DGKR_VSSOP8 EN_PD_HV_1# 2
3 2
2
3
PQ1204B
P
2
+
3
(>17.6V) 1 ACAV_IN_NB 5 1 2
1
2 O ACAV_IN_NB <34,57,66,67>
G
@ PR1218
PQ1214B
PQ1201B
4
6
5 VBUS1_ECOK 2 1 5 0_0402_5%
23.2K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
<26,67> EN_PD_HV_1
4
1
84.5K_0402_1%
1
@PR1220
PQ1201A
PR1219
PC1205
PC1206
<35,67> VBUS1_ECOK
4
1
1
2 0_0402_5%
PR1217
PC1207
2
6
2
1
PC1204 PR1222 @PR1223
2
2
0.1U_0402_10V7K 100K_0402_5% 0_0402_5%
PQ1204A
0_0402_5%
@ PR1216
2
2 1 2 2 1
PR1210 +3.3V_VDD_PIC AC_DISC# <34,57,67>
1M_0402_5% @ PR1254 0_0402_5%
1
2 1 1 2
1
PU1200
5
@ PR1211 0_0402_5% MC74VHC1G08DFT2G_SC70-5
1 2 1
P
<26,67> EN_PD_HV_1 B 4
1 2 2 O
(From TI GPIO1)
G
@ PR1215 A
0_0402_5%
3
@ PJP1202
1 2
1 2
JUMP_43X118
C
EMI Part
S3 C
+TBTA_Vbus_1 PQ1206
EMC@ PL1201
5A_Z120_25M_0805_2P AON7409_DFN8-5 PQ1205
1 2 1 @ PR1221 L2N7002WT1G_SC70-3
2 0_0402_5%
+TBTA_Vbus_1
D
1 2 5 3 1 2 3 1
+TBTA_VBUS EMC@ PL1202
<35> DCIN1_EN +3.3V_ALW +3.3V_ALW
5A_Z120_25M_0805_2P
100P_0402_50V8J
100P_0402_50V8J
2
100K_0402_5%
G
4
1 2
1
2
499K_0402_1%
100K_0402_5%
1000P_0402_50V7K
1500P_0402_50V7K
0.1U_0402_25V6
1
2
@ PR1235
0_0402_5%
@EMC@ PC1215
EMC@ PC1208
@EMC@ PC1209
PR1227
EMC@ PC1216
100K_0402_5%
2
1
@ PR1233
PR1228
@ PR1225
PR1226
100K_0402_5%
@ PR1242 +3.3V_ALW
PC1210
PR1224
100K_0402_5%
2
1
@ 0_0402_5%
2
1
PR1255 <35,57> VBUS2_ECOK 1 2
1
150K_0402_1%
2
<35,67> VBUS1_ECOK 1 2
PR1231 CMOUT <66>
@ PR1257 100K_0402_5%
0_0402_5% AC_DISC# <34,57,67>
+3.3V_VDD_PIC @ PR1245
3
0_0402_5% D
1
PQ1210B
1
G
1500P_0402_50V7K
6
D
1
PR1229 +3.3V_ALW 2
PQ1211A
PC1217
4
49.9K_0402_1% 2 5 G
PR1234 G G
PQ1211B
2
2
100K_0402_5% S PQ1210A
1
2
+TBTA_Vbus_1 +3.3V_VDD_PIC @ DMN65D8LDW-7_SOT363-6
4
S3 OVP PR1259
+3.3V_ALW
PROCHOT#_ISL88738 <66>
@ PD1205 100K_0402_5%
L2N7002WT1G_SC70-3
6
1
D
SDMK0340L-7-F_SOD323-2 @ PR1260 D
PQ1208A
1
1
1 2 +3.3V_VDD_PIC 0_0402_5% 2 2
PQ1216
100K_0402_1%
<26,67> EN_PD_HV_1 +3.3V_ALW

@ PR1238 1 2 G G
2
0_0402_5%
@ PR1237
3
3
1 2 D PR1230
PQ1208B
S
1
2
2
<26,66> AC1_DISC# 1 2 5 100K_0402_5%
2
PR1236 G
1
@ PR1244 PR1232
150K_0402_1%
100K_0402_5%
1
1
PR1240 0_0402_5% S 100K_0402_5%
4
LM393_P 100K_0402_1% PQ1209A @ PR1261
PR1239
6
B 2 DMN65D8LDW-7_SOT363-6 0_0402_5% D B
1 2 2 PQ1207A
2
PU1201B
3
@ PR1241 G DMN65D8LDW-7_SOT363-6
2
1
8
3
@ LM393DGKR_VSSOP8 @ PR1243 0_0402_5% D
5 0_0402_5% 1 2 5 S
P
<34,57,66,67> ACAV_IN_NB
1
+ 7 1 2 5 PQ1209B G PQ1207B
1200P_0402_50V7K
100P_0402_50V8J
6 O DMN65D8LDW-7_SOT363-6
0.01UF_0402_25V7K
G
-
1
100K_0402_1%
S
100P_0402_50V8J
4
1
1
@ PC1211
@ PC1213
100K_0402_1%
4
1
1
@ PR1246
@ PC1212
@ PC1214
1 2
PR1247
2
2
2
@ PR1258
2
0_0402_5%
OVP set t i ng: 5. 5

V
L2N7002WT1G_SC70-3
@ PR1248 @ PT1
1
D
0_0402_5% PAD~D
2 1 2 LPS_PROTECT#
PQ1212
G (From EC)
1
S @ PR1250
3
PR1249 0_0402_5%
10K_0402_5% 1 2 EN_PD_HV_1 <26,67>
2
A A
Title
ParkCity_TypeC_PD
Size Document Number Re v
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-E082P
5 4 3 2 1
5 4 3 2 1
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting

Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Rt=Rrefadj // (Rboot+Rref2) VGA Chip N16S-GMR-S
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] I_ripple=(6-0.9)*0.9/
(287Khz*0.22u*6)=12.12A OpenVReg Configurations Config B
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
Vout=Vmin+N*Vstep OCP=47.4A/2=23.7A per phase Rated TDP Power at Tj=102C 18W
Ivalley=23.7A-12.12A/2=17.64A
Vstep=(Vmax-Vmin)/Nmax
Boosted GPU Total at Tj=102C 23W
PWM-VID Spec and component Values
H-side MOS:CSD87351 L-side MOS:CSD87351 EDP-Continuous at Tj=102C 21A
Config C Rds(on): Rds(on):
D PWM-VID Spec Config A Config B 8.8m ohm(max)@Vgs=4.5V 3.1m ohm(max)@Vgs=4.5V D
EDP-Peak at Tj=102C 39.5A
Vmin 0.6V 0.6V 0.65V
Vmax 1.2V 1.2V 1.15V Istep max (Evaluation) 28A
Vboot 0.875V 0.9V 0.9V
OCP Setting Current 47.4A
Voltage step 6.25mV 6.25mV 25mV Choke: 0.22uH (Size:7*7*3)
96 96 20 Rdc=0.98mohm +-5%
N of Voltage level
Heat Rating Current=28A Rocset 9.76K
Rrefadj PR1307 39K 20K 39K Saturation Current=28A
Recommendation 2phase
Rref1 PR1303 39K 20K 30K
Rboot PR1306 1.5K 2K 3K C=1*330uF (6mohm)=330uF
Vripple=Iripple*ESR(min)=12.79A*6mohm=76.74mV Polymer Cap (330uF) 6mohm * 1
PR1308 30K 18K 24K
Rref2=PR10+PR12
PR1310 1.5K 0 3K
C PC1308 1.5nf 2.7nf 1.8nf
Operation phase Number
PSI Voltage setting
1 phase with DEM 0V to 0.8V
PWM VID and Output voltage control
1.Boot mode 1 phase with CCM 1.2V to 1.8V
2.Standby mode (don't support) @DSC@ PR1301 Active phase with CCM 2.4V to 5.5V +GPU_PWR_SRC
3.Normal mode 1K_0402_5% @EMCDSC@ PL1300
1 2 HCB2012KF-121T50_0805
+3.3V_RUN +PWR_SRC
1 2
1 2 GPU_PWM_VID <48> @ PJP1301

@DSC@ PR1302 1 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
DSC@ 0_0402_5%
1
C PC1301 DSC@ DSC@ PR1304 2.2_0603_5% PAD-OPEN 4x4m C
1
1U_0402_6.3V6K PR1303 U2_BOOT1
1 2
PC1302
@EMCDSC@ PC1303
DSC@ PC1304
DSC@ PC1305
2
20K_0402_1%
1 +VGA_CORE
2
PSI Pull high on HW side DSC@
EDP-Continuous 21 A
2
PC1306
@EMCDSC@
DSC@ PR1306 DSC@ PR1307 1 2
NVVDD_PSI <48> 0.22U_0603_25V7K EDP-Peak 39.5 A
2
2K_0402_5% 20K_0402_1% @DSC@ PR1305 OCP 47.4A
1 2 1 2 0_0402_5%
U2_UGATE1
DSC@ PR1309
18K_0402_1%
1
1K_0402_5%
2700P_0402_50V7K
0.01U_0402_25V7K
1
DSC@ 1 2
PR1308
3V3_MAIN_EN <48,52>
2
@DSC@ PC1307
1
1
Pull high on HW side

DSC@ PC1308
DSC@ PL1301 +GPU_CORE

2
7 0.22UH_PCME064T-R22MS0R985_28A_20%
2
2 U2_PHASE1_C
GPU_VID
6 1 2
2
@DSC@
0.1U_0402_25V6
330U_D2_2.5V_R6M
PR1310
@DSC@ PC1309
1
1
1
0_0402_5%
GPU_REFADJ
4.7_1206_5%
U2_BOOT1
U2_UGATE1
+
Reserve Location
RFDSC@ PR1311
DSC@ PC1311
1
GPU_PSI
DSC@
GPU_EN
8
PQ1300
U2_LGATE1 CSD87351Q5D_SON8-7 2
2
GPU_SNUB1
9.76K_0402_1%
1
DSC@ PR1312
6
DSC@ PU1300
DSC@ PR1300
UGATE1
BOOT1
VID
PSI
EN
REFADJ
680P_0603_50V7K
499K_0402_1%
2
+GPU_PWR_SRC
1
1 2
RFDSC@ PC1312
GPU_REFIN 7 24 U2_PHASE1
1 REFIN PHASE1
@DSC@
2
PC1300 GPU_VREF 8 23 U2_LGATE1
<49> GPU_VSS_SENSE VREF LGATE1
1 2 0.01UF_0402_25V7K
B
@DSC@ PR1313 2 GPU_TON 9 22 U2_PWM3 B
0_0402_5% TON GND/PWM3

1 2 GPU_FBRTN 10 21
RGND PVCC
1
U2_LGATE2 +GPU_PWR_SRC
TALERT/ISEN2
DSC@ PR1314 @DSC@ 11 20

VSNS LAGTE2
TSNS/ISEN3
100_0402_1% PC1313
VCC/ISNE1
47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2

2
SS PHASE2
UGATE2
PGOOD
BOOT2
<49> GPU_VDD_SENSE GPU_FB

1 2 DSC@ PR1316 2.2_0603_5%
GND
10U_0805_25V6K
10U_0805_25V6K
@DSC@ PR1315 U2_BOOT2 1 2
0_0402_5% 1
1
@DSC@ PC1315 RT8813AGQW_WQFN24_4X4 DSC@
DSC@ PC1316
DSC@ PC1317
25
13
14
15
16
17
18
0.01U_0402_25V7K PC1314
1 2 1 2 0.22U_0603_25V7K
2
2
GPU_TSNS/ISEN3
+GPU_CORE
GPU_DSBL/ISEN1
DSC@ PR1317 +3.3V_RUN U2_UGATE2

100_0402_1%
1
U2_UGATE2
GPU_VREF
U2_BOOT2
DSC@ PL1302 +GPU_CORE

1
DSC@ 7 0.22UH_PCME064T-R22MS0R985_28A_20%
PR1321 U2_PHASE2 3 6 U2_PHASE2_C 1 2
DGPU_PWROK <12,35,52>
1. VSNS Soft-Start time (Internal) is 0.7ms (PC1315 un-pop) 10K_0402_1% 5
+5V_RUN 4
18.7K_0402_1%
Tss=(Css*Vrefin)/Iss+2.3ms
1
4.7_1206_5%
2
=0.01U*0.9V/5uA+2.3ms=4.1ms (PC1315 pop)

DSC@PR1318
RFDSC@ PR1319
DSC@
8
470K_0402_5%_TSM0B474J4702RE
2. Switching frequency setting: PQ1301

2
2
DSC@ PR1320 CSD87351Q5D_SON8-7
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p) 2.2_0603_5% U2_LGATE2
=301.5Khz(Vin=13.5V) 1 2
GPU_SNUB2
1
1U_0402_6.3V6K
3. Thermal monitoring:
1
@DSC@ PH1300
@DSC@ PC1319
(VGPU_VREF-VTSNS)/PR620=VTSNS/Rth
680P_0603_50V7K
1
DSC@
A PC1318 A
2
1U_0402_6.3V6K
RFDSC@ PC1320
1
2
T_min T_typical T_max
2
96.73C
PR1318=18.7K 100C 103.1C
PR1318=13K 106.38C 110C 113.4C
vinafix THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title
Size
Document Number
+GPU_CORE
Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1
LA-E082P
5 4 3 2 1
5 4 3 2 1
D D
1 2
VRAM_EN <48,52>
@DSC@ PR1400
0_0402_5%
EN_+1.35_VRAM
1
1M_0402_1%
DSC@ PR1401 @ PJP1401
+1.35_VRAMP 1 2 +1.35V_MEM_GFX
2
1 2
JUMP_43X118
RFDSC@ PR1402 RFDSC@ PC1401

4.7_1206_5% 680P_0603_50V7K
2 SNB_+1.35_VRAM
+PWR_SRC @ PJP1400
+1.35_VRAM_B+
DSC@
PU1400
1 1 2
1 2 8 1 DSC@ PC1403 @DSC@ PR1403

100P_0402_50V8J
100P_0402_50V8J
IN EN 0.1U_0603_25V7K 0_0603_5%
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 1x2m~D 6 BST_+1.35_VRAM1 2BST_+1.35_VRAM_C
1 2 DSC@ PL1400
BS
1
1
1UH_6.6A_20%_5X5X3_M
RFDSC@ PC1400
RFDSC@ PC1402
@DSC@ PC1404
DSC@ PC1405
C 9
GND LX
10 SW _+1.35_VRAM 2 1 +1.35_VRAMP C
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
330P_0402_50V7K
1
1
4 FB_+1.35_VRAM
FB
DSC@ PC1406
DSC@ PC1407
DSC@ PC1408
DSC@ PC1409
DSC@ PC1410
30.1K_0402_1%
1
ILMT_+1.35_VRAM 3 7
+3.3V_ALW
2
ILMT BYP
DSC@ PR1404
4.7U_0603_6.3V6K
+3.3V_ALW 2 5LDO_+1.35_VRAM
4.7U_0603_6.3V6K
PG LDO
1
DSC@ PC1412
DSC@ PR1405
1K_0402_5%
1
SYX196DQNC_QFN10_3X3
DSC@ PC1411
2
1
2
@DSC@
2
PR1406
2
2
ILMT_+1.35_VRAM
1
DSC@
1
PR1408
@DSC@ 24K_0402_1%
PR1407
0_0402_5%
2
2
+1.35_VRAM
TDC 4.13 A
Peak Current 5.9 A
B
OCP Current 9 A Fix by IC B
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A
vinafix DELL CONFIDENTIAL/PROPRIETARY
A

Title
GPU_VRAM(SYX198D)
0.1
LA-E082P
5 4 3 2 1
5 4 3 2 1
D D
+GPU_CORE nVidia GB4-64 package

Under GPU
DSC@ PC1500
DSC@ PC1501
DSC@ PC1502
DSC@ PC1503
DSC@ PC1504
DSC@ PC1505
DSC@ PC1506
DSC@ PC1507
DSC@ PC1508
DSC@ PC1509
4.7uF 0603 * 10
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
1uF 0402 * 4
2
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
DSC@ PC1510
DSC@ PC1511
DSC@ PC1512
DSC@ PC1513
1
1
2
2
C C
+GPU_CORE
nVidia GB4-64 package
Near GPU
47uF 0805 *1
22uF 0805 *1
47U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
DSC@ PC1514
DSC@ PC1515
DSC@ PC1516
DSC@ PC1517
DSC@ PC1518
DSC@ PC1519
DSC@ PC1520
1
1
4.7uF 0805 *5
2
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR DECOUPLING
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1Type-C PD 2016 Change the S4 fast turn off circuit to Re-connect the PR1251.1 and PQ1215.3 from +VBUS_DC_SS to +AC_IN.
1 67 Selector 05/20 Compal avoid the leakage. X01
Add PR960 0_0402_5%(SD028000080) and depop PR919 0_0402_5%(SD028000080)
2016 Add the Circuit for Multiple Input Detach let the PU901.20 CMIN connect to GND.
2 66 CHARGER 05/30 Compal detection & PROCHOT# X01
PU901.23 add cross page net PROCHOT#_ISL88738
1Type-C PD 2016 Add the Circuit for Multiple Input Detach Add PQ1216 DMN65D8LW-7_SOT323-3(SB00000UO00) to drive the PROCHOT#
3 67 Selector 05/30 Compal detection & PROCHOT# Reserve PC1217 1500P_0402_50V7K(SE074152K80) X01
1Type-C PD 2016 For Temp/Voltage test to fine tune the DC-IN

4 67 Selector 06/13 Compal detect voltage from 17.6V to 16.9V PR1219 change from 22.6K to 23.2K(SD034232280) X01
63~ VCCSA_ISL95857 IA_CORE change location PU603 to PU610, PL603 to PL610

5 64 VCC_CORE/ 2016 Compal GT_CORE change location PU604 to PU612, PL604 to PL612 X01
06/13 location alignment
GT_ISL95857 SA_CORE change location PU606 to PU614, PL601 to PL614
6 2016 Compal To decrease the charger input leakage voltage for PD903 change from SDMK0340L-7-F_SOD323-2~D(SCS0340L010) X01
66 CHARGER 06/13 TypeC AC. to RB520SM-30T2R_EMD2-2(SCS00006C00)
C C
PR12, PR11, PR1205, PR1207, PR1228 change from 1M_0402_5%(SD028100480)

to 499K_0402_1%(SD034499380) X01
+DCIN
57 1Type-C PD 2016 To solve the MOS leakage problem to avoid PR16, PR18, PR1212, PR1213, PR1229 change from 1M_0402_5%(SD028100480)
7 67 06/20 Compal the error active.
Selector to 49.9K_0402_1%(SD034499280)
PR10, PR1251 and PR1202 change from 100K_0402_5%(SD028100380)
to 300K_0402_1%(SD034300380)
PC621, PC647 change from 680P(SE074681K80) to 1200P(SE074122K80)

2016 PR640 change from 383_0402_1%(SD034383080) to 365_0402_1%(SD034365080) X01
8 63 VCCSA_ISL95857 06/22 Compal IA/GT/SA CORE static LL optimization PR638 change from 374_0402_1%(SD034374080) to 340_0402_1%(SD00000KT80)
PR629 change from 93.1K_0402_1%(SD034931280) to 95.3K_0402_1% (SD034953280)
PR921 change from 2.2_0603_5%(SD013220B80) to 4.7_0603_5%(SD013470B80)
2016 PR914 change from 0_0603_5%(SD013000080) to 3.3_0603_1%(SD014330B80)
9 66 CHARGER 06/27 Compal EMI request pop PR923, PR924 4.7_1206_5%(SD001470B80) X01
pop PC940, PC941 680P_0603_50V7K(SE025681K80)
B +5V/+3.3V pop PC100, PC103, PC115, PC116, PC301, PC303, PC409, PC1400, PC1402 B
58~61+1.2V_MEN 2016 100P_0402_50V8J(SE071101J80)

68~69+0.6V_DDR 06/28 Compal RF request pop PC1320, PC1312, PC204, PC302, PC112 680P_0603_50V7K(SE025681K80)
10 X01
1VALWP/VCCIO PRIM pop PR1319, PR1311, PR202, PR303, PR106 4.7_1206_5%(SD000010280)
GPU_COREP/GPU_VRAM
Depop PJP1202, PR1255, PR1239, PR1246, PC1211, PR1237, PC1212

2016 , PD1205, PC1213, PC1214, PR1248
11 66 CHARGER 07/01 Compal Reserve the OVP function to protect the typeC device.
X01
Change PR1247 from 200K_0402_1%(SD034200380) to 100K_0402_1%(SD034100380)
Re-modify the S11 OVP description to S3 OVP.
2016 Change PU901 from ISL88738HRTZ REV.A-T TQFN 32P PWM(SA00009VW10)

12 66 CHARGER 07/01 Compal Change the charger version from A version to B version.to ISL88738HRTZ REV.B-T TQFN 32P PWM(SA00009VW20) X01
2016 For IT8010 voltage leakage issue Add PR953 100K_0402_1%(SD034100380)

13 66 CHARGER 09/02 Compal X03
+VCCSA_ISL95857 2016 Change CPU core version to MP version. Change PU602 from SA0000A4A00 to SA0000A4A0L
A 14 63 09/21 Compal X03 A
Unpop PR410 0_0402_5%(SD028000080)

15 61 VCCIO/PRIM 2016 Compal PCH LPM function Pop PR426 0_0402_5%(SD028000080)
09/29 DELL CONFIDENTIAL/PROPRIETARY
Title
P.I.R
LA-E082P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request Owner Issue Solution
Item Page# Title Date Rev.
Description Description
D D
1 34 HW 2016/05/24 COMPAL For Schematic align Remove RA2 0.2(X01)
2 35 HW 2016/05/24 COMPAL Symbol pin name change UE1.C1 pin name change to GPIO024/nRESETI 0.2(X01)
3 9 HW 2016/05/24 COMPAL Symbol pin name change UT5.A6/A7/A8/B7 pin name change to GND, 0.2(X01)
UT5.D6 pin name change to HRESET
4 25 HW 2016/05/24 COMPAL Symbol pin name change UT9.20 pin name change to SNK_CAD/DCI_DAT, 0.2(X01)
UT9.32 pin name change to HPDIN/DCI_CLK
5 6 HW 2016/05/24 COMPAL DP HPD base on INTEL PDG Delete RC312/RC242 0.2(X01)
6 25 HW 2016/05/24 COMPAL Disable AUX snoop feature Pop RT308 0.2(X01)
7 33,40 HW 2016/05/24 COMPAL Remove HDD LED MUX feature Depop RN100/RN101 0.2(X01)
C C
8 35 HW 2016/05/24 COMPAL PORT80_DET# Reserve RE513 100k (SD028100380) to GND 0.2(X01)
Delete RC179/RC180/RC181/RC182
9 6 HW 2016/05/24 COMPAL Follow Intel PDG AUX topology Add test point T281/T282 for CPU_DP1_AUXN and CPU_DP1_AUXP 0.2(X01)
10 17 HW 2016/05/24 COMPAL S0ix(modern standy) support for VCCPLL_OC Pop RZ120 and Depop UZ34
Add net name VCCSTG_EN(UZ19.4) and connect to RZ120.1 0.2(X01)
11 46 0.2(X01)
1.add CLIP1
43,46 0.2(X01)
12
25 HW 2016/05/27 COMPAL For Schematic align SW2_DP1_HPD Add RT380 place near TUSB546 0.2(X01)
13
CZ28,CZ29 change from 0.047uF to 0.01uF
B
30 HW 2016/06/01 INTEL Intel reviwe result CZ27 change from 0.1uF(@)_0201 to 10uF_0603 B
CZ32/CZ31/CZ29 place near JNGFF1.2/JNGFF1.4 0.2(X01)

14
CZ27/CZ30/CZ28 place near JNGFF1.72/JNGFF1.74
37,38 HW 2016/06/07 DELL change to Nuvoton TPM form ATMEL TPM Delete ATMEL TPM circuit, Add Nuvoton TPM circuit 0.2(X01)
15
Add CC331 2.2PF (SE07122AC80) for HDA_RST#
12 HW 2016/06/07 INTEL Intel MOW request Add CC332 2.2PF (SE07122AC80) for HDA_SDIN0 0.2(X01)
16 Add CC333 2.2PF (SE07122AC80) for HDA_SDOUT
Intel reviwe result Add RZ128 0 ohm connect WWAN_COEX3 and WLAN_COEX3
33 HW 2016/06/07 INTEL (WWAN Coex feature support) Add RZ129 0 ohm connect WWAN_COEX2 and WLAN_COEX2
17 0.2(X01)
Add RZ130 0 ohm connect WWAN_COEX1 and WLAN_COEX1
18 33 HW 2016/06/07 COMPAL Debug card reserve Add RZ131, RZ132 for PORT80_DET# and HOST_DEBUG_TX 0.2(X01)
19 35 HW 2016/06/07 COMPAL For MEC5105K-D1-TN sample 1.UE1 change to SA00009GL00(S IC MEC5105K-D1-TN WFBGA 169P EC) 0.2(X01)
A
2.Depop RE361,Pop RE360,RE362 A
20 46 HW 2016/06/17 COMPAL Base on ME drawing H10 change from H_4P0 to H_3P0 0.2(X01)
Title
EE P.I.R (1/6)
LA-E082P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R.

List ) Request Issue Solution
Item Page# Title Date Owner Rev.
D D
21 42 HW 2016/06/17 COMPAL Base on USB3 EA result,B_EQ change to13dB Depop RI42,pop RI44 0.2(X01)
22 11 HW 2016/06/17 COMPAL Base on Crystal EA result CC23 change form 15pF to 12pF 0.2(X01)
23 41 HW 2016/06/17 COMPAL BITS284924-HDD is still working after press Depop RN5 0.2(X01)
power button into S5 during POST.
1.JKBTP1 change from HRS_TF49-20S-0P5SH_20P-T to

24 38,45 HW 2016/06/20 COMPAL ME request CVILU_CF5020FD0RK-05-NH_20P-T 0.2(X01)
2.JUSH1 change from HRS_TF49-26S-0P5SH_26P-T to
CVILU_CF5026FD0RK-05-NH_26P-T
25 34 HW 2016/06/20 COMPAL Base on Audio EA result RA7,RA8 change from 24.9 to 16.2 ohm(SD00001U900) 0.2(X01)
26 30 HW 2016/06/22 COMPAL EMI request CL22 change from 1500pF to 10pF

(SE167100J80 S CER CAP 10P 3KV J NPO 1808 AC250V X2Y3) 0.2(X01)
C C
27 29 HW 2016/06/22 COMPAL EMI request Change LV1 from SM01000BV00 to SM01000NY00 0.2(X01)
28 29 HW 2016/06/22 COMPAL ME request JIR1 change from SP010023D00 to SP010013W20

0.2(X01)
29 35 HW 2016/06/22 DELL The posibility of GPIO map update,RTCRST_ON Add RE514(@),RE515 for RTCRST_ON
change from GPIO141 to GPIO122 0.2(X01)
30 36 0.2(X01)
31 29 HW 2016/06/22 COMPAL RF request 、

CA7、
CZ1 change to 100pF(0201)SE174101J80 0.2(X01)
12 HW 2016/06/22 COMPAL BIOS need detect Storage type and dynamic UE1.D7 add HDD_DET#
32 change the name 0.2(X01)
33 24 HW 2016/06/28 COMPAL For VGA test result Pop RV121/RV122/CV132/CV133 0.2(X01)
34 46 HW 2016/06/28 COMPAL For DFX request CLIP1.1 change from GND to NC 0.2(X01)
B B
38 HW 2016/06/29 COMPAL X8 have no difference JUSH1 pin define Depop DZ7,Pop RZ87
35 concern 0.2(X01)
36 38 HW 2016/06/29 COMPAL Let USH_PWR_STATE# keep low at S5 RZ10 change from 1M to 100k ohm 0.2(X01)
37 36 HW 2016/06/29 COMPAL Foe X01 Board ID RE79 change from 240k to 130k ohm 0.2(X01)
38 41 HW 2016/06/29 COMPAL BITS283552 - [BR_CSLP] FFS AP no function FFS VDD_IO change to +3.3V_RUN 0.2(X01)
when execute FF generator or shake SU
39 29 HW 2016/08/04 COMPAL RF request POP CC27 & change value from 22p to 47p 0.3(X02)
0.3(X02)
39 18 HW 2016/08/04 COMPAL DSC BOM change Pop RC385, Depop RC386
A A
Title
EE P.I.R (2/6)
LA-E082P
5 4 3 2 1
5 4 3 2 1

D D
40 34, 35 HW 2016/08/04 COMPAL Vendor schematic review 1. Add net WRST# to UE2.4 and CE500 1uf (SE000000K80) 0.3(X02)
2. Add RE523 0 ohm for UE2 power pin soft start
3. Change RE14,RE15,RE18 from 100k ohm to 10k ohm
4. Change RPE12.1 to RE524 (10Kohm) for EXPANDER_GPU_SMDAT
5. Change RPE12.2 to RE525 (10Kohm) for EXPANDER_GPU_SMCLK
6. Reserve CE504~CE505 for EXPANDER_GPU_SMDAT/CLK to GND.
41 14 HW 2016/08/04 COMPAL Intel suggestion RC137 change from 1K to 3K 0.3(X02)

42 27 HW 2016/08/04 COMPAL For UT7 2nd source issue Add RT393 PD 100K ohm to +5V_PD_VDD for discharging instantly 0.3(X02)
43 45 HW 2016/08/04 COMPAL Touchpad I2C EA Chagne RZ20, RZ21 from 4.7k ohm to 2.2k ohm
Change CZ80, CZ81 from 330pf to 10pf 0.3(X02)
44 26 HW 2016/08/04 COMPAL For PD sample Change UT5 from SA00009W200 to SA00009W210 0.3(X02)
45 42 HW 2016/08/05 COMPAL BITS290368-System can't be waked from S3 USB3 repeater power rail
when connect to right USB port Add RI79 0ohm to +3.3V_RUN and De-pop it. 0.3(X02)
via USB3.0 to LAN Dongle. Add RI80 0ohm to +3.3V_ALW_PCH and pop it.
C 46 11 HW 2016/08/08 COMPAL EMI request add RC417 (0 ohm) for Xtak24_IN 0.3(X02) C
47 42 HW 2016/08/08 COMPAL schematic modify 1. pop RI37

2. RI79, RI80 footprint change form 0402 to 0603 0.3(X02)
3. add QI1 controlling USB3 repeater PD#
48 32, 37 HW 2016/08/09 COMPAL DFB request SMT concern DZ1, DZ2, DZ5, DZ6 PCB pad is too small, 0.3(X02)
suggest use the symbol "RB520SM-30T2R_EMD2-2" follow PD903
49 18 0.3(X02)
50 48 0.3(X02)
51 33, 35, 48 HW 2016/08/10 COMPAL Footprint align DA8,DE1,DV10 follow symbol "RB520SM-30T2R_EMD2-2" 0.3(X02)
52 42 HW 2016/08/11 COMPAL schematic modify change USB repeater PD# enable pin to "USB_PWR_SHR_VBUS_EN" 0.3(X02)
53 35 HW 2016/08/11 COMPAL schematic align add power rail +3.3V_ALW_UE2 for UE2 0.3(X02)
54 42 HW 2016/08/12 COMPAL schematic modify delete QI1, depop RI37, 0.3(X02)
add RI81 connecting "USB_PWR_SHR_VBUS_EN" & "USB3_PD#'
55 42 HW 2016/08/16 COMPAL EA request depop RI38, RI44, RI53, RI57 for USB3 repeater 0.3(X02)
B B
56 9 HW 2016/09/08 COMPAL DGPU_PWR_EN need to use BIOS solution depop RC385,pop RC386 0.4(X03)
57 38 HW 2016/09/08 COMPAL TPM change to NPCT650VB2YX Change UZ12 from to SA00008EL70 to SA00008EL80 0.4(X03)
58 35 HW 2016/09/08 COMPAL Expander I/O change from ITE8010 to MCP23008 Change UE2 from SA00009VL00 to SA0000ADQ00, remove RE523
Change RE524, RE525 from 10Kohm to 2.2Kohm
0.4(X03)
59 34 HW 2016/09/08 COMPAL Board ID Change RE79 to 33kohm (SD028330280)
60 34 HW 2016/09/08 COMPAL schematic align Reserve RE526(10K) PU for USH_DET# to +3.3V_ALW 0.4(X03)
61 34 HW Add RE505 PU to +3.3V_ALW for LOM_CABLE_DETECT# (Reserve) 0.4(X03)
2016/09/08 COMPAL EC request for power consumption Add RE532 PU to +3.3V_ALW for BCM5882_ALERT#
62 37 HW 2016/09/08 COMPAL USH/B de-pop, pop on MB side POP RZ8,RZ9 for USH SMBus 0.4(X03)
63 35 HW 2016/09/20 COMPAL DELL request Add RE536/RE537 for resistors for PCH_DPWROK circuit 0.4(X03)
64 34 HW 2016/09/20 COMPAL WDT schematic option 2 use Option2: pop RE361 / depop RE362 0.4(X03)
65 33 HW 2016/09/20 COMPAL 1. L6~L9 change to 80ohm bead (BLM15PD800SN1D, SM01000N000) for BR14/15
EMI request 2. depop CA2, CA3 0.4(X03)
A
3. RA55,RA56 change location toLA15, LA16 with 33ohm bead A
(BLM15PX330SN1D,SM01000NA00)
66 39 HW 2016/09/20 COMPAL NV GPU seqest CV247 change from 3900pf t0 4700pf (SE075472K80) 0.4(X03)
CV248 change form 220pf to 470pf (SE074471K80) DELL CONFIDENTIAL/PROPRIETARY
67 35 HW 2016/09/20 COMPAL EMI request RC295/RC417 change from 0 to 33 ohm Compal Electronics, Inc.
Title
EE P.I.R (2/6)
LA-E082P
5 4 3 2 1
5 4 3 2 1

D D
68 35 HW 2016/10/04 COMPAL BITS294007 - Sometimes need to CE12 change to 2.2u (SE000008880) 0.4(X03)
press power button twice to power on system. RE33 change to 1K (SD028100180)
69 24 HW 2016/10/04 COMPAL U-line VGA EA PASS depop RV121/RV122 0.4(X03)
70 26 HW 2016/10/04 COMPAL TI CC pin for ESD request CT85,CT86 change to 470p.(SE074471k80) 0.4(X03)
71 25 HW 2016/10/04 COMPAL BR14 OTP issue RE77 change to 1.69K_1% (SD00000JB80) 0.4(X03)
72 35 HW 2016/10/04 COMPAL EC watchdog reserve add QE13,RE530,CE503 0.5(X04)
73 34 HW 2016/10/06 COMPAL UE1.H8 to prevent EOS issue on MEC5105 Add RE539(100ohm) to CV2_ON 0.5(X04)
74 36 HW 2016/10/06 COMPAL BOARD ID Change RE79 to 8.2k ohm(SD028820180) 0.5(X04)
75 36 HW 2016/10/31 COMPAL BOARD ID Change RE79 to 4.3k ohm(SD028430180) 1.0(A00)
76 36 HW 2016/10/31 COMPAL Change R1 to R3 for MP part Change UL1 CP/N to SA000081G1L
Change UE1 CP/N to SA00009GL30 1.0(A00)
change UV1 CP/N to SA00009S01L
C
77 36 HW 2016/10/31 COMPAL For DFB request. Close solder mask CMOS1 (-NPM) and other co-lay part 1.0(A00) C
78 36 HW 2016/10/31 COMPAL Service Mode Switch remove Depop SW1 and RC222 and RC221 change to short pad 1.0(A00)
79 36 HW 2016/10/31 COMPAL RE374 change BS to LPC@ RE374 change BS to LPC@ 1.0(A00)
80 36 HW 2016/10/31 COMPAL For MEC5105 rev. C Pop RE362,RE536; 1.0(A00)
Depop RE361,QE13,CE503,RE530,UE7,CE5,CE6,RE348,RE537
81 36 1.0(A00)
IGS
B B
A A
Title
EE P.I.R (2/6)
LA-E082P
Date: Wednesday, December 14, 2016 Sheet 75 of 75
5 4 3 2 1

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A B C D E

BR14 KBL-U DSC

REV : 1.0 (A00)

DAA000CR000 PCB 1SD LA-E082P REV0 MB DSC 1

Layout Dell logo

Breckenridge 14 DSC Block Diagram Reverse Type

Memory BUS (DDR4) DDR4-SO-DIMM X2

2-Lane eDP1.3 USB2.0[8]

PCIE[4] PCIE[3] PAGE 6~19

Card reader Intel Jacksonville M.2,3042 Key B M.2,3030 Key A

Trough eDP Cable

Non-AR Type C CPU&PCH XDP Port

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)

PM TABLE PCIE-8 SATA-1

+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist OFF OFF OFF

SIO_SLP_SUS# CPU PWR

BATTERY 3V3_MAIN_EN AUD_PWR_EN

TYPE-C EM5209VF 3V3_MAIN_EN

+3.3V_ALW_PCH 200 DIMMB

For 2LANE EDP,BR/SB12

2 1 CPU_DP1_CTRL_CLK E55 C47

B31 CSI2_DN6 AP2

<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]

DDR4, Ballout for side by side(Non-Interleave) <20> DDR_A_D[0..63] <21> DDR_B_D[0..63]

<20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]

DDR4 COMPENSATION SIGNALS

SOFTWARE TAA RF Request SML0_SMBCLK 1 2

PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R SML0_SMBCLK 1 2

<36> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R LPC@ RC27 8.2K_0402_5%

<36> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R SML1_SMBCLK 1 2

@ RC31 1K_0402_5% @RF@ CC320 33P_0402_50V8J +3.3V_ALW_PCH

Internal 20k PD RC400

For Non AR,Breckenridge 14/15 DSC

SYSTEM POWER MANAGEMENT

BB15 AP16 INTRUDER# 11

<30> PM_LANPHY_ENABLE AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 14 13

@ RC215 0_0402_5% ESD Request:place near CPU side

10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.

HIGH ENABLE HIGH DISABLE

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

For Skylake , RC120 depop

PROC_SELECT#:This pin is for compatibility

2 1 CPU_XDP_PREQ# Place near JXDP1.47

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

Place close CPU side

CAD Note: Place the PU resistors close to CPU

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

UC1M CPU@ SKL-U

N64 VCCGT VCCGTX_AM58 AU58

22U_0603_6.3V6M BB32 AM30

CC296 BB41 AM42 +VCC_SA

SIO_SLP_S3# HIGH HIGH LOW

+1.0V_VCCST source +1.0V_VCCSTG source

close UC1.AL1 and <120mil +1.0V_MPHYGT

@ RC235 0_0402_5% T19