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5 4 3 2 1 D D Thurman UMA Schematics Document C C uFCPGA Mobile
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D
Thurman UMA Schematics Document
C
C
uFCPGA Mobile Merom
Intel Crestline-GM + ICH8M
2007-11-19
B
B
REV : -1 (DELL:A00)
A
<Variant Name>
<Variant Name>
<Variant Name>
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
COVER PAGE
COVER PAGE
COVER PAGE
-1
-1
-1
Date:
Date:
Date:
Friday, January 18, 2008
Friday, January 18, 2008
Friday, January 18, 2008
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5 4 3 2 1 System DC/DC Thurman UMA Block Diagram 41 TPS51120 INPUTS OUTPUTS
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System DC/DC
Thurman UMA Block Diagram
41
TPS51120
INPUTS
OUTPUTS
Project code:91.4C301.001
+5V_ALW +5V_SUS
+PWR_SRC
+3.3V_SUS
+3.3V_RTC_LDO
PCB P/N
:06253
System DC/DC
Thermal Sensor
Clock Generator
Intel Mobile CPU
REVISION
:SB
42
D
TPS51124
D
EMC4001
28
CY28547LFXC
SMBus
6
Merom 4M
FSB:667/ 800 Mhz
+PWR_SRC
+1.05V_VCCP
+1.5V_RUN
7,8
DDR2 DC/DC
200-PIN DDR2 SODIMM
43
TPS51117
HOST BUS
FSB 667/800MHz
UNBUFFERED
+1.8V_SUS
RGB
DDRII 533/667MHz
+PWR_SRC
CRT
DDR2 SODIMM
18
Crestline-GM
Socket
LDO
LVDS
15
LCD
43
TPS51100
19
AGTL+ CPU I/F
UNBUFFERED
+1.8V_SUS
+0.9V_DDR_VTT
DDRII 533/667MHz
V_DDR_MCH_REF
SDVO
DDR Memory I/F
DDR2 SODIMM
1394
HDMI
1394
LDO
HDMI
SIL 1392
EXTERNAL GRAHPICS
Socket
Ricoh R5C833
CONN
29
18
16
44
SC339SKTRT
17
8 in 1 card reader
7 in1
8 in1
9,10,11,12,13,14
1394
+PWR_SRC
+1.25V_RUN
C
28
CONN
29
C
SPDIF
Power Switch
DMI x4
C-LINK0
PCI BUS
AZALIA
26
Express Card
PCI Express (4)
PCIE#4
Slot 54mm
Intel
SATA
USB#6
26
Battery Charger
SATA HDD
26
ICH8-M
38
MAX8731
USB#7
Enhanced
Buletooth 2.1 29
PATA IDE
INPUTS
OUTPUTS
ODD Bay
USB 2.0/1.1 ports (10)
USB2.0 (7)
26
USB#0
PCI Express ports (6)
USB*1 left side
+PWR_SRC
+VCHGR
38
CPU DC/DC
High Definition Audio
USB#1
USB*1 Right side 38
39,40
ISL6260C
ATA 66/ 100
Headphone AMP.
SATA (3)
Mini-Card
SIM
INPUTS
OUTPUTS
PCIE#1
LINE OUT / HP
MAX4401A
LPC I/F
WWAN
27
CONN
27
+PWR_SRC
+VCC_CORE
31
SPI
B
B
USB#8
ACPI 1.1
Mini-Card
PCIE#2
PCI/PCI BRIDGE
802.11a/g/n
27
PCB LAYER
Digital MIC 19
Azalia CODEC
AZALIA
20,21,22,23,24
PCIE#6
RJ45
STAC 9228
LAN BCM5906
L1:TOP
MIC IN
30
CONN
10/100 NIC
25
25
L2:GND
BIOS
USB#5
L3:Signal
LINE OUT / HP
SPI FLASH
SPI
Camera
Headphone AMP.
19
16Mb
33
L4:Signal
MAX9789A
EC
SIO Expander
BC
INT. SPKR *2
31
SMSC MEC5025
SMSC ECE5021
L5:VCC
31
32
33
L6:Signal
PS/2
L7:GND
CIR
USB#4
LCD
38
A
<Variant Name>
<Variant Name>
<Variant Name>
L8:BOT
A
19
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Digital MIC 19
LCD Module
KBC
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Int. KB
Touch
SMSC ECE1077
Biometric
Pad
34
Title
Title
Title
34
34
34
Thurman UMA
Thurman UMA
Thurman UMA
Camera
23
19
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Touch Pad Module
A3
A3
A3
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
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SPI
BC
LPC
5 4 3 2 1 ICH8 SMBus Block Diagram KBC SMBus Block Diagram +3.3V_RUN +3.3V_ALW
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ICH8 SMBus Block Diagram
KBC SMBus Block Diagram
+3.3V_RUN
+3.3V_ALW
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
SRN2K2J-1-GP
SRN2K2J-1-GP
+3.3V_RUN
SRN2K2J-1-GP
SRN4K7J-8-GP
CLK GEN.
KSO17/GPIOA1/AB1H_DATA
CKG_SMBDAT
‧ CLK_SDATA
SDATA
D
ICH8-M
DIMM 1
D
KSO16/GPIOA0/AB1H_CLK
CKG_SMBCLK
‧ CLK_SCLK
SCLK
ICH_SMBCLK
MEM_SCLK
SMBCLK
SCL
(Reverse Type)
ICH_SMBDATA
MEM_SDATA
SMBDATA
SDA
+5V_RUN
+5V_ALW
SMBus address:D2
2N7002DW-7F-GP
SMBus Address : A0
2N7002DW-7F-GP
DIMM 2
+5V_RUN
SRN2K2J-1-GP
MEM_SCLK
SRN2K2J-1-GP
SCL
(Reverse Type)
MEM_SDATA
SDA
Capacity Button
SMBus Address : A4
AB1A_DATA
DOCK_SMBDAT
DOCK_SMBDAT_C
SDATA
Board
DOCK_SMBCLK
DOCK_SMBCLK_C
SCLK
AB1A_CLK
Express
WWAN
SMBus address:86
Card
2N7002DW-7F-GP
Minicard
ICH_SMBCLK
+3.3V_ALW
SMB_CLK
MEM_SCLK
ICH_SMBDATA
SMB_CLK
SMB_DATA
MEM_SDATA
SIO
SMB_DATA
MEC5025
SRN4K7J-8-GP
C
C
+3.3V_WLAN
Battery Conn.
GPIO87/AB1C_DATA
PBAT_SMBDAT
100R2F-L1-GP-U
PBAT_SMBCLK1
CLK_SMB
GPIO86/AB1C_CLK
PBAT_SMBCLK
100R2F-L1-GP-U
PBAT_SMBDAT1
DAT_SMB
+3.3V_SUS
SMBus address:16
SRN2K2J-1-GP
WLAN
Minicard
Charger
ICH_SMBCLK
SMB_CLK
SCL
+3.3V_ALW
SMB_DATA
SDA
SMBus address:12
2N7002DW-7F-GP
ICH_SMBDATA
SRN4K7J-8-GP
GPIO90/AB1E_CLK
THRM_SMBCLK
SMBCLK
GPIO91/AB1E_DATA
THRM_SMBDAT
+3.3V_ALW
SMDATA
Thermal
B
B
SMBus address:5E
SRN8K2J-3-GP
AB1B_CLK/GPIOA4
LCD_SMBCLK
INVERTER
AB1B_DATA/GPIOA2
LCD_SMBDAT
+3.3V_RUN
SMBus address:58
LVDS
SRN8K2J-1-GP
+5V_RUN
LCD_DDCLK
LDDC_CLK
LDDC_DATA
LCD_DDCDAT
+2.5V_RUN
SMBus address:72
SRN1K5J-GP
SDADDC
Crestline-GM
SDA
HDMI CONN
A
A
SCLDDC
SCL
SRN2K2J-1-GP
HDMI_SDATA
SDVO_CTRL_CLK
SASDA
<Variant Name>
<Variant Name>
<Variant Name>
SDVO_CTRL_DATA
HDMI_SCLK
Sil 1932
SDASCL
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
C
C
C
SMBus Block Diagram
SMBus Block Diagram
SMBus Block Diagram
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
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5 4 3 2 1 CLOCK GEN CY28547 PCIE Routing USB TABLE INTEL CRESTLINE STRAP
5
4
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CLOCK GEN CY28547
PCIE Routing
USB TABLE
INTEL CRESTLINE STRAP PIN
ICH
27M_SS/LCD96_100M SELECTION TABLE
USB0
USB1
LANE1
MiniCard WWAN
*
IO_VOUT[2,1,0] BYTE 15
is Default setting
USB1
USB2
BYTE 10
LANE2
MiniCard WLAN
Bit2
Bit1
Bit0
IO_VOUT[2,1,0]
CFG Strap
Low
High
USB2
Bit5 S1
Bit4 S0
Spread Spectrum S[1:0]
IO_VOUT2
IO_VOUT1
IO_VOUT0
LANE3
No use
0
0
-0.5%(Default)
0
0
0
0.3V
CFG 5
DMI X 2
DMI X 4
USB3
*
0
1
-1.0%
0
0
1
0.4V
LANE4
Express Card
1
0
-1.5%
0
1
0
0.5V
CFG 6
Moby Dick
Calistoga
USB4
Biometric
*
1
1
-2.0%
0
1
1
0.6V
LANE5
No use
1
0
0
0.7V
CFG 7
DT/Transportable CPU
Mobile CPU
USB5
Camera
*
1
0
1
0.8V(Default)
LANE6
10/100 LOM
D
D
1
1
0
0.9V
CFG 9
Reserved Lane
Normal Operation
USB6
Express Card
*
1
1
1
1.0V
CFG 10
Reserved
Mobility
USB7
BT
*
PCI ROUTING
PIN34
CFG 11
Calistoga
Reserved
USB8
*
0 UMA
1 DISC.
CFG 16
USB9
MINI Card WWAN
FCTSEL1
FSB Dynamic ODT
Disabled
Enabled
*
PIN43
DOT96T
27M_NonSpread
IDSEL
INT
REQ
GNT
CFG 18
PIN44
DOT96C
27M_Spread
VCC Select
1.05V
1.5V
*
1394/
AD17
C
1
1
PIN47
LCD100/96T
SRCT_0
CFG 19
MediaCard
D
DMI Lane Reserved
Normal Operation
Reserved Lane
*
PIN48
LCD100/96C
SRCC_0
CFG 20
PCIE/SDVO Select
Only PCIE or SDVO
is operation
PCIE and SDVO
*
are operation simu
SDVO Device present
SEL2 SEL1 SEL0
SDVO_CTRLDATA
No SDVO Device
present
*
CPU
FSB
FSC
FSB
FSA
CFG[13:12]
1
0
1
100M
X
LL
Reserved
0
0
1
133M
X
LH
XOR Mode Enabled
C
0
1
1
166M
667M
HL
All Z Mode Enabled
C
0
1
0
200M
800M
HH
Normal Operation
*
INTEL ICH8-M STRAP PIN
INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS
Signal
Usage/When Sampled
Comment
XOR Chain Entrance Strap
SIGNAL
Resistor Type/Value
HDA_SDOUT
XOR Chain Entrance/
PCIE Port Config 1 bit1,
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
ICH_RSVD
tp3
AZ_DOUT_ICH
Description
HDA_BIT_CLK
PULL-DOWN 20K
0
0
RSVD
0
1
Enter XOR Chain
HDA_RST#
NONE
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
1
0
Normal Operation(default)
1
1
Set PCIE port cofig bit1
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SYNC
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
HDA_SDOUT
PULL-DOWN 20K
GNT2#
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
HDA_SYNC
PULL-DOWN 20K
GNT[3:0]
PULL-UP 20K
GPIO20
Reserved
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
GPIO[20]
PULL-DOWN 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
A16 swap override strap
GNT3#
Top-Block Swap Override.
Sampled low:Top-Block Swap mode(inverts A16 for all
cycles targeting FWH BIOS space).
LAN_RXD[2:0]
PULL-UP 20K
B
B
PCI_GNT#3
low = A16 swap override enable
Rising Edge of PWROK.
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
high = default
LDRQ[0]
PULL-UP 20K
BOOT BIOS Strap
LDRQ[1]/GPIO23
PULL-UP 20K
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
GNT0#
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
PME#
PULL-UP 20K
SPI_CS1#
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
0
1
SPI
1
0
PCI
PWRBTN#
PULL-UP 20K
1
1
LPC(Default)
INTVRMEN
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.
SATALED#
PULL-UP 20K
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
integrated VccSus1_05,VccSus1_5,VccCL1_5
SPI_CS1#
PULL-UP 20K
SM_INTVRMEN
High=Enable
Low=Disable
SPI_CLK
PULL-UP 20K
integrated VccLan1_05VccCL1_05
Integrated VccLAN1_05
Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high
SPI_MOSI
PULL-UP 20K
LAN100_SLP
LAN100_SLP
VccCL1_05 VRM enable
/Disable. Always sampled.
High=Enable
Low=Disable
SPI_MISO
PULL-UP 20K
TACH_[3:0]
PULL-UP 20K
SATALED#
PCIE LAN REVERSAL.Rising
Edge of PWROK.
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
DEFAULE HIGH
SPKR
PULL-DOWN 20K
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
No Reboot Strap
TP[3]
PULL-UP 20K
SPKR
No Reboot.
Rising Edge of PWROK.
SPKR
LOW = Defaule
USB[9:0][P,N]
PULL-DOWN 15K
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
CL_RST#
TBD
A
<Variant Name>
<Variant Name>
<Variant Name>
A
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
Wistron Corporation
Wistron Corporation
Wistron Corporation
GPIO33/
Flash Descriptor Security
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
HDA_DOCK_EN#
Override Strap
Rising Edge of PWROK.
Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
This should only be used in manufacturing
environments
8.2K PULL HIGH
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Table of Content
Table of Content
Table of Content
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
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5 4 3 2 1 D CPU ITP Conn. D TCK(PIN 5) TCK(PIN AC5) FBO(PIN
5
4
3
2
1
D
CPU
ITP Conn.
D
TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
+1.05V_VCCP
+3.3V_RUN
C
C
70105
R30
R30
R29
R29
R28
R28
R27
R27
R24
R24
150R2F-1-GP
150R2F-1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
51R2F-2-GP
51R2F-2-GP
51R2F-2-GP
51R2F-2-GP
39D2R2F-L-GP
39D2R2F-L-GP
R23
R23
150R2F-1-GP
150R2F-1-GP
ITP1
ITP1
29
ITP_TDI
1
7
ITP_TDI
ITP_TMS
2
7
ITP_TMS
ITP_TRST#
3
7 ITP_TRST#
4
ITP_TCK
5
7
ITP_TCK
6
ITP_TDO
7
7
ITP_TDO
CLK_CPU_ITP#
8
H_CPURST# use pull-up Resistor close
6
CLK_CPU_ITP#
CLK_CPU_ITP
9
6
CLK_CPU_ITP
ITP connector 500 mil ( max )
10
11
ITP_RESET#
1
2
12
7,9
H_RESET#
ITP_BPM#5
R36R36
22D6R2F-L1-GP22D6R2F-L1-GP
13
7
ITP_BPM#5
14
ITP_BPM#4
15
7
ITP_BPM#4
DY
DY
16
ITP_BPM#3
17
7
ITP_BPM#3
18
ITP_BPM#2
19
7
ITP_BPM#2
20
ITP_BPM#1
21
7
ITP_BPM#1
B
B
22
ITP_BPM#0
23
7
ITP_BPM#0
24
ITP_DBRESET#
25
7,22,33
ITP_DBRESET#
26
27
+1.05V_VCCP
R25
R25
R26
R26
28
+1.05VRUN use Decoupling Capacitor close
680R2J-3-GP
680R2J-3-GP
27D4R2F-L1-GP
27D4R2F-L1-GP
30
ITP connector 100 mil ( max )
MLX-CON28-3-GP
MLX-CON28-3-GP
20.K0116.028
20.K0116.028
ITP Debug Conn.
A
<Variant Name>
<Variant Name>
<Variant Name>
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
ITP Debug
ITP Debug
ITP Debug
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
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12
12
12
12
12
12
12
12
SCD1U10V2KX-4GP SCD1U10V2KX-4GP C320 C320 5 4 3 2 1 +CK_VDD_REF Place near C10 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C320
C320
5
4
3
2
1
+CK_VDD_REF
Place near C10
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L52
L52
R502
R502
L55
L55
C323
C323
+CK_VDD_MAIN2
+CK_VDD_A
+CK_VDD_MAIN
C349
C349
1
2
1
2
1
2
+3.3V_RUN
+3.3V_RUN
BLM21PG600SN-1GP
BLM21PG600SN-1GP
BLM21PG600SN-1GP
BLM21PG600SN-1GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
2D2R3J-2-GP
2D2R3J-2-GP
60ohm 100MHz
C319
C319
C708
C708
3000mA 0.05ohm DC
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CLKREQ PULL HIGH
60ohm 100MHz
3000mA 0.05ohm DC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+CK_VDD_48
C717
C717
C699
C699
C317
C317
+CK_VDD_A
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C347
C347
RN39
RN39
D
Pull low to Decide
VTT_PWRGO Low active
D
SATA_CLKREQ#
C721
C721
C350
C350
1 10
+3.3V_RUN
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
CLK_PWRGD
2 9
CLK_PWRGD
22
MINI1CLK_REQ#
CARD_CLK_REQ#
+CK_VDD_REF
3 8
1
2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
MINI2CLK_REQ#
CLK_3GPLLREQ#
R219R219
1R3F-GP1R3F-GP
PGMODE
4 7
1
DY
DY
2
+3.3V_RUN
CLK_SDATA
32
C315
C315
LOM_CLKREQ#
R501
R501
10KR2J-3-GP
10KR2J-3-GP
5 6
+3.3V_RUN
+CK_VDD_48
1
2
RN44
RN44
SRN10KJ-L3-GP
SRN10KJ-L3-GP
R489R489
2R3J-2-GP2R3J-2-GP
1
DY
DY
2
R500
R500
10KR2J-3-GP
10KR2J-3-GP
1 4
+3.3V_RUN
2 3
U20
U20
SRN2K2J-1-GP
SRN2K2J-1-GP
CLK_CPU_BCLK#
1 CPU_BCLK#
4
7
CLK_CPU_BCLK#
CLK_SCLK
32
CLK_CPU_BCLK
2 CPU_BCLK
3
7
CLK_CPU_BCLK
RN43
RN43
SRN33J-5-GP-U
SRN33J-5-GP-U
CLK_SDATA
13
17
CPUC0
SDATA
CLK_SCLK
2 DREF_SSCLK
14
16
3
CPUT0
SCLK
DREF_SSCLK
10
CLK_MCH_BCLK#
1 MCH_BCLK#
1 DREF_SSCLK#
4
10
4
9
CLK_MCH_BCLK#
CPUC1
DREF_SSCLK#
10
CLK_MCH_BCLK
2 MCH_BCLK
RN112
RN112
SRN33J-5-GP-U
SRN33J-5-GP-U
3
11
9
CLK_MCH_BCLK
CPUT1
RN42
RN42
SRN33J-5-GP-U
SRN33J-5-GP-U
DOT96_SSC
2 CLK_PCIE_SATA
47
3
SRCT_0/LCD100MT
CLK_PCIE_SATA
20
H_STP_CPU#
DOT96_SSC#
1 CLK_PCIE_SATA#
24
48
4
22 H_STP_CPU#
CPU_STP#
SRCC_0/LCD100MC
CLK_PCIE_SATA#
20
SB:70306
PCIE_SATA
RN30
RN30
SRN33J-5-GP-U
SRN33J-5-GP-U
50
SRCT_1
delete
PCIE_SATA#
2 CLK_MCH_3GPLL
51
3
SRCC_1
CLK_MCH_3GPLL
10
SATA_CLKREQ#
1 CLK_MCH_3GPLL#
46
52
4
22
SATA_CLKREQ#
CLKREQ1#
SRCT_2
CLK_MCH_3GPLL#
10
RN31
RN31
SRN33J-5-GP-U
SRN33J-5-GP-U
26
53
CLKREQ2#
SRCC_2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
MCH_3GPLL_REQ#
MCH_3GPLL
2 CLK_PCIE_LOM
2
1
28
55
3
10 CLK_3GPLLREQ#
CLKREQ3#
SRCT_3
CLK_PCIE_LOM
25
C325
C325
R206R206
475R2F-L1-GP475R2F-L1-GP 25 LOM_CLKREQ#
LOM_CLKREQ#
MCH_3GPLL#
1 CLK_PCIE_LOM#
57
56
4
CLKREQ4#
SRCC_3
CLK_PCIE_LOM#
25
Enable ITP
CARD_CLK_REQ#
PCIE_LOM
RN32
RN32
SRN33J-5-GP-U
SRN33J-5-GP-U
29
58
26
CARD_CLK_REQ#
CLKREQ5#
SRCT_4
PCIE_LOM#
2 CLK_PCIE_EXPCARD
62
59
3
CLKREQ6#
SCRC_4
CLK_PCIE_EXPCARD
26
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3.3V_RUN
C
PCIE_EXPCARD
1 CLK_PCIE_EXPCARD#
C
38
60
4
CLKREQ7#
SRCT_5
CLK_PCIE_EXPCARD#
26
C334
C334
MINI2CLK_REQ#
PCIE_EXPCARD#
RN33
RN33
SRN33J-5-GP-U
SRN33J-5-GP-U
71
61
27
MINI2CLK_REQ#
CLKREQ8#
SCRC_5
R199R199
10KR2J-3-GP10KR2J-3-GP
PCI_ICH
MINI1CLK_REQ#
1
72
63
27
MINI1CLK_REQ#
CLKREQ9#
SRCT_6
64
SRCC_6
PCIE_ICH
66
SRCT_7
R491R491
10KR2J-3-GP10KR2J-3-GP
PCI_PCCARD
PCIE_ICH#
CLK_PCIE_ICH
1
67
2
3
SRCC_7
CLK_PCIE_ICH
21
CPU_MCH_BSEL1
PCIE_MINI2
CLK_PCIE_ICH#
45
70
1
4
FSB/TEST_MODE
SRCT_8
CLK_PCIE_ICH#
21
R487R487
33R2J-2-GP33R2J-2-GP
FSAFSA
PCIE_MINI2#
RN35
RN35
SRN33J-5-GP-U
SRN33J-5-GP-U
1
41
69
22
CLK_ICH_48M
48M/FSA
SRCC_8
R196R196
33R2J-2-GP33R2J-2-GP
PCI_ICH
PCIE_MINI1
CLK_PCIE_MINI2
1
37
3
1 4
21
CLK_PCI_ICH
PCIF0/ITP_SEL
SRCT_9
CLK_PCIE_MINI2
27
Enable TMP
PCIE_MINI1#
CLK_PCIE_MINI2#
2
2 3
SRCC_9
CLK_PCIE_MINI2#
27
H_STP_PCI#
CPU_ITP
RN38
RN38
SRN33J-5-GP-U
SRN33J-5-GP-U
25
6
22 H_STP_PCI#
PCI_STP#
CPUT2_ITP/SRCT_10
SB:70306
PCI_TPM
CPU_ITP#
1 CLK_PCIE_MINI1
34
5
4
PCI4/FCTSEL1
CPUC2_ITP/SRCC_10
CLK_PCIE_MINI1
27
delete
2 CLK_PCIE_MINI1#
3
CLK_PCIE_MINI1#
27
RN40
RN40
33
PCI3
R203R203
SB:70312
SRN33J-5-GP-U
SRN33J-5-GP-U
33R2J-2-GP33R2J-2-GP
PCI_PCCARD
CLK_DOTT
CLK_CPU_ITP
1
32
43
1
4
28 CLK_PCI_PCCARD
PCI2
DOT96T/27M_NSS
CLK_CPU_ITP
5
R207R207
33R2J-2-GP33R2J-2-GP
PCI_SIO
CLK_DOTC
CLK_CPU_ITP#
1
27
44
2
3
32
CLK_PCI_5025
PCI1/TME
DOT96C/27M_SS
CLK_CPU_ITP#
5
RN41
RN41
SRN33J-5-GP-U
SRN33J-5-GP-U
2 MCH_DREFCLK
3
MCH_DREFCLK
10
1 MCH_DREFCLK#
4
MCH_DREFCLK#
10
RN106
RN106
SRN33J-5-GP-U
SRN33J-5-GP-U
61229
CLK_ICH_48M
CY28547LFXCT-GP
CY28547LFXCT-GP
CLK_PCI_ICH
Solder Thermal Pad to
GND add min 4 vias
CLK_PCI_PCCARD
CLK_PCI_5025
B
B
CLK_XTAL_IN
CLK_ICH_14M
X2
X2
CLKREF
R211R211
33R2J-2-GP33R2J-2-GP
2
1
CLK_ICH_14M
22
CLK_XOUT
CLK_XTAL_OUT
1
2
1
2
R212
R212
470R2J-2-GP
470R2J-2-GP
X-14D31818M-25GP
X-14D31818M-25GP
SB:70215
FSC
SB:70312
C343
C343
C346
C346
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
ICS: 71.09333.A03 ICS9LPR333CKLFT
For wireless performance
Close to CLK GEN
SB:70216
SB:70215
SB:70312
SC:70423
SB:70312
SC:70423
SB:70312
PIN9
PIN39
+3.3V_RUN
FSA
R484R484
2K2R2J-2-GP2K2R2J-2-GP
CPU_MCH_BSEL0
1
CPU_MCH_BSEL0
7,10
PGMODE
DISCRIPTION
CPU_MCH_BSEL1
CPU_MCH_BSEL1
7,10
FSC
R210R210
2K2R2J-2-GP2K2R2J-2-GP
CPU_MCH_BSEL2
1
CPU_MCH_BSEL2
7,10
0 VTT_PWRGD#/PD
PIN34
R490
R490
0 UMA
1 DISC.
1 CKPWRGD/PD#(DEFAULT)
10KR2J-3-GP
10KR2J-3-GP
DY
DY
FCTSEL1
PIN43
DOT96T
27M_NonSpread
SE:70412
PCI_TPM
delete
SEL2 SEL1 SEL0
PIN44
DOT96C
27M_Spread
A
<Variant Name>
<Variant Name>
<Variant Name>
A
CPU
FSB
R202
R202
FSC
FSB
FSA
PIN47
LCD100/96T
SRCT_0
10KR2J-3-GP
10KR2J-3-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
PIN48
LCD100/96C
SRCC_0
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
0
1
100M
X
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
0
0
1
133M
X
Title
Title
Title
0
1
1
166M
667M
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
0
1
0
200M
800M
A3
A3
A3
CLK_GEN CY28547
CLK_GEN CY28547
CLK_GEN CY28547
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
6
6
6
of
of
of
46
46
46
5
4
3
2
1
12
C701
C701
SC8P250V2CC-GP
SC8P250V2CC-GP
12
C313
C313
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
12
C328
C328
SC8P250V2CC-GP
SC8P250V2CC-GP
12
C336
C336
SC8P250V2CC-GP
SC8P250V2CC-GP
12
C340
C340
SC12P50V2JN-3GP
SC12P50V2JN-3GP
12
12
1
2
1
2
12
12
1
2
12
12
20
XIN
19
7
XOUT
VDDA
40
VDD_48
65
VDD_SRC
23
54
REF0/FSC_TEST_SEL
VDD_SRC
22
49
REF1
VDD_SRC
36
VDD_PCI
30
VDD_PCI
21
VSS_REF
15
18
VSS_CPU
VDD_REF
12
VDD_CPU
68
1
VSS_SRC
VDD_SRC
4
VSS_SRC
35
12
VSS_PCI
31
39
VSS_PCI
VTT_PWRGD#/PD
42
VSS_48
8
9
VSSA
VSS_CPU
12
73
GND
12
12
12
1
2
12
12
12
5 4 3 2 1 DATA GRP0 DATA GRP0 DATA GRP1 DATA GRP1 H_A#[ 3
5
4
3
2
1
DATA GRP0
DATA GRP0
DATA GRP1
DATA GRP1
H_A#[ 3
35]
9
TP10TP10
1
U54A
U54A
1
1
OF 4
OF 4
+1.05V_VCCP
H_A#3
H_ADS#
J4
H1
A3#
ADS#
H_ADS#
9
H_A#4
H_BNR#
L5
E2
A4#
BNR#
H_BNR#
9
H_A#5
H_BPRI#
L4
G5
A5#
BPRI#
H_BPRI#
9
H_A#6
K5
A6#
H_A#7
H_DEFER#
R72
R72
D
M3
H5
D
A7#
DEFER#
H_DEFER#
9
H_A#8
H_DRDY#
56R2J-4-GP
56R2J-4-GP
N2
F21
A8#
DRDY#
H_DRDY#
9
H_A#9
H_DBSY#
J1
E1
A9#
DBSY#
H_DBSY#
9
H_D#[0
63]
9
H_A#10
N3
A10#
H_A#11
H_BR0#
P5
F1
A11#
BR0#
H_BR0#
9
H_A#12
P2
A12#
H_A#13
H_IERR#
L2
D20
A13#
IERR#
H_A#14
H_INIT#
P4
B3
A14#
INIT#
H_INIT#
20
H_A#15
U54B
U54B
2
2
OF 4
OF 4
P1
A15#
H_A#16
H_LOCK#
R1
H4
A16#
LOCK#
H_LOCK#
9
H_ADSTB#0
H_RESET#
H_D#0
H_D#32
M1
C1
E22
Y22
9 H_ADSTB#0
9 H_REQ#[0 4]
ADSTB0#
RESET#
H_RESET#
5,9
D0#
D32#
H_D#1
H_D#33
F24
AB24
H_RS#[0
2]
9
D1#
D33#
H_REQ#0
H_RS#0
H_D#2
H_D#34
K3
F3
E26
V24
REQ0#
RS0#
D2#
D34#
H_REQ#1
H_RS#1
H_D#3
H_D#35
H2
F4
G22
V26
REQ1#
RS1#
D3#
D35#
H_REQ#2
H_RS#2
H_D#4
H_D#36
K2
G3
F23
V23
REQ2#
RS2#
D4#
D36#
H_REQ#3
H_TRDY#
H_D#5
H_D#37
J3
G2
G25
T22
REQ3#
TRDY#
H_TRDY#
9
D5#
D37#
H_REQ#4
H_D#6
H_D#38
L1
E25
U25
REQ4#
D6#
D38#
H_HIT#
H_D#7
H_D#39
G6
E23
U23
HIT#
H_HIT#
9
D7#
D39#
H_A#17
H_HITM#
H_D#8
H_D#40
Y2
E4
K24
Y25
A17#
HITM#
H_HITM#
9
D8#
D40#
H_A#18
H_D#9
H_D#41
U5
G24
W22
A18#
D9#
D41#
H_A#19
ITP_BPM#0
H_D#10
H_D#42
R3
AD4
J24
Y23
A19#
BPM0#
ITP_BPM#0 5
D10#
D42#
H_A#20
ITP_BPM#1
H_D#11
H_D#43
W6
AD3
J23
W24
A20#
BPM1#
ITP_BPM#1 5
D11#
D43#
H_A#21
ITP_BPM#2
H_D#12
H_D#44
U4
AD1
H22
W25
A21#
BPM2#
ITP_BPM#2 5
D12#
D44#
H_A#22
ITP_BPM#3
H_D#13
H_D#45
Y5
AC4
F26
AA23
A22#
BPM3#
ITP_BPM#3 5
D13#
D45#
H_A#23
ITP_BPM#4
H_D#14
H_D#46
U1
AC2
K22
AA24
A23#
PRDY#
ITP_BPM#4 5
D14#
D46#
H_A#24
ITP_BPM#5
H_D#15
H_D#47
R4
AC1
H23
AB25
A24#
PREQ#
ITP_BPM#5 5
D15#
D47#
H_A#25
ITP_TCK
H_DSTBN#0
H_DSTBN#2H_DSTBN#2
T5
AC5
J26
Y26
A25#
TCK
ITP_TCK
5
9
H_DSTBN#0
DSTBN0#
DSTBN2#
H_DSTBN#2
9
H_A#26
ITP_TDI
H_DSTBP#0
H_DSTBP#2H_DSTBP#2
T3
AA6
H26
AA26
A26#
TDI
ITP_TDI
5
9
H_DSTBP#0
DSTBP0#
DSTBP2#
H_DSTBP#2
9
H_A#27
ITP_TDO
H_DIV#0
H_DIV#2H_DIV#2
W2
AB3
H25
U22
A27#
TDO
ITP_TDO
5
9
H_DIV#0
DINV0#
DINV2#
H_DIV#2
9
C
H_A#28
ITP_TMS
C
W5
AB5
A28#
TMS
ITP_TMS 5
H_A#29
ITP_TRST#
Y4
AB6
A29#
TRST#
ITP_TRST# 5
H_A#30
ITP_DBRESET#
H_D#16
H_D#48
U2
C20
N22
AE24
A30#
DBR#
ITP_DBRESET#
5,22,33
D16#
D48#
H_A#31
H_D#17
H_D#49
V4
K25
AD24
A31#
D17#
D49#
H_A#32
H_D#18
H_D#50
W3
P26
AA21
A32#
H_THRMDA
24
D18#
D50#
H_A#33
AA4
THERMAL
THERMAL
H_D#19
H_D#51
R23
AB22
A33#
D19#
D51#
H_A#34
H_D#20
H_D#52
AB2
L23
AB21
A34#
D20#
D52#
H_A#35
EC_CPU_PROCHOT#
C225
C225
H_D#21
H_D#53
AA3
D21
DY
DY
M24
AC26
A35#
PROCHOT#
EC_CPU_PROCHOT#
32
D21#
D53#
H_ADSTB#1
H_THRMDA
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
H_D#22
H_D#54
V1
A24
L22
AD20
9
H_ADSTB#1
ADSTB1#
THRMDA
D22#
D54#
H_THRMDC
H_D#23
H_D#55
B25
M23
AE22
THRMDC
D23#
D55#
H_A20M#
H_D#24
H_D#56
A6
P25
AF23
20
H_A20M#
A20M#
H_THRMDC
24
D24#
D56#
H_FERR#
H_THERMTRIP#
H_THERMTRIP#
H_D#25
H_D#57
A5
C7
P23
AC25
20
H_FERR#
FERR#
THERMTRIP#
H_THERMTRIP#
24
D25#
D57#
H_IGNNE#
H_D#26
H_D#58
C4
P22
AE21
20
H_IGNNE#
IGNNE#
D26#
D58#
+1.05V_VCCP
H_D#27
H_D#59
2
1
T24
AD21
+1.05V_VCCP
D27#
D59#
H_STPCLK#
R88R88
56R2J-4-GP56R2J-4-GP
H_D#28
H_D#60
D5
R24
AC22
20
H_STPCLK#
STPCLK#
D28#
D60#
H_INTR#
C6
HCLK
HCLK
CLK_CPU_BCLK
H_D#29
H_D#61
A22
L25
AD23
20
H_INTR#
LINT0
BCLK0
CLK_CPU_BCLK
6
D29#
D61#
H_NMI#
CLK_CPU_BCLK#
H_D#30
H_D#62
B4
A21
T25
AF22
20
H_NMI#
LINT1
BCLK1
CLK_CPU_BCLK#
6
D30#
D62#
H_SMI#
R377
R377
H_D#31
H_D#63
A3
N25
AC23
20
H_SMI#
SMI#
D31#
D63#
H_DSTBN#1
H_DSTBN#3
1KR2F-3-GP
1KR2F-3-GP
L26
AE25
9
H_DSTBN#1
DSTBN1#
DSTBN3#
H_DSTBN#3
9
TP9TP9
1 CPU_RSVD01
H_DSTBP#1
H_DSTBP#3
M4
M26
AF24
RSVD#M4
9
H_DSTBP#1
DSTBP1#
DSTBP3#
H_DSTBP#3
9
+1.05V_VCCP
TP8TP8
1 CPU_RSVD02
H_DIV#1
H_DIV#3
N5
N24
AC20
RSVD#N5
9
H_DIV#1
DINV1#
DINV3#
H_DIV#3
9
TP3TP3
1 CPU_RSVD03
T2
RSVD#T2
TP2TP2
1 CPU_RSVD04
V_CPU_GTLREF
COMP0
R70R70
27D4R2F-L1-GP27D4R2F-L1-GP
V3
AD26
R26
2
1
RSVD#V3
GTLREF
COMP0
TP22TP22
1 CPU_RSVD05
TP23TP23
TEST1
B2
1
C23
MISC
MISC
COMP1
R67R67
54D9R2F-L1-GP54D9R2F-L1-GP
U26
2
1
RSVD#B2
TEST1
COMP1
TP16TP16
1 CPU_RSVD06
TP15TP15
TEST2
COMP2
R57R57
27D4R2F-L1-GP27D4R2F-L1-GP
C3
1
D25
AA1
2
1
RSVD#C3
TEST2
COMP2
TP12TP12
1 CPU_RSVD07
R376
R376
TEST3
COMP3
R60R60
54D9R2F-L1-GP54D9R2F-L1-GP
R87
R87
D2
C24
Y1
2
1
DY
DY
RSVD#D2
TEST3
COMP3
TP13TP13
1 CPU_RSVD08
2KR2F-3-GP
2KR2F-3-GP
TP77TP77
TEST4
200R2F-L-GP
200R2F-L-GP
D22
1
AF26
RSVD#D22
TEST4
TP14TP14
1 CPU_RSVD09
TEST5
H_DPRSTP#
D3
AF1
E5
RSVD#D3
TEST5
DPRSTP#
H_DPRSTP#
10,20,39
TP11TP11
1 CPU_RSVD10
TP85TP85
F6
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
TEST6
H_DPSLP#
1
A26
B5
H_DPSLP#
B
RSVD#F6
TEST6
DPSLP#
20
B
H_DPWR#H_DPWR#
D24
DPWR#
H_DPWR#
9
CPU_MCH_BSEL0
H_PWRGOODH_PWRGOOD
B1
B22
D6
KEY_NC
6,10
CPU_MCH_BSEL0
BSEL0
PWRGOOD
CPU_MCH_BSEL1
H_CPUSLP#
B23
D7
6,10
CPU_MCH_BSEL1
BSEL1
SLP#
H_CPUSLP#
9
SKT-CPU478P-GP
SKT-CPU478P-GP
CPU_MCH_BSEL2
H_PSI#
C21
AE6
6,10
CPU_MCH_BSEL2
BSEL2
PSI#
H_PSI#
39
H_PWRGOOD
20
62.10079.021
62.10079.021
TP24TP24
1
TP1TP1
SKT-CPU478P-GP
SKT-CPU478P-GP
1
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
62.10079.021
62.10079.021
ICH
ICH
Use old Symbol replace New P/N
original value:SKT-CPU478P-GP
+1.05V_VCCP
TEST3 and TEST5
H_DPSLP#
2
DY
DY
1
For the purpose of testability,
route thes signals through a ground
R123
R123
56R2J-4-GP
56R2J-4-GP
H_DPRSTP#
2
referenced Zo=55ohm trace that ends
DY
DY
1
R115
R115
56R2J-4-GP
56R2J-4-GP
in a via that is near a
GND via
H_FERR#
2
1
R128R128
56R2J-4-GP56R2J-4-GP
EC_CPU_PROCHOT#
2
1
and is accessible through an
oscilloscope connection.
R73R73
56R2J-4-GP56R2J-4-GP
A
<Variant Name>
<Variant Name>
<Variant Name>
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
CPU-FSB(1/2)
CPU-FSB(1/2)
CPU-FSB(1/2)
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
7
7
7
of
of
of
46
46
46
5
4
3
2
1
RESERVED
RESERVED
XDP/ITP SIGNALS
XDP/ITP SIGNALS
CONTROL
CONTROL
12
1
2
1
2
1
2
DATA GRP2DATA
DATA GRP2DATA
GRP3
GRP3
1
2
SCD1U10V2KX-4GP SCD1U10V2KX-4GP C102 C102 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C122 C122 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C102
C102
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C122
C122
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C178
C178
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C147
C147
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C149
C149
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C91
C91
5
4
3
2
1
U54D
U54D
4
4
OF 4
OF 4
A4
P6
VSS
VSS
A8
P21
VSS
VSS
+VCC_CORE
+VCC_CORE
A11
P24
VSS
VSS
U54C
U54C
3
3
OF 4
OF 4
A14
R2
VSS
VSS
A16
R5
VSS
VSS
A19
R22
A7
AB20
VSS
VSS
VCC
VCC
D
A23
R25
A9
AB7
D
VSS
VSS
VCC
VCC
AF2
T1
A10
AC7
VSS
VSS
VCC
VCC
B6
T4
A12
AC9
VSS
VSS
VCC
VCC
B8
T23
A13
AC12
VSS
VSS
VCC
VCC
B11
T26
A15
AC13
VSS
VSS
VCC
VCC
B13
U3
A17
AC15
VSS
VSS
VCC
VCC
B16
U6
A18
AC17
VSS
VSS
VCC
VCC
B19
U21
A20
AC18
VSS
VSS
VCC
VCC
B21
U24
B7
AD7
VSS
VSS
VCC
VCC
B24
V2
B9
AD9
VSS
VSS
VCC
VCC
SB:70312
C5
V5
B10
AD10
VSS
VSS
VCC
VCC
C8
V22
B12
AD12
VSS
VSS
VCC
VCC
C11
V25
B14
AD14
VSS
VSS
VCC
VCC
C599
C599
C14
W1
B15
AD15
VSS
VSS
VCC
VCC
C16
W4
DY
DY
DY
DY
B17
AD17
VSS
VSS
VCC
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C19
W23
B18
AD18
VSS
VSS
VCC
VCC
C2
W26
B20
AE9
VSS
VSS
VCC
VCC
C22
Y3
C9
AE10
VSS
VSS
VCC
VCC
C25
Y6
C10
AE12
VSS
VSS
VCC
VCC
D1
Y21
C12
AE13
VSS
VSS
VCC
VCC
D4
Y24
C13
AE15
VSS
VSS
VCC
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
D8
AA2
C15
AE17
VSS
VSS
VCC
VCC
SB:70312
SB:70312
D11
AA5
C17
AE18
VSS
VSS
VCC
VCC
D13
AA8
C18
AE20
VSS
VSS
VCC
VCC
D16
AA11
D9
AF9
VSS
VSS
VCC
VCC
C669
C669
D19
AA14
D10
AF10
VSS
VSS
VCC
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
D23
AA16
DY
DY
DY
DY
D12
AF12
VSS
VSS
VCC
VCC
C679
C679
C129
C129
C99
C99
C671
C671
D26
AA19
D14
AF14
VSS
VSS
VCC
VCC
E3
AA22
D15
AF15
VSS
VSS
VCC
VCC
C
C
E6
AA25
D17
AF17
VSS
VSS
VCC
VCC
+1.05V_VCCP
E8
AB1
D18
AF18
VSS
VSS
VCC
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
E11
AB4
E7
AF20
VSS
VSS
VCC
VCC
C680
C680
C128
C128
C601
C601
C670
C670
E14
AB8
E9
VSS
VSS
VCC
E16
AB11
E10
G21
VSS
VSS
VCC
VCCP
E19
AB13
E12
V6
VSS
VSS
VCC
VCCP
SC:70330
E21
AB16
E13
J6
VSS
VSS
VCC
VCCP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
E24
AB19
E15
K6
DY
DY
VSS
VSS
VCC
VCCP
C678
C678
C598
C598
C603
C603
C127
C127
C126
C126
TC2
TC2
F5
AB23
E17
M6
VSS
VSS
VCC
VCCP
ST220U6D3VDM-13GP
ST220U6D3VDM-13GP
F8
AB26
DY
DY
E18
J21
VSS
VSS
VCC
VCCP
F11
AC3
E20
K21
VSS
VSS
VCC
VCCP
F13
AC6
F7
M21
VSS
VSS
VCC
VCCP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
F16
AC8
F9
N21
VSS
VSS
VCC
VCCP
C273
C273
C677
C677
C600
C600
C673
C673
F19
AC11
F10
N6
VSS
VSS
VCC
VCCP
F2
AC14
F12
R21
VSS
VSS
VCC
VCCP
F22
AC16
F14
R6
VSS
VSS
VCC
VCCP
F25
AC19
F15
T21
VSS
VSS
VCC
VCCP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SB:70312
G4
AC21
F17
T6
VSS
VSS
VCC
VCCP
C275
C275
C675
C675
C676
C676
C672
C672
G1
AC24
F18
V21
VSS
VSS
VCC
VCCP
+1.5V_RUN
G23
AD2
F20
W21
VSS
VSS
VCC
VCCP
C103
C103
G26
AD5
AA7
VSS
VSS
VCC
H3
AD8
DY
DY
AA9
B26
VSS
VSS
VCC
VCCA
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VID[0 6]
H6
AD11
AA10
C26
VSS
VSS
VCC
VCCA
VID[0
6]
39
C274
C274
C271
C271
C602
C602
C104
C104
H21
AD13
AA12
VSS
VSS
VCC
VID0
H24
AD16
AA13
AD6
VSS
VSS
VCC
VID0
VID1
C633
C633
C640
C640
J2
AD19
AA15
AF5
VSS
VSS
VCC
VID1
VID2
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
J5
AD22
AA17
AE5
VSS
VSS
VCC
VID2
VID3
J22
AD25
AA18
AF4
VSS
VSS
VCC
VID3
VID4
J25
AE1
AA20
AE3
Layout note:
B
VSS
VSS
VCC
VID4
B
VID5
K1
AE4
AB9
AF3
VSS
VSS
VCC
VID5
VID6
K4
AE8
10uF 0805 X5R -> 85 degree C ,
Or better such As X6S and X7R
AC10
AE2
VSS
VSS
VCC
VID6
K23
AE11
AB10
place C59 near
PIN B26
VSS
VSS
VCC
+VCC_CORE
K26
AE14
AB12
VSS
VSS
VCC
VCCSENSE
L3
AE16
AB14
AF7
VSS
VSS
VCC
VCCSENSE
VCCSENSE
39
L6
AE19
AB15
1
VSS
VSS
VCC
R49R49
100R2F-L1-GP-U100R2F-L1-GP-U
L21
AE23
AB17
VSS
VSS
VCC
VSSSENSE
L24
AE26
AB18
AE7
VSS
VSS
VCC
VSSSENSE
VSSSENSE
39
M2
A2
VSS
VSS
M5
AF6
1
VSS
VSS
SKT-CPU478P-GP
SKT-CPU478P-GP
R50R50
100R2F-L1-GP-U100R2F-L1-GP-U
M22
AF8
VSS
VSS
62.10079.021
62.10079.021
M25
AF11
VSS
VSS
N1
AF13
VSS
VSS
N4
AF16
VSS
VSS
N23
AF19
VSS
VSS
N26
AF21
Layout note:
VSS
VSS
P3
A25
VSS
VSS
AF25
VSS
Place R53 and R54 within 1" of CPU.
Routing VCC_SENSE and VSS_SENSE at
27.4 ohms with 50 mils spacing.
SKT-CPU478P-GP
SKT-CPU478P-GP
62.10079.021
62.10079.021
A
<Variant Name>
<Variant Name>
<Variant Name>
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
06.CPU-POWER (2/2)
06.CPU-POWER (2/2)
06.CPU-POWER (2/2)
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
8
8
8
of
of
of
46
46
46
5
4
3
2
1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
C101
C101
C100
C100
C272
C272
C674
C674
12
12
12
12
12
12
12
1
2
12
12
1
2
1
2
12
5 4 3 2 1 D D U56A U56A 1 1 OF 10 OF 10
5
4
3
2
1
D
D
U56A
U56A
1
1
OF 10
OF 10
7 H_D#[0 63]
H_A#[ 3
35]
7
H_D#0
H_A#3
E2
J13
H_D#0
H_A#3
H_D#1
H_A#4
G2
B11
H_D#1
H_A#4
H_D#2
H_A#5
G7
C11
H_D#2
H_A#5
H_D#3
H_A#6
M6
M11
H_D#3
H_A#6
H_D#4
H_A#7
H7
C15
H_D#4
H_A#7
H_D#5
H_A#8
H3
F16
H_D#5
H_A#8
H_D#6
H_A#9
G4
L13
H_D#6
H_A#9
H_D#7
H_A#10
F3
G17
H_D#7
H_A#10
+1.05V_VCCP
H_D#8
H_A#11
N8
C14
H_D#8
H_A#11
H_D#9
H_A#12
H2
K16
H_D#9
H_A#12
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_D#10
H_A#13
M10
B13
H_D#10
H_A#13
H_D#11
H_A#14
N12
L16
H_D#11
H_A#14
H_D#12
H_A#15
R465
R465
N9
J17
H_D#12
H_A#15
H_D#13
H_A#16
221R2F-2-GP
221R2F-2-GP
H5
B14
H_D#13
H_A#16
H_D#14
H_A#17
P13
K19
H_D#14
H_A#17
H_D#15
H_A#18
K9
P15
H_D#15
H_A#18
H_D#16
H_A#19
H_SWING
M2
R17
H_SWING Resistors and
Capacitors close
Caliistoga 500 mil ( MAX )
H_D#16
H_A#19
H_D#17
H_A#20
W10
B16
H_D#17
H_A#20
H_D#18
H_A#21
Y8
H20
H_D#18
H_A#21
H_D#19
H_A#22
V4
L19
H_D#19
H_A#22
From Schematic Design
Checklit v.1201
R464
R464
H_D#20
H_A#23
C683
C683
M3
D17
100R2F-L1-GP-U
100R2F-L1-GP-U
H_D#20
H_A#23
H_D#21
H_A#24
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
J1
M17
H_D#21
H_A#24
H_D#22
H_A#25
N5
N16
221 1% pull high 100
1% pull low
H_D#22
H_A#25
H_D#23
H_A#26
N3
J19
H_D#23
H_A#26
H_D#24
H_A#27
W6
B18
H_D#24
H_A#27
C
H_D#25
H_A#28
C
W9
E19
H_D#25
H_A#28
H_D#26
H_A#29
N2
B17
H_D#26
H_A#29
H_D#27
H_A#30
Y7
B15
H_D#27
H_A#30
H_D#28
H_A#31
Y9
E17
H_D#28
H_A#31
H_D#29
H_A#32
P4
C18
H_D#29
H_A#32
H_D#30
H_A#33
W3
A19
H_D#30
H_A#33
H_D#31
H_A#34
N1
B19
H_SCOMP and H_SCOMP# Resistors
and Capacitors close Caliistoga
500 mil ( MAX )
H_D#31
H_A#34
H_D#32
H_A#35
AD12
N19
H_D#32
H_A#35
Zo=55ohms
H_D#33
AE3
H_D#33
H_D#34
H_ADS#
AD9
G12
H_D#34
H_ADS#
H_ADS#
7
H_D#35
H_ADSTB#0
AC9
H17
H_D#35
H_ADSTB#0
H_ADSTB#0
7
+1.05V_VCCP
H_D#36
H_ADSTB#1
AC7
G20
H_D#36
H_ADSTB#1
H_ADSTB#1
7
H_D#37
H_BNR#
AC14
C8
H_D#37
H_BNR#
H_BNR#
7
H_D#38
H_BPRI#
H_SCOMP
AD11
E8
2
1
H_D#38
H_BPRI#
H_BPRI#
7
H_D#39
H_BR0#
R417R417
54D9R2F-L1-GP54D9R2F-L1-GP
AC11
F12
H_D#39
H_BREQ#
H_BR0#
7
+1.05V_VCCP
H_D#40
H_DEFER#
AB2
D6
H_D#40
H_DEFER#
H_DEFER#
7
H_D#41
H_DBSY#
AD7
C10
H_D#41
H_DBSY#
H_DBSY#
7
H_D#42
CLK_MCH_BCLK
H_SCOMP#
AB1
AM5
2
1
H_D#42
HPLL_CLK
CLK_MCH_BCLK
6
H_D#43
CLK_MCH_BCLK#
R420R420
54D9R2F-L1-GP54D9R2F-L1-GP
Y3
AM7
H_D#43
HPLL_CLK#
CLK_MCH_BCLK#
6
H_D#44
H_DPWR#
AC6
H8
H_D#44
H_DPWR#
H_DPWR#
7
H_D#45
H_DRDY#
AE2
K7
H_D#45
H_DRDY#
H_DRDY#
7
H_D#46
H_HIT#
AC5
E4
H_D#46
H_HIT#
H_HIT#
7
H_D#47
H_HITM#
AG3
C6
H_D#47
H_HITM#
H_HITM#
7
H_D#48
H_LOCK#
AJ9
G10
H_D#48
H_LOCK#
H_LOCK#
7
H_D#49
H_TRDY#
AH8
B7
H_D#49
H_TRDY#
H_TRDY#
7
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
H_D#50
AJ14
H_D#50
H_D#51
AE9
H_D#51
H_D#52
AE11
H_D#52
H_D#53
H_RCOMP
AH12
2
1
B
H_D#53
B
H_D#54
H_DIV#0
R463R463
24D9R2F-L-GP24D9R2F-L-GP
AJ5
K5
H_D#54
H_DINV#0
H_DIV#0
7
H_D#55
H_DIV#1
AH5
L2
H_D#55
H_DINV#1
H_DIV#1
7
H_D#56
H_DIV#2
AJ6
AD13
H_D#56
H_DINV#2
H_DIV#2
7
H_D#57
H_DIV#3
AE7
AE13
H_D#57
H_DINV#3
H_DIV#3
7
H_D#58
AJ7
H_D#58
H_D#59
H_DSTBN#0
AJ2
M7
H_D#59
H_DSTBN#0
H_DSTBN#0
7
H_D#60
H_DSTBN#1
AE5
K3
H_D#60
H_DSTBN#1
H_DSTBN#1
7
H_D#61
H_DSTBN#2
AJ3
AD2
H_D#61
H_DSTBN#2
H_DSTBN#2
7
H_REF Decoupling Crestline
close Crestline 100 mil
H_D#62
H_DSTBN#3
AH2
AH11
H_D#62
H_DSTBN#3
H_DSTBN#3
7
H_D#63
AH13
H_D#63
H_DSTBP#0
L7
H_DSTBP#0
H_DSTBP#0
7
H_DSTBP#1
K2
H_DSTBP#1
H_DSTBP#1
7
H_SWING
H_DSTBP#2
B3
AC2
H_SWING
H_DSTBP#2
H_DSTBP#2
7
+1.05V_VCCP
H_RCOMP
H_DSTBP#3
C2
AJ10
H_RCOMP
H_DSTBP#3
H_DSTBP#3
7
H_REQ#[0
4]
7
H_SCOMP
H_REQ#0
W1
M14
H_SCOMP
H_REQ#0
H_SCOMP#
H_REQ#1
W2
E13
H_SCOMP#
H_REQ#1
R467
R467
H_REQ#2
A11
H_REQ#2
H_RESET#
H_REQ#3
1KR2F-3-GP
1KR2F-3-GP
B6
H13
5,7
H_RESET#
H_CPURST#
H_REQ#3
H_CPUSLP#
H_REQ#4
E5
B12
7 H_CPUSLP#
H_CPUSLP#
H_REQ#4
H_RS#[0
2]
7
H_RS#0
E12
H_RS#0
H_REFH_REFH_REF
H_RS#1
B9
D7
H_AVREF
H_RS#1
H_RS#2
A9
D8
H_DVREF
H_RS#2
R459
R459
2KR2F-3-GP
2KR2F-3-GP
C684
C684
71.CREST.00U
71.CREST.00U
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CRESTLINE-GP-U
CRESTLINE-GP-U
A
<Variant Name>
<Variant Name>
<Variant Name>
A
Change to 71.CREST.M02
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
GMCH-FSB LIBC (1/6)
GMCH-FSB LIBC (1/6)
GMCH-FSB LIBC (1/6)
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
9
9
9
of
of
of
46
46
46
5
4
3
2
1
1
2
1
2
1
2
HOST
HOST
1
2
12
12
5 4 3 2 1 * is Default setting U56B U56B 2 2 OF 10
5
4
3
2
1
*
is Default setting
U56B
U56B
2
2
OF 10
OF 10
CFG Strap
Low
High
M_CLK_DDR0
P36
AV29
RSVD#P36
SM_CK0
M_CLK_DDR0
15
CFG 5
DMI X 2
DMI X 4
M_CLK_DDR1
P37
BB23
*
RSVD#P37
SM_CK1
M_CLK_DDR1
15
+1.8V_SUS
M_CLK_DDR2
R35
BA25
RSVD#R35
SM_CK3
M_CLK_DDR2
16
CFG 6
Moby Dick
Calistoga
M_CLK_DDR3
N35
AV23
*
RSVD#N35
SM_CK4
M_CLK_DDR3
16
AR12
RSVD#AR12
CFG 7
DT/Transportable CPU
Mobile CPU
M_CLK_DDR#0
AR13
AW30
*
RSVD#AR13
SM_CK#0
M_CLK_DDR#0
15
M_CLK_DDR#1
R362
R362
AM12
BA23
RSVD#AM12
SM_CK#1
M_CLK_DDR#1
15
CFG 9
Reserved Lane
Normal Operation
M_CLK_DDR#2
1KR2F-3-GP
1KR2F-3-GP
AN13
AW25
*
RSVD#AN13
SM_CK#3
M_CLK_DDR#2
16
M_CLK_DDR#3
J12
AW23
RSVD#J12
SM_CK#4
M_CLK_DDR#3
16
CFG 10
Reserved
Mobility
D
AR37
*
D
RSVD#AR37
DDR_CKE0_DIMMA
AM36
BE29
RSVD#AM36
SM_CKE0
DDR_CKE0_DIMMA
15
CFG 11
Calistoga
Reserved
DDR_CKE1_DIMMA
AL36
AY32
*
RSVD#AL36
SM_CKE1
DDR_CKE1_DIMMA
15
DDR_CKE2_DIMMB
AM37
BD39
RSVD#AM37
SM_CKE3
DDR_CKE2_DIMMB
16
CFG 16
DDR_CKE3_DIMMB
C563
C563
C570
C570
R365
R365
D20
BG37
RSVD#D20
SM_CKE4
DDR_CKE3_DIMMB
16
FSB Dynamic ODT
Disabled
Enabled
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
3K01R2F-3-GP
3K01R2F-3-GP
*
DDR_CS0_DIMMA#
BG20
SM_CS#0
DDR_CS0_DIMMA#
15
CFG 18
DDR_CS1_DIMMA#
BK16
SM_CS#1
DDR_CS1_DIMMA#
15
VCC Select
1.05V
1.5V
DDR_CS2_DIMMB#
BG16
*
SM_CS#2
DDR_CS2_DIMMB#
16
DDR_CS3_DIMMB#
H10
BE13
RSVD#H10
SM_CS#3
DDR_CS3_DIMMB#
16
CFG 19
B51
RSVD#B51
DMI Lane Reserved
Normal Operation
Reserved Lane
M_ODT0
BJ20
BH18
*
RSVD#BJ20
SM_ODT0
M_ODT0 15
M_ODT1
BK22
BJ15
RSVD#BK22
SM_ODT1
M_ODT1 15
CFG 20
PCIE and SDVO
M_ODT2
BF19
BJ14
RSVD#BF19
SM_ODT2
M_ODT2 16
PCIE/SDVO Select
Only PCIE or SDVO
is operation
M_ODT3
C564
C564
C571
C571
R363
R363
BH20
BE16
*
are operation simu
RSVD#BH20
SM_ODT3
M_ODT3 16
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1KR2F-3-GP
1KR2F-3-GP
BK18
RSVD#BK18
No SDVO Device
present
SDVO Device present
SM_RCOMP_VOH
BJ18
BK31
RSVD#BJ18
SM_RCOMP_VOH
SDVO_CTRLDATA
SM_RCOMP_VOL
BF23
BL31
*
RSVD#BF23
SM_RCOMP_VOL
BG23
CLOSE PIN BL15 BK14
RSVD#BG23
SM_RCOMP
R367R367
20R2F-GP20R2F-GP
BC23
BL15
2
1
+1.8V_SUS
RSVD#BC23
SM_RCOMP
SM_RCOMP#
R366R366
20R2F-GP20R2F-GP
BD24
BK14
2
1
RSVD#BD24
SM_RCOMP#
CFG[13:12]
AR49
V_DDR_MCH_REF
SM_VREF#AR49
LL
Reserved
BH39
AW4
RSVD#BH39
SM_VREF#AW4
AW20
RSVD#AW20
LH
XOR Mode Enabled
BK20
RSVD#BK20
HL
All Z Mode Enabled
MCH_DREFCLK
B42
DPLL_REF_CLK
MCH_DREFCLK
6
MCH_DREFCLK#
B44
C42
RSVD#B44
DPLL_REF_CLK#
MCH_DREFCLK#
6
C
HH
Normal Operation *
DREF_SSCLK
C
C44
H48
RSVD#C44
DPLL_REF_SSCLK
DREF_SSCLK
6
DREF_SSCLK#
A35
H47
RSVD#A35
DPLL_REF_SSCLK#
DREF_SSCLK#
6
CFG[2
0]
FSB Select
B37
RSVD#B37
RSVD
RSVD
CFG
CFG
PM
PM
NC
NC
CLK_MCH_3GPLL
B36
K44
RSVD#B36
PEG_CLK
CLK_MCH_3GPLL
6
LHL
FSB 800
CLK_MCH_3GPLL#
B34
K45
RSVD#B34
PEG_CLK#
CLK_MCH_3GPLL#
6
C34
RSVD#C34
LHH
FSB 667
Other
Reserved
DMI_MRX_ITX_N0
AN47
DMI_RXN0
DMI_MRX_ITX_N0 21
DMI_MRX_ITX_N1
AJ38
DMI_RXN1
DMI_MRX_ITX_N1 21
CPU_MCH_BSEL0
DMI_MRX_ITX_N2
P27
AN42
6,7
CPU_MCH_BSEL0
CFG0
DMI_RXN2
DMI_MRX_ITX_N2 21
CPU_MCH_BSEL1
DMI_MRX_ITX_N3
N27
AN46
6,7
CPU_MCH_BSEL1
CFG1
DMI_RXN3
DMI_MRX_ITX_N3 21
CPU_MCH_BSEL2
N24
6,7
CPU_MCH_BSEL2
CFG2
DMI_MRX_ITX_P0
C21
AM47
CFG3
DMI_RXP0
DMI_MRX_ITX_P0 21
DMI_MRX_ITX_P1
C23
AJ39
CFG4
DMI_RXP1
DMI_MRX_ITX_P1 21
DMI_MRX_ITX_P2
F23
AN41
CFG5
DMI_RXP2
DMI_MRX_ITX_P2 21
DMI_MRX_ITX_P3
N23
AN45
CFG6
DMI_RXP3
DMI_MRX_ITX_P3 21
Layout Note:
G23
CFG7
DMI_MTX_IRX_N0
J20
AJ46
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
CFG8
DMI_TXN0
DMI_MTX_IRX_N0 21
DMI_MTX_IRX_N1
C20
AJ41
CFG9
DMI_TXN1
DMI_MTX_IRX_N1 21
DMI_MTX_IRX_N2
R24
AM40
CFG10
DMI_TXN2
DMI_MTX_IRX_N2 21
DMI_MTX_IRX_N3
L23
AM44
CFG11
DMI_TXN3
DMI_MTX_IRX_N3 21
J23
CFG12
DMI_MTX_IRX_P0
E23
AJ47
CFG13
DMI_TXP0
DMI_MTX_IRX_P0 21
+1.25V_RUN
DMI_MTX_IRX_P1
E20
AJ42
CFG14
DMI_TXP1
DMI_MTX_IRX_P1 21
DMI_MTX_IRX_P2
K23
AM39
CFG15
DMI_TXP2
DMI_MTX_IRX_P2 21
DMI_MTX_IRX_P3
M20
AM43
CFG16
DMI_TXP3
DMI_MTX_IRX_P3 21
M24
B
CFG17
B
R396
R396
L32
CFG18
1KR2F-3-GP
1KR2F-3-GP
N33
CFG19
L35
CFG20
E35
GFX_VID0
A39
GFX_VID1
PM_BMBUSY#
G41
C38
22 PM_BMBUSY#
PM_BM_BUSY#
GFX_VID2
H_DPRSTP#
L39
B39
7,20,39
H_DPRSTP#
PM_DPRSTP#
GFX_VID3
R58
R58
0R2J-2-GP
0R2J-2-GP
PM_EXTTS#0
R387
R387
1
L36
E36
21 SB_NB_PCIE_RST#
DY
DY
15
PM_EXTTS#0
PM_EXT_TS#0
GFX_VR_EN
PM_EXTTS#1
C615
C615
392R2F-GP
392R2F-GP
J36
16
PM_EXTTS#1
PM_EXT_TS#1
ICH_PWRGD
Layout Note:
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AW49
22,36
ICH_PWRGD
PWROK
PLTRST#C
1
AV20
17,21,25,26,27,32
PLTRST#
RSTIN#
R63R63
100R2J-2-GP100R2J-2-GP
THERMTRIP_MCH#
N20
24 THERMTRIP_MCH#
THERMTRIP#
MCH_CLVREF ~= 0.350V
Width/Spacing = 12/12
+2.5V_RUN
R145R145
0R0402-PAD0R0402-PAD
DPRSLPVR_R
2
1
G36
22,33,39
DPRSLPVR
DPRSLPVR
2
1
+1.05V_VCCP
R119R119
56R2J-4-GP56R2J-4-GP
CL_CLK0
AM49
CL_CLK
CL_CLK0
22
CL_DATA0
BJ51
AK50
NC#BJ51
CL_DATA
CL_DATA0
22
ICH_CL_PWROK
BK51
AT43
NC#BK51
CL_PWROK
ICH_CL_PWROK
22,32
+3.3V_RUN
ICH_CL_RST0#
RN105
RN105
BK50
AN49
NC#BK50
CL_RST#
ICH_CL_RST0#
22
MCH_CLVREF
BL50
AM50
SRN4K7J-8-GP
SRN4K7J-8-GP
NC#BL50
CL_VREF
PM_EXTTS#1
4
1
BL49
NC#BL49
PM_EXTTS#0
SB:70213
3
2
BL3
NC#BL3
RN1
RN1
SRN10KJ-5-GP
SRN10KJ-5-GP
BL2
NC#BL2
BK1
NC#BK1
61229
SDVO_CTRLCLK
BJ1
H35
NC#BJ1
SDVO_CTRL_CLK
SDVO_CTRLCLK
17
SDVO_CTRLDATA
E1
K36
NC#E1
SDVO_CTRL_DATA
SDVO_CTRLDATA
17
CLK_3GPLLREQ#
A5
G39
NC#A5
CLKREQ#
CLK_3GPLLREQ#
6
MCH_ICH_SYNC#
C51
G40
A
<Variant Name>
<Variant Name>
<Variant Name>
NC#C51
ICH_SYNC#
MCH_ICH_SYNC#
22
A
B50
NC#B50
A50
NC#A50
TEST1_GMCH
A49
A37
NC#A49
TEST1
Wistron Corporation
Wistron Corporation
Wistron Corporation
TEST2_GMCH
BK2
R32
NC#BK2
TEST2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
R113
R113
R466
R466
CRESTLINE-GP-U
CRESTLINE-GP-U
71.CREST.00U
71.CREST.00U
20KR2J-L2-GP
20KR2J-L2-GP
0R0402-PAD
0R0402-PAD
Title
Title
Title
Thurman UMA
Thurman UMA
Thurman UMA
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
GMCH-DMI/DDR (2/6)
GMCH-DMI/DDR (2/6)
GMCH-DMI/DDR (2/6)
-1
-1
-1
Date:
Date:
Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
10
10
10
of
of
of
46
46
46
5
4
3
2
1
CLK
CLK
MISC
MISC
ME
ME
GRAPHICS VID
GRAPHICS VID
DMI
DMI
DDR MUXING
DDR MUXING
12
12
1
2
1
4
2
3
12
12
1
2
1
2
1
2
1
2
12
12
12
5 D DDR_A_D[0 63] 15 DDR_A_D[0 63] C B A 5
5
D
DDR_A_D[0 63]
15 DDR_A_D[0 63]
C
B
A
5

4

3

2

1

2]

16

16

7]

16

7]

7]

16

16

16

D

C

63] C B A 5 4 3 2 1 2] 16 16 7] 16 7] 7]

B

A

U56D U56D 4 4 OF 10 OF 10 DDR_A_BS[0 2] DDR_A_BS[0 2] 15 U56E U56E
U56D
U56D
4 4
OF 10
OF 10
DDR_A_BS[0 2]
DDR_A_BS[0
2]
15
U56E
U56E
5 5
OF 10
OF 10
DDR_B_BS[0 2]
DDR_A_D0
DDR_A_BS0
DDR_B_D[0 63]
AR43
BB19
SA_DQ0
SA_BS0
16 DDR_B_D[0 63]
DDR_A_D1
DDR_A_BS1
DDR_B_D0
DDR_B_BS0
AW44
BK19
AP49
AY17
SA_DQ1
SA_BS1
SB_DQ0
SB_BS0
DDR_A_D2
DDR_A_BS2
DDR_B_D1
DDR_B_BS1
BA45
BF29
AR51
BG18
SA_DQ2
SA_BS2
SB_DQ1
SB_BS1
DDR_A_D3
DDR_B_D2
DDR_B_BS2
AY46
AW50
BG36
SA_DQ3
SB_DQ2
SB_BS2
DDR_A_D4
DDR_A_CAS#
DDR_B_D3
AR41
BL17
AW51
SA_DQ4
SA_CAS#
DDR_A_CAS#
15
SB_DQ3
DDR_A_D5
DDR_A_DM[0 7]
DDR_B_D4
DDR_B_CAS#
AR45
AN51
BE17
SA_DQ5
DDR_A_DM[0
7]
15
SB_DQ4
SB_CAS#
DDR_A_D6
DDR_A_DM0
DDR_B_D5
DDR_B_DM[0 7]
AT42
AT45
AN50
SA_DQ6
SA_DM0
SB_DQ5
DDR_A_D7
DDR_A_DM1
DDR_B_D6
DDR_B_DM0
AW47
BD44
AV50
AR50
SA_DQ7
SA_DM1
SB_DQ6
SB_DM0
DDR_A_D8
DDR_A_DM2
DDR_B_D7
DDR_B_DM1
BB45
BD42
AV49
BD49
SA_DQ8
SA_DM2
SB_DQ7
SB_DM1
DDR_A_D9
DDR_A_DM3
DDR_B_D8
DDR_B_DM2
BF48
AW38
BA50
BK45
SA_DQ9
SA_DM3
SB_DQ8
SB_DM2
DDR_A_D10
DDR_A_DM4
DDR_B_D9
DDR_B_DM3
BG47
AW13
BB50
BL39
SA_DQ10
SA_DM4
SB_DQ9
SB_DM3
DDR_A_D11
DDR_A_DM5
DDR_B_D10
DDR_B_DM4
BJ45
BG8
BA49
BH12
SA_DQ11
SA_DM5
SB_DQ10
SB_DM4
DDR_A_D12
DDR_A_DM6
DDR_B_D11
DDR_B_DM5
BB47
AY5
BE50
BJ7
SA_DQ12
SA_DM6
SB_DQ11
SB_DM5
DDR_A_D13
DDR_A_DM7
DDR_B_D12
DDR_B_DM6
BG50
AN6
BA51
BF3
SA_DQ13
SA_DM7
SB_DQ12
SB_DM6
DDR_A_D14
DDR_A_DQS[0 7]
DDR_B_D13
DDR_B_DM7
BH49
AY49
AW2
SA_DQ14
DDR_A_DQS[0
7]
15
SB_DQ13
SB_DM7
DDR_A_D15
DDR_A_DQS0
DDR_B_D14
DDR_B_DQS[0 7]
BE45
AT46
BF50
SA_DQ15
SA_DQS0
SB_DQ14
DDR_A_D16
DDR_A_DQS1
DDR_B_D15
DDR_B_DQS0
AW43
BE48
BF49
AT50
SA_DQ16
SA_DQS1
SB_DQ15
SB_DQS0
DDR_A_D17
DDR_A_DQS2
DDR_B_D16
DDR_B_DQS1
BE44
BB43
BJ50
BD50
SA_DQ17
SA_DQS2
SB_DQ16
SB_DQS1
DDR_A_D18
DDR_A_DQS3
DDR_B_D17
DDR_B_DQS2
BG42
BC37
BJ44
BK46
SA_DQ18
SA_DQS3
SB_DQ17
SB_DQS2
DDR_A_D19
DDR_A_DQS4
DDR_B_D18
DDR_B_DQS3
BE40
BB16
BJ43
BK39
SA_DQ19
SA_DQS4
SB_DQ18
SB_DQS3
DDR_A_D20
DDR_A_DQS5
DDR_B_D19
DDR_B_DQS4
BF44
BH6
BL43
BJ12
SA_DQ20
SA_DQS5
SB_DQ19
SB_DQS4
DDR_A_D21
DDR_A_DQS6
DDR_B_D20
DDR_B_DQS5
BH45
BB2
BK47
BL7
SA_DQ21
SA_DQS6
SB_DQ20
SB_DQS5
DDR_A_D22
DDR_A_DQS7
DDR_A_DQS#[0 7]
DDR_B_D21
DDR_B_DQS6
BG40
AP3
BK49
BE2
SA_DQ22
SA_DQS7
DDR_A_DQS#[0
7]
15
SB_DQ21
SB_DQS6
DDR_A_D23
DDR_A_DQS#0
DDR_B_D22
DDR_B_DQS7
DDR_B_DQS#[0 7]
BF40
AT47
BK43
AV2
SA_DQ23
SA_DQS#0
SB_DQ22
SB_DQS7
DDR_A_D24
DDR_A_DQS#1
DDR_B_D23
DDR_B_DQS#0
AR40
BD47
BK42
AU50
SA_DQ24
SA_DQS#1
SB_DQ23
SB_DQS#0
DDR_A_D25
DDR_A_DQS#2
DDR_B_D24
DDR_B_DQS#1
AW40
BC41
BJ41
BC50
SA_DQ25
SA_DQS#2
SB_DQ24
SB_DQS#1
DDR_A_D26
DDR_A_DQS#3
DDR_B_D25
DDR_B_DQS#2
AT39
BA37
BL41
BL45
SA_DQ26
SA_DQS#3
SB_DQ25
SB_DQS#2
DDR_A_D27
DDR_A_DQS#4
DDR_B_D26
DDR_B_DQS#3
AW36
BA16
BJ37
BK38
SA_DQ27
SA_DQS#4
SB_DQ26
SB_DQS#3
DDR_A_D28
DDR_A_DQS#5
DDR_B_D27
DDR_B_DQS#4
AW41
BH7
BJ36
BK12
SA_DQ28
SA_DQS#5
SB_DQ27
SB_DQS#4
DDR_A_D29
DDR_A_DQS#6
DDR_B_D28
DDR_B_DQS#5
AY41
BC1
BK41
BK7
SA_DQ29
SA_DQS#6
SB_DQ28
SB_DQS#5
DDR_A_D30
DDR_A_DQS#7
DDR_B_D29
DDR_B_DQS#6
AV38
AP2
BJ40
BF2
SA_DQ30
SA_DQS#7
SB_DQ29
SB_DQS#6
DDR_A_D31
DDR_A_MA[0 14]
DDR_B_D30
DDR_B_DQS#7
AT38
BL35
AV3
SA_DQ31
DDR_A_MA[0
14]
15
SB_DQ30
SB_DQS#7
DDR_A_D32
DDR_A_MA0
DDR_B_D31
DDR_B_MA[0 14]
AV13
BJ19
BK37
SA_DQ32
SA_MA0
SB_DQ31
DDR_A_D33
DDR_A_MA1
DDR_B_D32
DDR_B_MA0
AT13
BD20
BK13
BC18
SA_DQ33
SA_MA1
SB_DQ32
SB_MA0
DDR_A_D34
DDR_A_MA2
DDR_B_D33
DDR_B_MA1
AW11
BK27
BE11
BG28
SA_DQ34
SA_MA2
SB_DQ33
SB_MA1
DDR_A_D35
DDR_A_MA3
DDR_B_D34
DDR_B_MA2
AV11
BH28
BK11
BG25
SA_DQ35
SA_MA3
SB_DQ34
SB_MA2
DDR_A_D36
DDR_A_MA4
DDR_B_D35
DDR_B_MA3
AU15
BL24
BC11
AW17
SA_DQ36
SA_MA4
SB_DQ35
SB_MA3
DDR_A_D37
DDR_A_MA5
DDR_B_D36
DDR_B_MA4
AT11
BK28
BC13
BF25
SA_DQ37
SA_MA5
SB_DQ36
SB_MA4
DDR_A_D38
DDR_A_MA6
DDR_B_D37
DDR_B_MA5
BA13
BJ27
BE12
BE25
SA_DQ38
SA_MA6
SB_DQ37
SB_MA5
DDR_A_D39
DDR_A_MA7
DDR_B_D38
DDR_B_MA6
BA11
BJ25
BC12
BA29
SA_DQ39
SA_MA7
SB_DQ38
SB_MA6
DDR_A_D40
DDR_A_MA8
DDR_B_D39
DDR_B_MA7
BE10
BL28
BG12
BC28
SA_DQ40
SA_MA8
SB_DQ39
SB_MA7
DDR_A_D41
DDR_A_MA9
DDR_B_D40
DDR_B_MA8
BD10
BA28
BJ10
AY28
SA_DQ41
SA_MA9
SB_DQ40
SB_MA8
DDR_A_D42
DDR_A_MA10
DDR_B_D41
DDR_B_MA9
BD8
BC19
BL9
BD37
SA_DQ42
SA_MA10
SB_DQ41
SB_MA9
DDR_A_D43
DDR_A_MA11
DDR_B_D42
DDR_B_MA10
AY9
BE28
BK5
BG17
SA_DQ43
SA_MA11
SB_DQ42
SB_MA10
DDR_A_D44
DDR_A_MA12
DDR_B_D43
DDR_B_MA11
BG10
BG30
BL5
BE37
SA_DQ44
SA_MA12
SB_DQ43
SB_MA11
DDR_A_D45
DDR_A_MA13
DDR_B_D44
DDR_B_MA12
AW9
BJ16
BK9
BA39
SA_DQ45
SA_MA13
SB_DQ44
SB_MA12
DDR_A_D46
DDR_A_MA14
DDR_B_D45
DDR_B_MA13
BD7
BJ29
BK10
BG13
SA_DQ46
SA_MA14
SB_DQ45
SB_MA13
DDR_A_D47
DDR_B_D46
DDR_B_MA14
BB9
BJ8
BE24
SA_DQ47
SB_DQ46
SB_MA14
DDR_A_D48
DDR_A_RAS#
DDR_B_D47
BB5
BE18
BJ6
SA_DQ48
SA_RAS#
DDR_A_RAS#
15
SB_DQ47
DDR_A_D49
M_A_RCVEN#
DDR_B_D48
DDR_B_RAS#
AY7
AY20
1
BF4
AV16
SA_DQ49
SA_RCVEN#
SB_DQ48
SB_RAS#
DDR_B_RAS#
16
DDR_A_D50
TP6TP6
DDR_B_D49
M_B_RCVEN#
AT5
BH5
AY18
1
SA_DQ50
SB_DQ49
SB_RCVEN#
DDR_A_D51
DDR_A_WE#
DDR_B_D50
TP5TP5
AT7
BA19
BG1
SA_DQ51
SA_WE#
DDR_A_WE#
15
SB_DQ50
DDR_A_D52
DDR_B_D51
DDR_B_WE#
AY6
BC2
BC17
SA_DQ52
SB_DQ51
SB_WE#
DDR_B_WE#
16
DDR_A_D53
DDR_B_D52
BB7
BK3
SA_DQ53
SB_DQ52
DDR_A_D54
DDR_B_D53
AR5
BE4
SA_DQ54
SB_DQ53
DDR_A_D55
DDR_B_D54
AR8
BD3
SA_DQ55
SB_DQ54
DDR_A_D56
DDR_B_D55
AR9
BJ2
SA_DQ56
SB_DQ55
DDR_A_D57
DDR_B_D56
AN3
BA3
SA_DQ57
SB_DQ56
DDR_A_D58
DDR_B_D57
AM8
BB3
SA_DQ58
SB_DQ57
DDR_A_D59
DDR_B_D58
AN10
AR1
SA_DQ59
SB_DQ58
DDR_A_D60
DDR_B_D59
AT9
AT3
SA_DQ60
SB_DQ59
DDR_A_D61
DDR_B_D60
AN9
AY2
SA_DQ61
SB_DQ60
DDR_A_D62
DDR_B_D61
AM9
AY3
SA_DQ62
SB_DQ61
DDR_A_D63
DDR_B_D62
AN11
AU2
SA_DQ63
SB_DQ62
DDR_B_D63
AT2
SB_DQ63
CRESTLINE-GP-U 71.CREST.00U
CRESTLINE-GP-U 71.CREST.00U
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B

CRESTLINE-GP-U 71.CREST.00U

CRESTLINE-GP-U 71.CREST.00U

DDR_B_BS[0

DDR_B_CAS#

DDR_B_DM[0

DDR_B_DQS[0

DDR_B_DQS#[0

DDR_B_MA[0

14]

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Name> <Variant Name> Title Title Title Size Size Size Wistron Corporation Wistron Corporation

Size

Size

Size

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

Thurman UMA

Thurman UMA

A3

A3

A3

Document Number

Document Number

Document Number

GMCH-DDR (3/6)

GMCH-DDR (3/6)

GMCH-DDR (3/6)

Rev

Rev

Rev

-1

-1

-1

Date:

Date:

Date:

Wednesday, November 07, 2007