UNIVERSIDADE FEDERAL DO CEARÁ – CAMPUS SOBRAL

CURSO DE ENGENHARIA ELÉTRICA

DISCIPLINA: MICROPROCESSDORES
PROFESSOR: MARCELO M. S. SOUZA

ATIVIDADE DE MICROPROCESSADORES

JOÃO PEDRO DA SILVA RODRIGUES – 385518

SOBRAL – CE
2019
 Sumário
INTRODUÇÃO ................................................................................................................ 4
OBJETIVO: ...................................................................................................................... 5
SOFTWARES UTILIZADOS: ........................................................................................ 5
EXERCÍCIOS ................................................................... Erro! Indicador não definido.
PARTE 2 ........................................................................................................................ 16
CONCLUSÃO ................................................................................................................ 25
REFERÊNCIAS BIBLIOGRÁFICAS ........................................................................... 26
OBJETIVO:
• Desenvolver atividades de programação na linguagem Assembler para o
microcontrolador PIC18F4550.
SOFTWARES UTILIZADOS:
• Mplab IDE v8.92;
• Proteus versão 8.0.
INTRODUÇÃO

Microcontrolador PIC18F4550 faz parte da popular família de microcontroladores

série PIC18F, possui alto valor de memória RAM e Flash o que o torna ideal para para
aplicações de monitoramento onde é exigido conexões com computadores de forma
periódica para fazer upload, downloads de dados e atualizações de firmware.

Figura 1

Fonte: <http://www.institutodigital.com.br/pd-637642-microcontrolador-pic18f4550.html>
OBJETIVO:
• Desenvolver códigos no microcontrolador PIC18f4550.

SOFTWARES UTILIZADOS:
• Mplab X IDE versão 3.55;
• Proteus versão 8.0.
EXERCÍCIOS

PARTE 1
O1 - Desenvolva um programa que calcule a soma de duas variáveis de memória de
16 bits armazenando o resultado em uma terceira variável, também de 16 bits.
Código:

; PIC18F4550 Configuration Bit Settings

; Assembly source line config statements

#include "p18f4550.inc"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler
Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src:
/2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used
in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source
comes directly from the primary oscillator block with no
postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT
oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable
bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator
Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit
(PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits
(Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits
(Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable
bit (USB voltage regulator disabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT
disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale
Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2
input/output is multiplexed with RC1)
 CONFIG PBADEN = ON ; PORTB A/D Enable bit
(PORTB<4:0> pins are configured as analog input channels on
Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator
Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin
enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset
Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit
(Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit
Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set
Enable bit (Instruction set extension and Indexed Addressing
mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0
(000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1
(002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2
(004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3
(006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit
(Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection
bit (Data EEPROM is not code-protected)

; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0
(000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1
(002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2
(004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3
(006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write
Protection bit (Configuration registers (300000-3000FFh) are not
write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection
bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection
bit (Data EEPROM is not write-protected)

; CONFIG7L
 CONFIG EBTR0 = OFF ; Table Read Protection bit
(Block 0 (000800-001FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit
(Block 1 (002000-003FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit
(Block 2 (004000-005FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit
(Block 3 (006000-007FFFh) is not protected from table reads
executed in other blocks)

; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read
Protection bit (Boot block (000000-0007FFh) is not protected
from table reads executed in other blocks)

; TODO INSERT CONFIG CODE HERE USING CONFIG BITS GENERATOR

VARS UDATA_ACS 0x0000

L1 equ 0x0008 ;definido posição de memória 0x0009 como L1
L2 equ 0x0003 ;definido posição de memória 0x0004 como L2
soma equ 0x0020; definido posição de memória 0x0010 como soma

RES_VECT CODE 0x0000 ; processor reset vector

GOTO START ; go to beginning of program

; TODO ADD INTERRUPTS HERE IF USED

;início do exercicio 1 da atividade individual

MAIN_PROG CODE ; let linker place main

program

START
movlw .5 ; w recebe o valor 4 em decimal
movwf L1 ; L1 recebe o valor de w
movlw .13 ; w recebe o valor 10 em decimal
movwf L1+1 ; a variável logo após L1 recebe o valor de w
movlw .9 ;recebe o valor 4 em decimal
movwf L2; L2 recebe o valor de w
movlw .6; w recebe o valor 6 em decimal
movwf L2+1; a variável logo após L2 recebe o valor de w
movf L1+1,w ; L1+1 vai para w,ou w recebe L1+1
addwf L2+1,w; a variável logo após L2 recebe o valor de w
movwf soma+1; soma+1 recebe w
movf L1,w; L1 vai para w,ou w recebe L1
addwfc L2,w; w recebe soma L2 + w + Cy
movwf soma; recebe valor de w

GOTO $ ; loop forever

END
Abaixo o resultado obtido,
Figura 2

Fonte: autor.

02 - Desenvolva um programa que conte a quantidade de bits “1” existentes em uma

variável de memória de 8 bits guardando o resultado em outra variável de memória
também de 8 bits.
Encontra-se abaixo o código do exercício 2:
; TODO INSERT CONFIG CODE HERE USING CONFIG BITS GENERATOR
#include "p18f4550.inc"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler
Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src:
/2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used
in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source
comes directly from the primary oscillator block with no
postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT
oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable
bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator
Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit
(PWRT disabled)
 CONFIG BOR = ON ; Brown-out Reset Enable bits
(Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits
(Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable
bit (USB voltage regulator disabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT
disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale
Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2
input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit
(PORTB<4:0> pins are configured as analog input channels on
Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator
Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin
enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset
Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit
(Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit
Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set
Enable bit (Instruction set extension and Indexed Addressing
mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0
(000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1
(002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2
(004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3
(006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit
(Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection
bit (Data EEPROM is not code-protected)

; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0
(000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1
(002000-003FFFh) is not write-protected)
 CONFIG WRT2 = OFF ; Write Protection bit (Block 2
(004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3
(006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write
Protection bit (Configuration registers (300000-3000FFh) are not
write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection
bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection
bit (Data EEPROM is not write-protected)

; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit
(Block 0 (000800-001FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit
(Block 1 (002000-003FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit
(Block 2 (004000-005FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit
(Block 3 (006000-007FFFh) is not protected from table reads
executed in other blocks)

; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read
Protection bit (Boot block (000000-0007FFh) is not protected
from table reads executed in other blocks)

;Definição da posição das variaveis

NO equ 0x00 ;Numero NO
CONT equ 0x01 ;Contador

RES_VECT CODE 0x0000 ; processor reset vector

GOTO START ; go to beginning of
program
;início do exercicio 2 da atividade individual
START

;Definindo os valores p/as variaveis NA e CONT

MOVLW b'11001000' ;Move o numero de 8 bits para W
MOVWF NO ;Move o numero de 8 bits do W p/ NO

MOVLW b'00000000' ;Move o numero de 8 bits para W

MOVWF CONT ;Move o numero de 8 bits do W p/ a variavel CONT

;BTFSC=Testar se o bit está em 0 ou 1

; Se for zero pula para a próxima linha
BTFSC NO,0 ; Verificando o bit
;INCFSZ=De maneira geral, incrementa f, guardando o resultado em
d
;E pula a próxima linha caso o valor seja for zero
;10001011

INCFSZ CONT ;Incrementa CONT

BTFSC NO,1 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,2 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,3 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,4 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,5 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,6 ;Verificando o bit, se é 0 ou 1

INCFSZ CONT ;Incrementa CONT

BTFSC NO,7 ;Verificando o bit , se é 0 ou 1

GOTO $ ; loop

END

Abaixo o código compilado no MPLAB.

Figura 3

Fonte: autor
03 - Desenvolva um programa que calcule a soma dos 4 bits mais significativos e dos
4 bits menos significativos de uma variável de memória de 8 bits. O resultado da
soma deve ser armazenado em outra variável de memória de 8 bits.
Código:

; PIC18F4550 Configuration Bit Settings

; Assembly source line config statements

#include "p18f4550.inc"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler
Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src:
/2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used
in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source
comes directly from the primary oscillator block with no
postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT
oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable
bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator
Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit
(PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits
(Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits
(Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable
bit (USB voltage regulator disabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT
disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale
Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2
input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit
(PORTB<4:0> pins are configured as analog input channels on
Reset)
 CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator
Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin
enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset
Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit
(Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit
Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set
Enable bit (Instruction set extension and Indexed Addressing
mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0
(000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1
(002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2
(004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3
(006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit
(Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection
bit (Data EEPROM is not code-protected)

; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0
(000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1
(002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2
(004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3
(006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write
Protection bit (Configuration registers (300000-3000FFh) are not
write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection
bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection
bit (Data EEPROM is not write-protected)

; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit
(Block 0 (000800-001FFFh) is not protected from table reads
executed in other blocks)
 CONFIG EBTR1 = OFF ; Table Read Protection bit
(Block 1 (002000-003FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit
(Block 2 (004000-005FFFh) is not protected from table reads
executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit
(Block 3 (006000-007FFFh) is not protected from table reads
executed in other blocks)

; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read
Protection bit (Boot block (000000-0007FFh) is not protected
from table reads executed in other blocks)

VARS UDATA_ACS 0x000

B RES 2
K RES 2

RES_VECT CODE 0x0000 ; processor reset vector

GOTO START ; go to beginning of program

; Esta é a questão 3 da Parte 1 do trabalho.

MAIN_PROG CODE
START
; Os endereços foram escolhidos aleatoriamente e
representados em base decimal.

MOVLW .7 ; Move valor armazenado no endereço 7 para W.

MOVWF B ; Move valor de W para B.

MOVLW .1 ; Move valor armazenado no endereço 1 para W.

MOVWF B+1 ; Move valor de W para B+1.

MOVLW .11 ; Move valor armazenado no endereço 11 para W.

MOVWF K ; Move valor de W para K.

MOVLW .20 ; Move valor armazenado no endereço 20 para W.

MOVWF K+1 ; Move valor de W para K+1.

MOVF B, W ; Move valor de B para W.

ANDLW .20 ; Operação AND entre W e o número.
MOVWF B+1 ; Move valor de W para B+1.
SWAPF B ; Faz troca dos bits mais significativos e os
bits menos significativos.
MOVF B, W ; Move valor de B para W.
ANDLW .20 ; Operação AND entre W e o número.
MOVWF K ; Move valor de W para K.
MOVF B+1, W ; Move valor de B+1 para W.
ADDWF B, W ; Realiza a soma entre K E W, e armazena
resultado em W.
MOVWF K+1 ; Move valor de W para K+1.

GOTO $ ; loop forever

END
Figura 4

Fonte: autor.

PARTE 2

2.1
Desenvolva um projeto no MPLABX para gerar, em três pinos de E/S distintos do
PIC18F4550, as formas de onda apresentadas no trabalho.
A constante T é definida pela fórmula:

Sendo N o último dígito de seu número de matrícula.

N=8 nesse caso, logo, T=800 us para N > 0.
Código
; PIC18F4550 Configuration Bit Settings

; Assembly source line config statements

#include "p18f4550.inc"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler
Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src:
/2])
 CONFIG USBDIV = 1 ; USB Clock Selection bit (used
in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source
comes directly from the primary oscillator block with no
postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT
oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable
bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator
Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit
(PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits
(Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits
(Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable
bit (USB voltage regulator disabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT
disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale
Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2
input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit
(PORTB<4:0> pins are configured as analog input channels on
Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator
Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin
enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset
Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit
(Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit
Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set
Enable bit (Instruction set extension and Indexed Addressing
mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0
(000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1
(002000-003FFFh) is not code-protected)
 CONFIG CP2 = OFF ; Code Protection bit (Block 2
(004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3
(006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit
(Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection
bit (Data EEPROM is not code-protected)

; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0
(000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1
(002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2
(004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3
(006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write
Protection bit (Configuration registers (300000-3000FFh) are not
write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection
bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection
bit (Data EEPROM is not write-protected)

; CONFIG7L
CONFIG EBTR0 = OFF
(Block 0 (000800-001FFFh)
executed in other blocks)
CONFIG EBTR1 = OFF
(Block 1 (002000-003FFFh)
executed in other blocks)
CONFIG EBTR2 = OFF
(Block 2 (004000-005FFFh)
executed in other blocks)
CONFIG EBTR3 = OFF
(Block 3 (006000-007FFFh)
executed in other blocks)
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads

; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read
Protection bit (Boot block (000000-0007FFh) is not protected
from table reads executed in other blocks)
RES_VECT CODE 0x0000 ; processor reset vector
GOTO START ; go to beginning of program

MAIN_PROG CODE ; let linker place main

program
;Joaquim Osterwald Frota Moura Filho
START;inicio do programa.
 MOVLW b'00000000'; organiza os endereços que serão
utilizados do micro.
MOVWF TRISD
MOVLW b'11101011'
MOVWF PORTD

LOOP
bsf PORTD, RD0 ; RD0,RD2,RD4, são as portas do micro que
serão conectados o gerador de onda.
bcf PORTD, RD2
bcf PORTD, RD4
call onda800us ; chamada da onda quadrada com tempo T de
800us.
bcf PORTD, RD0 ;
bsf PORTD, RD2
call onda800us ;
bsf PORTD, RD4; gerar as três ondas pedidas na questão.
bcf PORTD, RD2
call onda800us

GOTO LOOP ; um loop infinito no programa.

CONTA_ATRASO equ 0x00 ; função para a realização dos

atrasos das ondas.

onda800us

movlw .56
movwf CONTA_ATRASO

rep1
nop ;
nop
nop
nop
decfsz CONTA_ATRASO ;
bra rep1 ;
return ;

END;

Figura 5
Fonte:autor.

Figura 6

Fonte:autor

2.1
Desenvolva um cronômetro regressivo de minutos. Esse cronômetro deve iniciar
sem contar com um valor inicial de contagem de 60 minutos, sendo esta
configurável em incrementos, de 10 em 10 minutos, a cada acionamento de um dos
botões. A contagem inicia pelo acionamento do outro botão e não poderá mais ser
ajustada e nem parada. Ao término da contagem, um buzzer de alarme deve ser
acionado emitindo um beep de duração de 250 milisegundos a cada 1 segundo.
Nessa ocasião o alarme será interrompido se quaisquer das teclas for acionada,
levando assim o cronômetro ao seu estado inicial: contagem parada, alarme
desativado e contagem inicial de 60 minutos.
Código:

; TODO INSERT CONFIG CODE HERE USING CONFIG BITS GENERATOR

#include "p18f4550.inc"

; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits
(No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler
Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src:
/2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used
in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source
comes directly from the primary oscillator block with no
postscale)

; CONFIG1H
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT
oscillator (XT))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable
bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator
Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit
(PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits
(Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits
(Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable
bit (USB voltage regulator disabled)

; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT
disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale
Select bits (1:32768)

; CONFIG3H
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2
input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit
(PORTB<4:0> pins are configured as analog input channels on
Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator
Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin
enabled; RE3 input pin disabled)

; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset
Enable bit (Stack full/underflow will cause Reset)
 CONFIG LVP = OFF ; Single-Supply ICSP Enable bit
(Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit
Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set
Enable bit (Instruction set extension and Indexed Addressing
mode disabled (Legacy mode))

; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0
(000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1
(002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2
(004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3
(006000-007FFFh) is not code-protected)

; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit
(Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection
bit (Data EEPROM is not code-protected)

; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0
(000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1
(002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2
(004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3
(006000-007FFFh) is not write-protected)

; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write
Protection bit (Configuration registers (300000-3000FFh) are not
write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection
bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection
bit (Data EEPROM is not write-protected)

; CONFIG7L
CONFIG EBTR0 = OFF
(Block 0 (000800-001FFFh)
executed in other blocks)
CONFIG EBTR1 = OFF
(Block 1 (002000-003FFFh)
executed in other blocks)
CONFIG EBTR2 = OFF
(Block 2 (004000-005FFFh)
executed in other blocks)
CONFIG EBTR3 = OFF
(Block 3 (006000-007FFFh)
executed in other blocks)
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads
; Table Read Protection bit
is not protected from table reads
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read
Protection bit (Boot block (000000-0007FFh) is not protected
from table reads executed in other blocks)

FLAGS equ 0x00 ; Variável flags no endereço 0x00

CONTAGEM equ 0x01 ; Variável contagem no endereço 0x01
TEMP1 equ 0x02 ; Variável TEMP1 (Atraso)
TEMP2 equ 0x03 ; Variável TEMP2 (Atraso)

PARADO equ 0 ; Bit 0 da variavel FLAGS

SW0 equ 0 ; Push button RC0
SW1 equ 1 ; Push button RC1

RES_VECT CODE 0x0000 ; processor reset vector

GOTO START ; go to beginning of program

MAIN_PROG CODE ; let linker place main program

START
clrf CONTAGEM ; Zera variavel CONTAGEM
bsf FLAGS,PARADO ; Flag PARADO <- TRUE
clrf TRISC ; TRISC <- 00000000 (DISPLAYS)
bsf TRISD,SW0 ; RDO entrada (SW0)
bsf TRISD,SW1 ; RD1 entrada (SW1)
clrf PORTC ; Mostra 00 no display
LOOP
btfss PORTD,SW0
bra EVENTO_SW0
btfss PORTD,SW1
btg FLAGS,PARADO ; Complementa estado da flag parado
bra TESTA_FLAG

EVENTO_SW0
clrf CONTAGEM ; ZERA CONTAGEM
bsf FLAGS,PARADO ; PARA A CONTAGEM
clrf PORTC

TESTA_FLAG
btfsc FLAGS,PARADO
bra ATRASO
incf CONTAGEM,w
daw
movwf CONTAGEM
movwf PORTC
ATRASO
rcall ATRASO_1s ;
GOTO LOOP ; loop forever

;***************************************************************
****************
; Rotina ATRASO_1s
; Gera um atraso correspondente a 1 segundo
; para o microcontrolador operando a um clock
; de 4MHz
;***************************************************************
****************

ATRASO_1s
MOVLW .200
MOVWF TEMP2
L1
RCALL ATRASO_1ms
RCALL ATRASO_1ms
RCALL ATRASO_1ms
RCALL ATRASO_1ms
RCALL ATRASO_1ms
DECFSZ TEMP2
BRA L1
RETURN

;***************************************************************
****************
; Rotina ATRASO
; Gera um atraso correspondente a 1 ms
; para o microcontrolador operando a um clock
; de 4MHz
;***************************************************************
****************

ATRASO_1ms
MOVLW .100 ; Executa
MOVWF TEMP1
LOOP2
NOP
NOP
NOP
NOP
NOP
DECFSZ TEMP1
BRA LOOP2
RETURN
END
Figura 7

Fonte: Autor

CONCLUSÃO

Assim, estão presentes neste relatório o código fonte e a solução de todos os exercícios
propotos. Estão presentes também as simulações feitas no Proteus da parte 2 das
atividades propostas.
REFERÊNCIAS BIBLIOGRÁFICAS

Microcontrolador PIC18F4550. Instituto Digital. Disponível em:<

http://www.institutodigital.com.br/pd-637642-microcontrolador-pic18f4550.html>.
Acessado em: 30 de outubro de 2019.