5

BMW Z4 14" Schematics Document

Ivy/Sandy Bridge
Panther Point

.co

2012-04-02
REV : A00

se
fix

w
w
w

.ro

DY : None Installed
UMA: UMA only installed
SG: PX solution installed.
B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cover Page
5

Size
A3

Document Number

Date:

Monday, April 02, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

CHARGER
40
BQ24727
OUTPUTS
INPUTS

Project Code: 91.4UV01.001

PCB P/N
: 48.4SB02.011
Revision
: 11289-1

Block Diagram
(Discrete / UMA)

AD+

BT+

SYSTEM DC/DC
TPS51125RGER 41
INPUTS
OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5
15V_S5

DCBATOUT

CPU DC/DC

Intel CPU
Ivy / Sandy Bridge

DDRIII 1600MHz Channel A

17W
VRAM(GDDR5)
128M x 16b x 4(1GB)

AMD

GDDR5

PCIe x 8

DDRIII 1600MHz Channel B

Thames Pro

88,89

DDRIII
Slot A
1600MHz

14

DDRIII
Slot B
1600MHz

15

5V_S5

VCC_CORE

GFX DC/DC
VT1318+VT1323 44
INPUTS
OUTPUTS
5V_S5

VCC_GFXCORE

SYSTEM DC/DC

BGA1023

83.84,85,86,87

VT1318+VT1326 42,43
INPUTS
OUTPUTS

VT386
INPUTS
OUTPUTS

4,5,6,7,8,9,10

5V_S5

1D05V_PCH
VCCP_CPU

FDIx4x2

45

DMIx4

SYSTEM DC/DC
HDMI

51

LCD

49

TMDS

Intel

*1

PCIE x 1

USB2.0 x 1

PCH
Panther Point

VT385(DIS)/RT9026
VT386(UMA)/RT9026

26

Mini-Card
USB2.0 x 1 SATA GENIII x 1

WWAN

49

14 USB 2.0/1.1 ports

59

Codec
IDT
92HD94

HDA

PCIE x 1

0D85_S0

VCCP_CPU

VGA DC/DC

6 SATA ports

INPUTS

8 PCIE ports

92
VT358
OUTPUTS

5V_S5

LPC I/F

2CH Speaker
( 2W, 4ohm /channel )

ACPI 4.0a
Left side

1D8V_S0

48
APL5916
INPUTS
OUTPUTS

Combo Jack

High Definition Audio

31

VGA_CORE

VGA DC/DC
93
APL5930
INPUTS
OUTPUTS
26

USB3.0 x 1

1D5V_S3

USB3.0 / PowerShare

USB3.0 x 1

USB PowerShare
TI
62
TPS2541A

62

USB2.0 x 1

Right side

USB3.0 Redriver
TI
SN65LVPE502RGER

1D5V_S3
5V_S5
3D3V_S5
3D3V_S5
3D3V_S5
1D8V_S0
1D5V_S3

USB 3.0

USB2.0 x 1

LPC BUS

USB2.0 x 1

71
17,18,19,20,21,22,23,24,25

CardReader
Realtek
RTS5179

Connector
SD/SDHC/SDXC/SD UHS-I
MMC/MMC+, MS/MS Pro

Fan Control
GMT
G991P11U 28

SMBUS

L1:Top
L2:GND
L3:Signal
L4:Signal

SATA GenIII x 1

HDD

56

SATA GenII x 1

ODD

56

KBC

L5:VCC
L6:Signal
L7:GND
L8:Bottom

SPI

NUVOTON
NPCE885P
27

Flash ROM
60
8MB

PS2

Int.
KB69

1D5V_S0
5V_S0
3D3V_S0
3D3V_WLAN_AOAC
3D3V_VGA_S0
1D8V_VGA_S0
1D5V_VGA_S0

UMA/Discrete
PCB LAYER

Thermal
NUVOTON
NCT7718W 28

1V_VGA_S0

Switches
INPUTS
OUTPUTS

Debug Port

LPC debug port

SYSTEM DC/DC

4 USB 3.0 ports

RJ45

SYSTEM DC/DC

3D3V_S5

Daughter Board

Internal Digital MIC

10/100 Lan
ATHEROS
AR8162

66

HM77

USB2.0 x 1

OUTPUTS
1D5V_S3
0D75V_S0
DDR_VREF_S3 46

47
RT8068A
INPUTS
OUTPUTS

SIM

mSATA
66

Camera

INPUTS

65

DCBATOUT

LVDS

BGA989

Mini-Card
802.11a/b/g/n
BT V4.0 combo

Touch
PAD69

I 2C

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

*1: Transition minimized differential signaling

5

Block Diagram

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

PCH Strapping

Name

SPKR

B
Chief River Schematic Checklist Rev.0_72
Schematics Notes

Pin Name

The signal has a weak internal pull-down.

If the signal is sampled high, this indicates that the system is strapped to the
"No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature).

Configuration

Weak internal pull-up. Leave as "No Connect".

INTVRMEN

Integrated 1 V VRMs is enabled when high, External when low.

GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51

GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.

DF_TVS

DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms 5% resistor.

HAD_DOCK_EN#
/GPIO[33]

This signal controls the external Intel HD Audio docking isolation logic. This is
an active-low-signal. When deasserted the external docking switch is in isolate mode.
When asserted the external docking switch electrically connects the Intel HD Audio
dock signals to the corresponding Panther Point signals. This signal can instead
be used as GPIO33.

Sandy Bridge + Ivy Bridge DDR3 VREF, M1 and M3 function are required.
DDR3 VREF
No change.

PROC_SELECT#
&
DF_TVS

VCCIO_SEL

No change.

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no
Sandy Bridge + Ivy Bridge longer a need for a separate VR for the processor at 1.0 V and
the PCH at 1.05 V. A single VR may be shared for both.
No change.

Ivy Bridge
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

GPIO15

Low (0)
Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High (1)
Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Sandy Bridge + Ivy Bridge VCCSA[0:1] are the select pin of VCCSA's power control.
VCCSA_VID[0:1]
No change.

Ivy Bridge

3
Power Plane

Processor Strapping

Power Plane

Voltage

5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
1V_S0
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0

5V
3.3V
1.8V
1.5V
1.05V
1V
0.85V
0.75V
0.3V to 1.3V
0 to 1.25V
1.8V
3.3V
1V

Actice Status

Description

Chief River Schematic Checklist Rev.0_72

Pin Name

Strap Description

Configuration (Default value for each bit is

1 unless specified otherwise)

CFG[2]

PCI-Express Static
Lane Reversal

1:
0:
1:

CFG[4]

S0

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor

Sandy Bridge + Ivy Bridge through a 1K5% series resistor. PROC_SELECT# also needs a 2.2K5%
pull up resistor to PCH VccDFTERM rail.
Ivy Bridge

HDA_SDO

E
Chief River Schematic Checklist Rev.0_xx

Schematic Notes

Ivy Bridge
INIT3_3V#

Sandy & Ivy Bridge Compatibility

CPU Core Rail

Graphics Core Rail

0:
CFG[6:5]

PCI-Express
Port Bifurcation
Straps

Normal Operation.
Lane Numbers Reversed

Default
Value

15 -> 0, 14 -> 1, ...

Disabled - No Physical Display Port attached to

Embedded DisplayPort.
Enabled - An external Display Port device is
connectd to the EMBEDDED display Port

POP
Value

11

10

11: 1x16 PCI Express

10: 2 x8 - PCI Express
01: Reserved
00: 1x8, 2x4 PCI Express

2
5V_USBX_S3
1D5V_S3
DDR_VREF_S3

5V
1.5V
0.75V

BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5

6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V

3D3V_LAN_S5
3D3V_AUX_KBC

3D3V_AUX_S5

3.3V
3.3V

3.3V

S3

USB Table

All S states

WOL_EN
DSW, Sx

G3, Sx

AC Brick Mode only

Legacy WOL
ON for supporting
Deep Sleep states
Powered by Li Coin Cell
in G3 and +V3ALW in Sx

PCIE Table

SATA Table

Pair

Device

USB3.0 port1, with Power Share

USB3.0 port2, debug port

NC

NC

Touch Panel

NC

NC

NC

WWAN

NC

10

Card reader

11

WLAN

Wistron Corporation

12

CAMERA

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

13

NC

PCIE
Lane

SATA

Device

Pair

Device

NC

HDD1

NC

mSATA

NC

NC

WLAN

NC

NC

ODD

Onboard LAN

NC

NC

NC

DMB40

Title

Table of Content

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet

of

105

SSID = CPU

Layout Note:
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

D
VCCP_CPU
1 OF 9

CPU1A

Layout Note:

[19] DMI_TXP[3:0]

[19] DMI_RXN[3:0]

[19] DMI_RXP[3:0]

[19] FDI_TXN[7:0]

C
Layout Note:
FDI trace length 2000~6500mil

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

K1
M8
N4
R2

DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

K3
M7
P4
T3

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

U7
W11
W1
AA6
W6
V4
Y2
AC9

FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

U6
W10
W3
AA7
W7
T4
AA3
AC8

FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3

U11

FDI_LSYNC0 AA10
FDI_LSYNC1 AG8

[19] FDI_LSYNC0
[19] FDI_LSYNC1

R402 1

N3
P7
P3
P11

FDI_INT

[19] FDI_INT

VCCP_CPU

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

FDI_FSYNC0 AA11
FDI_FSYNC1 AC12

[19] FDI_FSYNC0
[19] FDI_FSYNC1

DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3

2 24D9R2F-L-GP

DP_COMP

Layout Note:

FDI_INT
FDI0_LSYNC
FDI1_LSYNC

EDP_COMPIO
EDP_ICOMPO
EDP_HPD#

AG4
AF4

EDP_AUX#
EDP_AUX

AC3
AC4
AE11
AE7

EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3

AC1
AA4
AE10
AE6

EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
IVY-BRIDGE-GP-NF

71.00IVY.A0U

eDP

Signal Routing Guideline:

EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

AF3
AD2
AG11

FDI0_FSYNC
FDI1_FSYNC

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

Intel(R) FDI

[19] FDI_TXP[7:0]

M2
P6
P1
P10

DMI

DMI trace length 2000~8000mil

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

PCI EXPRESS -- GRAPHICS

[19] DMI_TXN[3:0]

G3
G1
G4

PEG_IRCOMP_R

R401

2 24D9R2F-L-GP

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0

1
SG
1
SG
1
SG
1
SG
1
SG
1
SG
1
SG
1
SG

2
2
2
2
2
2
2
2

C401
C402
C403
C404
C405
C406
C407
C408

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

PEG_TXN[7..0] [83]

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0

1
SG
1
SG
1
SG
1
SG
1
SG
1
SG
1
SG
1
SG

2
2
2
2
2
2
2
2

C417
C418
C419
C420
C421
C422
C423
C424

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_TXP[7..0] [83]

PEG_RXN[7..0]

PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

[83]

C
PEG_RXP[7..0] [83]

Layout Note:
PEG trace length 1500~9000mil

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(PCIE/DMI/FDI)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet

of

105

SSID = CPU

2 OF

SKTOCC#_R

F49
C57

PROC_SELECT#
PROC_DETECT#

VCCP_CPU
TPAD14-OP-GP

TP502

C49

CATERR#

H_PECI

A48

PECI

H_PROCHOT#_R

C45

PROCHOT#

H_THERMTRIP#

D45

THERMTRIP#

H_PROCHOT#

62R2J-GP

[22,27] H_PECI
R513

[27,40] H_PROCHOT#

56R2J-4-GP
[22] H_THERMTRIP#

THERMAL

H_CATERR#

R501

Layout Note:
R501, R513 place near to CPU

C48

X03 2/6
R504
0R0402-PAD-2-GP
1
2 H_CPUPW RGD_R

[22] H_CPUPW RGD

B46

PM_SYNC

UNCOREPWRGOOD

1 R503
2
10KR2J-3-GP
VDDPW RGOOD

[37] VDDPW RGOOD

BUF_CPU_RST#

R510
1K5R2F-2-GP

D44

RESET#

DY

C501
SC220P50V2KX-3GP

BCLK
BCLK#

J3
H2

CLK_EXP_P
CLK_EXP_N

AG3
AG1

CLK_DP_P_R1
CLK_DP_N_R2

CLK_EXP_P [20]
CLK_EXP_N [20]
RN503

DPLL_REF_CLK
DPLL_REF_CLK#

4
3

VCCP_CPU

SRN1KJ-7-GP

Layout Note:
Checking the connector pin's LAYOUT

SM_DRAMRST#

AT30

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

BF44
BE43
BG43

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

PRDY#
PREQ#

N53
N55

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

L56
L55
J58

XDP_TCLK
XDP_TMS
XDP_TRST#

TDI
TDO

M60
L59

XDP_TDI
XDP_TDO

SM_DRAMRST# [37]
R506 1
R508 1
R511 1

2 140R2F-GP
2 25D5R2F-GP
2 200R2F-L-GP

Layout Note:
XDP_PRDY# [71]
XDP_PREQ# [71]

Signal Routing Guideline:

SM_RCOMP keep routing length less than 500 mils.
Trace width = 15mil

RN501
XDP_TDI
XDP_TMS
XDP_TDO

DBR#

K58

XDP_DBRESET#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

G58
E55
E59
G55
G59
H60
J59
J61

XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7

C
VCCP_CPU

1
2
3
4

XDP_DBRESET# [19]

8
7
6
5

XDP

SRN51J-1-GP
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7

[71]
[71]
[71]
[71]
[71]
[71]
[71]
[71]

RN502
XDP_TRST#
XDP_TCLK

1
2

4
3

XDP

SRN51J-GP

R509
698R2F-GP

PLT_RST#

SM_DRAMPWROK

[18,27,31,65,66,71]

BE45

PWR MANAGEMENT

H_PM_SYNC

[19] H_PM_SYNC

JTAG & BPM

R507
4K99R2F-L-GP
1
2

DDR3
MISC

TP501

MISC

H_SNB_IVB#

[22] H_SNB_IVB#

CLOCKS

CPU1B

TPAD14-OP-GP

IVY-BRIDGE-GP-NF

71.00IVY.A0U

Layout Note:
C501 place near to CPU

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(THERMAL/CLOCK/PM)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet

of

105

SSID = CPU
4 OF 9

CPU1D
3 OF 9

[14] M_A_DQ[63:0]

[15] M_B_DQ[63:0]

M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

[14] M_A_BS0
[14] M_A_BS1
[14] M_A_BS2

BD37
BF36
BA28

SA_BS0
SA_BS1
SA_BS2

[14] M_A_CAS#
[14] M_A_RAS#
[14] M_A_W E#

BE39
BD39
AT41

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK0
SA_CK#0
SA_CKE0

AU36
AV36
AY26

M_A_DIMA_CLK_DDR0 [14]
M_A_DIMA_CLK_DDR#0 [14]
M_A_DIMA_CKE0 [14]

SA_CK1
SA_CK#1
SA_CKE1

AT40
AU40
BB26

M_A_DIMA_CLK_DDR1 [14]
M_A_DIMA_CLK_DDR#1 [14]
M_A_DIMA_CKE1 [14]

SA_CS#0
SA_CS#1

BB40
BC41

M_A_DIMA_CS#0 [14]
M_A_DIMA_CS#1 [14]

SA_ODT0
SA_ODT1

AY40
BA41

M_A_DIMA_ODT0 [14]
M_A_DIMA_ODT1 [14]

SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_B_DQ[63:0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

[15] M_B_BS0
[15] M_B_BS1
[15] M_B_BS2

BG39
BD42
AT22

SB_BS0
SB_BS1
SB_BS2

[15] M_B_CAS#
[15] M_B_RAS#
[15] M_B_W E#

AV43
BF40
BD45

SB_CAS#
SB_RAS#
SB_WE#

M_A_DQS#[7:0] [14]

M_A_DQS[7:0] [14]

M_A_A[15:0] [14]

DDR SYSTEM MEMORY B

CPU1C

SB_CK0
SB_CK#0
SB_CKE0

BA34
AY34
AR22

M_B_DIMB_CLK_DDR0 [15]
M_B_DIMB_CLK_DDR#0 [15]
M_B_DIMB_CKE0 [15]

SB_CK1
SB_CK#1
SB_CKE1

BA36
BB36
BF27

M_B_DIMB_CLK_DDR1 [15]
M_B_DIMB_CLK_DDR#1 [15]
M_B_DIMB_CKE1 [15]

SB_CS#0
SB_CS#1

BE41
BE47

M_B_DIMB_CS#0 [15]
M_B_DIMB_CS#1 [15]

SB_ODT0
SB_ODT1

AT43
BG47

M_B_DIMB_ODT0 [15]
M_B_DIMB_ODT1 [15]

SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQS#[7:0] [15]

M_B_DQS[7:0] [15]

M_B_A[15:0] [15]

IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF

71.00IVY.A0U

71.00IVY.A0U

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (DDR)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

SSID = CPU

TP704
TP705
TP706
TP707
TP708
TP709
TP710
TP711
TP712
TP713
TP714

1
1
1
1
1
1
1
1
1
1
1

TPAD14-OP-GP
TPAD14-OP-GP

TP715
TP716

1VCC_VAL_SENSE
1VSS_VAL_SENSE

H43
K43

VCC_VAL_SENSE
VSS_VAL_SENSE

TPAD14-OP-GP
TPAD14-OP-GP

TP717
TP718

1VAXG_VAL_SENSE
1VSSAXG_VAL_SENSE

H45
K45

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

TPAD14-OP-GP
TPAD14-OP-GP

TP719
TP720

1VCC_DIE_SENSE
1VSS_DIE_SENSE

F48
G48

VCC_DIE_SENSE
RSVD47

H48
K48

RSVD6
RSVD7

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

1
N59
N58

RSVD30
RSVD31
RSVD32
RSVD33

N42
L42
L45
L47

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

M13
M14
U14
W14
P13

RSVD39
RSVD40

AT49
K24

RSVD41
RSVD42
RSVD43
RSVD44

AH2
AG13
AM14
AM15

RSVD45

N50

BCLK_ITP
BCLK_ITP#

1
1

SG

TP721 TPAD14-OP-GP
TP722 TPAD14-OP-GP

1: Disabled; No Physical Display Port

attached to Embedded Display Port

CFG[4]

0: Enabled; An external Display Port device is

connected to the Embedded Display Port

CFG5

CFG6

PCIE Port Bifurcation Straps

R701

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

0:Lane Reversed

Display Port Presence Strap

DY 1KR2J-1-GP SG

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

CFG[2]

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

BCLK_ITP
BCLK_ITP#

1: Normal Operation; Lane #

definition matches socket pin map definition

1
1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

PEG Static Lane Reversal

R702
1KR2J-1-GP

TP_DC_TEST_A4
A4
1
C4
DC_TEST_C4_D3
D3
TP_DC_TEST_D1
D1
1
TP_DC_TEST_A58
A58
1
A59
TP_DC_TEST_A59_C59
C59
A61
TP_DC_TEST_A61_C61
C61
TP_DC_TEST_D61
D61
1
BD61 TP_DC_TEST_BD61 1
BE61
BE59 TP_DC_TEST_BE59_BE61
BG61
BG59 DC_TEST_BG59_BG61
BG58 TP_DC_TEST_BG58 1
TP_DC_TEST_BG4
BG4
1
BG3
DC_TEST_BE3_BG3
BE3
BG1
DC_TEST_BE1_BG1
BE1
TP_DC_TEST_BD1
BD1
1

TP723 TPAD14-OP-GP

R704
1KR2J-1-GP

CFG[6:5]

11: 1x16 PCI Express

10: 2 x8 - PCI Express

TP702
TP703

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

TPAD14-OP-GP
TPAD14-OP-GP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

RESERVED

[71] CFG0
TPAD14-OP-GP TP701

CFG2

5 OF 9

CPU1E

01: Reserved

TP724 TPAD14-OP-GP
TP725 TPAD14-OP-GP

00: 1x8, 2x4 PCI Express

TP726 TPAD14-OP-GP
TP727 TPAD14-OP-GP

TP728 TPAD14-OP-GP
TP729 TPAD14-OP-GP

TP730 TPAD14-OP-GP

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (RESERVED)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

SSID = CPU
CPU1F

POWER

6 OF 9
VCCP_CPU

33

VCCIO

1.05

8.5

VDDQ

1.5

VCCSA

0.9

VCCPLL

1.8

1.2

VCCP_CPU

DY
2

1
2
1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2
1

2
1
1

1
2

1
2

1
2
1
1

1
2
1
2

C873
SC22U6D3V5MX-2GP

2
1
2

C872
SC22U6D3V5MX-2GP

1
2
1

C871
SC22U6D3V5MX-2GP

2
1
2

1
2

PEG IO AND DDR IO

33

0~1.52

W16
W17

BC22

H_SNB_IVB#_PWRCTRL

TP801

TPAD14-OP-GP

X03 2/6
+V1.05S_VCCPQE_R
AM25
AN22

SVID

VIDALERT#
VIDSCLK
VIDSOUT

A44
B43
C44

R812
0R0402-PAD-2-GP
2

VCCP_CPU

VCCP_CPU

Layout Note:

C826
SC1U6D3V2KX-GP

R803, R804, R805 need close to CPU

Alert# signal must be routed between the Clock and Data
lines to reduce the cross talk between them

R804
130R2F-1-GP
2

R805
75R2F-2-GP
R803
43R2J-GP
1
2

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCPQE1
VCCPQE2

QUIET
RAILS

1
C840
SC2D2U6D3V2MX-GP
2

1
2

C829
SC10U6D3V3MX-GP

C827
SC2D2U6D3V2MX-GP

CORE SUPPLY

2
1
C810
SC22U6D3V5MX-2GP
1
2

C820
SC22U6D3V5MX-2GP

2
1
C809
SC22U6D3V5MX-2GP

2
1
C808
SC22U6D3V5MX-2GP
1
2

1
2

C828
SC22U6D3V5MX-2GP

C818
SC22U6D3V5MX-2GP

2
1
C807
SC22U6D3V5MX-2GP

2
1
C806
SC22U6D3V5MX-2GP
C816
SC22U6D3V5MX-2GP

2
1
C805
SC22U6D3V5MX-2GP

C824
SC22U6D3V5MX-2GP

C847
SC22U6D3V5MX-2GP
1

C817
SC10U6D3V5KX-1GP

2
1
C804
SC22U6D3V5MX-2GP
1
2

2
1
C823
SC22U6D3V5MX-2GP
1

C843
SC10U6D3V3MX-GP
2
1

C832
SC22U6D3V5MX-2GP
1

C815
SC10U6D3V5KX-1GP
2
1

C822
SC22U6D3V5MX-2GP

2
1

C813
SC22U6D3V5MX-2GP

C831
SC22U6D3V5MX-2GP
2
1
C814
SC10U6D3V5KX-1GP

2
1
C821
SC22U6D3V5MX-2GP
2

C812
SC22U6D3V5MX-2GP
C830
SC22U6D3V5MX-2GP
2
1

1
2

C803
SC10U6D3V5KX-1GP
2
1

2
1
C801
SC22U6D3V5MX-2GP
1

C811
SC22U6D3V5MX-2GP

2
1

C825
SC22U6D3V5MX-2GP
2
1

2
1
2

Iccmax(A)

SC1U6D3V2KX-GP
C892

C802
SC10U6D3V5KX-1GP

0.3~1.52

SC10U6D3V3MX-GP
C896

SC10U6D3V3MX-GP
C894

SC10U6D3V3MX-GP
C893

DY

SC1U6D3V2KX-GP
C891

DY

Voltage(V)

VCC_CORE(ULV)

SC10U6D3V3MX-GP
C882

DY

Voltage Rail

VAXG(ULV)

SC1U6D3V2KX-GP
C878

SC1U6D3V2KX-GP
C890

SC1U6D3V2KX-GP
C889

DY

SC10U6D3V3MX-GP
C881

SC10U6D3V3MX-GP
C880

DY

SC1U6D3V2KX-GP
C877

DY

DY

SC1U6D3V2KX-GP
C870

DY

SC1U6D3V2KX-GP
C868

DY

SC1U6D3V2KX-GP
C875

SC10U6D3V3MX-GP
C897

DY

DY

SC1U6D3V2KX-GP
C867

SC1U6D3V2KX-GP
C887

VCCIO_SEL

DY

SC10U6D3V3MX-GP
C879

VCCIO50
VCCIO51

DY

SC1U6D3V2KX-GP
C876

DY

DY

SC10U6D3V3MX-GP
C895

DY

DY

SC1U6D3V2KX-GP
C888

DY

DY

SC10U6D3V3MX-GP
C863

DY

DY

SC1U6D3V2KX-GP
C874

DY

DY

SC1U6D3V2KX-GP
C886

DY

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

SC1U6D3V2KX-GP
C884

DY

DY

VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45
VCCIO46
VCCIO47
VCCIO48
VCCIO49

DY

DY

Added, cause the

1.05V far away CPU

SC1U6D3V2KX-GP
C883

DY

DY

DY

SC1U6D3V2KX-GP
C869

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76

SC1U6D3V2KX-GP
C885

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

VCC_CORE

SC1U6D3V2KX-GP
C866

33A

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

SC1U6D3V2KX-GP
C865

VCCIO1
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29

8.5A

VCC_CORE

SC1U6D3V2KX-GP
C864

3/30
12/21
12/16
12/15
12/09

SC1U6D3V2KX-GP
C862

A00
X01
X01
X01
X01

VR_SVID_ALERT# [42]
H_CPU_SVIDCLK [42]
H_CPU_SVIDDAT [42]

Need place Pull Hi

at IMVP page

VCC_CORE

VCCSENSE
VSSSENSE

VCCSENSE [42]
VSSSENSE [42]
VCCP_CPU

R802
100R2F-L1-GP-U

1
AN16
AN17

R807
10R2F-L-GP

VCCIO_SENSE
VSS_SENSE_VCCIO

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

F43
G43

VCCIO_SENSE [45]
VSSIO_SENSE [45]

SENSE LINES

R801
100R2F-L1-GP-U

VCC_SENSE
VSS_SENSE

Layout Note:

IVY-BRIDGE-GP-NF

R806
10R2F-L-GP
2

71.00IVY.A0U

Layout Note:
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (VCC_CORE)
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

SSID = CPU

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

VREF

1.2

DY

1
2
1

1
2
1

1
2

1
2
1

DY

DY
2

DY

DY

DY

DY

1
2

DY

1
1

DY

1
2

DY

X03 2/6

1
BC43
BA43

1D5V_S0

R909
0R0402-PAD-2-GP
2

TP_VDDQ_SENSE
TP_VDDQ_VSS

TP901
TP902

1
1

TPAD14-OP-GP
TPAD14-OP-GP

VCCSA Power Select

Voltage(V)

VCCSA_SENSE

VCCSA_VID0
VCCSA_VID1

U10

D48
D49

VCCSA_SENSE

VCCSA_SEL0
VCCSA_SEL1

VCCSA_SEL0
VCCSA_SEL1

VID[0]

VID[1]

0.9

0.85

0.775

0.75

[48]

[48]
[48]

2
1

QUIET RAILS
SENSE LINES

AM28
AN26

RN901
SRN1KJ-7-GP

3
4

IVY-BRIDGE-GP-NF

VCCDQ1
VCCDQ2

VDDQ_SENSE
VSS_SENSE_VDDQ

VCCSA VID
lines

1.8V RAIL
SA RAIL

1
2
1
2

1
1
2

DY

1
2
1
2
1
2
1
2
1
2

1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2

1
2

- 1.5V RAILS
DDR3

GRAPHICS

2
1
C911
SC22U6D3V5MX-2GP

2
1
C919
SC22U6D3V5MX-2GP
C918
SC1U6D3V2KX-GP

2
1
C905
SC22U6D3V5MX-2GP
2
1
C922
SC22U6D3V5MX-2GP
2
1
C910
SC22U6D3V5MX-2GP
C917
SC1U6D3V2KX-GP
2
1

2
1
C904
SC22U6D3V5MX-2GP
2
1
C921
SC22U6D3V5MX-2GP
2
1
C909
SC22U6D3V5MX-2GP

C916
SC1U6D3V2KX-GP
2
1

C915
SC1U6D3V2KX-GP
2
1

2
1
C903
SC22U6D3V5MX-2GP
2
1
C920
SC22U6D3V5MX-2GP
2
1
C908
SC22U6D3V5MX-2GP
C914
SC1U6D3V2KX-GP
2
1

2
1
C902
SC22U6D3V5MX-2GP
2
1
C923
SC22U6D3V5MX-2GP
2
1
C907
SC22U6D3V5MX-2GP
C913
SC1U6D3V2KX-GP
2
1

2
1
C901
SC22U6D3V5MX-2GP
2
1
C955
SC22U6D3V5MX-2GP
2
1
C906
SC22U6D3V5MX-2GP

1.8

SC10U6D3V3MX-GP
C943

VCCPLL

SC1U6D3V2KX-GP
C953

SC10U6D3V3MX-GP
C942

DY

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16

0.9

SC1U6D3V2KX-GP
C952

DY

VCCPLL1
VCCPLL2
VCCPLL3

1.5

VCCSA

SC10U6D3V3MX-GP
C941

DY

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
SC1U6D3V2KX-GP
C931

DY

DY

SC10U6D3V3MX-GP
C926
SC1U6D3V2KX-GP
C932

DY

SC10U6D3V3MX-GP
C927
SC1U6D3V2KX-GP
C933

DY

SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
C928
C934

SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
C929
C935

SC10U6D3V3MX-GP
C930

DY

DY

SC10U6D3V3MX-GP
C940

6A

SC1U6D3V2KX-GP
C925

0D85V_S0

SC1U6D3V2KX-GP
C924

DY

BB3
BC1
BC4

1.2A

VDDQ

R904
100R2F-L1-GP-U

1D8V_S0

8.5

SC1U6D3V2KX-GP
C954

VAXG_SENSE
VSSAXG_SENSE

33

1.05

SC1U6D3V2KX-GP
C951

DY

+V1.5S_VCCD_Q

F45
G45

33

0~1.52

1D5V_S0

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

SC1U6D3V2KX-GP
C950

VCC_AXG_SENSE
VSS_AXG_SENSE

Iccmax(A)

5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26

R903
100R2F-L1-GP-U

[42] VCC_AXG_SENSE
[42] VSS_AXG_SENSE

0.3~1.52

SC10U6D3V3MX-GP
C939

C912
SC1U6D3V2KX-GP
2
1

DY

SRN1KJ-7-GP

SC1U6D3V2KX-GP
C949

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

Voltage(V)

VCC_CORE(ULV)

VCCIO
2
1

SC10U6D3V3MX-GP
C938

VCC_GFXCORE

Layout Note:

3
4

SC1U6D3V2KX-GP
C948

DY

BE7 DDR_WR_VREFA
BG7 DDR_WR_VREFB

SC10U6D3V3MX-GP
C937

DY

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

SC1U6D3V2KX-GP
C947

DY

RN902

SC10U6D3V3MX-GP
C936

DY

Voltage Rail

VAXG(ULV)

AY43

SC1U6D3V2KX-GP
C946

DY

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VAXG55
VAXG56

SM_VREF

SC1U6D3V2KX-GP
C945

DY

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

SC1U6D3V2KX-GP
C944

DY
C

Layout Note:
7 OF 9

33A

VCC_GFXCORE

POWER

CPU1G

X01 12/15

SENSE
LINES

X01 12/09

71.00IVY.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (VCC_GFXCORE)
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

of

105

SSID = CPU
8 OF 9

CPU1H

9 OF 9

CPU1I

VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180

VSS

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249

VSS

NCTF TEST PIN

A5,A57,BC61,BG5
BG57,C3,E1,E61

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90

NCTF

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59

VSS_NCTF_1#A5
VSS_NCTF_2#A57
VSS_NCTF_3#BC61
VSS_NCTF_8#BG5
VSS_NCTF_9#BG57
VSS_NCTF_10#C3
VSS_NCTF_13#E1
VSS_NCTF_14#E61

A5
A57
BC61
BG5
BG57
C3
E1
E61

VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_11
VSS_NCTF_12

BD3
BD59
BE4
BE58
C58
D59

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

IVY-BRIDGE-GP-NF

71.00IVY.A0U
Title

CPU (VSS)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

10

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

XDP
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

11

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

12

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

13

of

105

X01 12/15
X01 12/02

SSID = MEMORY

DM1

Place these caps

close to VTT1 and
VTT2.

[6] M_A_DQS#[7:0]

[6] M_A_DQS[7:0]
B

[6] M_A_DIMA_ODT0
[6] M_A_DIMA_ODT1
M_VREF_CA_DIMMA
M_VREF_DQ_DIMMA

Layout Note:
All VREF traces should
have width=20mil;
spacing=20 mil

[15,37]

DDR3_DRAMRST#
0D75V_S0

116
120
126
1
30
203
204

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

1
2

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

DY

1D5V_S3

1D5V_S3

DY

DY

X03 2/21

EC1408
SCD1U10V2KX-5GP

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

C1401
SCD1U10V2KX-5GP

EC1407
SCD1U10V2KX-5GP
2

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

SA0_DIMA
SA1_DIMA

EC1406
SCD1U10V2KX-5GP
2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

77
122
125

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

197
201

NC#1
NC#2
NC#/TEST

199

C1405
SC10U6D3V5KX-1GP
2
1

SA0
SA1

PCH_SMBDATA [15,20,65,66,69]
PCH_SMBCLK [15,20,65,66,69]
3D3V_S0

198

C1404
SC10U6D3V5KX-1GP

VDDSPD

200
202

SDA
SCL
EVENT#

11
28
46
63
136
153
170
187

12
29
47
64
137
154
171
188

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_DIMA_CLK_DDR1 [6]
M_A_DIMA_CLK_DDR#1 [6]

10
27
45
62
135
152
169
186

CK1
CK1#

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DIMA_CLK_DDR0 [6]
M_A_DIMA_CLK_DDR#0 [6]

102
104

R1402
0R0402-PAD-2-GP

C1417
SC1U6D3V2KX-GP

Layout Note:

101
103

R1401
0R0402-PAD-2-GP

C1416
SC1U6D3V2KX-GP

1
2

C1418
SC1U6D3V2KX-GP

1
2

DY

C1420
SC1U6D3V2KX-GP

1
2

C1419
SC1U6D3V2KX-GP

0D75V_S0

[6]
[6]

1
2

C1429
SCD1U10V2KX-5GP

1
2

DY

C1423
SC2D2U10V3KX-1GP

C1411
SCD1U10V2KX-5GP

M_VREF_DQ_DIMMA

M_A_DIMA_CKE0
M_A_DIMA_CKE1

Note:
SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

X01 12/20

C1403
SC10U6D3V5KX-1GP
2
1

R1404
0R0402-PAD-2-GP

73
74

SA0_DIMA
SA1_DIMA

Place these caps

close to VREF_DQ

[6]
[6]

Layout Note:

X03 2/6

M_A_DIMA_CS#0
M_A_DIMA_CS#1

C1415
SCD1U10V2KX-5GP

X03 2/16
DDR_VREF_S3

CK0
CK0#

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

114
121

1
2

C1426
SCD1U10V2KX-5GP

1
2

EC1428
SCD1U10V2KX-5GP

C1427
SCD1U10V2KX-5GP

M_VREF_CA_DIMMA

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_A_RAS# [6]
M_A_WE# [6]
M_A_CAS# [6]

Place these caps

close to VREF_CA

R1405
0R0402-PAD-2-GP

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

CKE0
CKE1

110
113
115

TC1401
ST330U2VDM-4-GP

Layout Note:

CS0#
CS1#

NP1
NP2

X03 2/6

NP1
NP2
RAS#
WE#
CAS#

[6] M_A_BS0
[6] M_A_BS1
[6] M_A_DQ[63:0]

DDR_VREF_S3

109
108

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

C1414
SCD1U10V2KX-5GP

[6] M_A_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

[6] M_A_A[15:0]

Layout Note:
Place these Caps near SO-DIMMA.

1D5V_S0

1D5V_S3

DY
C1421
SCD1U10V2KX-5GP
1

2
B

DY
C1424
SCD1U10V2KX-5GP

Layout Note:
For S3 reduction circuit's 1D5V return pass.

DDR3-204P-73-GP

62.10017.U81
2nd = 62.10017.P31
3rd = 62.10017.K11
4th = 62.10017.N91

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM1
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

14

of

105

X01 12/13

SSID = MEMORY

[6] M_B_DQS#[7:0]

[6] M_B_DQS[7:0]
B

M_VREF_CA_DIMMB
M_VREF_DQ_DIMMB

All VREF traces should

have width=20mil;
spacing=20 mil

[14,37]

126
1
30

DDR3_DRAMRST#
0D75V_S0

203
204

3D3V_S0

200
202

PCH_SMBDATA [14,20,65,66,69]
PCH_SMBCLK [14,20,65,66,69]

R1501
10KR2J-3-GP

3D3V_S0

198

197
201

SA0_DIMB
SA1_DIMB

C1501
SCD1U10V2KX-5GP

DY
SA1_DIMB
SA0_DIMB

X01 12/20

1D5V_S3
1

77
122
125

199

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

2
1D5V_S3

X01 01/09

1
2

C1510
SC10U6D3V5KX-1GP

C1509
SC10U6D3V5KX-1GP

1
2

DY

C1508
SC10U6D3V5KX-1GP
2
1

DY

EC1514
SCD1U10V2KX-5GP

DY

DY

C1507
SC10U6D3V5KX-1GP

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

R1502
0R0402-PAD-2-GP

C1513

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

12
29
47
64
137
154
171
188

M_B_DIMB_CLK_DDR1 [6]
M_B_DIMB_CLK_DDR#1 [6]

11
28
46
63
136
153
170
187

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

NC#1
NC#2
NC#/TEST

102
104

C1504
SC10U10V5ZY-1GP

10
27
45
62
135
152
169
186

116
120

[6] M_B_DIMB_ODT0
[6] M_B_DIMB_ODT1

Layout Note:

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SA0
SA1

[6]
[6]

M_B_DIMB_CLK_DDR0 [6]
M_B_DIMB_CLK_DDR#0 [6]

Place these caps

close to VTT1 and
VTT2.

VDDSPD

M_B_DIMB_CKE0
M_B_DIMB_CKE1

101
103

SCD1U10V2KX-5GP
2
1

1
2

C1521
SC1U6D3V2KX-GP

1
2

C1519
SC1U6D3V2KX-GP

1
2

DY

C1518
SC1U6D3V2KX-GP

Layout Note:

SDA
SCL
EVENT#

73
74

Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34

0D75V_S0

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

[6]
[6]

C1512
SCD1U10V2KX-5GP

Place these caps

close to VREF_DQ

C1517
SCD1U10V2KX-5GP

C1516
SC2D2U10V3KX-1GP

2
1
C1515
SCD1U10V2KX-5GP

Layout Note:

M_VREF_DQ_DIMMB

CK1
CK1#

BA0
BA1

M_B_DIMB_CS#0
M_B_DIMB_CS#1

X03 2/6
R1503
0R0402-PAD-2-GP

CK0
CK0#

M_B_RAS# [6]
M_B_WE# [6]
M_B_CAS# [6]

114
121

DDR_VREF_S3

CKE0
CKE1

110
113
115

C1503
SC10U10V5ZY-1GP

X03 2/16

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CS0#
CS1#

NP1
NP2

1
2

C1522
SCD1U10V2KX-5GP

1
2

EC1524
SCD1U10V2KX-5GP

C1523
SCD1U10V2KX-5GP

Layout Note:
Place these caps
close to VREF_CA

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

NP1
NP2
RAS#
WE#
CAS#

M_VREF_CA_DIMMB

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

C1511
SCD1U10V2KX-5GP

109
108

[6] M_B_BS0
[6] M_B_BS1
[6] M_B_DQ[63:0]

R1505
0R0402-PAD-2-GP

DY

[6] M_B_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DDR_VREF_S3

X03 2/6

DM2
[6] M_B_A[15:0]

X01 12/15

X03 02/16

Layout Note:
Place these Caps near SO-DIMMA.

DDR3-204P-75-GP

62.10017.Z81
2nd = 62.10017.N41
3rd = 62.10017.P61
4th = 62.10017.P41

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM2
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

15

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

16

of

105

SSID = PCH

3D3V_S0

[49] L_BKLT_CTRL

SRN2K2J-1-GP

RN1702

L_CTRL_CLK
L_CTRL_DATA

L_BKLT_EN
LVDS_VDD_EN

3
4

P45

L_BKLTCTL

LVDS_IBG
LVDS_VBG

L_DDC_CLK
L_DDC_DATA

T45
P39

LVD_IBG
LVD_VBG

AE48
AE47

LVD_VREFH
LVD_VREFL

[49] LVDSA_CLK#
[49] LVDSA_CLK

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

[49] LVDSA_DATA0#
[49] LVDSA_DATA1#
[49] LVDSA_DATA2#

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

[49] LVDSA_DATA0
[49] LVDSA_DATA1
[49] LVDSA_DATA2

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

AP43
AP45

SDVO_STALLN
SDVO_STALLP

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

RN1706
SRN2K2J-1-GP

L_CTRL_CLK
L_CTRL_DATA

AF37
AF36

TPAD14-OP-GP TP1701

SDVO_TVCLKINN
SDVO_TVCLKINP

Layout Note:
Close HDMI port

P38
M39

PCH_HDMI_CLK [51]
PCH_HDMI_DATA [51]

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

AT49
AT47
AT40

HDMI_PCH_DET

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

HDMI_DATA2_R# [51]
HDMI_DATA2_R [51]
HDMI_DATA1_R# [51]
HDMI_DATA1_R [51]
HDMI_DATA0_R# [51]
HDMI_DATA0_R [51]
HDMI_CLK_R# [51]
HDMI_CLK_R [51]

SDVO_CTRLCLK
SDVO_CTRLDATA

Place near PCH;

trace to trace spacing=20mil
C

Layout Note:
LVDS signal trace
length max 4000mil

3
4

3D3V_S0

Digital Display Interface

R1701
2K37R2F-GP

Layout Note:

LVDS

SRN100KJ-6-GP

L_BKLTEN
L_VDD_EN

LVDS_DDC_CLK_R
T40
LVDS_DDC_DATA_R K47

[49] LVDS_DDC_CLK_R
[49] LVDS_DDC_DATA_R

2
1

J47
M45

2
1

[27] L_BKLT_EN
[49] LVDS_VDD_EN

3D3V_S0

4 OF 10

PCH1D
L_CTRL_DATA
L_CTRL_CLK

4
3

3
4

RN1701

1
2

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

M47
M49

CRT_HSYNC
CRT_VSYNC

T43
T42

DAC_IREF
CRT_IRTN

P46
P42

Layout Note:
HDMI trace length to DC CAP. max 10000mil

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DDPD_CTRLCLK
DDPD_CTRLDATA

M43
M36

CRT_DDCCLK
CRT_DDCDATA

DAC_IREF_R

Layout Note:

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PANTHER-GP-NF

71.PANTH.00U
2

Place near PCH;

trace to trace spacing=30mil

R1702
1KR2J-1-GP

CRT

2
1

RN1707
SRN2K2J-1-GP

DDPC_CTRLCLK
DDPC_CTRLDATA

[51]

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (LVDS/CRT/DDI)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

17

of

105

SSID = PCH
5 OF 10

Trace Length :
PCH ~~9000mil~~Cap~~1000mil~~CONN

USB3.0/2.0 Mapping Table

C

USB 3.0 Port

USB3_RX1_N
USB3_RX2_N

[62] USB3_RX1_N
[82] USB3_RX2_N

USB 2.0 port

Port 1

Port 0

Port 2

Port 1

Port 3

Port 2

Port 4

Port 3

USB3_RX1_P
USB3_RX2_P

[62] USB3_RX1_P
[82] USB3_RX2_P
[62] USB3_TX1_N
[82] USB3_TX2_N

USB3_TX1_N
USB3_TX2_N

[62] USB3_TX1_P
[82] USB3_TX2_P

USB3_TX1_P
USB3_TX2_P

3D3V_S0
RN1803
SRN10KJ-6-GP
1
2
3
4

8
7
6
5

PCH_GPIO50
PCH_GPIO54
PCH_GPIO02

TPAD14-OP-GP TP1803

BBS_BIT1

TPAD14-OP-GP TP1804

BBS_BIT0

BBS_BIT0 [21]

TPAD14-OP-GP TP1801

[56] SATA_ODD_DA#
[65] BLUETOOTH_EN

Boot Bios Strap

GNT1#/GPIO51

SATA1GP/GPIO19

Boot BIOS Location

PCH_GPIO50
PCH_GPIO52
PCH_GPIO54

C46
C44
E40

REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

BBS_BIT1
PCH_GPIO53
PCI_GNT3#

D47
E42
F46

GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

PCH_GPIO02

G42
G40
C42
D44

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

Reserved

Reserved

[71] CLK_PCI_LPC
[20] CLK_PCI_FB
[27] CLK_PCI_KBC

ER1807 1
R1805 1
R1806 1

DY

DY

DY

PCI_GNT3#

R1801
4K7R2J-2-GP

DY

[5,27,31,65,66,71]

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

RSVD25

AT8

Pair

Device

RSVD26
RSVD27

AY5
BA2

USB3.0 port1, with Power Share

USB3.0 port2

RSVD28
RSVD29

AT12
BF3

NC

NC

Touch Panel

NC

NC

NC

WWAN

NC

10

Card reader

11

WLAN

12

CAMERA

13

NC

USB Table

X01 12/20
X01 12/13

USB2.0 Signal Group

USBRBIAS#

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB_PN0
USB_PP0
USB_PN1
USB_PP1

USB_PN4 [82]
USB_PP4 [82]

USB_PN8 [66]
USB_PP8 [66]
USB_PN10
USB_PP10
USB_PN11
USB_PP11
USB_PN12
USB_PP12

C33 USB_RBIAS

USBRBIAS

B33

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

[62]
[62]
[82]
[82]

[82]
[82]
[65]
[65]
[49]
[49]

1
2
R1811
22D6R2F-L1-GP

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
PCH_GPIO14

Layout Note:
1. USBRBIAS/# use 50ohm single-ended impedance
spacing to other signal=15mil
2. Length < 500mil

PME#
PLTRST#

1. USB Ext. port 9 (HS) External debug port

use on Chief River platform.
2. 2011 July; Microsoft will support USB3.0
debug--> Port1 useable.

USB_OC#0_1 [62,82]

RN1802
SRN8K2J-2-GP-U

10
9
8
7
6

3D3V_S5

USB_OC#12_13
USB_OC#8_9
USB_OC#10_11
USB_OC#4_5

<Core Design>

1
1

DY

PCH_GPIO52
INT_PIRQB#
SATA_ODD_DA#
INT_PIRQA#

R1823
0R0402-PAD-2-GP

DY

RN1801
SRN8K2J-2-GP-U

2 PCI_PLTRST#

3D3V_S0

1
2
3
4
5

Wistron Corporation
10
9
8
7
6

INT_PIRQD#
PCH_GPIO05
INT_PIRQC#
BLUETOOTH_EN

R1816
100KR2J-1-GP

1
2
3
4
5

3D3V_S5

PLT_RST#

Low = A16 swap override/Top-Block

Swap Override enabled
High = Default

AT10
BC8

USB_OC#2_3
PCH_GPIO14
USB_OC#6_7
USB_OC#0_1

PCI_GNT#3

RSVD5
RSVD6

PANTHER-GP-NF

Swap Override jumper

AY7
AV7
AU3
BG4

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

X02 2/13
A16

RSVD1
RSVD2
RSVD3
RSVD4

EC1804

SPI(Default)

SC4D7P50V2CN-1GP

EC1802

C6

2 0R2J-2-GP CLK_PCI_LPC_R H49

2 22R2J-2-GP CLK_PCI_FB_R H43
2 22R2J-2-GP CLK_PCI_KBC_R J48
K42
H40

SC4D7P50V2CN-1GP

K10

LPC

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_PLTRST#

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

K40
K38
H38
G38

PCI_PME#

TP21
TP22
TP23
TP24

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

PCH_GPIO05

TPAD14-OP-GP TP1802

B21
M20
AY16
BG46

USB

Layout Note:

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

RSVD

PCH1E

C1801
SC220P50V2KX-3GP
3

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

3D3V_S0
Title

PCH (PCI/USB/NVRAM)
Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

18

of

105

SSID = PCH
3 OF 10

Layout Note:
DMI_ZCOMP keep W=4 mils and
routing length less than 500 1D05V_PCH
mils.
DMI_IRCOMP keep W=4 mils and
R1901 1
routing length less than 500
R1902 1
mils.

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

HIGH

Enabled (DEFAULT)

LOW

Disabled

DSWODVREN - On Die DSW VR Enable

FDI_FSYNC1

[4]

2 750R2F-GP

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC0

[4]

FDI_LSYNC1

BB10

FDI_LSYNC1

FDI_LSYNC1

[4]

DSWVRMEN

A18

DSW ODVREN

RBIAS_CPY

SUSACK#

C12

SUSACK#

2 10KR2J-3-GP
SYS_RESET#

P12

SYS_PWROK

L22

PWROK

2 0R0402-PAD-2-GP

2
0R2J-2-GP

MEPW ROK

L10

APWROK

B13

DRAMPWROK

[27] AC_PRESENT

DPWROK
WAKE#

BATLOW #

E10

PM_RI#

A10

ACPRESENT/GPIO31
BATLOW#/GPIO72
RI#

PCH_W AKE#

R1910

DY

2 0R2J-2-GP

G8

PM_SUS_STAT#

SUSCLK/GPIO62

N14

SUS_CLK

SLP_S5#/GPIO63

D10

PM_SLP_S5#

SLP_S4#

H4

PM_SLP_S4#

SLP_S3#

F4

PM_SLP_S3#

SLP_A#

G10

PM_SLP_A#

TP1903 TPAD14-OP-GP

SLP_SUS#

G16

PM_SLP_SUS#

TP1904 TPAD14-OP-GP

PMSYNCH

AP14

H_PM_SYNC

K14

PM_SLP_LAN#

TP1905 TPAD14-OP-GP

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

B9

SUS_STAT#/GPIO61

K16
E20

DSW ODVREN

R1917

2 330KR2J-L1-GP

PM_RSMRST#

X03 2/13

PM_CLKRUN#

SUS_PW R_ACK

H20

DY

2 10KR2J-3-GP
2 0R0402-PAD-2-GP

N3

RSMRST#

AC_PRESENT

PCH_DPW ROK

RTC_AUX_S5
R1911 1
R1927 1

CLKRUN#/GPIO32

C21

PM_PW RBTN#

E22

RTC_AUX_S5

3D3V_S0

PCH_W AKE#_EC [27]

X03 2/6

PM_RSMRST#

R1924
0R0402-PAD-2-GP

[27] PM_PW RBTN#

[4]

[4]

FDI_FSYNC1

X02 2/6
1

FDI_FSYNC0

BC10

[37] PM_DRAM_PW RGD

[27] RSMRST#_KBC

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

PW ROK
R1916 1

DY

FDI_INT

FDI_FSYNC0

X03 2/6

AW16

DMI_IRCOMP

X03 2/6

R1907

FDI_INT

FDI_TXP[7:0] [4]

DMI_ZCOMP

K3

[45,46,47] RUNPW ROK

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

BG25

R1905 1

1
2
R1921
0R0402-PAD-2-GP

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

2 49D9R2F-GP DMI_COMP_R

[5] XDP_DBRESET#

[27,36] S0_PW R_GOOD

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

AV12

TPAD14-OP-GP TP1907

[36] SYS_PW ROK

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

BJ24

3D3V_S0

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

SLP_LAN#/GPIO29

R1929

2 0R0402-PAD-2-GP

PM_CLKRUN#_EC [27]

PM_CLKRUN#

PCH_SUSCLK_KBC

PCH_SUSCLK_KBC

R1919

2 8K2R2J-3-GP

TP1901 TPAD14-OP-GP

X03 2/6
R1925

2 0R0402-PAD-2-GP

[27]

[4] DMI_TXP[3:0]

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

FDI_TXN[7:0] [4]

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

TP1902 TPAD14-OP-GP
EC1901
SC4D7P50V2CN-1GP

DY
1

[4] DMI_TXN[3:0]

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI

[4] DMI_RXP[3:0]

BC24
BE20
BG18
BG20

System Power Management

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI

PCH1C
[4] DMI_RXN[3:0]

PM_SLP_S4# [27,46]
PM_SLP_S3# [27,36,37,47]

H_PM_SYNC

[5]

PANTHER-GP-NF

Sequence:
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

71.PANTH.00U

3D3V_S5
RN1901

8
7
6
5

1
2
3
4

BATLOW #
PM_RI#
SUS_PW R_ACK
PCH_W AKE#

SRN10KJ-6-GP
R1909
R1920

1
2

DY

2 100KR2J-1-GP AC_PRESENT
1 10KR2J-3-GPPM_SLP_LAN#
<Core Design>

R1908

R1926
R1904

1
1

Wistron Corporation

1 10KR2J-3-GP PM_RSMRST#

DY

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

2 100KR2J-1-GP SYS_PW ROK

2 100KR2J-1-GP PW ROK

Title

PCH (DM I/FDI/PM)

5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

19

of

105

S5 power rail CLKREQ#:

PCIECLKRQ[0]#
PCIECLKRQ[7:3]#

C2001
C2002

1
1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

PCIE_TXN4_C
PCIE_TXP4_C

PCIE_TXN6_C
PCIE_TXP6_C

Layout Note:

PERN4
PERP4
PETN4
PETP4

BG37
BH37
AY36
BB36

PERN5
PERP5
PETN5
PETP5

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

Layout trace < 14000mil

X01 12/09

Layout Note:

CLK_PCIE_REQ1#

CLKOUT termination
place close to PCH <500mil

RN

[65] CLK_PCIE_W LAN#

[65] CLK_PCIE_W LAN
B

1
2

4
3

RN

[31] CLK_PCIE_LAN#
[31] CLK_PCIE_LAN
[31] PCIE_CLK_LAN_REQ#

1
2

4
3

NC
LAN
NC
NC

AB49
AB47

CLKOUT_PCIE1N
CLKOUT_PCIE1P

M1

CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2#/GPIO20

Y37
Y36

CLKOUT_PCIE3N
CLKOUT_PCIE3P

A8

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIE_CLK_REQ4#

L12

PCIECLKRQ4#/GPIO26

CLK_PCH_SRC5_N
CLK_PCH_SRC5_P

V45
V46

CLKOUT_PCIE5N
CLKOUT_PCIE5P

L14

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

E6

CLK_PCIE_REQ7#
TPAD14-OP-GP TP2007
TPAD14-OP-GP TP2008

1
1

PCIE_CLK_XDP_N_R
PCIE_CLK_XDP_P_R

G12

SML0_DATA

[37]

PCH_GPIO74
SML1_CLK

SML1DATA/GPIO75

M16

SML1_DATA

M7

CL_DATA1

T11

CL_DATA 1

TP2002 TPAD14-OP-GP

CLKOUT_PCIE6N
CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

1KR2J-1-GP

2
1

3
4
SRN2K2J-1-GP

CRB : 1K
CEKLT: 10K

PCH_SMBDATA [14,15,65,66,69]

CL_RST1#

P10

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

Q2001
2N7002KDW -GP

PCH_SMBCLK [14,15,65,66,69]
SMB_CLK

CL_RST# 1

TP2003 TPAD14-OP-GP

XTAL25_IN

M10

PEG_CLKREQ#_R

DY

CLKOUT termination
place close to PCH <500mil

PEG_CLKREQ# [85]

AB37
AB38
AV22
AU22

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

1
2

4
3

CLK_PCIE_VGA# [83]
CLK_PCIE_VGA [83]

SG

SRN0J-6-GP
1
4
2
3

CLKOUT_DMI_N
CLKOUT_DMI_P

C2008
SC15P50V2JN-2-GP

R2006
1M1R2J-GP

RN2016

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

X2001

Layout Note:

C2007
SC15P50V2JN-2-GP

XTAL25_OUT

XTAL-25MHZ-155-GP1

82.30020.D41
2nd = 82.30020.G61

CLK_EXP_N [5]
CLK_EXP_P [5]

RN2017 0R4P2R-PAD

AM12
AM13

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

CLK_BUF_EXP_N
CLK_BUF_EXP_P

2
RN2019 1
SRN10KJ-5-GP

3
4

CLKIN_GND1_N
CLKIN_GND1_P

BJ30
BG30

CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P

2
RN2008 1
SRN10KJ-5-GP

3
4

CLKIN_DOT_96N
CLKIN_DOT_96P

G24
E24

CLK_BUF_DOT96_N
CLK_BUF_DOT96_P

2
RN2020 1
SRN10KJ-5-GP

3
4

CLKIN_SATA_N
CLKIN_SATA_P

AK7
AK5

CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P

2
RN2021 1
SRN10KJ-5-GP

3
4

REFCLK14IN

K45

CLK_BUF_REF14

NC
WLAN CLK

NC
LAN
CLK

CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT

NC

A00 3/23

CLKOUT_DP_N
CLKOUT_DP_P

3D3V_S0

H45

CLK_PCI_FB

V47
V49

XTAL25_IN
XTAL25_OUT

R2008 1
10KR2J-3-GP
CLK_PCI_FB

UMA
B

BOARD_ID1
BOARD_ID2

[22] BOARD_ID2

R2012
10KR2J-3-GP

R2010
10KR2J-3-GP

SG

Layout Note:

BIOS UMA/DIS Strap pin

1500mil < Layout trace < 10000mil

BOARD_ID2

BOARD_ID1
PX(AMD)
1

+VCCDIFFCLKN

DIS

UMA

90D9R2F-1-GP

NC
NC

[18]

R2013
10KR2J-3-GP

R2007

Y47 XCLK_RCOMP

XCLK_RCOMP

V40
V42

SMB_DATA

SML1_DATA [27,28,85]

TP2001 TPAD14-OP-GP

NC

NC

SML1_CLK [27,28,85]

CL_CLK

CL_CLK1

10KR2J-3-GP

2
1

3D3V_S0

Layout Note:

PEG_B_CLKRQ#/GPIO56

AK14
AK13

DRAMRST_CNTRL_PCH

R2011 1

DRAMRST_CNTRL_PCH
R2009

RN2007

E14

FLEX CLOCKS

PCIE_CLK_REQ6#

SML0_CLK

C13

Layout trace < 14000mil

X01 12/09

DRAMRST_CNTRL_PCH

C8

SML1CLK/GPIO58

PCIECLKRQ5#/GPIO44

AB42
AB40

A12

SML1ALERT#/PCHHOT#/GPIO74

PCIECLKRQ3#/GPIO25

Y43
Y45

CLK_PEG_B_REQ#

SML0DATA

PCIECLKRQ1#/GPIO18

CLK_PCH_SRC3_N
CLK_PCH_SRC3_P

X01 12/09

SML0CLK

R2003
0R2J-2-GP

PCIECLKRQ0#/GPIO73

V10

RN2014 0R4P2R-PAD

Layout Note:

WLAN

PCIE_CLK_REQ2#

RN2012 0R4P2R-PAD

[65] CLK_PCIE_W LAN_REQ#

J2

PCH_GPIO74

Can Place Far away PCH

CLKOUT_PCIE0N
CLKOUT_PCIE0P

AA48
AA47

A00 3/23
X02 2/6

NC

SML0ALERT#/GPIO60

RN

PCIE_CLK_REQ0#

NC

PEG_A_CLKRQ#/GPIO47

Y40
Y39

R2005
10KR2J-3-GP

PCIE_RXN6
PCIE_RXP6
PCIE_TXN6
PCIE_TXP6

1
1

SG

C2005
C2006

PEG_CLKREQ#_R

EC_SW I# [27]

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

BF36
BE36
AY34
BB34

SMB_DATA

8 RN2004
7 SRN2K2J-2-GP
6
5

PERN3
PERP3
PETN3
PETP3

C9

SMBDATA

1
2
3
4

BG36
BJ36
AV34
AU34

SMB_CLK

SML0_DATA
SML0_CLK
SML1_CLK
SML1_DATA

PERN2
PERP2
PETN2
PETP2

EC_SW I#

H14

R2004
10KR2J-3-GP

BE34
BF34
BB32
AY32

E12

SMBCLK

1 RN2003
2 SRN2K2J-1-GP

3D3V_S5

UMA

SMBALERT#/GPIO11

4
3

PCIE_CLK_RQ5#
PCIE_CLK_RQ7#

NC

SMB_CLK
SMB_DATA

[31]
[31]
[31]
[31]

S0 power rail CLKREQ#:

PCIECLKRQ[2:1]#

8
7
6
5

PERN1
PERP1
PETN1
PETP1

Link

EC_SW I#
PCIE_CLK_LAN_REQ#
CLK_PCIE_REQ7#
CLK_PEG_B_REQ#

BG34
BJ34
AV32
AU32

SMBUS

X01 12/09

SRN10KJ-6-GP

[65]
[65]
[65]
[65]

PCIE_CLK_RQ2#
PCIE_CLK_RQ1#

2 OF 10

PCH1B

Controller

PCIE_CLK_RQ6#
PCIE_CLK_RQ3#
PCIE_CLK_RQ0#
PCIE_CLK_RQ4#

CLOCKS

PCIE_CLK_REQ6#
CLK_PCIE_W LAN_REQ#
PCIE_CLK_REQ0#
PCIE_CLK_REQ4#

PCI-E*

PCIE_CLK_REQ2#
CLK_PCIE_REQ1#

4
3

SRN10KJ-5-GP

8
7
6
5

SRN10KJ-6-GP
RN2002
1
2
3
4

3D3V_S5

RN2018

1
2

RN2001

1
2
3
4

3D3V_S5

X01 12/09

SSID = PCH

3D3V_S0

CLKOUTFLEX0/GPIO64

K43

JTAG_TCK

TP2004 TPAD14-OP-GP

CLKOUTFLEX1/GPIO65

F47

CARD_READER_48M

TP2005 TPAD14-OP-GP

CLKOUTFLEX2/GPIO66

H47

CLK_27M_VGA_R

TP2006 TPAD14-OP-GP

CLKOUTFLEX3/GPIO67

K49

BOARD_ID1

Optimus(NV)
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PANTHER-GP-NF
Title

71.PANTH.00U

PCH (PCI-E/SMBUS/CLOCK/CL)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

20

of

105

SSID = PCH

Layout Note:
RTC_AUX_S5

Place it at the open door location.

RN2102

Integrated SUS 1V VRM Enable

2
1
1M1R2J-GP
1
2

RTC_AUX_S5

A20

RTCX1

RTC_X2

C20

RTCX2

RTC_RST#

D20

RTCRST#

SRTC_RST#

G22

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

HDA_BITCLK

N34

HDA_BCLK

HDA_SYNC

L34

HDA_SYNC

T10

SPKR

HDA_RST#

K34

HDA_RST#

R2125
33R2J-2-GP
1

[82] HDA_CODEC_RST#

[82] HDA_CODEC_BITCLK

R2126
33R2J-2-GP
1

HDA_SDOUT

Place close together.

For RNxxxx later.

HDA_RST#

E34

HDA_SDIN0

Layout Note:

G34

HDA_SDIN1

HDA_SDO and HDA_BCLK must be

length matched to within 500 mils

C34

HDA_SDIN2

[82] HDA_SDIN0

HDA_BITCLK

R2107
1KR2J-1-GP
1
2

[27] ME_UNLOCK

Layout Note:

3D3V_S5

Flash Descriptor Security Overide/

Intel ME Debug Mode
Low = Default *
HDA_SDOUT High = Enable

R2111

R2118

R2119

R2120

Place at the separated point

HDA_SDOUT

A34

HDA_SDIN3
HDA_SDO

1PCH_GPIO33

C36

HDA_DOCK_EN#/GPIO33

TPAD14-OP-GP TP2102

1PCH_GPIO13

N32

HDA_DOCK_RST#/GPIO13

DY
DY
DY
DY

DY

[27,60] SPI_CLK_R
[27,60] SPI_CS0#_R

[27,60] SPI_SI_R
+3VS_+1.5VS_HDA_IO

[27,60] SPI_SO_R
1KR2J-1-GP

[27]

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

[56]
[56]
[56]
[56]

HDD1

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

[66]
[66]
[66]
[66]

mSATA

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1

PCH_JTAG_TCK_BUF

J3

JTAG_TCK

PCH_JTAG_TMS

H7

JTAG_TMS

SATAICOMPO

Y11

2 210R2F-L-GP

PCH_JTAG_TDI

K5

JTAG_TDI

SATAICOMPI

Y10

2 210R2F-L-GP

PCH_JTAG_TDO

H1

JTAG_TDO

[27,71]

LPC_FRAME# [27,71]

AM3
AM1
AP7
AP5

2 210R2F-L-GP

1
R2108
1
R2109

PCH_SPI_CLK
33R2J-2-GP
2 PCH_SPI_CS0#
33R2J-2-GP

1
R2110
1
R2115

2 PCH_SPI_SI
33R2J-2-GP
2 PCH_SPI_SO
33R2J-2-GP

SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4

[56]
[56]
[56]
[56]

ODD

Layout Note:
HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil
1D05V_PCH
SATA_COMP

R2112

2 37D4R2F-GP

1D05V_PCH

SATA3RCOMPO

AB12

SATA3COMPI

AB13

SATA3_COMP R2113

2 49D9R2F-GP

T3

SATA3RBIAS

AH1

RBIAS_SATA3 R2114

2 750R2F-GP

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4
U3

SPI_MOSI

SATALED#
SATA0GP/GPIO21

SPI_MISO

SATA1GP/GPIO19

P3

SATA_LED#

V14

PCH_GPIO21

P1

BBS_BIT0

Layout Note:

SATA_LED# [68]

Place close PCH(<500mil)

BBS_BIT0 [18]

HDA_SYNC

X01 12/21

PANTHER-GP-NF

71.PANTH.00U

PLL ODVR VOLTAGE

Low = 1.8V
HDA_SYNC High = 1.5V

2
0R0402-PAD-2-GP

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

2 51R2J-2-GP

Low = Default *
HDA_SPKR High = No Reboot

INT_SERIRQ

1
R2136

LPC_AD[3..0]

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

HDA_SPKR

No Reboot Strap

R2103 1

KB_DET# [69]

V5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SPI

2 1KR2J-1-GP

0R0402-PAD-2-GP
2
0R0402-PAD-2-GP
2
0R0402-PAD-2-GP
2
0R0402-PAD-2-GP
2

E36
K36

SERIRQ

3D3V_S0

R2106 1

1
1
1
1

LDRQ0#
LDRQ1#/GPIO23

SATA 6G

A36

TPAD14-OP-GP TP2101

LPC_LAD0_PCHR2116
LPC_LAD1_PCHR2121
LPC_LAD2_PCHR2127
LPC_LAD3_PCHR2128

D36 LPC_LFRAME#_PCH

SATA

[82] HDA_CODEC_SDOUT

Layout Note:

C38
A38
B37
C37

FWH4/LFRAME#

R2105
330KR2F-L-GP

[82] HDA_SPKR
R2123
33R2J-2-GP
1

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LPC_AD[3..0]

1 OF 10

IHDA

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

C2103
SC1U6D3V2KX-GP

2N7002K-2-GP

R2104

RTC_X1

JTAG

R2122
10KR2J-3-GP

Place near PCH

PCH1A

[27] RTCRST_ON

Layout Note:
A00 3/27

LPC

Q2102

Low = External VRs

High = Internal VRs*

INTVRMEN

GAP-OPEN

RTC

G2101

SC1U6D3V2KX-GP

C2104

4
3
SRN20KJ-1-GP

1
2

3D3V_S0
RN2103
INT_SERIRQ
PCH_GPIO21

Q2101

1
2

4
3

[36,37] RUN_ENABLE

SRN10KJ-5-GP
HDA_SYNC

D
R2124
HDA_CODEC_SYNC_R

S
2N7002K-2-GP

RTC_X1

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

1
R2101

<Core Design>

EC2103

Wistron Corporation

DY

X-32D768KHZ-65-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

C2102
SC15P50V2JN-2-GP

SC4D7P50V2CN-1GP

EC2102

2
1

DY

HDA_CODEC_SDOUT

HDA_CODEC_BITCLK

HDA_SYNC:
This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V
VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.

RTC_X2

2
10MR2J-L-GP

X2101

C2101
SC15P50V2JN-2-GP
2
1

R2117
1M1R2J-GP

SC4D7P50V2CN-1GP

33R2J-2-GP

[82] HDA_CODEC_SYNC

Title

PCH (SPI/RTC/LPC/SATA/IHDA)
82.30001.A41
2nd = 82.30001.841
2

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

21

of

105

SSID = PCH
6 OF 10

PCH1F

[27] EC_SMI#

TACH4/GPIO68

C40

SATA_ODD_PW RGT

A42

TACH1/GPIO1

TACH5/GPIO69

B41

BOARD_ID2

PCH_GPIO6

H36

TACH2/GPIO6

TACH6/GPIO70

C41

PCH_GPIO70

TP2201 TPAD14-OP-GP

EC_SCI#

E38

TACH3/GPIO7

TACH7/GPIO71

A40

PCH_GPIO71

TP2202 TPAD14-OP-GP

PCH_GPIO08

C10

GPIO8

P4

H_A20GATE_PCH

AU16

H_PECI_R

P5

H_RCIN#

PROCPWRGD

AY11

H_CPUPW RGD

THRMTRIP#

AY10

PCH_THERMTRIP_R

INIT3_3V#

T14

INIT3_3V#

DF_TVS

AY1

DF_TVS

TS_VSS1

AH8

TS_VSS2

AK11

TS_VSS3

AH10

TS_VSS4

AK10

3D3V_S0
[27] EC_SCI#
H_A20GATE_PCH
H_RCIN#
[60] RTC_DET#
3D3V_S0
RN2205
SRN10KJ-5-GP
1
4
2
3

[56] SATA_ODD_PRSNT#
SATA_ODD_PRSNT#
PCH_GPIO00

1
2
3
4

RN2206
SRN10KJ-6-GP
8
7
6
5

[27,86,92,93]

1
2
3
4

SATA_ODD_PRSNT#

U2

GPIO15

A20GATE
PECI

SATA4GP/GPIO16

T5

SCLOCK/GPIO22

COLOR_ENGINE

E8

GPIO24

PCH_GPIO27

[66] MSATA_DET#

TACH0/GPIO17

E16

GPIO27

PLL_ODVR_EN

P8

GPIO28

MSATA_DET#

K1

STP_PCI#/GPIO34

PCH_GPIO35

K4

GPIO35

PCH_GPIO36

V8

SATA2GP/GPIO36

PCH_GPIO37

M5

SATA3GP/GPIO37

PCH_GPIO38

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

[83] DGPU_HOLD_RST#

DGPU_HOLD_RST#

[93] DGPU_PW R_EN#

DGPU_PW R_EN#
PCH_GPIO49

V3

SATA5GP/GPIO49/TEMP_ALERT#

PCH_GPIO57

D6

GPIO57

3D3V_S5

2
R2221

DY
DY

R2224

2
B

R2201

DY

RTC_DET#
PCH_GPIO57

COLOR_ENGINE
1
10KR2J-3-GP
PCH_GPIO08
1
10KR2J-3-GP
PCH_GPIO15
1
1KR2J-1-GP

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

H_RCIN#

R2207
2K2R2J-2-GP
R2209
DF_TVS

P37

VSS_NCTF_15#BG2

BG2

PCH_NCTF_BG2

TP2203 TPAD14-OP-GP

VSS_NCTF_16#BG48

BG48

PCH_NCTF_BG48

TP2204 TPAD14-OP-GP

VSS_NCTF_17#BH3

BH3

PCH_NCTF_BH3

TP2205 TPAD14-OP-GP

VSS_NCTF_18#BH47

BH47

PCH_NCTF_BH47

TP2206 TPAD14-OP-GP

BJ46
BJ5

A6

VSS_NCTF_6#A6

VSS_NCTF_24#BJ6

BJ6

VSS_NCTF_25#C2

C2

PCH_NCTF_C2

TP2207 TPAD14-OP-GP

VSS_NCTF_26#C48

C48

PCH_NCTF_C48

TP2208 TPAD14-OP-GP

VSS_NCTF_27#D1

D1

VSS_NCTF_28#D49

D49

B47

VSS_NCTF_8#B47

BD49

VSS_NCTF_9#BD1
VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

VSS_NCTF_29#E1

E1

VSS_NCTF_30#E49

E49

BF1

VSS_NCTF_13#BF1

VSS_NCTF_31#F1

F1

BF49

VSS_NCTF_14#BF49

VSS_NCTF_32#F49

F49

2
1KR2J-1-GP

H_SNB_IVB# [5]

Check these fuor balls are connected firstly, then to GND

NC_1

VSS_NCTF_23#BJ5

PCH_NCTF_B47

Layout Note:

VSS_NCTF_5#A5

H_THERMTRIP# [5]

1D8V_S0

A5

TPAD14-OP-GP TP2212

2 2K2R2J-2-GP

TP2213 TPAD14-OP-GP

BJ45

VSS_NCTF_7#B3

R2202

[5]

VSS_NCTF_22#BJ46

B3

VCCP_CPU

2 390R2J-1-GP

VSS_NCTF_4#A46

PCH_NCTF_B3

H_PECI [5,27]

[27]

H_CPUPW RGD
R2204

H_A20GATE [27]

2 0R2J-2-GP

BJ44

DGPU_PW R_EN#
1
110KR2J-3-GP DGPU_HOLD_RST#
10KR2J-3-GP
DGPU_PW R_EN#
1
110KR2J-3-GP DGPU_HOLD_RST#
10KR2J-3-GP

DY

VSS_NCTF_21#BJ45

X01 12/09

DY
DY

VSS_NCTF_20#BJ44

BD1

2
R2225 2
R2226
2
R2227 2
R2228

R2203

R2205
0R0402-PAD-2-GP
2

BJ4

TPAD14-OP-GP TP2211

3D3V_S0

VSS_NCTF_19#BJ4

NCTF

RN2204
SRN10KJ-5-GP
4
3

A4

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49

1
2

A00 3/23

DBC_EN

D40

BOARD_ID2 [20]

LAN_PHY_PWR_CTRL/GPIO12

DGPU_PW ROK

TPAD14-OP-GP TP2209
PCH_GPIO49
MSATA_DET#
PCH_GPIO38
DBC_EN

EC_SMI#
EC_SCI#
PCH_GPIO6
DGPU_PW ROK

G2

DGPU_PW ROK

3D3V_S0
RN2201
SRN10KJ-6-GP
8
7
6
5

PCH_GPIO15

[49] DBC_EN

TPAD14-OP-GP TP2210

C4

RCIN#

[49] COLOR_ENGINE

3D3V_S0

RTC_DET#

SATA_ODD_PW RGT [56]

RN2203
SRN10KJ-5-GP
4
3

CPU/MISC

1
2

GPIO

BMBUSY#/GPIO0

EC_SMI#

T7

PCH_GPIO00

PANTHER-GP-NF

71.PANTH.00U
RN2202
SRN10KJ-5-GP
1
4
2
3

2
R2212

DY

PCH_GPIO36
PCH_GPIO37

PLL_ODVR_EN
1KR2J-1-GP
DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PLL ON DIE VR ENABLE

Title

Weakly internal pull up 20k.

High - Enable
LOW - Disable

GPIO28
(PLL_ODVR_EN)

PCH (GPIO/CPU)
4

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

22

of

105

SSID = PCH

Voltage Rail

VCCTX_LVDS4

AP37

0.001

V5REF

0.001

V5REF_Sus

0.001

VCCIO15

AN17

VCCIO16
VCCIO17

AN26

VCCIO18

AN27

VCCIO19

AP21

VCC3_3_6

VCC3_3_7

V34

VCCVRM3

VCCIO22

AP26

VCCIO23

AT24

VCCIO24

AN33

VCCIO25

AN34

VCCIO26

0.04A

AT20

VCCCLKDMI

AB36

1
2

C2315
SC10U6D3V3MX-GP

SCD1U10V2KX-5GP

0.228

VccADAC

3.3

0.063

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.7

VccDMI

1.1

0.047

VccIO

1.05

1D8V_S0

3.711

VccASW

1.05

R2301

0.903

VccSPI

3.3

0.01

VccDSW3_3

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6uA

VccSus3_3

3.3

0.095

VccSusHDA

3.3

0.01

VccVRM

1.5

0.167

VccClkDMI

1.05

0.07

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

0R0603-PAD-2-GP

3D3V_S0

X03 2/6

0.167A
1D05VS_VCC_DMI

VCCDMI1

3D3V_S0

R2304

C2319
SCD1U10V2KX-5GP

AT16

3.3

1D5V_S0
R2307
0R0402-PAD-2-GP
1
2

0.047A

VCCP_CPU
R2306
0R0402-PAD-2-GP
1
2

0.07A

1D05V_PCH
R2308
0R0402-PAD-2-GP
1
2

Refer to chipset EDS V.0.7

C2320
SC1U6D3V2KX-GP

+1.05VS_VCC_DMI_CCI

VCCIO21

AP24

0.001A

VCCVRM

VCCIO20

AP23

V33

Vcc3_3

X03 2/6

0.228A
1

AN16

AP36

C2318
SC22U6D3V5MX-2GP

VCCTX_LVDS3

+1.8VS_VCCTX_LVDS

AM38

C2317
SCD01U16V2KX-3GP

VCCTX_LVDS2

DY

0R0603-PAD-2-GP

AM37

C2314

VCCTX_LVDS1

SCD01U16V2KX-3GP

CRT

2
VSSALVDS

AK37

+3VS_VCCA_LVDS

VCCALVDS

AK36

VCCAPLLEXP

VCCIO

1
2

C2309
SC1U6D3V2KX-GP

C2308
SCD1U10V2KX-5GP

1
2

DY

C2307
SCD1U10V2KX-5GP

C2306
SC1U6D3V2KX-GP

EC2305
SCD1U10V2KX-5GP

1
2

X03 2/16

DY

C2313

C2316
SCD01U16V2KX-3GP

BJ22

AN21

3.711A

U47

VCCIO28

1D05V_PCH

VSSADAC

0.061A

VCCAPLLEXP

U48

Iccmax(A)

TPAD14-OP-GP TP2301

VCCADAC

AN19

3D3V_S0

7 OF 10

1D05V_PCH

VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE17

LVDS

1
2

C2304
SC1U6D3V2KX-GP

C2303
SC1U6D3V2KX-GP

DY

C2302
SC1U6D3V2KX-GP

1
2

C2301
SC10U6D3V5KX-1GP

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

HVCMOS

1.7A

DMI

1D05V_PCH

POWER

VCC CORE

PCH1G

Voltage(V)
1.05

V_PROC_IO

3D3V_S0

AG16

VCCDFTERM2

AG17

VCCVRM2

VCCVRM

VCCDFTERM3

AJ16

VCCDFTERM4

AJ17

BG6

VCCAFDIPLL

C2322
SCD1U10V2KX-5GP

1D05V_PCH

1D8V_S0

AP17

VCCIO27

AU20

VCCDMI2

1D05VS_VCC_DMI

VCCSPI

V1

3D3V_S5

0.01A
1

1VCCFDIPLL

FDI

TPAD14-OP-GP TP2302

C2321
SC1U6D3V2KX-GP

0.002A
1

AP16

DFT / SPI

VCC3_3_3

BH29

C2310
SCD1U10V2KX-5GP

VCCDFTERM1

0.228A

PANTHER-GP-NF

71.PANTH.00U

C2323
SC1U6D3V2KX-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (POWER1)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

23

of

105

SSID = PCH
PCH1J
TPAD14-OP-GP TP2401

+VCCSUS1

VCCAPLLDMI2

AL29

VCCIO14

AL24

DCPSUS3

VCCSUS3_3_9

V23

VCCSUS3_3_10

V24

VCCSUS3_3_6

P24

VCCIO34

T26

V5REF_SUS

M26

+5VA_PCH_VCC5REFSUS

DCPSUS4

AN23

+VCCA_USBSUS

VCCSUS3_3_1

AN24

(0.1uFx1)

VCCASW5

AA29

VCCASW6

AA31

VCCASW7

AC26

VCCASW8

AC27

VCCASW9
VCCASW10

AC31

VCCASW11

AC29

0.08A

VCCASW12

AD31

VCCASW13

W21

VCCASW14

W23

VCCASW15

W24

VCCASW16

W26

VCCASW17

W29

VCCASW18

W31

VCCASW19

W33

VCCASW20

3D3V_S0

3D3V_S5

V5REF

P34

VCCSUS3_3_2

N20

VCCSUS3_3_3

N22

VCCSUS3_3_4

P20

VCCSUS3_3_5

P22
AA16

VCC3_3_8

W16

VCC3_3_4

T34

3D3V_S0

V5REF_Sus
C2431
SCD1U10V2KX-5GP

1D05V_PCH

3D3V_S0

N16
Y49

VCCVRM4

BD47

+1.05VS_VCCA_B_DPL

BF47

VCCADPLLB

+VCCDIFFCLK

AF17
AF33
AF34
AG34

VCCIO7
VCCDIFFCLKN1
VCCDIFFCLKN2
VCCDIFFCLKN3

2
1

R2412
0R0603-PAD-2-GP
C2414
SC1U6D3V2KX-GP

VCCADPLLA

+V1.05S_SSCVCC

AG33

VCCAPLLSATA

1D05V_PCH

C2432
SC1U6D3V2KX-GP

AF14

DY

C2413
SC1U6D3V2KX-GP

C2436
SC1U6D3V2KX-GP

AF11

VCCVRM

TP2406
TPAD14-OP-GP

VCCIO3

AC17

VCCIO4

AD17

1D05V_PCH

PANTHER-GP-NF
71.PANTH.00U

MISC

VCCASW22

T21

VCCASW23

V21

VCCASW21

T19

0.001

0.001

Vcc3_3

3.3

0.228

VccADAC

3.3

0.063

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.7
0.047

VccDMI

1.1

VccIO

1.05

3.711

VccASW

1.05

0.903

VccSPI

3.3

0.01

VccDSW3_3

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6uA

VccSus3_3

3.3

0.095

VccSusHDA

3.3

0.01

VccVRM

1.5

0.167

VccClkDMI

1.05

0.07

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

VCCSUSHDA

P32

+3VS_+1.5VS_HDA_IO
3D3V_S5

0.01A

C2433
SCD1U10V2KX-5GP

VCCRTC

HDA

A22

V_PROC_IO

CPU

BJ8

C2435
SC1U6D3V2KX-GP

1D05V_PCH

DCPSUS1
DCPSUS2

0.001

AC16

DCPSST

RTC

C2420
SCD1U10V2KX-5GP

1
2
4

1
1

+V1.05S_SSCVCC

1
5

6uA
1

0.095A

C2417
SC4D7U6D3V3KX-GP
RTC_AUX_S5

R2404
0R0402-PAD-2-GP
1
2

1D05V_PCH

C2412
SC1U6D3V2KX-GP

1
2

0.001A
+VCCDIFFCLK

V16
T17
V19

DCPSUS

C2422
SCD1U10V2KX-5GP

R2403
0R0402-PAD-2-GP
1
2

C2418
SCD1U10V2KX-5GP

VCCP_CPU

C2421
SCD1U10V2KX-5GP

X03 2/6
1D05V_PCH

TP2405
1
TPAD14-OP-GP

1
2

C2415
SCD1U10V2KX-5GP

+VCCSST

Iccmax(A)

1.05

AK1
+V1.05S_VCCAPLL_SATA3

VCCVRM1
VCCIO2

VCCSSC

VCCIO13

AH14

X03 2/6

AH13

VCCIO6

+1.05VS_VCCA_A_DPL

+VCCDIFFCLKN

0.055A

VCCIO12

DCPRTC

VCCVRM

0.167A

SATA

C2411
SCD1U10V2KX-5GP

C2429
SCD1U10V2KX-5GP

X03 2/16

AF13

Voltage(V)

V_PROC_IO
V5REF

AJ2

VCCIO5

C2427
SC1U6D3V2KX-GP

Voltage Rail
C2430
SCD1U10V2KX-5GP

+VCCRTCEXT

10R2J-2-GP

3D3V_S0

VCC3_3_2

R2407

3D3V_S5

VCC3_3_1

D2402
CH751H-40PT-GP

83.R0304.A8F
2nd = 83.R2004.B8F

0.001A

1
C2410
SC1U6D3V2KX-GP

DY C2437
SC1U10V2KX-1GP

+5VS_PCH_VCC5REF

C2428
SC1U6D3V2KX-GP

5V_S0

VCCASW4

AA27

C2426
SCD1U10V2KX-5GP

0.001A

AA26

10R2J-2-GP

C2425
SCD1U10V2KX-5GP

1D05V_PCH

VCCASW3

3D3V_S5

AA24

R2408

VCCASW2

D2401
CH751H-40PT-GP

83.R0304.A8F
2nd = 83.R2004.B8F

C2424
SCD1U10V2KX-5GP

VCCASW1

AA21

+1.05VS_VCCA_B_DPL

T24

AA19

AD29
C2407
SC1U6D3V2KX-GP

C2408
SC10U6D3V5KX-1GP

+1.05VS_VCCA_A_DPL

VCCSUS3_3_8

0.095A

BH23

5V_S5

1
2

1
2

1
2

1
2

1
2

DY

SC1U6D3V2KX-GP
C2419

SC1U6D3V2KX-GP
C2405

SC1U6D3V2KX-GP
C2406

SC22U6D3V5MX-2GP
C2404

SC22U6D3V5MX-2GP
C2403

DY

0.08A

VCCSUS3_3_7

T23

3D3V_S5
3D3V_S5

+VCCAPLL_CPY_PCH

1D05V_PCH

T29

VCC3_3_5

EC2409
SCD1U10V2KX-5GP

T27

VCCIO33

TP2403
TPAD14-OP-GP

X01 1/9

68.10050.10Y
2nd = 68.1001E.10N

VCCIO32

C2438
SC1U6D3V2KX-GP

T38

DCPSUSBYP

USB

C2402
SC1U6D3V2KX-GP

DY

L2403
1
2
IND-10UH-218-GP

P28

V12

1D05V_PCH

0.93A

DY

P26

VCCIO31

DCPSUSBYP

1D05V_PCH

68.10050.10Y
2nd = 68.1001E.10N

VCCIO30

+V3.3S_VCC_CLKF33

TP2404
TPAD14-OP-GP

L2402
1
2
IND-10UH-218-GP

N26

VCCDSW3_3

PCI/GPIO/LPC

TP2402
TPAD14-OP-GP

T16

Clock and Miscellaneous

DY
2

C2401
SC10U6D3V5KX-1GP

+V3.3S_VCC_CLKF33

68.10050.10Y
2nd = 68.1001E.10N

1D05V_PCH

10 OF 10

VCCIO29

1
1

C2416
SCD1U10V2KX-5GP

3D3V_S0
L2401

POWER

VCCACLK

3D3V_S5

1
2
IND-10UH-218-GP

AD49

0.001A

DG: none
CRB: 10uH

VCCACLK

3D3V_S5

DMB40

Refer to chipset EDS V.0.7

Wistron Corporation

R2402
0R0402-PAD-2-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

X03 2/6
Title

VCCSUSHDA need to be at either 3.3V or 1.5V.

All the CODEC I/O Voltages need to be at the same
level either 3.3 V or 1.5 V.
3

PCH (POWER2)
Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

24

of

105

SSID = PCH
PCH1I

PCH1H

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

8 OF 10

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79

VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

PANTHER-GP-NF

71.PANTH.00U
A

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258

9 OF 10

VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS328
VSS329
VSS330
VSS331
VSS333
VSS334
VSS335
VSS337
VSS338
VSS340
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PANTHER-GP-NF

PCH (VSS)

71.PANTH.00U

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

25

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

26

of

105

R2724
64K9R2F-1-GP

1
2

C2717
SCD1U10V2KX-5GP

EC_AGND

C2710
SCD1U10V2KX-5GP

EC_VBKUP

47.0K

100.0K

64.9K

2.0V

100.0K

76.8

1.87V

Reserved

100.0K

100.0K

1.65V

Reserved

100.0K

143.0K

1.358V

Reserved

100.0K

174.0K

1.204V

Reserved

100.0K

215.0K

1.048V

1
MODEL_ID_DET

C2718
SCD1U10V2KX-5GP

R2739
100KR2F-L1-GP

DY

EC_AGND

PULL-HIGH RESISTOR

VOLTAGE
3.0V
2.902V
2.801V
2.702V
2.598V
2.492V
2.402V
2.304V
2.201V
2.093V
2.001V
1.905V
1.808V
1.709V
1.594V
1.499V
1.392V
1.299V
1.099V
0.994V

10.0K(64.10025.6DL)
13.7K(64.13725.6DL)
17.8K(64.17825.6DL)
22.1K(64.22125.6DL)
27.0K(64.27025.6DL)
32.4K(64.32425.6DL)
37.4K(64.37425.6DL)
43.2K(64.43225.6DL)
49.9K(64.49925.6DL)
57.6K(64.57625.6DL)
64.9K(64.64925.6DL)
73.2K(64.73225.6DL)
82.5K(64.82525.6DL)
93.1K(64.93125.6DL)
107K(64.10735.6DL)
120K(64.12035.6DL)
137K(64.13735.6DL)
154K(64.15435.6DL)
200K(64.20035.6DL)
232K(64.23236.6DL)

RTC_AUX_S5

90
92
86
87
91
117
112
110

114

75

1 0F 2

X03 2/6
R2778

LRESET#/GPIOF7
LCLK/GPIOF5
LFRAME#/GPIOF6
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2
LAD0/GPIOF1
SERIRQ/GPIOF0
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO85/GA20
KBRST#/GPIO86

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO5/AD4
GPIO4/AD5
GPIO3/AD6
GPIO7/AD7
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
GPIO97/DA3

GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

0R0402-PAD-2-GP
1
2
CLK_PCI_KBC [18]
LPC_FRAME# [21,71]

PLT_RST#_EC

7
2
3
1
128
127
126
125
8
9
29
124
121
122

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

INT_SERIRQ [21]
PM_CLKRUN#_EC
L_BKLT_EN [17]

ECSCI#_KBC

MOBILITY_CENTER#
H_A20GATE [22]
H_RCIN# [22]

27
25
11
10
71
72

BLON_OUT [49]
AD_IA_HW2 [40]
PWR_CHG_AD_OFF
INSTANT_LAUNCH#
TPDATA [69]
TPCLK [69]

AD_IA_HW2

PLT_RST# [5,18,31,65,66,71]
LPC_AD[3..0]

[21,71]

[19]

F_CS0#
F_SCK
F_SDI&F_SDIO1
F_SDIO&F_SDIO0
GPIO81/F_WP#

PSL_OUT_GPIO71#
PSL_IN2_GPI06#
PSL_IN1_GPI70#

GPIO20/TA2/IOX_DIN_DIO
GP/I/O84/IOX_SCLK/XORTR#
GPO82/IOX_LDSH/TEST#

70
69
67
68
119
120
24
28

31
63
64

[68] PWRLED#
[82] KBC_BEEP
[82] INSTANT_LAUNCH#_LED#
[38] AC_IN_KBC#
[82] AUDIO_PRESENT#_LED#
[19] PCH_WAKE#_EC
[82] MOBILITY_CENTER#_LED#
[68] CHG_AMBER_LED#

32
118
62
65
22
81
66
16

[82]
[65,66]

ECRST#
VCCP_CPU

R2721
1 43R2J-GP2
1
2

PROCHOT_EC

Need very close to EC

X03 2/6

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

[69]

KROW[0..7]

[69]

X03 2/6
ECSCI#_KBC

[22] EC_SCI#

R2764

2 0R0402-PAD-2-GP

[22] EC_SMI#

R2723

2 0R0402-PAD-2-GP

ECSMI#_KBC

[20] EC_SWI#

R2727

2 0R0402-PAD-2-GP

ECSWI#_KBC

X01 12/02
C2712
SC1U25V3KX-1-GP

For System Reset.

PM_CLKRUN#_EC

R2730

DY

2 0R2J-2-GP

H_A20GATE

R2731

DY

2 0R2J-2-GP

BOOST_MODE# [40]
DGPU_PWROK

[22,86,92,93]

3D3V_AUX_S5
1

X01 12/02

Layout Note:
Connect GND and AGND planes via either
0R resistor or connect directly.

ECRST#
3D3V_AUX_KBC

R2705
10KR2J-3-GP
2

X03 2/6

Need very close to EC

R2765
0R0402-PAD-2-GP
EC_AGND

R2713
10KR2B-GP

PECI
VTT

54
55
56
57
58
59
60
61

KCOL[0..16]

Layout Note:

X03 2/6
1

VCC_POR#

13
12

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
USB_DET#

NPCE885PA0DX-1-GP

Layout Note:

EC_AGND 103

VBAT

PECI
EC_VTT

KBSIN0/GPIOA0/N2TCK
KBSIN1/GPIOA1/N2TMS
KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
KBSIN6/GPIOA6
KBSIN7/GPIOA7

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

KBC_VCORF

44

AGND

GND1
GND2
GND3
GND4
GND5
GND6
18
45
78
89
116
5

AOAC Ambient temperature detect

GPIO0/EXTCLK
GPIO55/CLKOUT/IOX_DIN_DIO

85

R2720
0R0402-PAD-2-GP

LCD_TST_EN [49]
LCD_TST [49]

1 R2792 2
0R0402-PAD-2-GP
PSL_OUT#
PSL_IN2#
PSL_IN1#

74
93
73

Charger
PCH

KBSOUT0/GPOB0/JENK#
KBSOUT1/GPIOB1/TCK
KBSOUT2/GPIOB2/TMS
KBSOUT3/GPIOB3/TDI
GPIO15/A_PWM
KBSOUT4/GPOB4/JEN0#
GPIO21/B_PWM
KBSOUT5/GPIOB5/TDO
GPIO13/C_PWM
KBSOUT6/GPIOB6/RDY#
GPIO32/D_PWM
KBSOUT7/GPIOB7
GPIO45/E_PWM
KBSOUT8/GPIOC0
GPIO66/G_PWM
KBSOUT9/GPOC1/SDP_VIS#
GPIO33/H_PWM
KBSOUT10&P80_CLK/GPIOC2
GPIO40/F_PWM
KBSOUT11&P80_DAT/GPIOC3
KBSOUT12/GPIO64
KBSOUT13/GPIO63
GPIO46/CIRRXM/TRIST#
KBSOUT14/GPIO62
GPIO87/CIRRXM/SIN_CR
KBSOUT15/GPIO61/XOR_OUT
GP/I/O83/SOUT_CR/TRIST#
GPIO60/KBSOUT16
GPIO57/KBSOUT17

77
30

[19] PCH_SUSCLK_KBC
[82] AMP_MUTE#

TP

GPIO56/TA1
GPIO14/TB1
GPIO1/TB2

23
113
111

[21] ME_UNLOCK
AOAC_PCIE_WAKE#
[65] E51_TxD

[38]
[82]

BAT_SCL [39,40]
BAT_SDA [39,40]
SML1_CLK [20,28,85]
SML1_DATA [20,28,85]
PM_LAN_ENABLE [31]
RTCRST_ON [21]

VCORF

NPCE885PA0DX-1-GP

[28,36,85]

PURE_HW_SHUTDOWN#

84.T3906.A11
2nd = 84.03906.F11

C2715

RN2702

USB_DET#
MOBILITY_CENTER#
INSTANT_LAUNCH#
AUDIO_PRESENT#

1
2
3
4

8
7
6
5

RSTSW1
SW-TACT-130-GP-U

SRN100KJ-5-GP

62.40009.731
2nd = 62.40089.441

X03 2/6
G
H_PROCHOT#_EC

R2732
100KR2J-1-GP

R2733
0R0402-PAD-2-GP
1
2

3D3V_AUX_KBC
H_PROCHOT#

3
4

2
1

3D3V_WLAN_AOAC

SRN4K7J-8-GP
2

Power Switch Logic(PSL)

X01 12/09

RN2701
BAT_SCL
BAT_SDA

C2713
SC47P50V2JN-3GP

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

[5,40]

ECRST#

R2707 1

2 10KR2J-3-GP

R2706
100KR2J-1-GP

3D3V_AUX_S5

C2722
SCD1U10V2KX-5GP

3D3V_AUX_S5

R2704
330KR2J-L1-GP

X01 12/21

KBC_ON#_GATE_L

KBC_ON#_GATE

[40] AC_IN#

DY

84.02130.031
2ND = 84.03413.A31

1AOAC_PCIE_WAKE#_R

DY

3D3V_WWAN_AOAC

1
CH715FPT-GP

2 100KR2J-1-GP
2 100KR2J-1-GP

83.R0304.B81
2nd = 83.00040.E81

R2791
0R2J-2-GP

3D3V_S0

R2711
100KR2J-1-GP

Q2703
DMP2130L-7-GP

R2735
20KR2J-L2-GP

1KR2J-1-GP
PSL_IN1#

DY

G
D

R2768
0R0402-PAD-2-GP
1
2

DY

3D3V_LAN_S5
AC_IN_KBC# R2714 1
BAT_IN#
R2715 1

S
1

R2701
100KR2J-1-GP

PSL_OUT#

AOAC_PCIE_WAKE#

3D3V_AUX_KBC

PSL_IN2#

3D3V_AUX_S5

X01 12/13
R2716

R2767
0R0402-PAD-2-GP
1
2

X03 2/6

[68] KBC_PWRBTN#

R2734
330KR2J-L1-GP

3D3V_WLAN_AOAC
D2702
1

X01 12/20
X01 12/09

FAN_TACH1
3D3V_AUX_KBC

R2708 1

2 10KR2J-3-GP

PCIE_WAKE#

DY

Q2702
PROCHOT_EC

EC_AGND

C2725

C2726
SCD1U10V2KX-5GP

69.60013.131
2nd = 69.60011.201
3rd = 69.60037.011

R2740
0R2J-2-GP
1
2

SC100P50V2JN-3GP

R2703
NTC-10K-27-GP

EC_GPIO47 High Active

DY

B
Q2701
MMBT3906-4-GP

AMB_TEMP

[28] FAN_TACH1
[31] PCIE_WAKE#
[19,36,37,47] PM_SLP_S3#

[5,22] H_PECI
GPIO17/SCL1/N2TCK
GPIO22/SDA1/N2TMS
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4

2 0F 2

U2701B

DY

VBKUP

VSBY

102

VDD

VREF

GPIO02
GPIO24
GPIO30/F_WP#
GPIO34/CIRRXL
GPIO36
GPIO41/F_WP#
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO51/N2TCK
GPIO67/N2TMS
GPIO75
GPIO76
GPIO77

C2711
SC220P50V2KX-3GP
1
2

X01 12/12

EC_SPI_CS#_C
EC_SPI_CLK_C
EC_SPI_DI_C
EC_SPI_DO_C

[19] PM_PWRBTN#
[19] AC_PRESENT
[82] USB_PWR_EN#

2.24V

R2736 2
R2719 2
R2725 2
R2722 2

1
1
1
1

100.0K

A00

100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K

C2716
SCD1U10V2KX-5GP

33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP

[21,60] SPI_CS0#_R
[21,60] SPI_CLK_R
[21,60] SPI_SO_R
[21,60] SPI_SI_R
[68] TP_LOCK_LED#

X03

TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD

R2710
10KR2F-2-GP

79
6
109
14
15
80
17
20
21
26
123
82
83
84

ECSWI#_KBC

Need very close to EC

2.48V

3G_EN
ECSMI#_KBC

[65] WIFI_RF_EN
[65] AOAC_WLAN_EN#
[19,36] S0_PWR_GOOD

Layout Note:

33.0K

PULL-LOW RESISTOR

[28] FAN1_DAC
[40] AD_IA_HW
[82] AUDIO_PRESENT#
[36,42] IMVP_PWRGD

100.0K

101
105
106
107

[66] 3G_EN

X02

MODEL_ID_DET

[69] CAP_LED#
[36] S5_ENABLE
[68] BATT_WHITE_LED#
[39] BAT_IN#
[70] LID_CLOSE#
[19] RSMRST#_KBC
[19,46] PM_SLP_S4#
[62] USBCHG_EN

2.75V

97
98
99
100
108
96
95
94

AMB_TEMP

[66] AOAC_WWAN_EN#
[28] VGA_THRM
[62] USBCHARGER_CB0

3.0V

20.0K

SC1U6D3V2KX-GP

2 SCD1U10V2KX-5GP
PCB_VER_AD

10.0K

100.0K

C2714

104

AVCC

VCC1
VCC2
VCC3
VCC4
VCC5

EC_AGND
[40] AD_IA

[38] PSID_EC

100.0K

X01

MODEL_ID_DET(GPIO07)

R2794
0R0402-PAD-2-GP

U2701A

EC_AGND

X00

3D3V_AUX_S5

X03 2/6

19
46
76
88
115

1
2

DY

C2709
SC2D2U10V3KX-1GP
2
1

C2708
SCD1U10V2KX-5GP

1
2

DY

C2707
SCD1U10V2KX-5GP

C2706
SCD1U10V2KX-5GP

1
2

DY

C2705
SCD1U10V2KX-5GP

C2704
SCD1U10V2KX-5GP

1
2

C2701
SC2D2U10V3KX-1GP
2
1

DY

3D3V_AUX_KBC_VCC

R2726
100KR2F-L1-GP

DY

1
VBAT

VOLTAGE

Reserved

PCB_VER_AD
C2703
SC2D2U10V3KX-1GP

C2702
SCD1U10V2KX-5GP

VBAT

R2771
2D2R3-1-U-GP

R2702
1
2
0R0603-PAD-2-GP

X03 2/6

PULL-HIGH RESISTOR

A00 3/15
X03 2/16
X01 12/02

3D3V_S0

PULL-LOW RESISTOR

VBAT

3D3V_AUX_KBC

PCB VERSION A/D(PIN98)

VBAT

SSID = KBC

3D3V_AUX_KBC
1

3D3V_S5

D2707
USB_DET#

X01 12/21
X01 12/13
X01 12/02

R2709
10KR2J-3-GP

Q2704

G
2

KBC_ON#_GATE_L

BAT54CPT-GP

LID_CLOSE#

[62] USBDET_CON#

3G_EN

R2712 1

2 10KR2J-3-GP

<Core Design>

2100KR2J-1-GP

Wistron Corporation

S5_ENABLE

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

S
VGA_THRM

83.R2003.E81
2ND = 83.00054.Q81

C2720 2

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

DY

R2799 1

DY1SCD1U10V2KX-5GP
EC_AGND

Title

KBC Nuvoton NPCE885

Size
A2

Document Number

Date:

Tuesday, April 03, 2012

Rev

A00

BMW Z4 DIS
Sheet

27

of

105

SSID = Thermal
3D3V_S0
RN2801

2
1

3
4

Fan controller

SRN2K2J-1-GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

Q2804
2N7002KDW -GP

C2803

G991P11U-GP

74.00991.031
2nd = 74.02793.A31
3rd = 74.05606.A71

Layout Note:

THM_SML1_CLK

Need 10 mil trace width.

GND
GND
GND
GND

C2804
SCD1U10V2KX-5GP

FON#
VIN
VO
VSET

[27] FAN1_DAC

1
C2814
2

SC10U6D3V3MX-GP

C2813
SCD1U10V2KX-5GP

THM_SML1_DATA

[20,27,85] SML1_DATA

8
7
6
5

DY

5V_S0

U2802

1
2
3
4

SC4D7U6D3V3KX-GP

R2802
0R2J-2-GP
FON#
1
2
5V_S0
FAN_VCC

3D3V_S0

[20,27,85] SML1_CLK

84.03904.L06
2ND = 84.03904.P11
NCT7718_DXP

X03 2/6

ALERT#

R2815

2 18K7R2F-GP

T_CRIT#

R2814

2 2KR2F-3-GP

FAN_VCC

2
3

DY

D2802

DY

ACES-CON3-11-GP
C

20.F0772.003
2nd = 20.F1841.003

83.R5003.C8F
2ND = 83.R5003.H8H
3rd = 83.5R003.08F

Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

3D3V_S0

FAN_TACH1_C 1

AFTP2801

FAN_VCC

AFTP2802

EMI

X01 12/02
1

GPU thermal sensor

C2810

DY SC2200P50V2KX-2GP
2

C2815

4
1

Signal Routing Guideline:

Trace width = 15mil

Layout Note:
C2812 close U2801

C2809
SC4D7U6D3V3KX-GP

Layout Note:

3D3V_S0

FAN1
FAN_TACH1_C

T_CRIT#
2
0R0402-PAD-2-GP

DY

SCD1U10V2KX-5GP

1
R2813

SCD1U10V2KX-5GP
2
1

THERM_SYS_SHDN#

DY

74.07718.0B9

X03 2/13

R2807
0R0402-PAD-2-GP
1
2

[27] FAN_TACH1

NCT7718W -GP

2.System Sensor, Put on palm rest

C

ALERT#

NCT7718_DXN

THM_SML1_CLK
THM_SML1_DATA

8
7
6
5

CH551H-30PT-GP

1
C2812
SC2200P50V2KX-2GP

SCL
SDA
ALERT#
GND

C2808

C2816
SC470P50V3JN-2GP

VDD
D+
DT_CRIT#

DY

1
Q2803
PMBS3904-1-GP

U2801

1
2
3
4

C2817
SCD1U10V2KX-5GP

FAN_VCC

DY

[85] P2800_VGA_DXP

U2803

DY

DY

[85] P2800_VGA_DXN

TDR
TDL
GND
ADJ

4
3
2
1

VGA_THRM [27]
1

MISC_THRM

TP2803

TPAD14-OP-GP

DY
2

VCC
DXP
DXN
OTZ

5
6
7
8

EC2801
SCD1U16V2KX-3GP

R2837
402KR2F-GP

DY
2

VGA_THRM
C2818
SC2200P50V2KX-2GP

P2800EB0-GP

74.02800.B71

Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

Thermal Sensor
ADJ

Q2802

Temp.(C)

Pull high

95

Pull low

90

85

<Core Design>

Wistron Corporation

3D3V_S0

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

G
C2811
SCD1U10V2KX-5GP

Floating

THERM_SYS_SHDN#

[27,36,85] PURE_HW _SHUTDOW N#

DY

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

Title

Thermal NCT7718W/Fan Controllor P2793

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

28

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

29

of

105

(Blanking)
C

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

30

of

105

SSID = LOM
Q3106
PA102FMG-GP-U

1
2

D
1

Layout Note:
Close to pin13

[20] PCIE_RXP6
[20] PCIE_RXN6

C3118
C3117

[20] CLK_PCIE_LAN
[20] CLK_PCIE_LAN#

33
32

REFCLK_P
REFCLK_N

[20] PCIE_TXP6
[20] PCIE_TXN6

35
36

RX_P
RX_N

30
29

TX_P
TX_N

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

1
1

[59] LAN_MDI0P
[59] LAN_MDI0N

11
12

TRXP0
TRXN0

[59] LAN_MDI1P
[59] LAN_MDI1N

14
15

TRXP1
TRXN1

[27] PCIE_W AKE#

Layout Note:

PCIE_RXP6_L
PCIE_RXN6_L

3
4

CLK_LAN_REQ#_R

38
39
23

SMDATA
SMCLK

26
25

LAN_SMDATA
LAN_SMCLK

8
7

LAN_XTAL1
LAN_XTAL0

RBIAS
PERST#
ISOLAT#

10
2
5

RBIAS
PLT_RST#_LAN
ISOLATn
LOM_PPS 1

X03 2/6

3D3V_S0
TP3104

TPAD14-OP-GP

XTLI
XTLO

PPS

24

TESTMODE

27

LX

40

NC#17
NC#18
NC#19
NC#20
NC#21
NC#28

17
18
19
20
21
28

GND

41

WAKE#
CLKREQ#

R3136
30KR2J-4-GP

C3110
SCD1U10V2KX-5GP

DY

ISOLATn
RBIAS
TP3103

TPAD14-OP-GP

R3131
2K37R2F-GP
LX

1
2

1
2

C3112
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

Close to pin13

DVDDL_REG

AVDDH
DVDDL

C3119

Layout Note:

37

AVDDVCO

Close to pin1

C3106

C3107

AVDD33
AVDDL
AVDDL
AVDDL
AVDDL_REG
AVDDH_REG
AVDDH

Close to pin16

LED0
LED1
LED2

VDD33

16
13
31
34
6
9
22

Layout Note:

Layout Note:
AVDDL

U3101

AVDDL

1
2

1
2

1
2

1
2

1
2

DY

C3113
SCD1U10V2KX-5GP

C3114
SC1U6D3V2KX-GP

C3105
SC1KP50V2KX-1GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C3104

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

A00 3/23

3D3V_LAN_S5

C3103

2N7002K-2-GP

3D3V_LAN_S5

C3102

S
1

R3113
0R0402-PAD-2-GP

R3117
20KR2J-L2-GP

DY

R3122
100KR2J-1-GP

CLK_LAN_REQ#_R

0R2J-2-GP

C3101

1
Q3105

[27] PM_LAN_ENABLE

1
PLT_RST#_LAN

2PM_LAN_ENABLE_R

C3134

DY

Q3102
PMBS3904-1-GP

R3106

C3133

C3130
SC1U6D3V2KX-GP

PLT_RST#

1Q402_14
3

2
Q3101
PMBS3904-1-GP
3

[20] PCIE_CLK_LAN_REQ#

[5,18,27,65,66,71]

84.03904.L06
2ND = 84.03904.P11

R3116
10KR2J-3-GP

SCD1U10V2KX-5GP

CLK_LAN_REQ#_EN

S
C3132
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R3103
10KR2J-3-GP

RN3101
SRN10KJ-5-GP

LAN_ENABLE_R_C
2

DY

1
R3102
10KR2J-3-GP

3D3V_LAN_S5

84.00102.031
2nd = 84.02301.G31

3D3V_S5

3D3V_LAN_S5

3D3V_LAN_S5

Close to pin31
AR8162-AL3A-R-GP

71.08162.A03
AVDDH
B

DVDDL

L3102
BLM18KG601SN1D-GP

L3101
BLM18KG601SN1D-GP

68.00084.G71
2nd = 68.00335.091
3rd = 68.00230.131

68.00084.G71
2nd = 68.00335.091
3rd = 68.00230.131

Layout Note:
Close to pin37

Close to pin34
X3101
LAN_XTAL1

4
<Core Design>

LAN_XTAL0

XTAL-25MHZ-155-GP

Wistron Corporation

C3129
SC18P50V2JN-1-GP

82.30020.D41
2nd = 82.30020.G61

C3128
SC18P50V2JN-1-GP

DY
2

1
2

1
2

1
2

EC3101
SCD1U10V2KX-5GP

1
2

DY

C3124

Layout Note:

DY
2

1
2

68.4R71E.10R
2nd = 68.4R71G.10G

C3123

SC1U6D3V2KX-GP

L3103
IND-4D7UH-253-GP

C3125

SCD1U10V2KX-5GP

DY

C3126

SC10U6D3V5KX-1GP

2
C3127

SCD1U10V2KX-5GP

C3121
SC1U10V2KX-1GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

X01 12/15

C3120

SC1KP50V2KX-1GP

EC3122

X03 1/30
LX

Close to pin22

X01 12/15

Layout Note:

C3116

1
2

Close to pin9

Layout Note:

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

C3108

AVDDVCO

AVDDVCO

C3109

AVDDL

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Document Number

Date:

Friday, March 30, 2012

LOM

Rev

BMW Z4 DIS

A00
Sheet
1

31

of

105

(Blanking)

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

32

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
E

33

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

34

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

35

of

105

SSID = Reset.Suspend
2
D3601
BAS16-6-GP

[19,27] S0_PW R_GOOD

2
1
3

D3602
BAS16-6-GP

1
R3614
0R0402-PAD-2-GP
1
2

R3602
200KR2J-L1-GP

C3612
SCD01U50V2KX-1GP

S5_ENABLE [27]

R3603
1KR2J-1-GP

DY
2

Q3603
PS_S3CNTRL

DY

SYS_PW ROK [19]

[27,42] IMVP_PW RGD

[27,28,85]

83.00016.K11
2ND = 83.00016.F11

83.00016.K11
2ND = 83.00016.F11 X03 2/6

PURE_HW _SHUTDOW N#

[41] 3V_5V_EN

D
S
2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

ROSA Run Power

Rds(on) = 11 ~ 14mOhm
AO4468 MAX 11.6A

15V_S5
5V_S5

R3604
100KR2J-1-GP

5V_S0

U3601
AO4468-GP
D
S
D
S
D
S
D
G

1
2
3
4

5V_S0
1

8
7
6
5

3D3V_AUX_S5
5V_RUN_ENABLE

R3605
10KR2J-3-GP

PS_S3CNTRL

PS_S3CNTRL [37,93]

C3608
SCD01U50V2KX-1GP

C3603
SC10U6D3V5KX-1GP

5V_S0 Comsumption
Peak current 6A

84.04468.037
2nd = 84.04178.037
3rd = 84.02659.037

R3606
100KR2J-1-GP

Rds(on) =11 ~ 14mOhm

AO4468 MAX 11.6A

Q3602
2N7002KDW -GP

84.2N702.A3F
2nd = 84.DM601.03F

3D3V_S5

S G D 3rd = 84.2N702.E3F

8
7
6
5

4th = 84.2N702.F3F

3D3V_S0

PM_SLP_S3#

[21,37] RUN_ENABLE

C3605
SCD01U50V2KX-1GP

R3607
10KR2J-3-GP

3.3V_RUN_ENABLE

C3604
SC10U6D3V5KX-1GP

[19,27,37,47]

3D3V_S0

1
2
3
4

3D3V_S0 Comsumption
Peak current 2.5A

U3602
AO4468-GP
D
S
D
S
D
S
D
G

D G S

84.04468.037
2nd = 84.04178.037
3rd = 84.02659.037

1D5V_S3

1D5V_S0

1D5V_S0
D
D
D
D

U3606
S
S
S
G

1
2
3
4

8
7
6
5
2

R3630
10KR2J-3-GP

1.5V_RUN_ENABLE

TPCA8062-H-GP

C3609
SC10U6D3V5KX-1GP

TPCA8062-H-GP MAX 28A

Rds(on) = 4.1~5.6m Ohm
MAX Current 6A
<Core Design>
A

Wistron Corporation

84.08062.037
2nd = 84.00460.037

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

C3610
SCD01U50V2KX-1GP

Title

Power Plane Enable

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

36

of

105

SSID = Reset.Suspend

Close to DIMM
S3 Power Reduction Circuit PM_DRAM_PWRGD

1D5V_S0

0D75V_S0

Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation

R3703
22R2J-2-GP

Q3701_D

DY

M_VREF_DQ_DIMMA

+V_SM_VREF_CNT
Q3708

R3704
220R2J-L2-GP

DY

R3707
0R2J-2-GP
1
2

Q3702_D2

S
2

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

R3705
100KR2J-1-GP

DY

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

[36,93] PS_S3CNTRL

84.2N702.J31
2ND = 84.2N702.031

2N7002K-2-GP

Q3702
2N7002K-2-GP

Q3701
2N7002K-2-GP

[36,93] PS_S3CNTRL

[21,36] RUN_ENABLE

X03 2/6
R3710
0R0402-PAD-2-GP
1
2

[45,48] 1D05V_VTT_PW RGD

Close to CPU
S3 Power Reduction Circuit SM_DRAMRST#

1
R3716

PM_SLP_S3#

0D75V_EN

2
DY 22R2J-2-GP

1D5V_S3

DY

C3705
SCD1U10V2KX-5GP

0D75V_EN [46]

[19,27,36,47]

Q3704

R3706
1KR2J-1-GP

G
D

Q3703

S
S

[5] SM_DRAMRST#

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
PM_DRAM_PWRGD must have a maximum of 15ns rise or fall time
over VDDQ * 0.55 200mV and the edge must be monotonic

SM_DRAMRST#_D 1

DDR3_DRAMRST#

[14,15]

R3718
1KR2J-1-GP

[20] DRAMRST_CNTRL_PCH

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

C3703
SCD047U10V2KX-2GP
B

S3 Power Reduction Circuit

SM_DRAMRST#

0D75V_EN

[36,93] PS_S3CNTRL

C3702
SC100P50V2JN-3GP
B

Close to CPU
S3 Power Reduction Circuit PM_DRAM_PWRGD
1D5V_S0

X01 11/28

3D3V_S0

R3714
10KR2J-3-GP

DY
[19] PM_DRAM_PW RGD

U3701

PM_DRAM_PW RGD

R3702
200R2F-L-GP

X01 12/02

5
1D05V_VTT_PW RGD

2
VDDPW RGOOD_R

VDDPW RGOOD [5]

TC7SZ08FU-2-GP

73.7SZ08.EAH
2ND = 73.01G08.L04
3rd = 73.7SZ08.DAH

R3719
910R2F-1-GP

R3722

R3720
750R2F-GP

DY 39R2J-L-GP

Q3709
DMB40

[36,93] PS_S3CNTRL

DY

VDDPW RGOOD_D

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

S
2N7002K-2-GP

PM_DRAM_PW RGD
5

R3717
0R2J-2-GP
1

DY

Title

S3 Power Reduction
2

VDDPW RGOOD_R
4

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

37

of

105

SSID = PWR.Support

PD3803
BAV99-5-GP-U

PSID_DISABLE#_R_C

PR3811
100KR2J-1-GP

3D3V_S5

PMBS3904-1-GP
PQ3802

PQ3802_1 1

3D3V_S5
PR3803
10KR2J-3-GP

84.03904.L06
2nd = 84.03904.P11

PR3802
15KR2J-1-GP

5V_S5

PR3806
2K2R2J-2-GP

PR3819

PR3807
PS_ID_R2

1
2
0R0603-PAD-2-GP

PS_ID_R

83.00099.T11
2nd = 83.3X101.011

PQ3801
FDV301N-NL-GP

X03 2/6

X03 2/6

PS_ID

PSID_EC [27]

33R2J-2-GP

84.00301.A31
2nd = 84.3K329.031
PR3808

DY
3

Layout Note:
PSID Layout width > 25mil

PD3804

DY

33R2J-2-GP

SM24DTCT-GP-U

DCIN1

R1

E
R2
PDTC124EU-1-GP

PC3806
SC10U25V5KX-GP

1
2

PC3804
SCD01U50V2KX-1GP

PC3803
SCD01U50V2KX-1GP

1
2

PC3805
SCD01U50V2KX-1GP

PR3809
240KR3-GP

Id=-9.6A
Qg=-25nC
Rdson=18~30mohm

PR3810
47KR3J-L-GP

PDTA124EU-1-GP

8
7
6
5

SI7121DN-T1-GE3-GP

1
AD_OFF_R

X01 12/19
D
D
D
D

84.06675.030
2nd = 84.07121.037

E
C

PU3801
S
S
S
G

84.00124.K1K
2nd = 84.05124.A11

84.00124.H1K
2nd = 84.05124.011

AD_OFF_L

R1

PQ3809
2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

PQ3804

AD+

1
2
3
4

PQ3805
PR3814
100KR2J-1-GP

83.P6SBM.AAG
2nd = 83.22R03.03G
R2

DY

PC3801
SC1U25V5KX-1GP

2
PQ3809_D

22.10261.401

PC3802
SCD1U25V3KX-GP

PD3801
P6SBMJ24APT-GP

3K3R6J-GP

DC-JACK255-GP

PR3816

X03 1/30
6
7
8
9

+DC_IN

5
4
3
2
1

X01 12/02
PQ3810

[27] PW R_CHG_AD_OFF

G
B

AC_IN#_G
B

[27] AC_IN_KBC#

DY

84.2N702.J31

2N7002K-2-GP
PR3815
100KR2J-1-GP

DY

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

DCIN

Rev

A00

BMW Z4 DIS
Sheet
1

38

of

105

SSID = PWR.Support

BT+

Batt CONN

C3901
SC2200P50V2KX-2GP

DY

X01 12/02

PD3903
1SMA18AT3G-GP

BATT1

DY
2

C3902
SCD1U50V3KX-GP

11
9
8
7
6
5
4
3
2

X01 12/20
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
SYS_PRES1#

A00 3/15
X01 12/02

2100R2J-2-GP
2100R2J-2-GP
2100R2J-2-GP

SYS_PRES1#

SYS_PRES1#

EC3901
SC10P50V2JN-4GP

EC3902
SC10P50V2JN-4GP

DY DY

R3901
0R2J-2-GP

1
10

DY

R3902 1
R3903 1
R3904 1

[27,40] BAT_SCL
[27,40] BAT_SDA
[27] BAT_IN#

1
4

6
3
NP2
2
NP1

SYN-CON9-24-GP

20.81755.009
2nd = 20.81771.009

BATSW 1
SW -SLIDE77-GP

AFTP3902
AFTP3903
AFTP3904
AFTP3905

62.40068.021
2nd = 62.40018.641

PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+

X01 12/02
BAT_SCL

DY

BAT_SDA

BAT_IN#
D3902
BAV99-5-GP-U

83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11

D3901
BAV99-5-GP-U

D3903
BAV99-5-GP-U

DY

DY

83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11

Note: Mark the ON/OFF on the MB.

1
1
1
1

83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
B

3D3V_AUX_KBC

Layout Note:
Place near Battery CONN

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

BATT CONN

Rev

BMW Z4 DIS

A00
Sheet
1

39

of

105

SSID = Charger

PWR_CHG_ILIM

10

SRP
ILIM

3D3V_AUX_KBC

[27] BOOST_MODE#

PR4019

2 10R2F-L-GP

2
7D5R2F-GP

1
2

EC4002
SCD1U25V2ZY-1GP

9
D1
Q2
10 D2/S1

5 S2

PC4019

DY

NC#11

CHG_AGND

DY

CHG_AGND

CHG_AGND

PWR_CHG_CSON_1

DY

PWR_CHG_ACOK

PWR_CHG_CSOP_1

CHG_AGND

PR4028
100KR2J-1-GP

PR4039
100KR2J-1-GP

PC4021
SCD1U25V2KX-GP
2
1
2

PWR_CHG_REGN

3D3V_AUX_S5

AD_IA [27]

2
PR4027
100KR2J-1-GP

[27] AC_IN#

PR4022
0R0402-PAD-2-GP

PC4023
SCD1U25V2KX-GP

PG4011
2

GAP-CLOSE-PWR-3-GP

CHG_AGND

CHG_AGND

1
1 PC4022
SC220P50V2JN-3GP

1
3D3V_AUX_S5

PWR_CHG_IOUT

X03 2/16

14

BQ24727RGRR-GP

74.24727.073
X01 12/12

IOUT

1 PR4024
8K45R2F-2-GP

GND

GND

ACOK#

21

3D3V_AUX_KBC

PWR_CHG_CMPOUT

1
PR4012

A00 3/23
5

DY

DY

PWR_CHG_SRN

DY PR4026
100KR2J-1-GP

PR4035
10KR2F-2-GP

PQ4001
2N7002A-7-GP

CHG_AGND

DY

1 PWR_CHG_IFAULT
11

PWR_CHG_SRP

12

PR4018
0R2J-2-GP

DY 32K4R2F-1-GP

13

SRN

PR4023

68.2R210.20T
2nd = 68.2R21D.10Y

SCD1U25V3KX-GP

LODRV

SDA

PWR_CHG_BAT_SDA 8
1
GAP-CLOSE-PWR-3-GP

BT+_R

SCL

2
PG4008

2
PG4007

EC4001
SC2200P50V2KX-2GP

4
D1

PC4018
SCD1U25V2KX-GP
2
1

BAT_SCL
BAT_SDA

PC4020
SCD1U25V2KX-GP
1

[27,39]
[27,39]

CHG_AGND
PR4017
100KR2J-1-GP

PWR_CHG_BAT_SCL 9
1
GAP-CLOSE-PWR-3-GP

BT+

PR4033
D01R3721F-GP-U

PL4001
1

IND-2D2UH-161-GP-U
CHG_AGND

3
D1

1
2
D1

2
1
G1
Q1

6 S2

7 S2

DY

PC4013
SC3300P50V3KX-1GP

SC10U25V5KX-GP
PC4017

15

PWR_CHG_LODRV

SC10U25V5KX-GP
PC4016

PWR_CHG_PHASE

Charger Current=1.25A

SC10U25V5KX-GP
PC4025

PWR_CHG_HIDRV

19

X01 12/21

PWR_CHG_CMPIN

18

84.07200.A37
2nd = 84.05524.037

PHASE

PWR_CHG_REGN

PU4002
FDMC7200S-GP

CMPIN

CMPOUT
HIDRV

PWR_CHG_BTST

16

DY

DY

17

8 G2

1
BTST
REGN

2
PC4007
SC1U25V3KX-1-GP

1
2

PWR_CHG_ACN
ACN

ACDET

PC4011
SCD047U25V2KX-GP

PG4012
GAP-CLOSE-PWR-3-GP
1
2

PR4014
3D3MR2J-GP

PG4002

PD4001
SD103AWS-1-GP
PR4009
0R3J-0-U-GP
1
2CHG_PHASE
K
A

PG4009
GAP-CLOSE-PWR-3-GP
1
2

1
PR4020
3K3R2F-2-GP

3D3V_AUX_KBC

VCC

PWR_CHG_CMPOUT

DY

GAP-CLOSE-PWR-3-GP
1

1
2

PWR_CHG_ACDET

PR4021
3K3R2F-2-GP

PR4013
49K9R2F-L-GP

PU4001
20

83.1R504.A8F
2nd = 83.1R504.B8F
CHG_AGND

CHG_AGND

3D3V_AUX_KBC

PR4011
19K1R2F-GP

PR4031
1

PC4012
SCD01U50V2KX-1GP

49K9R2F-L-GP
2

2
20R5J-GP
2

1
PR4010

PWR_CHG_ACP

316KR2F-GP

PWR_CHG_IOUT

CHG_AGND

CHG_AGND

PWR_CHG_VCC

PC4024
SCD1U25V3KX-GP

SC10U25V5KX-GP
PC4009

PC4004
SCD1U25V3KX-GP

SC10U25V5KX-GP
PC4006

PR4007

Id=-8.6A
Qg=-65nC
Rdson=15~18mohm

SC10U25V5KX-GP
PC4008

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F PR4008
4th = 84.2N702.F3F 20R5J-GP

84.06675.030
2nd = 84.07121.037

PC4002
SCD1U25V2KX-GP

DY

2N7002KDW-GP

8
7
6
5

AD+

PR4015
120KR2J-L-GP

D
D
D
D

SI7121DN-T1-GE3-GP

PR4006
0R2J-2-GP
2

ACP

PU4006
S
S
S
G

PR4025
470KR2J-2-GP

DY

1
2
3
4

AD+
PG4003
GAP-CLOSE-PWR-3-GP

PWR_CHG_ACOK

D01R3721F-GP-U

PC4003
SC1U25V3KX-1-GP
2
1

PQ4002

PC4010
SCD47U25V3KX-1GP

Id= -10A
Qg= -22nC
Rdson=14~13mohm

1
S

84.06675.030
2nd = 84.07121.037

2
PWR_CHG_CMPOUT

AD+_G_2

AD+_G_1

PQ4005
2N7002A-7-GP

84.2N702.E31
2nd = 84.2N702.J31

BT+
PR4002
1

PR4003
100KR2J-1-GP

1
PR4004
3KR5J-GP

PR4032
100KR2J-1-GP

1
2
3
4

SI7121DN-T1-GE3-GP

DC_IN_D

[5,27] H_PROCHOT#

PU4004
S
S
S
G

D
D
D
D

PR4001
10KR2F-2-GP

8
7
6
5

X03 1/30
D

PWR_CHG_REGN

DCBATOUT

AD+_TO_SYS

AD+

PQ4006
2N7002A-7-GP
G

AC_IN#

DY
S

PR4036
120KR2F-L-GP

84.2N702.E31
2nd = 84.2N702.J31

EC Code for BQ24727

H_PROCHOT#

AD_IA_HW

65W

AD_IA_HW2
0

90W

130W

PWR_CHG_CMPIN 1

PR4030
54K9R2F-L-GP
2

PQ4004
PQ4904_3

[27] AD_IA_HW2

CHG_AGND
AD_IA_HW
PQ4004_6 2

2N7002KDW-GP

[27]

PWR_CHG_CMPIN

PR4038
19K6R2F-GP
A

CHG_AGND

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CHARGER BQ24727
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

40

of

105

SSID = PWR.Plane.Regulator_5v3p3v
PWR_5V3D3V_VCLK

DY

1
2
0R0402-PAD-2-GP

PD4104
BZT52C15S-GP

2
3

PC4107
SCD1U25V3KX-GP

DCBATOUT

1
2

1
2

1
2

PWR_5V_CS1
1

PR4102
120KR2F-L-GP

VCLK

19

PWR_5V3D3V_VCLK

PR4103
33KR2F-GP

DY

GND

21

PR4119
100KR2J-1-GP

DY

GAP-CLOSE-PWR-3-GP
PG4128
1
2
PR4115
15KR2F-GP

GAP-CLOSE-PWR-3-GP
PG4129
1
2

PWR_5V_FB1_R
2

1 2

PR4114
0R2J-2-GP

GAP-CLOSE-PWR-3-GP
PG4130
1
2

DY

PC4125
SC18P50V2JN-1-GP

GAP-CLOSE-PWR-3-GP
PG4131
1
2

PR4121
10KR2F-2-GP

3D3V_PWR_2

3D3V_AUX_S5

X03 2/13
1

GAP-CLOSE-PWR-3-GP
PG4132
1
2

DY PC4128
2

SC1U6D3V2KX-GP
PC4126

3D3V_S5

5V_PWR_2

SC22U6D3V5MX-2GP

SC4D7U6D3V3KX-GP

PC4127

13

2
1

X01 12/13

GAP-CLOSE-PWR-3-GP
PG4126
1
2

X01 12/02

GAP-CLOSE-PWR-3-GP

PG4101
1
2

PWR_3D3V_FB2_R
PC4124
SC18P50V2JN-1-GP

74.51225.073

GAP-CLOSE-PWR-3-GP
PG4125
1
2

77.52271.09L
2nd = 77.92271.03L

GAP-CLOSE-PWR-3-GP
PG4127
1
2

TPS51225RUKR-GP
3D3V_PWR_2

GAP-CLOSE-PWR-3-GP
PG4124
1
2

VREG3

PGOOD

PC4123
SC560P50V-GP

77.52271.09L
2nd = 77.92271.03L

GAP-CLOSE-PWR-3-GP
PG4123
1
2

VREG5

84.07696.037
2nd = 84.00406.037

DY

SE220U6D3VM-30-GP
PT4104
2
1

PG4117 PC4120

PR4111
2D2R5F-2-GP

PWR_5V_EN1

1PWR_5V3D3V_VREG3

1 2

20

DY

GAP-CLOSE-PWR-3-GP
PG4122
1
2

68.1R510.10J
2nd = 68.1R51A.10E
1

D 8
D 7
D 6
D 5

PWR_3D3V_CS2

PR4117
10KR2F-2-GP
2

PWR_5V_FB1

GAP-CLOSE-PWR-3-GP
PG4121
1
2

1
2
IND-1D5UH-34-GP

SE220U6D3VM-30-GP
PT4103
2
1

CS1

PWR_5V_VO1

PL4101

GAP-CLOSE-PWR-3-GP
PG4120
1
2

Design Current = 12A

18A<OCP< 21.6A

CS2

14

PG4119
1

5V_PWR

2
EN1

PWR_5V_DRVL1

EN2

PWR_5V_LL1

15

84.03664.037
2nd = 84.06920.037

5V_S5

5V_PWR

DY

VFB1

18

FDMS3600-02-RJK0215-COLAY-GP

PC4116

PWR_3D3V_EN2

DY

X03 2/16

VFB2

16

PWR_5V_DRVH1

1PWR_5V_SNUB

1 S
2 S
3 S
4 G

1PWR_3D3V_SNUB
2

PWR_3D3V_FB2

PR4113
0R2J-2-GP

PR4112
6K65R2F-GP

GAP-CLOSE-PWR-3-GP

VIN
S
S
S
G
1
2
3
4
1
2

1
3D3V_TER

SE220U6D3VM-30-GP
PT4101
2
1

1
2

VO1

PU4106
SIS406DN-T1-GE3-GP

X01 12/12

GAP-CLOSE-PWR-3-GP
PG4143
1
2

DRVL1

PWR_5V_VBST1

PC4115

SCD1U10V2KX-4GP

DY

PC4121
SC330P50V3KX-GP

SW1

DRVL2

17

SCD1U25V3KX-GP
PC4118
2PWR_5V_VBST1_1 1
2

PC4130 PC4114

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
PG4142
1
2

DY D

DRVH1

SW2

X03 2/20
X03 2/16

SCD1U25V3KX-GP

77.52271.09L
2nd = 77.92271.03L
X01 12/02

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
PG4141
1
2

SCD1U10V2KX-4GP

DY

PR4110
2D2R5F-2-GP

PG4116

PWR_3D3V_DRVL211

VBST1

PR4109
1D5R3F-GP
1

7
6
5

SC10U25V5KX-GP

PC4119

GAP-CLOSE-PWR-3-GP
PG4140
1
2

PWR_3D3V_LL2

68.2R210.20B
2nd = 68.2R21B.10J

GAP-CLOSE-PWR-3-GP
PG4139
1
2

PL4102
2
1
IND-2D2UH-46-GP-U

GAP-CLOSE-PWR-3-GP
PG4138
1
2

PR4108
PC4117
1D5R3F-GP
1PWR_3D3V_VBST2_1
1
2 PWR_3D3V_VBST2
9
VBST2
SCD1U25V3KX-GP
PWR_3D3V_DRVH2
10
DRVH2

PC4129

SC10U25V5KX-GP

GAP-CLOSE-PWR-3-GP
PG4137
1
2

2
3
4
10

SC10U25V5KX-GP

PG4136
3D3V_PWR

PWR_DCBATOUT_5V
PU4102

SC10U25V5KX-GP

3D3V_PWR
2

PU4101

X01 12/12

84.08884.A37
2nd = 84.00412.037
PU4105
SIS412DN-T1-GE3-GP

PC4113

12

D 8
D 7
D 6
D 5

DY

1
2

PC4111
SC10U25V5KX-GP

SCD1U25V3KX-GP

SC10U25V5KX-GP

Design Current = 7.64A

12.1A<OCP< 14.2A

PC4110

SCD01U50V2KX-1GP

SC10U25V5KX-GP

PC4112
PC4109

PC4108
SCD1U25V3KX-GP

PWR_DCBATOUT_3D3V

GAP-CLOSE-PWR-3-GP

3D3V_S5

PC4106
SC1U25V3KX-1-GP

3V_5V_EN [36]

83.15R03.C3F
2nd = 83.15R03.E3F

GAP-CLOSE-PWR-3-GP
PG4110
1
2

PC4108_1

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
PG4109
1
2

PWR_3D3V_EN2

5V_PWR

PG4105
GAP-CLOSE-PWR-3-GP

X03 2/10

GAP-CLOSE-PWR-3-GP
PG4135
1
2

83.00054.Y81
2nd = 83.0R203.081

GAP-CLOSE-PWR-3-GP
PG4108
1
2

15V_PWR

83.00054.Y81
2nd = 83.0R203.081
15V_S5

PD4101
BAT54S-7F-GP

X03 2/10

PR4130
GAP-CLOSE-PWR-3-GP
PG4118
1
2

PD4103
BAT54S-7F-GP

PR4133
0R0402-PAD-2-GP

GAP-CLOSE-PWR-3-GP
PG4115
1
2

GAP-CLOSE-PWR-3-GP
PG4107
1
2

3PC4102_2 2

PR4131
0R2J-2-GP
1

GAP-CLOSE-PWR-3-GP
PG4106
1
2

PD4102
BAT54-7-F-GP

DY

GAP-CLOSE-PWR-3-GP
PG4114
1
2

PWR_5V_EN1_R

1
PR4127
1
2
0R0402-PAD-2-GP

GAP-CLOSE-PWR-3-GP
PG4104
1
2

X03 2/10
PWR_5V_EN1

GAP-CLOSE-PWR-3-GP
PG4113
1
2

PC4103

GAP-CLOSE-PWR-3-GP
PG4103
1
2

PR4132
0R2J-2-GP

DY

GAP-CLOSE-PWR-3-GP
PG4112
1
2

PC4102

GAP-CLOSE-PWR-3-GP
PG4102
1
2

PG4111
2

SC1KP50V2KX-1GP

PG4144
1

PC4104

PWR_DCBATOUT_3D3V

SCD1U25V3KX-GP

3D3V_AUX_S5

DCBATOUT

PWR_DCBATOUT_5V

SCD1U25V3KX-GP

DCBATOUT

3PC4103_2 2

X03 2/16

PR4116
0R0402-PAD-2-GP

GAP-CLOSE-PWR-3-GP
PG4133
1
2

PWR_5V3D3V_PGOOD

GAP-CLOSE-PWR-3-GP
PG4134
1
2
GAP-CLOSE-PWR-3-GP
PG4145
1
2
GAP-CLOSE-PWR-3-GP
PG4146
1
2
GAP-CLOSE-PWR-3-GP
PG4147
1
2
GAP-CLOSE-PWR-3-GP
PG4148
1
2
GAP-CLOSE-PWR-3-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

TPS51123_5V/3D3V
A

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
E

41

of

105

SSID = CPU.Regulator
VCCP_CPU
1
PR4224
1
PR4225
1
PR4226

[8] VR_SVID_ALERT#
H_CPU_SVIDDAT

[8] H_CPU_SVIDDAT

H_CPU_SVIDCLK

[8] H_CPU_SVIDCLK

2
75R2F-2-GP
2
130R2F-1-GP
2
54D9R2F-L1-GP

DY

Volterra's suggestion:
VCC 26x22uF(0805) 1-PHASE VCC
VCCAXG 23x22uF(0805) for 1-PHASE VCCAXG

boot voltage=0V

1
2

VT1318MFQX-1-GP

74.01318.B73

GND_1318

PWR_AXG_SENSE2_N

[8] VCCSENSE

1
2

DY

X02 2/13

PR4252
0R0402-PAD-2-GP
1
2
1

VCC_AXG_SENSE

PR4229
1K96R2F-1-GP
2

[44]

2
1KR2F-3-GP

[9]

VSS_AXG_SENSE [9]

X03 2/10

15KR2F-GP

PR4212
0R0402-PAD-2-GP

GND_1318

PWR_AXG_SENSE2_P

DY

PR4218
0R2J-2-GP

PR4246

X03 2/10

49
GND

R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE
R_OSC
R_SEL0
R_SEL1

48
47
46
45
44
43
42
41
40
39
38
37

PWR_AXG_IPH2_1_R
PWR_AXG_PWM2_1 [44]
PWR_AXG_TS_FAULT#2 [44]

13
14
15
16
17
18
19
20
21
22
23
24

1
2

PWR_VCORE_R_SEL5
PWR_AXG_PWM2_2
PWR_AXG_PWM2_1
PWR_AXG_TS_FAULT#2
PWR_AXG_IPH2_1
PWR_AXG_MRAMP2

SC10P50V2JN-4GP

PWR_VCORE_R_SEL2
PWR_VCORE_R_SEL3
PWR_VCORE_R_REF

15K4R2F-GP

36
35
34
33
32
31
30
29
28
27
26
25

PC4201

R_SEL2
R_SEL3
R_REF
IPH2_2
R_SEL5
PWM2_2
PWM2_1
TS_FAULT#2
IPH2_1
MRAMP2
SENSE2+
SENSE2-

PR4257

SENSE1+
SENSE1A_ERR1
A2_IN1
A2_OUT1
A3_IN1
A3_OUT1
A3_OUT2
A3_IN2
A2_OUT2
A2_IN2
A_ERR2

1
2

1
1
1
2
1

402R2F-GP

PR4210

20KR2F-L-GP

PR4209

0R0402-PAD-2-GP

PC4236
SC33P50V2JN-3GP
VCORE_IN1_L0
1
2
PR4235

PR4264
7K5R2F-1-GP

191R2F-GP

PR4236
953R2F-GP

PR4207

2VCORE_IN1_R1

PC4238
SC680P50V3JN-GP

PR4208

X01 12/21
1
2
PR4237
487R2F-GP

DY

PWR_VCORE_R_SEL1

6K81R2F-1-GP

PWR_VCORE_R_SEL0

SC22P50V2JN-4GP

VDD3
VDD
VDD
VIN_UVLO
PWM1_3
PWM1_2
PWM1_1
TS_FAULT#1
IPH1_3
IPH1_2
IPH1_1
MRAMP1

PWR_AXG_A_ERR2
PWR_AXG_A2_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A3_OUT2
PWR_VCORE_A3_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A2_IN1
PWR_VCORE_A_ERR1

PR4234
1

DY

PR4258
0R2J-2-GP

PR4215
13KR2F-GP

PC4232
1 VCORE_IN1_R0

DY
0R0402-PAD-2-GP

PWR_VCORE_IPH1_1
PWR_VCORE_MRAMP1

DY
0R0402-PAD-2-GP

PC4231
SC22P50V2JN-4GP
2

PR4261

[43] PWR_VCORE_IPH1_1_L

SC10P50V2JN-4GP

X02 2/13

PR4219

PC4229

1
2
3
4
5
6
7
8
9
10
11
12

PWR_VCORE_VIN_UVLO
PWR_VCORE__PWM3
PWR_VCORE__PWM2
PWR_VCORE__PWM1
PWR_VCORE__TP_FAULT#1

2
PR4216
1K96R2F-1-GP

825R2F-GP

PR4211

PU4201

[43] PWR_VCORE__PWM1
[43] PWR_VCORE__TP_FAULT#1
2

GND_1318

PWR_VCORE_VDD3

PR4256
750R2F-GP

X03 2/10

PR4223
0R0402-PAD-2-GP
1D8V_S0

PWR_VCORE_R_OSC

SCD1U10V2KX-5GP

X03 2/13
1

280R2F-1-GP

SCD1U10V2KX-5GP

GND_1318

PR4262

PC4214

PWR_VCORE_VR_ENABLE

PC4237

0R0402-PAD-2-GP

PWR_VCORE_R_SEL4
PWR_VCORE_VR_TT#
PWR_VCORE_VR_READY1
PWR_VCORE_VR_READY2
PWR_VCORE_R_SEL6

1
PWR_VCORE_VIN_UVLO_R
PR4263
100KR2F-L1-GP

61K9R2F-GP

PR4231
10R2F-L-GP

PC4211
SC1U6D3V2KX-GP

PR4228

PR4260
866KR2F-GP

825R2F-GP

21D5R2F-1-GP

X03 2/10

PR4205

3D3V_S5

PR4204

PR4201

1D8V_S0
5V_S5

[48] D85V_PWRGD

PR4254
0R0402-PAD-2-GP

PR4251
1
2
0R0402-PAD-2-GP

PWR_VCORE_SENSE_P

PR4233
10KR2F-2-GP

PC4235

SC22P50V2JN-4GP

PC4233 SC22P50V2JN-4GP

X03 2/21
PR4250
[8] VSSSENSE

PWR_VCORE_SENSE_N

1
2
0R0402-PAD-2-GP

PR4255
30K1R2F-L-GP

X03 2/16
2VCORE_IPH1_R0 1

1
PR4245

PG4201
1

PR4238
2K7R2F-GP

PC4218
AXG_IN2_L1
1

SC1000P50V3JN-GP-U

PR4244
1

DY

6K81R2F-1-GP

PC4234
1
2

DY

SC22P50V2JN-4GP

X01 12/21
2
10KR2F-2-GP

2AXG_IN2_R1 1

PR4249
7K68R2F-GP

PC4213
SC3300P50V2KX-1GP

AXG_IN2_R0

2
PR4240
665R2F-2-GP

2
PR4239
300R2F-GP

X03 2/21

GAP-CLOSE-PWR-3-GP
GND_1318
B

1
PC4219

AXG_IPH2_R0 1

SCD01U16V2KX-3GP

PR4243
3K24R2F-GP

3D3V_S0
VCC_CORE

PR4202
1

PWR_VCORE_MRAMP1

PWR_VCORE_VR_READY1

PR4222
10KR2F-2-GP

43KR2F-GP

X03 2/13

PR4203
1

PWR_VCORE_VR_READY2

IMVP_PWRGD

[27,36]

PR4253
0R0402-PAD-2-GP

10KR2F-2-GP

VCC_GFXCORE

PWR_AXG_MRAMP2

PR4227
56K2R2F-2-GP

VCCP_CPU

PWR_VCORE_VR_TT#

PC4202
SC47P50V2JN-3GP

62R2J-GP

PR4206
1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VT1318+1323_CPU_CORE1+1(1/3)

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

42

of

105

X03 2/20
X03 2/16
X01 12/13

SSID = CPU.Regulator

PW R_CPU

5V_S5
EG4301
1
2
GAP-CLOSE-PW R-3-GP
EG4302
1
2
GAP-CLOSE-PW R-3-GP
EG4303
1
2

PW R_CPU

GAP-CLOSE-PW R-3-GP
EG4304
1
2

Layout Note:

B1

PR4301

B2

ISENSE

[42] PW R_VCORE__PW M1

B3

PWM

PC4303

2
10R2F-L-GP

A2

GND

SCD1U25V2KX-GP

C3

C2

1
2

PC4309
SC1U6D3V2KX-GP
2
1

PC4308
SC1U6D3V2KX-GP
2
1

PC4307
SC10U6D3V3MX-GP
2
1

PC4306
SC10U6D3V3MX-GP
2
1

C4
VX#D1
VX#D2
VX#D3
VX#D4
VX#F1
VX#F2
VX#F3
VX#F4
VX#H1
VX#H2
VX#H3
VX#H4
VX#K1
VX#K2
VX#K3
VX#K4

D1
D2
D3
D4
F1
F2
F3
F4
H1
H2
H3
H4
K1
K2
K3
K4

GAP-CLOSE-PW R-3-GP
EG4308
1
2

PW R_CORE_BT1
PC4301
SCD22U10V3KX-2GP

D.C. = 25A
P.C. =33A
VCC_CORE

PL4301

GAP-CLOSE-PW R-3-GP
EG4310
1
2

PW R_CORE_VX1 1
2
IND-D1UH-26-GP

68.R1010.10T
2nd = 68.R1010.10X

GAP-CLOSE-PW R-3-GP
EG4309
1
2

X01 12/19
X01 12/12
PR4303

DY

GAP-CLOSE-PW R-3-GP
EG4311
1
2
GAP-CLOSE-PW R-3-GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

[42] PW R_VCORE_IPH1_1_L

B4

100R5F-2-GP

1D8V_S0

VDD

GAP-CLOSE-PW R-3-GP
EG4307
1
2

PW R_VCORE_PU4301_VDD
C

GAP-CLOSE-PW R-3-GP
EG4306
1
2

VCC

GAP-CLOSE-PW R-3-GP
EG4305
1
2
PC4310
SCD1U10V2KX-5GP

A4

BST

TS_FAULT#

VDDH

A1

VDDH

[42] PW R_VCORE__TP_FAULT#1

PC4302
SC4D7U6D3V3KX-GP

VDDH

PU4301

VDDH

X01 12/21

C1

1D8V_S0

PC4305
SC10U6D3V3MX-GP
2
1

PC4304
SC10U6D3V3MX-GP
2
1

Small Cap close IC

74.01326.A7Z

E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
L1
L2
L3
L4

VT1326SFCX-1-GP

X03 2/16
B

PG4301
2

GAP-CLOSE-PW R-3-GP
GND_1323S_1

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VT1318+1326_CPU_CORE2+1(2/3)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

43

of

105

SSID = CPU.Regulator

X03
X03
X01
X01

2/20
2/16
12/20
12/13

PW R_CPU

5V_S5
EG4401
1
2
GAP-CLOSE-PW R-3-GP
EG4402
1
2

GAP-CLOSE-PW R-3-GP
EG4403
1
2
GAP-CLOSE-PW R-3-GP
EG4404
1
2

X01 12/20
GAP-CLOSE-PW R-3-GP
EG4405
1
2

PW R_CPU

GAP-CLOSE-PW R-3-GP
EG4406
1
2

Small Cap close IC

PC4407
SC1U6D3V2KX-GP
2
1

PC4406
SC10U6D3V3MX-GP
2
1

PC4405
SC10U6D3V3MX-GP
2
1

1D8V_S0

PC4404
SC10U6D3V3MX-GP
2
1

PC4403
SC10U6D3V3MX-GP
2
1

Layout Note:

GAP-CLOSE-PW R-3-GP
EG4407
1
2

PC4408
SCD1U10V2KX-5GP

GAP-CLOSE-PW R-3-GP
EG4408
1
2
GAP-CLOSE-PW R-3-GP
EG4409
1
2

VCC

C4

C3

C2

VX#H4
VX#H3
VX#H2
VX#H1
VX#F4
VX#F3
VX#F2
VX#F1
VX#D4
VX#D3
VX#D2
VX#D1

H4
H3
H2
H1
F4
F3
F2
F1
D4
D3
D2
D1

GAP-CLOSE-PW R-3-GP
EG4410
1
2

PW R_AXG_BT3

D.C. = 22A
P.C. =33A

PW R_AXG_PU4401_VDD

1D8V_S0

PR4401

VDD

[42] PW R_AXG_IPH2_1_R

B2

ISENSE

[42] PW R_AXG_PW M2_1

B3

PWM

PC4409
SCD22U10V3KX-2GP

68.R1010.10T
2nd = 68.R1010.10X

PR4402

DY
2

A2

GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

10R2F-L-GP

GAP-CLOSE-PW R-3-GP

1
2
IND-D1UH-26-GP

PC4402

VCC_GFXCORE

PL4401
PW R_AVG_VX1

SCD1U25V2KX-GP
VT1323SFCX-1-GP

74.01323.A7Z

GAP-CLOSE-PW R-3-GP
EG4411
1
2

E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4

B1

B4

100R5F-2-GP

BST

A4

VDDH

TS_FAULT#

VDDH

A1

VDDH

[42] PW R_AXG_TS_FAULT#2

PC4401
SC4D7U6D3V3KX-GP

VDDH

PU4401

C1

X01 12/21

X03 2/16
B

PG4401
2

GAP-CLOSE-PW R-3-GP
GND_1323S_3

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VT1318+1323_CPU_CORE1+1(3/3)
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

44

of

105

SSID = PWR.Plane.Regulator_1p05v
X03 2/16

1D05VTT_PW R

1D05V_PCH

1D05VTT_PW R

PG4501
1
2

VCCP_CPU

PG4508
1
2

3D3V_S0

PR4718
10KR2J-3-GP

GAP-CLOSE-PW R-3-GP
PG4502
1
2

GAP-CLOSE-PW R-3-GP
PG4509
1
2

GAP-CLOSE-PW R-3-GP
PG4503
1
2

GAP-CLOSE-PW R-3-GP
PG4510
1
2

GAP-CLOSE-PW R-3-GP
PG4504
1
2

GAP-CLOSE-PW R-3-GP
PG4511
1
2

GAP-CLOSE-PW R-3-GP
PG4506
1
2

GAP-CLOSE-PW R-3-GP
PG4512
1
2

GAP-CLOSE-PW R-3-GP
PG4507
1
2

GAP-CLOSE-PW R-3-GP
PG4513
1
2

GAP-CLOSE-PW R-3-GP

GAP-CLOSE-PW R-3-GP
PG4514
1
2

PW R_1D05V_STAT

5V_PW R_1D05V

Layout Note:

5V_S5

A00 3/29
X03 2/16

X03 2/16

140mil

SC22U6D3V5MX-2GP
PC4508

1
2

SCD1U10V2KX-5GP
PC4515
2
1

EC4507
SCD1U10V2KX-5GP
2
1

DY PC4531
SC2200P50V2KX-2GP

SC4D7U6D3V3KX-GP
PC4514

2
EL4501
MPZ1608S300AT-GP

68.00212.051

GAP-CLOSE-PW R-3-GP
PG4515
1
2

PU4501

68.R2010.20B
2nd = 68.R2010.10Q

VT386FCX-ADJ-GP

PC4539
SCD1U10V2KX-4GP
2
1

COIL-D2UH-2-GP

X01 12/12

AGND_1D05V_386

PR4501
25K5R2F-GP

DY

PC4525

PC4527

DY

PC4526
SC22U6D3V5MX-2GP
2
1

DY

DY

PC4520
SC22U6D3V5MX-2GP
2
1

AGND_1D05V_386

SC22U6D3V5MX-2GP

GAP-CLOSE-PW R-3-GP

SC22U6D3V5MX-2GP
2
1

PG4517
2

PC4516
SC22U6D3V5MX-2GP
2
1
PC4517

PC4513
SC22U6D3V5MX-2GP
2
1

VCCP_CPU

PC4512
SC22U6D3V5MX-2GP
2
1

X03 2/16

PC4506
SCD1U10V2KX-5GP
2
1

PC4501
SC4700P50V2KX-1GP

2
PC4532
SC3300P50V2KX-1GP

X03 2/16
PC4522
SCD1U10V2KX-5GP
2
1

B1
C1

OE

PC4529
SC22U6D3V5MX-2GP
2
1

A1

GND
GND

STAT

A5

GAP-CLOSE-PW R-3-GP

1D05VTT_PW R

400mil

1
VCCIO_SENSE_1

AGND

A4

Layout Note:

PL4501

DY

PR4515
150R2F-1-GP
1
2

DY

C2
C3
C4

PC4530
SC22U6D3V5MX-2GP
2
1

PW R_1D05V_STAT
PR4522
PU4501_OE
1
2
0R0402-PAD-2-GP

VX#C2
VX#C3
VX#C4

EC4528
SCD1U10V2KX-5GP
2
1

X03 2/10
[19,46,47] RUNPW ROK

SENSE+
SENSE-

PC4511
SC22U6D3V5MX-2GP
2
1

PR4507
6K81R2F-1-GP

A2
A3

GAP-CLOSE-PW R-3-GP
PG4516
1
2

D.C. =10.67A
16.77A < OCP < 19.82A

EC4521
SCD1U10V2KX-5GP
2
1

PW R_1D05V_VSENSE+
PW R_1D05V_VSENSE-

PW R_1D05V_VX

PC4510
SC22U6D3V5MX-2GP
2
1

B2
B3
B4

PC4509
SC22U6D3V5MX-2GP
2
1

2
PR4506
2K74R2F-GP

VX#B2
VX#B3
VX#B4

PC4523
SC22U6D3V5MX-2GP
2
1

VDD
VDD

PC4519
SC22U6D3V5MX-2GP
2
1

B5
C5

Diff. pair

PC4518
SC22U6D3V5MX-2GP
2
1

Layout Note:

SC22U6D3V5MX-2GP
2
1

PR4523
1
2
0R0402-PAD-2-GP

[37,48] 1D05V_VTT_PW RGD

X03 2/10

DY

X03 2/10
VCCIO_SENSE_C

PR4510 1

2 0R0402-PAD-2-GP

VCCIO_SENSE

PR4511 1

2 0R0402-PAD-2-GP

VSSIO_SENSE [8]

[8]

Layout Note:
Close CPU output
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D05V_PCH & VCCP_CPU

5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

45

of

105

SSID = PWR.Plane.Regulator_1p5v0p75v

3D3V_S0

EL4601
BLM18PG330SN1D-GP

SC22U6D3V5MX-2GP
PC4628

1
2

PC4607
SC22U6D3V5MX-2GP

2
1

1
2

PC4617
SCD1U10V2KX-5GP

PC4611
SC4D7U6D3V3KX-GP

UMA VT386
SG VT385

68.00143.041
2nd = 68.00212.051

PC4624
SC22U6D3V5MX-2GP
2
1

5V_S5

PC4608
SC22U6D3V5MX-2GP
2
1

X01 12/13

PC4524
SC2200P50V2KX-2GP

PC4622
SC22U6D3V5MX-2GP
2
1

PC4610
SC22U6D3V5MX-2GP
2
1

PW R_1D5V_STAT
5V_PW R_1D5V

[19,45,47] RUNPW ROK

PR4626
1
2
0R0402-PAD-2-GP

1D5V_S0

PR4616
10KR2J-3-GP

X03 2/10

2
EL4602
BLM18PG330SN1D-GP

68.00143.041
2nd = 68.00212.051

PU4602

SC4700P50V2KX-1GP

VT385FCX-ADJ-GP

2
1

2
1

PC4632
SCD1U10V2KX-5GP

DY

PC4625

PR4613
13KR2F-GP

PC4631
SCD1U10V2KX-5GP

GND
GND
GND

68.R2010.201
2nd = 68.R2010.10P

PC4609
SCD1U10V2KX-5GP
1
2

AGND

B1
C1
D1

1D5V_S3

2
COIL-D20UH-GP
PC4627
SC6800P25V2KX-1GP
2
1

A1

PC4621
SC22U6D3V5MX-2GP
2
1

AGND_1D5V_385

PW R_1D5V_VX

720mil

PC4619
SC22U6D3V5MX-2GP
2
1

PC4618 SC3300P50V2KX-1GP

B2
B3
B4
C2
C3
C4
D2
D3
D4

VX#B2
VX#B3
VX#B4
VX#C2
VX#C3
VX#C4
VX#D2
VX#D3
VX#D4

D.C. =13.7A
21.6A < OCP < 25.4A

Layout Note:
PL4601

PC4613
SC22U6D3V5MX-2GP
2
1

STAT
OE

X01 12/15
EC4638
SCD1U10V2KX-4GP
2
1

1
2
PR4614
150R2F-1-GP

A4
A5

B5
C5
D5

PC4623
SC22U6D3V5MX-2GP
2
1

PR4612
4K53R2F-1-GP

DY

PW R_1D5V_STAT
PW R_1D5V_OE

VDD
VDD
VDD

PC4620
SC22U6D3V5MX-2GP
2
1

4K7R2F-GP

SENSE+
SENSE-

1 PR4609 2

A2
A3

PC4633
SCD1U10V2KX-5GP

PW R_1D5V_VSENSE+
PW R_1D5V_VSENSE-

X01 12/12

DY

DY

DY

PC4637
SC22U6D3V5MX-2GP
2
1

DY

PC4636
SC22U6D3V5MX-2GP
2
1

PR4623
1
2
0R0402-PAD-2-GP

[19,27] PM_SLP_S4#

DY

PC4635
SC22U6D3V5MX-2GP
2
1

X03 2/16

PC4634
SC22U6D3V5MX-2GP
2
1

PR4622
1
2
0R0402-PAD-2-GP

X03 2/10

PC4612
SC22U6D3V5MX-2GP
2
1

PR4621
1
2
0R0402-PAD-2-GP

PW R_1D5V_VSENSE-_R_1

PC4615
SC22U6D3V5MX-2GP
2
1

X02 2/10

PC4616
SC22U6D3V5MX-2GP
2
1

PW R_1D5V_VSENSE-_R

DY

PG4601
2

GAP-CLOSE-PW R-3-GP

AGND_1D5V_385

RT9026 for 0D75V_S0

X03 2/16 1D5V_S3

5V_S5

PG4602
2

GAP-CLOSE-PW R-3-GP

PC4605
SCD1U10V2KX-5GP

2
1

PC4606
SC10U6D3V3MX-GP

PC4603
SC1U6D3V2KX-GP

0D75V_PW R_VLDOIN

D.C. =0.7A

PU4601

X03 2/10

1
2

RT9026PFP-GP

PC4601
SC10U6D3V3MX-GP

PC4630
SCD1U10V2KX-4GP
2
1

DY

PC4602
SCD1U10V2KX-5GP

DY

0D75V_PW R_S3
DDR_VREF_S3

X03 2/16
1

PC4604
SC10U6D3V3MX-GP

2 0R0402-PAD-2-GP

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS

0D75V_PW R_S5

0D75V_PW R

1
2
3
4
5

GND

PR4602

[37] 0D75V_EN

2 0R0402-PAD-2-GP

PC4629
SCD1U10V2KX-4GP
2
1

11

PR4611

[19,27] PM_SLP_S4#

10
9
8
7
6

0D75V_S0

PG4603
2

<Core Design>
A

GAP-CLOSE-PW R-3-GP
PG4604
1
2

Wistron Corporation

GAP-CLOSE-PW R-3-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

VT385_1D5V_S3/RT9026_0D75V_S0

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

46

of

105

SSID = PWR.Plane.Regulator_1p8v

3D3V_S5

RT8068A for 1D8V_S0

X03 2/16
PG4701
2

D.C. =0.87A
1.29A < OCP <1.52A
PU4701

GAP-CLOSE-PW R-3-GP
PG4702
1
2

FB

EN

PGOOD

1
2
IND-1D5UH-71-GP-U

68.1R510.20J
2nd = 68.1R51B.10Q

PR4703
102KR2F-GP

GND

R1

11

RT8068AZQW ID-GP-U

PW R_1D8V_FB

74.08068.A43

PR4704
51KR2F-L-GP

R2

PC4706

PC4707

GAP-CLOSE-PW R-3-GP
PG4706
1
2
GAP-CLOSE-PW R-3-GP
PG4707
1
2
C

GAP-CLOSE-PW R-3-GP

X03 2/11

GAP-CLOSE-PW R-3-GP
PG4705
1
2

NC#7

PW R_1D8V_PHASE

LX#3

PC4705

LX#2

SVIN

PVIN

PC4703
SC1U6D3V2KX-GP
PW R_1D8V_EN

1D8V_S0

PG4704
1
2

PL4701

SC22P50V2JN-4GP

2
1
2

LX#1

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

PC4701

PVIN

SC10U6D3V3MX-GP

PC4702

DY

SC10U6D3V3MX-GP

GAP-CLOSE-PW R-3-GP

PW R_1D8V_SVIN

10

GAP-CLOSE-PW R-3-GP
PG4703
1
2

X03 2/16

1D8V_PW R
PW R_1D8V_PVDD
PR4701
1
2
2D2R2F-GP

PM_SLP_S3#

PR4702
0R0402-PAD-2-GP

[19,27,36,37]

DY

PC4704
SC22P50V2GN-GP

Vo=0.6*(1+(R1/R2))
[19,45,46] RUNPW ROK

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

RT8068A_1D8V_S0
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

47

of

105

SSID = PWR.Plane.Regulator_vccsa
X02 1/9
VCCP_CPU

X03 2/16
PW R_VCCSA_VIN

PG4801
2

GAP-CLOSE-PW R-3-GP
PG4802
1
2
GAP-CLOSE-PW R-3-GP
PG4803
1
2
GAP-CLOSE-PW R-3-GP
PG4804
1
2
GAP-CLOSE-PW R-3-GP
PG4805
1
2

5V_S5

A00 3/23

GAP-CLOSE-PW R-3-GP
PG4806
1
2

PR4801
0R0402-PAD-2-GP

GAP-CLOSE-PW R-3-GP
PW R_VCCSA_VCNTL

VOUT
VOUT

3
4

R1

FB

PR4804
10KR2F-2-GP

2
1

DY

GAP-CLOSE-PW R-3-GP
PG4809
1
2
GAP-CLOSE-PW R-3-GP
PG4810
1
2
GAP-CLOSE-PW R-3-GP
PG4811
1
2

Vout=0.8*(1+R1/R2)
B

PQ4801
2N7002BK-GP

DY
G

PWR_VCCSA_SEL1

PR4806
160KR2F-GP

GND

R2
PR4805
80K6R2F-GP

74.05916.031
2nd = 74.00977.031

PC4806
SC10U6D3V5KX-1GP

PW R_VCCSA_FB

APL5916KAI-TRL-GP

PC4805
SC10U6D3V5KX-1GP

DY

GAP-CLOSE-PW R-3-GP
PG4808
1
2

PC4804
SC100P50V2JN-3GP

DY

PC4809
SC1U6D3V2KX-GP

0D85V_S0
PG4807
1
2

EN

Note: LDO solution VCCSA is 0.9V.

X03 2/16

VCCSA_PW R

PW R_VCCSA_EN

PR4803
0R0402-PAD-2-GP
PR4808
47KR2F-GP

5
9

[37,45] 1D05V_VTT_PW RGD

VIN
VIN

POK

A00 3/23

Iomax=4A
OCP>9A
VCCSA=0.9V

VCNTL

PU4801

[42] D85V_PW RGD

PC4803

PC4802

SC10U6D3V5KX-1GP

PC4801
SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

PR4802
10KR2J-3-GP

3D3V_S0

GAP-CLOSE-PW R-3-GP
PG4812
1
2

GAP-CLOSE-PW R-3-GP

84.07002.I31
2nd = 84.2N702.W31
3rd = 84.2N702.J31
PR4807
PW R_VCCSA_SEL0

DY

VCCSA_SEL1 [9]

10KR2J-3-GP

DY

PC4807
SCD1U10V2KX-4GP

<Core Design>

TPAD14-OP-GP

TP4801

VCCSA_SEL0 [9]

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

TPAD14-OP-GP

TP4802

VCCSA_SENSE [9]

Title

APL5916_VCCSA
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

48

of

105

SSID = VIDEO

SSID = VIDEO

X01 12/20
X01 12/02

LCD Power for ROSA

RN4901
LCD_TST_C
BLON_OUT_C

LVDS CONN

2
1

DCBATOUT_LCD

X03 2/13
LCD_POW ER

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

35

36

[27] LCD_TST_EN

R4902
33R2J-2-GP

USB_CAMERA#
USB_CAMERA
COLOR_ENGINE_R

D4901
[17] LVDS_VDD_EN

L_BKLT_CTRL [17]

3D3V_S0

BAT54CPT-GP

3D3V_CAMERA_S0

R4909
100KR2J-1-GP
U4901

83.R2003.E81
2ND = 83.00054.Q81

LCDVDD

1
2
3

3D3V_S0

[82]
[82]

EN
GND
OUT

IN#5

IN#4

4
1

AUD_DMIC_CLK
AUD_DMIC_IN0

LCDVDD_EN

LVDSA_DATA1 [17]
LVDSA_DATA1# [17]

Trace width = 80mil

1
2

3D3V_LCD_ROM

4
3

DY
2

37

74.05285.07F
2nd = 74.09724.09F

LVDS_DDC_DATA_R [17]
LVDS_DDC_CLK_R [17]

RN4902
SRN100J-3-GP

3D3V_S0

LCDVDD
C4901
SCD1U10V2KX-5GP

DYEC4907
SCD1U25V3KX-GP

A00 3/27

LVDSA_DATA0 [17]
LVDSA_DATA0# [17]
LVDS_DDC_DATA_R_1
LVDS_DDC_CLK_R_1
LCD_TST_C

40

C4907
SC4D7U6D3V3KX-GP

G5285T11U-GP

Layout Note:

RN4903
SRN2K2J-1-GP

LVDSA_DATA2 [17]
LVDSA_DATA2# [17]

C4908
SC4D7U6D3V3KX-GP

1
2

LVDSA_CLK [17]
LVDSA_CLK# [17]

4
3

34

BLON_OUT_C
LCD_BRIGHTNESS
DBC_EN_C

33

2
EL4901 BLM18PG330SN1D-GP

C4902
SC1U6D3V2KX-GP

3D3V_LCD_ROM

R4901

32

68.00143.041
2nd = 68.00212.051

39

31

SRN100J-3-GP
R4908
100KR2J-1-GP

38

LCD_TST [27]
BLON_OUT [27]

LCD1

3
4

F4902

FOX-CON30-4-GP

20.F2173.030
2nd = 20.F2089.030

2 0R3J-0-U-GP

1
1

DY

FUSE-2A32V-16-GP

X03 2/6
DBC_EN_C

DBC_EN [22]

R4912
0R0402-PAD-2-GP
COLOR_ENGINE_R

DY

COLOR_ENGINE

[22]

X03 2/16

R4913
0R2J-2-GP

EC4911
SC3D3P50V2CN-GP

EC4910
SC3D3P50V2CN-GP
2
1

1
2

EC4909
SC3D3P50V2CN-GP

EC4908
SC3D3P50V2CN-GP
2
1

1
2

EC4906
SC3D3P50V2CN-GP
2
1

1
2

1
2

EC4905
SC3D3P50V2CN-GP

69.10103.041
2nd = 68.00201.141

EC4904
SC3D3P50V2CN-GP

FILTER-4P-6-GP

EC4902
SC3D3P50V2CN-GP

TR4902

USB_CAMERA#

[18] USB_PN12

EC4901
SC3D3P50V2CN-GP

LVDSA_CLK
LVDSA_CLK#
LVDSA_DATA0
LVDSA_DATA0#
LVDSA_DATA1
LVDSA_DATA1#
LVDSA_DATA2
LVDSA_DATA2#
COLOR_ENGINE_R

A00 3/27
X01 12/30

USB_CAMERA

[18] USB_PP12

Camera Power
DCBATOUT_LCD
3D3V_S0

DCBATOUT

3D3V_CAMERA_S0
R4904

1
C4903
SC10U6D3V5KX-1GP

C4905
SCD1U25V3KX-GP

DY

EC4903
SCD1U10V2KX-5GP

2
C4904
SC1KP50V2KX-1GP
1
2

2
0R3J-0-U-GP

F4901

<Core Design>

POLYSW -1D1A24V-GP-U

Wistron Corporation

69.50007.A31
2nd = 69.50007.A41

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD Connector
Size
A3

Document Number

Date:

Tuesday, April 03, 2012

Rev

A00

BMW Z4 DIS
Sheet

49

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT Connector
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

50

of

105

SSID = VIDEO
HDMI Level Shifter

[17] HDMI_DATA0_R#
[17] HDMI_DATA0_R

[17] HDMI_DATA1_R#
[17] HDMI_DATA1_R

C5105
C5106

1
1

C5110
C5107
C5108
C5109

1
1
1
1

2
2

HDMI_CLK_R_C#
HDMI_CLK_R_C

2
2

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

HDMI_DATA0_R_C#
HDMI_DATA0_R_C

2
2

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

HDMI_DATA1_R_C#
HDMI_DATA1_R_C

2
2

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

HDMI_DATA2_R_C#
HDMI_DATA2_R_C

8
7
6
5

[17] HDMI_DATA2_R#
[17] HDMI_DATA2_R

1
1

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

RN5107
SRN680J-GP

R5101
1
2
0R0603-PAD-2-GP

HDMI_CLK_R_C_CON

HDMI_CLK_R_C#

R5102
1
2
0R0603-PAD-2-GP

HDMI_CLK_R_C#_CON

HDMI CONN

HDMI_DATA0_R_C

R5103
1
2
0R0603-PAD-2-GP

HDMI1

22
20
1

HDMI_DATA2_R_C_CON
HDMI_DATA0_R_C_CON

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

HDMI_DATA2_R_C#_CON
HDMI_DATA1_R_C_CON
HDMI_DATA0_R_C#

R5104
1
2
0R0603-PAD-2-GP

HDMI_DATA0_R_C#_CON

HDMI_DATA2_R_C

R5105
1
2
0R0603-PAD-2-GP

HDMI_DATA2_R_C_CON

HDMI_DATA1_R_C#_CON
HDMI_DATA0_R_C_CON
HDMI_DATA0_R_C#_CON
HDMI_CLK_R_C_CON
HDMI_CLK_R_C#_CON

R5106

1
2
3
4

1
2
3
4

RN5106
SRN680J-GP

HDMI_PLL_GND

HDMI_CLK_R_C

8
7
6
5

[17] HDMI_CLK_R#
[17] HDMI_CLK_R

X03 2/6

C5103
C5104

HDMI_DATA2_R_C#

1
2
0R0603-PAD-2-GP

HDMI_DATA2_R_C#_CON

DDC_CLK_HDMI
DDC_DATA_HDMI

5V_HDMI_S0

R5107
C5102
SCD1U10V2KX-5GP
HDMI_DATA1_R_C#_CON

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

SKT-HDMI19P-69-GP

3D3V_S0

22.10296.211
2nd = 22.10296.431

1
2
0R0603-PAD-2-GP

HPD_HDMI_CON

HDMI_DATA1_R_C#

Q5103
2N7002K-2-GP

5V_S0

HDMI_DATA1_R_C_CON

R5108

1
2
0R0603-PAD-2-GP

HDMI_DATA1_R_C

HDMI_HPD_E

84.03904.L06
2nd = 84.03904.P11

DY

R5110
200KR2J-L1-GP

5V_S0

1
R5111

R5125
0R0402-PAD-2-GP
R5112
10KR2J-3-GP

[17] HDMI_PCH_DET

X03 02/14
X03 01/09

1 HDMI_HPD_B 2
150KR2J-L1-GP
2

Q5102
PMBS3904-1-GP

X03 2/6

83.00056.G11
2nd = 83.00056.E11

F5101

RN5101
SRN2K2J-1-GP

[17] PCH_HDMI_CLK

FUSE-1D1A6V-4GP-U

1
2

5V_HDMI_S0

5V_S0

3D3V_S0

Q5104

X03 02/14
X01 12/27
X01 12/02

4
3

D5102_1

D5102_2

D5102
BAW 56-2-GP

69.50007.691
2nd = 69.50007.771

DDC_CLK_HDMI

1
2N7002KDW -GP

[17] PCH_HDMI_DATA

DDC_DATA_HDMI

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HDMI Level Shifter/Connector

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

51

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

52

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

53

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

54

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ITP/Fan Connector

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

55

of

105

SSID = SATA
3D3V_S0

HDD CONN

5V_S0

X01 12/15
EC5601
SCD1U10V2KX-5GP
C5605
SC10U6D3V5KX-1GP

5V_S5

C5606

DY SCD1U10V2KX-5GP

HDD1

Due to layout, HDD1 pin 23 modify 5V_S5

DY

C5604
SC10U6D3V5KX-1GP

X01 12/02

Layout Note:
AC coupling Cap;
place near CONN(<100mils)

3D3V_S0

P1
P2
P3

V33
V33
V33

5V_S0

P7
P8
P9

V5
V5
V5

P13
P14
P15

V12
V12
V12

SATA_TXP0_C
SATA_TXN0_C

S2
S3

A+
A-

SATA_RXP0_C
SATA_RXN0_C

S6
S5

B+
B-

23
24

23
24

GND
GND
GND
GND
GND
GND
GND
GND

S1
S4
S7
P4
P5
P6
P10
P12

DAS/DSS

P11

SKT-SATA7P-15P-85-GP
[21] SATA_TXP0
[21] SATA_TXN0

C5614
C5613

2
2

1 SCD01U16V2KX-3GP
1 SCD01U16V2KX-3GP

SATA_TXP0_C
SATA_TXN0_C

[21] SATA_RXP0
[21] SATA_RXN0

C5615
C5616

1
1

2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP

SATA_RXP0_C
SATA_RXN0_C

20.81599.022
2nd = 22.10300.C51

ODD CONN

SATA_RX4-_C
SATA_RX4+_C

C5607 1
C5608 1

2SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP

SATA_RXN4 [21]
SATA_RXP4 [21]
3D3V_S0

SATA_ODD_DA#_C

SATA_ODD_PRSNT# [22]

R5607
10KR2J-3-GP

SATA_ODD_DA# [18]

R5602
0R2J-2-GP

210KR2J-3-GP

DY

DY

SATA_ODD_DA#_C 2

R5604 1

ODD_PW R_5V

Q5601
2N7002KDW -GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

2
3
4
5
6

SATA_TXP4 [21]
SATA_TXN4 [21]

2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP

C5612 1
C5611 1

R5605
100KR2J-1-GP

AC coupling Cap;
place near CONN(<100mils)

ODD_PWRGT#

SATA_TXP4_C
SATA_TXN4_C

Layout Note:

15
NP2
S1
S2
S3
S4
S5
S6
S7

5V_S0

SATA_RX- and SATA_RX+ Trace

Length match within 20 mil

ODD1

NP1
14
SATA_ODD_PW RGT

SATA_ODD_DA#

SKT-SATA7P+6P-77-GP-U

2nd = 20.81152.013
[22] SATA_ODD_PW RGT

Zero Power ODD Power Sequence

EN
VIN
VIN
GND

OC#
VOUT#6
VOUT#7
VOUT#8

5
6
7
8

UP7534PRA8-15-GP

74.07534.D79
2nd = 74.00547.G79

ODD_PW R_5V

4
3
2
1

100 mil
C5618
SC10U6D3V5KX-1GP

1
2

C5617
SC10U6D3V5KX-1GP

ODD_PW R_5V

U5602

5V_S0

<Core Design>

Wistron Corporation
1
R5606

2
DY 0R5J-6-GP

1
R5603

2
DY 0R5J-6-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

HDD/ODD
Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet

56

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS
Sheet
1

A00
57

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

58

of

105

SSID = LOM
D

XF5901
1CT:1CT
[31] LAN_MDI1N
AVDD_CEN

16

MDO1-

14

XFR_CMT1

MDO1+

10

MDO0-

11

XFR_CMT0

MDO0+

15

[31] LAN_MDI1P

XFR_CMT2

Tx Side
1CT:1CT
[31] LAN_MDI0N
AVDD_CEN
C

Rx Side

XFR_CMT3

XFORM-12P-36-GP

68.HD081.30B
2nd = 68.0NS14.30B

8
7
6
5

C5901

RN5901
SRN75J-1-GP

X03 2/29

1
2
3
4

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

C5903

C5904
SCD1U10V2KX-5GP

DY
2

SCD1U10V2KX-5GP

C5905

[31] LAN_MDI0P

LAN_TERMINAL

C5902
SC1000P3KV8KX-L1-GP

RJ45 Connector

RJ45
AFTP5901

XFR_CMT3

AFTP5903
AFTP5904

1
1

MDO1XFR_CMT2

AFTP5906
AFTP5907

1
1

MDO1+
MDO0-

AFTP5908

MDO0+

10
8
7
6
5
4
3
2
DMB40

1
9

Wistron Corporation

RJ45-8P-28-GP-U
A

AFTP5909

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

22.10277.B61

Title

RJ45+Transfermer

Size
A4

Document Number

Date: Tuesday, April 03, 2012

5

Rev

BMW Z4 DIS
2

A00
Sheet

59

of
1

105

SSID = Flash.ROM
SPI Flash ROM(8M) for PCH
3D3V_S5
3D3V_S5

DY

C6002
SCD1U10V2KX-5GP

4
3

C6001
SC10U6D3V5KX-1GP

RN6001
SRN4K7J-8-GP

PCH

1
2

R6003
4K7R2J-2-GP

SPI_HOLD_0#

SPI

3D3V_S5

U6001

X01 12/21
SPI_CLK_R [21,27]
SPI_SI_R [21,27]

W 25Q64CVSSIG-GP

DY

DY
72.25Q64.B01
2nd = 72.25640.D01
EC6003
3rd = 72.25Q64.F01
4th = 72.25Q64.D01 SC4D7P50V2CN-1GP

EC6002
SC4D7P50V2CN-1GP

8
7
6
5

KBC

SPI_W P#

CS#
VCC
DO/IO1 HOLD#/IO3
WP#/IO2
CLK
GND
DI/IO0

DY
2

1
2
3
4

[21,27] SPI_CS0#_R
[21,27] SPI_SO_R

EC6001
SC10P50V2JN-4GP

Layout Note:
KBC----10"----PCH
KBC----1.5"~6.5"----SPI
PCH----0.5"~6.5"----SPI

X01 12/02

SSID = RBATT
3D3V_AUX_S5
B

RTC_AUX_S5

D6001

+RTC_VCC

3
2

RTC1

3
1

CH715FPT-GP

2
4

C6003
SC1U6D3V2KX-GP

RTC_PW R

R6002
1KR2J-1-GP
1
2

X01 12/02

83.R0304.B81
2nd = 83.00040.E81

TPAD14-OP-GP

TP6001

ACES-CON2-11-GP

20.F0772.002
2nd = 20.F1035.002

TPAD14-OP-GP

TP6002

+RTC_VCC

R6006
100R2J-2-GP

DY

Q6002

RTC_PW R

R6007
10MR2J-L-GP

RTC_DET# [22]

<Core Design>

Wistron Corporation

2N7002K-2-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

Title

Flash/RTC
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

60

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS
5

A00
Sheet
1

61

of

105

SSID = USB
USB3.0 Port1 with power share
A00 3/27
X01 12/23

USB_PP0_RR

USB20_DP0_C

USB30_VCCA
USB1

VBUS

TR6204

USB20_DN0_C
USB20_DP0_C

FILTER-4P-62-GP

69.10080.021
2nd = 69.10103.061
USB_PN0_RR

2
3

DD+

10
11
12
13

10
11
12
13

USB20_DN0_C

SSRXSSRX+

5
6

USB30_RXDN1_C
USB30_RXDP1_C

SSTXSSTX+

8
9

USB30_TXDN1_C
USB30_TXDP1_C

PGND

USBDET

GND

SKT-USB13-70-GP-U

22.10341.691
A00 3/23
X01 12/15
X01 12/02
1

[18] USB3_TX1_N

USB30_TXDN1_R

C6223
SCD1U10V2KX-5GP

USB30_TXDN1_C

[18] USB3_RX1_N

R6281
0R0402-PAD-2-GP

USB30_RXDN1_C

2
R6283
0R0402-PAD-2-GP

USBDET

USBDET_CON# [27]

R6208
0R2J-2-GP
U6204

[18] USB3_TX1_P

USB30_TXDP1_R

C6222
SCD1U10V2KX-5GP

USB30_TXDP1_C

[18] USB3_RX1_P

R6282
0R0402-PAD-2-GP

USB30_VCCA

USB20_DN0_C

USB20_DP0_C

USB30_RXDP1_C

USB30_TXDP1_C

USB30_RXDN1_C

USB30_TXDN1_C

USB30_RXDP1_C

2
R6284
0R0402-PAD-2-GP

DY
X01 12/13

AZ1065-06Q-GP

5V_S5

USB Charger
USB30_VCCA

U6201

[27] USBCHG_EN
[27] USBCHARGER_CB0

1
R6203 1
R6204 1
R6205

CTL1
2
20R0402-PAD-2-GP CTL2
20R0402-PAD-2-GP CTL3
0R0402-PAD-2-GP

5
6
7
8

DM_OUT
DP_OUT

DSC
CTL1
CTL2
CTL3

ILIM0
ILIM1

16
15

GND
GND

14
17

USB_PN0 [18]
USB_PP0 [18]
ILIM0
ILIM1

1
R6210 1
R6211

DY

2
2 20KR2J-L2-GP
20KR2J-L2-GP

CTL1

CTL2

CTL3

CDP

DCP

TC6201
ST100U6D3VAM-3-GP

NC#9

2
3

ILIM_SEL

TPS2541 charging type setting

USB_PN0_RR
USB_PP0_RR

C6203
SC10U6D3V5KX-1GP

X03 2/6

11
10

R6202

ILIM_SEL
2
0R0402-PAD-2-GP

12

C6202
SCD1U10V2KX-5GP

FAULT#

X03 2/6
1

OUT
DM_IN
DP_IN

IN

1
13

[18,82] USB_OC#0_1

X03 01/30
C6201
SC1U25V3KX-1-GP

80.10715.B1L
2nd = 78.10710.52L
3rd = 77.C1071.22L

TPS2541RTER-GP

74.02541.A73

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

USB 3.0

Rev

BMW Z4 DIS

A00
Sheet
1

62

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

(Reserved)

Rev

BMW Z4 DIS

A00
Sheet
1

63

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Finger Printer

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

64

of

105

SSID = Wireless

Mini Card Connector(802.11a/b/g/n)

WLAN CONN
D

X03 2/6
1D5V_S0

W LAN1

[27] E51_TxD

R6504

DY

E51_RxD_R
E51_TxD_R
2
0R2J-2-GP

[20] PCIE_RXN4
[20] PCIE_RXP4
[20] PCIE_TXN4
[20] PCIE_TXP4
C

3D3V_W LAN_AOAC

5V_S5

R6508
10KR2J-3-GP
1

DY

[18] BLUETOOTH_EN

X03 2/6
W LAN_22

1
2
R6505
0R0402-PAD-2-GP
PCH_SMBCLK
PCH_SMBDATA

DY

C6504
SC10U6D3V5MX-3GP

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C6503

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

C6502

C6501
SC10U6D3V5KX-1GP

4
6
8
10
12
14
16

[20] CLK_PCIE_W LAN#

[20] CLK_PCIE_W LAN
TPAD14-OP-GP

C6505

3
5
7
9
11
13
15

W LAN_ACT
BT_ACT
CLK_PCIE_W LAN_REQ#_C

TP6503

W LAN_W AKE#

1
1

1D5V_S0

SCD1U10V2KX-5GP

TP6501
TP6502

SCD1U10V2KX-5GP

TPAD14-OP-GP
TPAD14-OP-GP

3D3V_W LAN_AOAC

[27,66] AOAC_PCIE_W AKE#

53
NP1
1

SCD1U10V2KX-5GP

R6502
0R0402-PAD-2-GP
1
2

A00 3/23

W IFI_RF_EN [27]
PLT_RST# [5,18,27,31,66,71]

USB_PP11_R

2
R6503
0R0603-PAD-2-GP

[18] USB_PP11

PCH_SMBCLK [14,15,20,66,69]
PCH_SMBDATA [14,15,20,66,69]

USB_PN11_R
USB_PP11_R
C

W LAN_LED#
W PAN_LED#

W LAN_LED# [68]
W PAN_LED# [68]

USB_PN11_R

2
R6506
0R0603-PAD-2-GP

[18] USB_PN11

SKT-MINI52P-54-GP-U

62.10043.981
2nd = 20.F1764.052
3rd = 62.10043.F11
X01 12/15
X01 12/09

3D3V_W LAN_AOAC
3D3V_S5

3D3V_W LAN_AOAC

U6502
AO3404A-GP

3D3V_W LAN_AOAC

X01 12/02

DY

2
U6501_D

DY

1
[27] AOAC_W LAN_EN#

Q6503
2N7002K-2-GP

R6510
100KR2J-1-GP

0R2J-2-GP

C6506
SCD01U50V2KX-1GP

3D3V_S5
CLK_PCIE_W LAN_REQ#_C

R6509
100KR2J-1-GP

R6511

VAUX_G_SW

Q6502
PMBS3904-1-GP
3

[20] CLK_PCIE_W LAN_REQ#

15V_S5

84.03904.L06
2ND = 84.03904.P11

CLK_WLAN_REQ#_EN

R6512
10KR2J-3-GP

R6507
100R2J-2-GP
B

AO3404A MAX 4.9A

Rds(on) =33 ~ 40mOhm

R6513
10KR2J-3-GP

DY

84.03404.B31
2nd = 84.03404.C31

84.2N702.J31
AOAC_W LAN_EN#
2ND = 84.2N702.031
U6501
3rd = 84.07002.I31
2N7002K-2-GP
4th = 84.2N702.W31
84.2N702.J31
2ND = 84.2N702.031

AOAC_W LAN_EN#
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

WLAN/BT

Rev

BMW Z4 DIS

A00
Sheet
1

65

of

105

SSID = Wireless

WWAN CONN
X03 1/30
W W AN1

A00 3/23

C6602
SC33P50V2JN-3GP

[18] USB_PP8

USB_PP8_R

1D5V_S0

R6602
0R0603-PAD-2-GP
1
2

C6603
SCD047U10V2KX-2GP

UIM_CLK_L

WWAN

UIM_PW R
UIM_DATA
2 33R2J-2-GP UIM_CLK
UIM_RESET
UIM_VPP

R6604 1

WWAN WWAN
3D3V_W W AN_AOAC

[27] 3G_EN
[5,18,27,31,65,71] PLT_RST#

3G_EN

A00 3/23

MSATA_WWANC6604
USB_PN8_R

1
2
R6601
0R0603-PAD-2-GP

[18] USB_PN8

W W AN_22

R6616
0R0402-PAD-2-GP

[14,15,20,65,69] PCH_SMBCLK
[14,15,20,65,69] PCH_SMBDATA

SCD1U10V2KX-5GP

USB_PN8_R
USB_PP8_R
[68] W W AN_LED#

W W AN_LED#

4
6
8
10
12
14
16

3
5
7
9
11
13
15

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

W W AN_W AKE#

R6615
0R2J-2-GP
1

DY

AOAC_PCIE_W AKE# [27,65]

D

SATA_RXP1_C
SATA_RXN1_C

C6612
C6601

1
1

SCD01U16V2KX-3GP
2
MSATA
SCD01U16V2KX-3GP
2
MSATA

SATA_RXP1 [21]
SATA_RXN1 [21]

SATA_TXN1_C
SATA_TXP1_C

C6613
C6615

1
1

SCD01U16V2KX-3GP
2
MSATA
SCD01U16V2KX-3GP
2
MSATA

SATA_TXN1 [21]
SATA_TXP1 [21]

3D3V_W W AN_AOAC

DAS
MSATA_DET#

TP6601

TPAD14-OP-GP

MSATA_DET# [22]

MSATA_WWAN
C

MSATA_WWAN

SKT-MINI52P-54-GP-U

1
2

MSATA_WWAN

1
2

1
2

MSATA_WWAN

UIM_RESET
UIM_VPP
UIM_CLK_L
UIM_DATA

WWAN

MSATA_WWAN

WWAN

77.22271.27L
2nd = 79.22710.20L

C6608
SCD047U10V2KX-2GP

C5
C2
C6
C3
C7

C6607
SCD047U10V2KX-2GP

UIM_PW R

C6606
SC33P50V2JN-3GP

2
WWAN

C6605
SC33P50V2JN-3GP

1
8
C1

TC6601
ST220U6D3VDM-20GP

SIM1

3D3V_W W AN_AOAC
EC6602
SC1U6D3V2KX-GP

10

53
NP1
1

62.10043.981
2nd = 20.F1764.052
3rd = 62.10043.F11

X01 12/09

9
11
3D3V_S5

SDCARD-10P-1-GP

3D3V_W W AN_AOAC

U6607
AO3404A-GP

3D3V_W W AN_AOAC

62.10051.971
D

DY

U6608
2N7002K-2-GP

2
1

R6613
100KR2J-1-GP

DY

DY

WWAN WWAN
2

SC33P50V2JN-3GP
EC6607

UIM_DATA
SC10P50V2JN-4GP
EC6606

WWAN WWAN
2

4
U6601
SRV05-4-2-GP

[27] AOAC_W W AN_EN#

C6609

3D3V_S5

MSATA_WWAN

3
EC6601
SC33P50V2JN-3GP

SC33P50V2JN-3GP

UIM_CLK_L
EC6605

DY

R6605
0R3J-0-U-GP
1
2

UIM_PW R

W W AN_G_SW

DY
R6612
100KR2J-1-GP

MSATA_WWAN

U6605_D

15V_S5

3D3V_W W AN_AOAC

DY
G

R6603
0R3J-0-U-GP
1
2

3D3V_S0

UIM_VPP

SCD01U50V2KX-1GP

UIM_RESET

AOAC_W W AN_EN#
U6605
2N7002K-2-GP

6
B

DY

AO3404A MAX 4.9A

Rds(on) =33 ~ 40mOhm

DATA & CLK keep about 20mil

R6611
100R2J-2-GP

84.03404.B31
2nd = 84.03400.B37

Layout Note:

DY

84.2N702.J31
2ND = 84.2N702.031

AOAC_W W AN_EN#

Layout Note:
Close to SIM1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

WWAN/MSATA

Rev

BMW Z4 DIS

A00
Sheet
1

66

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

67

of

105

SSID = User.Interface

PWRBTN

Front Power LED

LOW actived from KBC GPIO

X01 12/02

LED_PW R

FPOW ER_LED_A

2 POW ER_SW _LED_B

1KR2J-1-GP

DY

R2
C

PW LED2

2 POW ER_SW _LED_C

1KR2J-1-GP

1
R6811

K
PW SW 1
SW -TACT-130-GP-U

83.19213.H70 LED-W -45-GP

2nd = 83.00191.F70

SATA_LED_R

84.00144.P11
2nd = 84.DT144.A11

EC6810
SC220P50V2KX-3GP

PDTA144VT-GP

Battery LED2(White_LED)
LOW actived from KBC GPIO

62.40009.731
2nd = 62.40089.441

R1

[21] SATA_LED#

83.19213.H70 LED-W -45-GP

2nd = 83.00191.F70

Q6805

SATA HDD LED

LOW actived from PCH GPIO

6
PW LED1

R6808

5V_S0

FPOW ER_LED_A [82]

84.00144.P11
2nd = 84.DT144.A11

R6802
100R2F-L1-GP-U

PDTA144VT-GP

EC6801
SC220P50V2KX-3GP

R1

KBC_PW RBTN#_C

R2
[27] PW RLED#

R6806
680R2J-3-GP

5V_S5
Q6801

[27] KBC_PW RBTN#

DY

HDD_LED_A

HDD_LED_A [82]

R6812
680R2J-3-GP

5V_S5

X01 12/02

Q6809
R2

R1

[27] BATT_W HITE_LED#

LED_BATCHG

BAT_W HITE_LED_A

BAT_W HITE_LED_A [82]

R6804
680R2J-3-GP

DY

5V_S5
Q6808
R2

E
LED_BAT

R1

EC6802
SC220P50V2KX-3GP
2
1

EC6804
SC220P50V2KX-3GP
2
1

84.00144.P11
2nd = 84.DT144.A11

[27] CHG_AMBER_LED#

A00 3/22

PDTA144VT-GP

Battery LED1(Amber_LED)
LOW actived from KBC GPIO

X01 12/15

PDTA144VT-GP

84.00144.P11
2nd = 84.DT144.A11

BAT_AMBER_LED_A

BAT_AMBER_LED_A [82]

R6805
680R2J-3-GP

DY

TPLOCK LED
LOW actived from KBC GPIO
B

5V_S0
Q6807
TP_LOCK_LED_R

1
1

R1

PDTA144VT-GP

84.00144.P11
2nd = 84.DT144.A11

DY

WLAN LED
LOW actived from KBC GPIO

EC6812
SC220P50V2KX-3GP

R2

[27] TP_LOCK_LED#

E
TP_LOCK_LED_A

TP_LOCK_LED_A [82]

R6818
680R2J-3-GP

X03 1/30

A00 3/22

A00 3/22

83.R5003.G8H
2nd = 83.R5003.H8H

DY

D6803
B0530W S-7-F-GP
K
A

84.00144.P11
2nd = 84.DT144.A11

W LAN_LED_R
EC6811
SC220P50V2KX-3GP

PDTA144VT-GP

X03 01/30

<Core Design>

2
BAT54A-7-F-1-GP

[65] W LAN_LED#

R1

AOAC_LED#

3
[65] W PAN_LED#

Q6806

R2

[66] W W AN_LED#

5V_S0

83.R2003.P81
2nd = 83.00056.G11

D6801
A

W LAN_LED_A

Wistron Corporation

W LAN_LED_A [82]

R6815
680R2J-3-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

LED Bar/Power Button

3

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

68

of

105

SSID = KBC

SSID = Touch.Pad

Internal Keyboard Connector

TP_VDD

TP_VDD

TP_VDD

A00 3/27

3D3V_S0

R6909

1
2

KROW [0..7]

[27]

KCOL[0..16]

[27]

RN6901
SRN10KJ-5-GP

2
0R3J-0-U-GP

X01 12/02

C6901
SCD1U10V2KX-5GP

1
AFTP6935
TPAD1

7
1
R6911
R6910

[27] TPCLK
[27] TPDATA

EC6917
SC33P50V2JN-3GP
CAP_LED

Touch Pad Connector

AFTP6909
AFTP6910
AFTP6911
AFTP6913
AFTP6912
AFTP6914
AFTP6916
AFTP6915
AFTP6917
AFTP6919
AFTP6918
AFTP6920
AFTP6922
AFTP6921
AFTP6923
AFTP6925
AFTP6924
AFTP6926
AFTP6928
AFTP6927
AFTP6929
AFTP6931
AFTP6930
AFTP6932
AFTP6934

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

KB_DET# [21]
KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10

4
3

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

1
1

2 0R2J-2-GP
2 0R2J-2-GP

AFTP6901

DY DY
2

1
31
1

KB1
D

EC6918
SC33P50V2JN-3GP

TPCLK_C
TPDATA_C

2
3
4
5
6

[14,15,20,65,66] PCH_SMBCLK
[14,15,20,65,66] PCH_SMBDATA

3D3V_S5

8
PTW O-CON6-12-GP

CAP_LED

20.K0382.006
2nd = 20.K0320.006

AFTP6902

Due to layout, TPAD1 pin 8 modify to 3D3V_S5

ACES-CON30-14-GP
TP_VDD
TPCLK_C
TPDATA_C
PCH_SMBCLK
PCH_SMBDATA

20.K0700.030
2nd = 20.K0750.030

CAP LED Control

LOW actived from KBC GPIO

AFTP6906
AFTP6907
AFTP6908
AFTP6933
AFTP6937

CAP_LED

Q6902
R2

E
R6906

R1

[27] CAP_LED#

5V_S0

1
1
1
1
1

CAP_LED_Q

PDTA144VT-GP

CAP_LED

1KR2J-1-GP

84.00144.P11
2nd = 84.DT144.A11

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Key Board/Touch Pad

5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

69

of

105

SSID = User.Interface
D

3D3V_S5

C7001
SCD1U10V2KX-5GP

LIDSW1

VDD

OUT

VSS

[27] LID_CLOSE#

LID_CLOSE#

DY

S-5711ACDL-M3T1S-GP

C7002
SCD047U16V2KX-1-GP

74.05711.07B
2nd = 74.05712.0BB
3rd = 74.01803.07B

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Hall Sensor
Size
A4

Document Number

Date: Friday, March 30, 2012

5

Rev

A00

BMW Z4 DIS
2

Sheet

70

of
1

105

SSID = DEBUG PORT

Debug Connector
A00 3/15

Layout Note:
Place near trace separated point 3D3V_S0
[21,27] LPC_AD[3..0]

LPC_AD[3..0]
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

[21,27] LPC_FRAME#
[5,18,27,31,65,66] PLT_RST#

R7101
R7102

1
2
3
4

LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R
LPC_FRAME#_DEBUG
PLT_RST#_DEBUG

LPC

1
1

LPC
LPC

DB1

11
1

RN7101
SRN0J-7-GP
8
7
6
5

2
2 0R2J-2-GP
0R2J-2-GP

2
3
4
5
6
7
8
9
10
12

[18] CLK_PCI_LPC

PAD-10P-177042-GP

ZZ.00PAD.Y41

SSID = CPU

CPU XDP

XDP_PREQ#
XDP_PRDY#

1
1

TP7101 TPAD14-OP-GP
TP7102 TPAD14-OP-GP

[5] XDP_BPM0
[5] XDP_BPM1

XDP_BPM0
XDP_BPM1

1
1

TP7103 TPAD14-OP-GP
TP7104 TPAD14-OP-GP

[5] XDP_BPM2
[5] XDP_BPM3

XDP_BPM2
XDP_BPM3

1
1

TP7105 TPAD14-OP-GP
TP7106 TPAD14-OP-GP

[5] XDP_BPM4
[5] XDP_BPM5

XDP_BPM4
XDP_BPM5

1
1

TP7107 TPAD14-OP-GP
TP7108 TPAD14-OP-GP

[5] XDP_BPM6
[5] XDP_BPM7

XDP_BPM6
XDP_BPM7

1
1

TP7109 TPAD14-OP-GP
TP7110 TPAD14-OP-GP

CFG0

TP7111 TPAD14-OP-GP

[5] XDP_PREQ#
[5] XDP_PRDY#

[7]

CFG0

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Dubug connector

BMW Z4 DIS

Rev

A00
Sheet
1

71

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

72

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

73

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS
Sheet
1

A00
74

of

105

(Blanking)

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

(Reserved)

Rev

BMW Z4 DIS

A00
Sheet
1

75

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

76

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

77

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

78

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

79

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

80

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

BMW Z4 DIS

A00
Sheet
1

81

of

105

SSID = User.Interface

Due to layout, TPLED1 pin 5 modify 3D3V_S5

X01 12/02

5V_S5

3D3V_S5

MEDIA1
LEDBD1

9
1

2
3
4
5
6
7
8
10

TPLED1

INSTANT_LAUNCH#_LED_1
1
AUDIO_PRESENT#_LED_1
R8201 1
MOBILITY_CENTER#_LED_1 R8202 1
R8203

2
21KR2J-1-GP
21KR2J-1-GP
1KR2J-1-GP

INSTANT_LAUNCH#_LED# [27]
AUDIO_PRESENT#_LED# [27]
MOBILITY_CENTER#_LED# [27]
INSTANT_LAUNCH# [27]
AUDIO_PRESENT# [27]
MOBILITY_CENTER# [27]

5
1

FPOW ER_LED_A

FPOW ER_LED_A [68]

2
3
4
5
6

HDD_LED_A
BAT_W HITE_LED_A
BAT_AMBER_LED_A
W LAN_LED_A

HDD_LED_A [68]
BAT_W HITE_LED_A [68]
BAT_AMBER_LED_A [68]
W LAN_LED_A [68]

PTW O-CON6-12-GP

INSTANT_LAUNCH#_LED#
AUDIO_PRESENT#_LED#
MOBILITY_CENTER#_LED#

AFTP8201
AFTP8202
AFTP8203

1
1
1

INSTANT_LAUNCH#_LED_1
AUDIO_PRESENT#_LED_1
MOBILITY_CENTER#_LED_1

AFTP8205
AFTP8206
AFTP8207
AFTP8208

1
1
1
1

INSTANT_LAUNCH#
AUDIO_PRESENT#
MOBILITY_CENTER#
GND

1
EC8203 1
EC8204 1
EC8205

ACES-CON4-10-GP-U

20.K0382.006
2nd = 20.K0320.006

2
2 SC470P50V-2-GP
2 SC470P50V-2-GP
SC470P50V-2-GP

AFTP8209
AFTP8210
AFTP8211
AFTP8212
AFTP8213
AFTP8216

20.K0320.004
2nd = 20.K0382.004

5V_S0
FPOW ER_LED_A
HDD_LED_A
BAT_W HITE_LED_A
BAT_AMBER_LED_A
W LAN_LED_A
GND

1
1
1
1
1
1

TPAN1

1
7
1

DY

TPAN_PW R

2
3
4
5
6

DY
DY

R8205
2 0R3J-0-U-GP

AFTP8215
AFTP8214

5V_S0
CRTBD1

11
1
2
3
4
5
6
7
8
9
10
12

A00 3/23
X01 12/23
X01 12/13
USB_PP1_C

ER8201 1

2 0R0603-PAD-2-GP

TP_LOCK_LED_A
GND

A00 3/15

USB_PN4 [18]
USB_PP4 [18]

X03 1/30
X01 12/20
X01 12/02

1
1

R8204
2 0R3J-0-U-GP

ACES-CON6-39-GP

3D3V_S0

20.K0667.008
2nd = 20.K0665.008

TP_LOCK_LED_A [68]

2
3
4

A00 3/15
X03 2/6
X01 12/20

ACES-CON8-40-GP

USB_PP1 [18]

IOBD1

VGA_R [85]
VGA_G [85]
VGA_B [85]
VGA_CRT_DDCCLK [85]
VGA_CRT_DDCDATA [85]
VGA_CRT_HSYNC [85]
VGA_CRT_VSYNC [85]
3D3V_VGA_S0

PAD-10P-177042-GP

48

ZZ.00PAD.Y41

45

46

47

ER8202 1

2 0R0603-PAD-2-GP

USB_PN1 [18]

3D3V_S0

AUD_PC_BEEP

AUD_PC_BEEP

C8253
C8254

1
1

2 SCD1U10V2KX-5GP SB_SPKR_R
2 SCD1U10V2KX-5GP KBC_BEEP_R

R8233
R8234

HDA_CODEC_SDOUT
HDA_SDIN0

[21]

[21]

HDA_CODEC_SYNC [21]
AMP_MUTE# [27]
HDA_CODEC_RST# [21]

USB_PP10_C
USB_PN10_C

AUD_DMIC_CLK [49]
AUD_DMIC_IN0 [49]
USB_PW R_EN# [27]
USB_OC#0_1 [18,62]

R8230
10KR2J-3-GP

A00 3/23
X01 12/23
X01 12/13
USB_PP10_C

ER8203 1

2 0R0603-PAD-2-GP

USB_PP10 [18]

ER8204 1

2 0R0603-PAD-2-GP

HDA_SPKR [21]
KBC_BEEP [27]

R8231
10KR2J-3-GP

HDA_CODEC_BITCLK_C

USB_PN10_C

2
2100KR2J-1-GP
100KR2J-1-GP

A00 3/23
X01 12/23
X01 12/13

HDA_CODEC_BITCLK_C
USB3_TX2_P [18]
USB3_TX2_N [18]

1
1

USB_PP1_C
USB_PN1_C

44

USB_PN1_C
5V_S0

5V_S5

USB_PN10 [18]

43

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51

42

50
1

41

1
2
ER8205
0R0402-PAD-2-GP

HDA_CODEC_BITCLK

[21]

EC8206
SC10P50V2JN-4GP

USB3_RX2_N [18]
USB3_RX2_P [18]
5V_S5

5V_S0

3D3V_S0

49

C8205

2
1

EC8207

C8203

2
1

EC8202

1
2

2
1

EC8201

DY

SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

DY

SC10U6D3V3MX-GP

X01 12/09 Request by EMI

SCD1U16V2KX-3GP

DY

SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

20.F2091.040
2nd = 20.F2089.040

C8202

FOX-CON40-2R-1-GP
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

IO Board Connector

Size
A3

Document Number

Date:

Friday, March 30, 2012

A00 3/27
3

Rev

BMW Z4 DIS

A00
Sheet
1

82

of

105

SSID = VIDEO
[4] PEG_TXP[7..0]

PEG_RXP[7..0] [4]

1 OF 7

VGA1A

[4] PEG_TXN[7..0]

PEG_RXN[7..0] [4]

AF30
AE31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AH30 PEG_C_RXP0
AG31 PEG_C_RXN0

C8318
C8317

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP0
SCD1U10V2KX-5GP PEG_RXN0

PEG_TXP1
PEG_TXN1

AE29
AD28

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AG29 PEG_C_RXP1
AF28 PEG_C_RXN1

C8320
C8319

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP1
SCD1U10V2KX-5GP PEG_RXN1

PEG_TXP2
PEG_TXN2

AD30
AC31

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27 PEG_C_RXP2
AF26 PEG_C_RXN2

C8321
C8322

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP2
SCD1U10V2KX-5GP PEG_RXN2

PEG_TXP3
PEG_TXN3

AC29
AB28

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

AD27 PEG_C_RXP3
AD26 PEG_C_RXN3

C8323
C8328

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP3
SCD1U10V2KX-5GP PEG_RXN3

PEG_TXP4
PEG_TXN4

AB30
AA31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

AC25 PEG_C_RXP4
AB25 PEG_C_RXN4

C8327
C8326

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP4
SCD1U10V2KX-5GP PEG_RXN4

PEG_TXP5
PEG_TXN5

AA29
Y28

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

Y23 PEG_C_RXP5
Y24 PEG_C_RXN5

C8335
C8336

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP5
SCD1U10V2KX-5GP PEG_RXN5

PEG_TXP6
PEG_TXN6

Y30
W31

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

AB27 PEG_C_RXP6
AB26 PEG_C_RXN6

C8330
C8329

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP6
SCD1U10V2KX-5GP PEG_RXN6

PEG_TXP7
PEG_TXN7

W29
V28

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

Y27 PEG_C_RXP7
Y26 PEG_C_RXN7

C8332
C8331

1
1

SG22
SG

SCD1U10V2KX-5GP PEG_RXP7
SCD1U10V2KX-5GP PEG_RXN7

V30
U31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

W24
W23

U29
T28

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

V27
U26

T30
R31

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

U24
U23

R29
P28

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

T26
T27

P30
N31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

T24
T23

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

P27
P26

M30
L31

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

P24
P23

L29
K30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

M27
N26

PCI EXPRESS INTERFACE

PEG_TXP0
PEG_TXN0

X01 12/15
C

CLOCK

AK30
AK32

[20] CLK_PCIE_VGA
[20] CLK_PCIE_VGA#

X03 2/6
[22] DGPU_HOLD_RST#

PCIE_REFCLKP
PCIE_REFCLKN

2
0R0402-PAD-2-GP

R8322

VGA_RST# [85]

1V_VGA_S0
CALIBRATION

1
R8317

SG

PW RGOOD
10KR2F-2-GP

N10

VGA_RST# AL27

PERST#

C8333
ROBSON-GP-U
SC47P50V2JN-3GP

Y22 PCIE_CALRP

PCIE_CALRN

AA22 PCIE_CALRN

1
R8326

1
R8318

SG
SG

2
1K27R2F-L-GP

2
2KR2F-3-GP

SG

DY

PWRGOOD

PCIE_CALRP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_PEG/STRAPPING(1/5)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Sheet
1

Rev

A00

BMW Z4 DIS
83

of

105

SSID = VIDEO

1D5V_VGA_S0

SG R8410
40D2R2F-GP

R8414
100R2F-L1-GP-U

SG

MVREFSA
C8403

R8415
100R2F-L1-GP-U

SG SCD1U10V2KX-5GP

SG

C8402
SCD1U10V2KX-5GP

MVREFDA

SG

R8411
40D2R2F-GP

SG

1D5V_VGA_S0

Layout Note:
Place MVREF R & C close to GPU

R8403 1
R8406 1

SG
SG

2 240R2F-1-GP MEM_CALRN0
2 240R2F-1-GP MEM_CALRP0

R8407
150R2F-1-GP
1
2

2
R8402
10R2J-2-GP

SG

25mm (Max)

SC120P50V2JN-1GP

C8401

DRAM_RST

SG

R8404
5K1R2F-2-GP

5mm (Max)

MVREFDA
MVREFSA

MEM_CALRP1/DPC_CALR
MEM_CALRP0

DRAM_RST_1

K26
J26

TP8401
TPAD14-OP-GP

SG

1CLKTESTA
1CLKTESTB

TP8402
TPAD14-OP-GP

MEM_CALRN0
TESTEN

J8
K25

MEM_CALRP1/DPC_CALR
MEM_CALRP0

L10

DRAM_RST

MAA0_8
MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14/BA0
MAA_15/BA1
MAA_BA2

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G20
J16
L15
G11

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

W CKA0_0 [88]
W CKA0_0# [88]
W CKA0_1 [88]
W CKA0_1# [88]
W CKA1_0 [89]
W CKA1#_0 [89]
W CKA1_1 [89]
W CKA1#_1 [89]

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ODTA0
ODTA1

L18
K16

ADBIA0 [88]
ADBIA1 [89]

CLKA0
CLKA0#

H26
H25

CLKA0 [88]
CLKA0# [88]

CLKA1
CLKA1#

G9
H9

CLKA1 [89]
CLKA1# [89]

RASA0#
RASA1#

G22
G17

RASA0# [88]
RASA1# [89]

CASA0#
CASA1#

G19
G16

CASA0# [88]
CASA1# [89]

CSA0#_0
CSA0#_1

H22
J22

CSA0#_0 [88]

CSA1#_0
CSA1#_1

G13
K13

CSA1#_0 [89]

CKEA0
CKEA1

K20
J17

CKEA0 [88]
CKEA1 [89]

WEA0#
WEA1#

G25
H10

PX_EN

AB16

MAA0_[8..0] [88]

MAA1_[8..0] [89]

MAA0_8
MAA1_6
MAA1_7
MAA1_5
MAA1_8

[88]
[88]
[88]
[88]
[89]
[89]
[89]
[89]

[88]
[88]
[88]
[88]
[89]
[89]
[89]
[89]

X01 11/28

W EA0# [88]
W EA1# [89]
PX_EN_R

K8
L7

CLKTESTA
CLKTESTB

R8408
0R2J-2-GP
2

DY

PX_EN [86]

X01 12/12

SG

RSVD#G14

G14

MAA1_8

R8412
4K7R2J-2-GP

SG

ROBSON-GP-U

SG

MVREFDA
MVREFSA

MEM_CALRN0 J25
TESTEN
K7

[85] TESTEN

SG

[88,89] MEM_RST

R8405
51R2J-2-GP
1
2

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

1D5V_VGA_S0

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

[89] DQA1_[31..0]

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MEMORY INTERFACE

3 OF 7

VGA1C

[88] DQA0_[31..0]

25mm (Max)
DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Layout Note:
Title

Place all these components very close to GPU

(Within 25mm) and keep all component close
to each Other (within 5mm) except R_MEM_2

GPU Memory(2/5)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

84

of

105

SSID = VIDEO
MEMORY ID Table
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

STRAPS

PIN

RECOMMEND

GPIO0

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED

0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

BIF_GEN2_EN_A

GPIO2

0:Advertises the PCIe device as 2.5GT/s capable at power on.

1:Advertises the PCIe device as 5.0GT/s capable at power on.

GPIO5_AC_BATT

GPIO5

optional input allow the system to request a fast

power reduction by setting GPIO5 to low.

GPIO8_ROMSO

GPIO8

RESERVED

VGA_DIS
ROMIDCFG[2:0]

GPIO[13:11]

GDDR5 1.25GHZ Hynix-H5GQ2H24AFR-T2C 128M*16

0001

GDDR5 1.25GHZ Hynix-H5GQ2H24MFR-T2C 128M*16

VGA1B

GDDR5 1.25GHZ SAMSUNG-K4G20325FD-FC04 128M*16

1D8V_VGA_S0

X01 12/02
R8519
R8518

HYNIX_RTS
1
2
1
2
HYNIX

2 OF 7

M93-S3/M92-S2

DVPDATA[0:3] Default:Pull down

0
0 0 1
(256MB)

BIOS_ROM_EN=1, Config[2:0] defines the ROM type

BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

Description

0011

0000

0:VGA Controller capacity enabled

1:The device won't be recognized as the system's VGA controller

GPIO9

DVPDATA[3:0]

PLATFORM
SETTING

Transmitter Power Savings Enable

0: 50% Tx output swing 1: Full Tx output swing

TX_PWRS_ENB

10KR2J-3-GP MEM_ID1
10KR2J-3-GP MEM_ID0

AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

DVCNTL_0/DVPDATA_18
DVCNTL_1/NC#L9
DVCNTL_2/TESTEN#2
DVDATA_12/DVPDATA_16
DVDATA_11/DVPDATA_20
DVDATA_10/DVPDATA_22
DVDATA_9/DVPDATA_12
DVDATA_8/DVPDATA_14
DVDATA_7/DVPCNTL_0
DVDATA_6/DVPDATA_8
DVDATA_5/DVPDATA_6
DVDATA_4DVPDATA_4
DVDATA_3/DVPDATA_19
DVDATA_2/DVPDATA_21
DVDATA_1/DVPDATA_2
DVDATA_0/DVPDATA_0

TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N

DPA

TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N

DVO

TX5P_DPB0P
TX5M_DPB0N

1D8V_VGA_S0

AC6
AC5

330mA

L8507

AUD[0]

VSYNC

SG

AUD[1:0]:11-Audio for both DisplayPort and HDMI

C8527

SC1U6D3V2KX-GP

BLM15BD121SS1D-GP

DY
2

68.00084.F81
2ND = 68.00217.701

DY

DPC_PVDD/DVPDATA_11
DPC_PVSS/GND
DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23
DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17

U1
W1
U3
Y6
AA1

AJ7
AH6
RN8504
SRN4K7J-8-GP

AK8
AL7

SG

DVPDATA_7/TX0P_DPC2P
DVPDATA_1/TX0M_DPC2N

Q8503

DPC_VSSR#1/DVPCLK
DVPDATA_13/TX2P_DPC0P
DPC_VSSR#2/DVPDAT5
DVPCNTL_1/TX2M_DPC0N
DPC_VSSR#3/GND
DPC_VSSR#4/GND
NC#AA12
DPC_VSSR#5/DVPCNTL_MV0

V4
U5

W3
V2

SML1_CLK [20,27,28]

SG

2N7002KDW-GP

Y4
W5

SML1_DATA [20,27,28]
GPIO_VGA_03_DATA

AA3
Y2

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

AA12

X03 2/6

DPC
AVDD_A2VDDQ

1
2
TX_PWRS_ENB

R8541

TX_DEEMPH_EN

R8535

TX_PWRS_ENB
TX_DEEMPH_EN
BIF_GEN2_EN_A
GPIO_VGA_03_DATA
GPIO_VGA_04_CLK
GPIO5_AC_BATT
GPIO6_VGA
VGA_BLEN
1R8523
2
10KR2J-3-GPGPIO_8_ROMSO
VGA_DIS
GPIO_10_ROMSCK
CONFIG0
CONFIG1
CONFIG2

BIF_GEN2_EN_A
TPAD14-OP-GP

TP8501

A00 3/15
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
C

10KR2J-3-GP

R8533

SG
DY
DY

R8534

CONFIG0

R8538

CONFIG1

R8520

CONFIG2

[92] PWRCNTL_0

SG

1 R8503

GPIO17_VGA

DY

1 R8530

GPIO5_AC_BATT

10KR2J-3-GP

10KR2J-3-GP

DY
DY

TPAD14-OP-GP

TP8502

TPAD14-OP-GP

TP8503

SG

VGA_DIS

DY

TPAD14-OP-GP

TP8504

TPAD14-OP-GP

TP8505

PWRCNTL_0
GPIO16_SSIN
GPIO17_VGA
GPIO18_VGA
THERMTRIP_VGA
PWRCNTL_1

[92] PWRCNTL_1

PEG_CLKREQ#

[20] PEG_CLKREQ#

1 R8540

VGA_CRT_VSYNC

1 R8542

VGA_CRT_HSYNC

R8545

PWRCNTL_0

TPAD14-OP-GP

TP8506

JTAG_TRST#_VGA
JTAG_TDI_VGA
JTAG_TCK_VGA
JTAG_TMS_VGA
JTAG_TDO_VGA
RSVD
1

R8544

PWRCNTL_1

TPAD14-OP-GP
TPAD14-OP-GP

TP8507
TP8508

1
1

1D8V_VGA_S0

3KR2J-2-GP

SG
SG

3KR2J-2-GP

AB13
W8
W9
W7
GENERICE_HPD4
AD10
AC14

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB

JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
RSVD#AF24

G
G#

HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2/NC#AM12
R2#/NC#AK12
G2/NC#AL11
G2#/NC#AJ11
B2/NC#AK10
B2#/NC#AL9

DAC2

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

VDD2DI/NC#AD19
VSS2DI/NC#AC19

HPD1

A2VDD/NC#AE20

SG

C8514
SCD1U10V2KX-5GP

AC16

R2SET/NC#AG13

R8509 1

DY

2 10KR2J-3-GP

JTAG_TRST#_VGA

R8512 1

DY

2 10KR2J-3-GP

JTAG_TMS_VGA

DY

R8517 1
R8526 1

TESTEN

TESTEN [84]

C8509
SC10U6D3V3MX-GP

JTAG_TDO_VGA

1
2

R8506

GPU_RSET

AD22

1
R8539

AG24
AE22

AVDD_A2VDDQ

AE23
AD23

VDD1DI

2
499R2F-2-GP

SG

C8544

DY

AUX1P
AUX1N

AM28
AK28

AC22
AB22

DPLL_VDDC

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N

NC#AC22/XO_IN
NC#AB22/XO_IN2

DDC6CLK
DDC6DATA

THERMAL
P2800_VGA_DXP
P2800_VGA_DXN

T4
T2

NC#AD20/DDCCLK_AUX3P
NC#AC20/DDCDATA_AUX3N

45mA

0R0603-PAD-2-GP
C8545
SCD1U10V2KX-5GP

DY

AVSSQ

X03 2/6
AM12
AK12

AVSSQ

R8507

0R0402-PAD-2-GP

AL11
AJ11

LVDS Interface
AVSSQ

AK10
AL9

VGA1F

6 OF 7
RN8502
SRN10KJ-5-GP

AH12
AM10
AJ9

LVDS CONTROL

VARY_BL
DIGON

AB11
AB12

VARY_BL
DIGON

1
2

SG

4
3

AL13
AJ13
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AD19
AC19

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AE20
AE17

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

A00 3/15

AE19
AG13

R2SET

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
2

DY

TXOUT_U3P
TXOUT_U3N

AE6
AE5

VGA_CRT_DDCCLK [82]
VGA_CRT_DDCDATA [82]

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AC11
AC13

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AD13
AD11

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AE16
AD16

SG

AD20
AC20

AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23

LVTMDP

AD2
AD4

AC1
AC3

AH20
AJ19

TXOUT_L3P
TXOUT_L3N

AL15
AK14
AH16
AJ15
AL17
AK16
AH18
AJ17
AL19
AK18

ROBSON-GP-U

DPLUS
DMINUS
B

DY

SG

C8521
SC1U6D3V2KX-GP

SG

SG

68.00084.F81
2ND = 68.00217.701

2 10KR2J-3-GP

2 0R2J-2-GP XO_IN
2 0R2J-2-GP XO_IN2

TP8511
1
TPAD14-OP-GP

5mA

BLM15BD121SS1D-GP

JTAG_TCK_VGA

DY

TSVDD

DY

DY

[28] P2800_VGA_DXN
L8509

1
2 10KR2J-3-GP

DPLL_PVDD
DPLL_PVSS

X01 12/02

C8523
SC2200P50V2KX-2GP

2 5K11R2F-L1-GP

DY

DY
DY

[28] P2800_VGA_DXP

1D8V_VGA_S0

SG

DY

XTALIN_R
XTALOUT_R

0R2J-2-GP

R8525
XTALIN_R

2 10KR2J-3-GP

DY

DDC1CLK
DDC1DATA

DDC/AUX

C8519

DY

DY

C8502
SC10U6D3V3MX-GP

FAN_PWM_C

R5
AD17
AC17

C8522
SCD1U10V2KX-5GP

TS_FDO
TSVDD
TSVSS

SG

ROBSON-GP-U

R8513 1

AF14
AE14
AD14

JTAG_TDI_VGA

C8518
SCD1U10V2KX-5GP

2 10KR2J-3-GP

C8508
SC10U6D3V3MX-GP

AVSSQ

1
[82]
[82]

M92-S2/M93-S3

PLL/CLOCK

125mA
SC1U6D3V2KX-GP

DY

VGA_CRT_HSYNC
VGA_CRT_VSYNC

715R2F-GP

M92-S2/M93-S3

DPLL_VDDC

BLM18PG471SN1D-GP

A2VDDQ/NC#AE17
VREFG
A2VSSQ

75mA

R8508 1

VGA_B [82]

SC1U6D3V2KX-GP
DY

DY

R8501

68.00143.181
2nd = 68.00214.211

DY

VDD1DI

SG

DY

L8512

SG

C8536
SC10U6D3V3MX-GP

[82]

AH26
AJ27

DY

R8516
249R2F-GP

C8516

1V_VGA_S0

3D3V_VGA_S0

C/NC#AH12
Y/NC#AM10
COMP/NC#AJ9
H2SYNC
V2SYNC

SCD1U10V2KX-5GP

C8515

DY

C8505
SC10U6D3V3MX-GP

68.00143.181
2nd = 68.00214.211

SC1U6D3V2KX-GP

BLM18PG471SN1D-GP

VGA_G [82]

AH24
AG25

L8508

SG

VGA_R

AL25
AJ25

M92-S2/M93-S3

GPU_VREFG

B
B#

DAC1

AM26
AK26

DPLL_PVDD

L6
L5
L3
L1
K4
AF24

GEN_A
GEN_B

TP8509
1
TPAD14-OP-GP
TP8510
1HDMI_HPD_DET
TPAD14-OP-GP

R8515

SG 499R2F-2-GP
1D8V_VGA_S0

U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7

R8537

0R0603-PAD-2-GP
C8543

10KR2J-3-GP

SG
SG
SG

C8542

3KR2J-2-GP

SC1U6D3V2KX-GP

R
R#

GENERAL PURPOSE I/O

3KR2J-2-GP

SCD1U10V2KX-5GP

I2C

SCL
SDA

R1
R3

1D8V_VGA_S0

70mA

R8504

3D3V_VGA_S0

R8524 1

3D3V_VGA_S0

AK6
AM5

DY
BACO_SCL
BACO_SDA

R8514 1

AK5
AM3

M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N

RN8505
SRN4K7J-8-GP

Straps Pin

R8543

AK3
AK1

GPIO_VGA_04_CLK

DVPCNTL_MV1/TX1P_DPC1P
DVPDATA_9/TX1M_DPC1N

3D3V_VGA_S0

4
3

RESERVED

HSYNC

AA5
AA6

DPC_VDD10

RESERVED

GENERICC

C8528

H2SYNC

RSVD
AUD[1]

RSVD

AH3
AH1

M93-S3/M92-S2
W6
V6
1V_VGA_S0

VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.

V2SYNC

BIOS_ROM_EN GPIO_22_ROMCSB
VIP_DEVICE_STRAP_EN

0
X

AG3
AG5

1
2

RESERVED
0:Disable external BIOS ROM device
1:Enable external BIOS ROM device

SCD1U10V2KX-5GP

GPIO21

GPIO21_BB_EN

AF2
AF4

DESCRIPTION OF DEFAULT SETTINGS

4
3

CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

THERMTRIP_R

X8501

THERMTRIP_VGA

4
R8522
10KR2J-3-GP

XTAL_X1

SG

DY

SGC8524

SG

SC18P50V2JN-1-GP

84.2N702.A3F
2nd = 84.DM601.03F

XTAL_X2

DY2
R8511
1MR2F-GP

6
Q8501
2N7002KDW-GP

SG
XTAL-27MHZ-84-GP

C8525
SC18P50V2JN-1-GP

PURE_HW_SHUTDOWN#

R8521

[83] VGA_RST#

DY

[27,28,36]

Q5801_2

82.30034.651
2nd = 82.30034.681

0R2J-2-GP

C8529

DY SCD1U10V2KX-4GP
X01 11/28

3D3V_VGA_S0

3D3V_VGA_S0

SG

VDD_100M
VDD_27M

27M

1
10

XIN
XOUT
SS_SEL0
SS_SEL1

CLK_27R

R8502
CLK_100R
1
R8510

SG
SG

2
2

XO_IN
47R2J-2-GP
XO_IN2
33R2J-2-GP

3.3V
3.3V

SG
GND_27M
GND_100M
GND

2
6
11

7
3

R8536
10KR2J-3-GP

SG

6V40088DNBGI8-GP

71.64088.003
2nd = 71.16020.003

DMB40

R8528
10KR2J-3-GP

1.8V

R8527
150R2F-1-GP

SS_SEL0
SS_SEL1

10KR2J-3-GP

4
8

100M

2
2 10KR2J-3-GP

DY
DY

DY

U8506
3D3V_S0_U8606

XTAL_X1
XTAL_X2

1
R8531 1
R8532

XTALIN_R

C8535
SCD1U10V2KX-5GP

DY SG C8532 DY C8534 SG
SC1U6D3V2KX-GP

X01 11/28

SC1U6D3V2KX-GP

C8533

DY

R8529
124R2F-U-GP

SCD1U10V2KX-5GP

SG

68.00082.531
2nd = 68.00226.031
3rd = 68.00040.111

1
L8501

BLM18BD601SN1D-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_DP/LVDS/CRT/GPIO(3/5)
5

Size
A1

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS
1

A00
Sheet

85

of

105

SSID = VIDEO

VGA1D

4 OF 7

1D8V_VGA_S0

1D5V_VGA_S0
MEM I/O

C8694
SCD1U10V2KX-5GP

C8692
SC1U6D3V2KX-GP

1
2

SG

C8663
SC10U6D3V3MX-GP

SG

C8602
SC1U6D3V2KX-GP

2
1

DY

1V_VGA_S0

1
2
1
2

C8650
SC22U6D3V5MX-2GP

C8603
SC1U6D3V2KX-GP

2
1

C8642
SC22U6D3V5MX-2GP

C8638
SC1U6D3V2KX-GP

1
2
1

C8647
SC22U6D3V5MX-2GP

SG

SG

SG

DY

2
1
C8658
SC1U6D3V2KX-GP

SG

C8664
SC4D7U25V5KX-GP

VGA_CORE
C8660
SC1U6D3V2KX-GP

C8657

DY
1

C8656

SG

SCD1U10V2KX-5GP

SG

C8655

SCD1U10V2KX-5GP

SG

SPVSS

SG

SG

3.9A

SPV10

SG

SG

DY

DY

C8662
SC4D7U6D3V3KX-GP

1
2

C8636
SC1U6D3V2KX-GP

SG

C8651
SC10U6D3V3MX-GP
2
1

1
2

C8637
SC1U6D3V2KX-GP

DY

SG

C8654
SC10U6D3V3MX-GP
2
1

1
2

C8634
SC1U6D3V2KX-GP

1
2

C8639
SC1U6D3V2KX-GP

C8645
SC10U6D3V3MX-GP
2
1

SG

DY

M13
M15
M16
M17
M18
M20
M21
N20

55mA

SG

C8604
SC1U6D3V2KX-GP

VGA_CORE

SPV18

BBP#1
BBP#2

SG

1
2

C8632
SC1U6D3V2KX-GP

1
2

C8631
SC1U6D3V2KX-GP

1
2

C8630
SC1U6D3V2KX-GP

C8629
SC1U6D3V2KX-GP

SG

C8633
SC1U6D3V2KX-GP
C8643
SC10U6D3V3MX-GP
2
1

1
2

C8616
SC1U6D3V2KX-GP

1
2

C8615
SC1U6D3V2KX-GP

1
2

C8617
SC1U6D3V2KX-GP

1
2

C8613
SCD1U10V2KX-5GP

C8614
SCD1U10V2KX-5GP

C8628
SC1U6D3V2KX-GP

BIF_VDDC

BACK BIAS
M11
M12

DY

C8659
SC1U6D3V2KX-GP

MPV18

DY

DY

1
2

DY

J7

ROBSON-GP-U

DY

DY

1
2

DY

C8611
SC10U6D3V3MX-GP

68.00084.F81
2ND = 68.00217.701

DY

C8649
SCD1U10V2KX-5GP

SPV18

50mA
2

H8
C8646
SC1U6D3V2KX-GP

DY

DY

SG
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

PCIE_PVDD

SG

SG

SPV10

2
1

SG

VSSRHA

SG

SCD1U10V2KX-5GP

L8

68.00143.181
2nd = 68.00214.211

BLM15BD121SS1D-GP

MPV18

H7
1

ISOLATED
CORE I/O

PLL

SPV18

BLM18PG471SN1D-GP

SG

L16

AM30

SG

22A
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
R21
U21

VDDRHA

MPV18

L8605

100mA

L8604

MEM CLK
L17

SG

DY

NC#V11/VDDR5
NC#U11

SG

C8640
SC1U6D3V2KX-GP

C8690
SCD1U10V2KX-5GP

C8691
SCD1U10V2KX-5GP
2
1

SG
2

DY

C8619
SC1U6D3V2KX-GP

SG

C8612
SC10U6D3V3MX-GP
2
1

1V_VGA_S0

C8622
SC1U6D3V2KX-GP
2
1

1
2

DY

C8620
SC10U6D3V3MX-GP
2
1

68.00143.181
2nd = 68.00214.211

NC#AA11/VDDR4
DVCLK/VDDR4

C8674

SG

SG

BLM18PG471SN1D-GP

VDDR4/VDDR5
VDDR4
VDDR4/VDDR5

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

MPV18

150mA

L8603

V11
U11

68.00084.F81
2ND = 68.00217.701
1

AA11
Y11

I/O

DY

1.1A

BLM15BD121SS1D-GP

V12
Y12
U12

VDDR3
VDDR3
VDDR3
VDDR3

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC/BIF_VDDC
CORE

SG

1
1

1
2

C8652
SC1U6D3V2KX-GP

C8678
SC1U6D3V2KX-GP

DY

VDD_CT
VDD_CT
VDD_CT
VDD_CT

M93-S3/M92-S2
AA17
AA18
AB17
AB18

SCD1U10V2KX-5GP

170mA

SG

C8667
C8653
SC1U6D3V2KX-GP SCD1U10V2KX-5GP

L8602

DY

DY

C8668
SC1U6D3V2KX-GP

VDDR4

SG

C8681
SC1U6D3V2KX-GP
C8618
SC10U6D3V3MX-GP

DY

2
1

60mA

DY

3D3V_VGA_S0

SG

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

LEVEL
TRANSLATION

VDDC_CT
AA20
AA21
AB20
AB21

C8626
SC10U6D3V3MX-GP

SG

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

POWER

BLM15BD121SS1D-GP

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

C8641
SC1U6D3V2KX-GP

1
2

DY DY

C8625
SC4D7U6D3V3KX-GP

C8610
SC1U6D3V2KX-GP

2
1
2

C8624
SC4D7U6D3V3KX-GP

1
2

1
2

1
2

C8609
SC1U6D3V2KX-GP
C8623
SC4D7U6D3V3KX-GP

DY

SG

68.00084.F81
2ND = 68.00217.701

C8608
SC1U6D3V2KX-GP

DY

SG

17mA

L8601
1

DY

SG

C8644
SC10U6D3V3MX-GP
2
1

1D8V_VGA_S0

C8607
SC1U6D3V2KX-GP

2
1
2

DY

DY

SG

C8648
SC10U6D3V3MX-GP
2
1

C8606
SC1U6D3V2KX-GP

C8621
SC10U6D3V3MX-GP
2
1

SG

440mA

PCIE
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

C8661
SC10U6D3V3MX-GP
2
1

1.2A

VGA_CORE

2N7002K-2-GP
[84] PX_EN

A00 3/27

G
D

BIF_VDDC

VGA_CORE
R8612
0R0402-PAD-2-GP
1
2

8209A_EN/DEM_VGA

[92,93]

DY
Q8601

84.2N702.J31
2ND = 84.2N702.031

X01 12/15
X01 11/28

X01 11/28
VGA_CORE

DY

84.03400.B37
2nd = 84.03203.031

U8604
AO3418-GP
D

BIF_VDDC_1V

DY

3D3V_VGA_S0

R8603
1KR2J-1-GP

1V_VGA_S0

DY

84.03418.031
2nd = 84.P8503.031

DY

84.03418.031
2nd = 84.P8503.031

R8604
1KR2J-1-GP

DY

U8602
AO3418-GP

BIF_VDDC

84.03400.B37
2nd = 84.03203.031

BIF_VDDC_CORE

DY
3D3V_VGA_S0

U8603
AO3400A-GP
D

U8601
AO3400A-GP

BIF_VDDC

PX_EN_VDDC

PX_EN_1V

X01 12/15
X01 11/28

X01 12/15

X01 11/28
Q8602

[22,27,92,93]

DGPU_PWROK

R8601
0R2J-2-GP
2

DY

Q6802_5

PX_EN_VDDC

3
2

PX_EN_1V

DY

2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F
<Core Design>

PX4.0
PX4.0
Mode

PX_EN

PX_EN_1V

PX_EN_VDDC

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

BIF_VDDC
POP

DIS

Low

Low

High

VGA_CORE

BACO

High

High

Low

1V_VGA_S0

Q8601, Q8602, R8601, U8601, U8602, U8603

U8604, R8603, R8604, R8408

POP

DY

R8612
4

R8612
Title

DY

Wistron Corporation

PX5.0

GPU_POWER(4/5)

Q8601, Q8602, R8601, U8601, U8602, U8603

U8604, R8603, R8604, R8605, R8408

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

86

of

105

SSID = VIDEO
For Video output port power rail.
1D8V_VGA_S0
1D8V_VGA_S0

DPEF_VDD18

DPAB_VDD18
7 OF 7

VGA1G

330mA

L8703

L8701

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

SG

VSS_MECH
VSS_MECH
VSS_MECH

A32 VSS_MECH1
AM1 VSS_MECH2
AM32 VSS_MECH3

AF16
AG17

DPF_VDD18
DPF_VDD18

DPB_VDD18
DPB_VDD18

AE13
AF13

DPAB_VDD18

DPEF_VDD10

SG

330mA

1
2

1
2

DY

68.00084.F81
2ND = 68.00217.701

1V_VGA_S0
L8704

C8732

DY

SG

BLM15BD121SS1D-GP

SG

BLM15BD121SS1D-GP

68.00084.F81
2ND = 68.00217.701

DPAB_VDD10

DPCD_CALR

R8701
150R2F-1-GP

DY

SC10U6D3V3MX-GP

AE1
AE3
AG1
AG6
AH5

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

DY

DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR

C8712
SC1U6D3V2KX-GP

AG14
AH14
AM14
AM16
AM18

330mA
1

DPA_VDD10
DPA_VDD10

DPE_VDD10
DPE_VDD10

AF6
AF7

DPEF_VDD18

C8714
SCD1U10V2KX-5GP

1
DPAB_VDD10

AG20
AG21

DY

C8734

SC10U6D3V3MX-GP

DY

C8719
SCD1U10V2KX-5GP

1
2

1
2

DY

C8718
SC1U6D3V2KX-GP

DY

DPEF_VDD10

DY

C8703
SC1U6D3V2KX-GP

68.00084.F81
2ND = 68.00217.701

AE11
AF11

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11

DPA_VDD18
DPA_VDD18

C8702
SCD1U10V2KX-5GP

GND
GND
GND/EVDDQ
GND
GND
GND/EVDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DPE_VDD18
DPE_VDD18

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

SC10U6D3V3MX-GP

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

AG15
AG16

C8725
SCD1U10V2KX-5GP

SG

BLM15BD121SS1D-GP C8726

DY

5 OF 7

VGA1E

DY

L8702

DY

C8720
SC1U6D3V2KX-GP

1V_VGA_S0

C8731

68.00143.181
2nd = 68.00214.211

SC10U6D3V3MX-GP

BLM18PG471SN1D-GP

DP A/B POWER

DP E/F POWER

SG

1
D

AF22
AG22

DPF_VDD10
DPF_VDD10

DPB_VDD10
DPB_VDD10

AF8
AF9

AF23
AG23
AM20
AM22
AM24

DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

AF10
AG9
AH8
AM6
AM8

AF17

DPEF_CALR

DPAB_CALR

330mA

AE10 DPAB_CALR

DPEF_VDD18

DPAB_VDD18

AG18
AF19
DPEF_VDD18

AG19
AF20

DPE_PVDD
DPE_PVSS

DPF_PVDD
DPF_PVSS

DP PLL POWER

SG

DPA_PVDD
DPA_PVSS

AG8
AG7

DPB_PVDD
DPB_PVSS

AG10
AG11

SG

R8703
150R2F-1-GP

DPAB_VDD18

ROBSON-GP-U

TP8701
TP8702
TP8703

1
1
1

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

ROBSON-GP-U

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_DPPWR/GND(5/5)

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

87

of

105

SG

[84,89]

VRAM1_ZQ

RESET#

J10
J13
J1

[84] WCKA0_1
[84] WCKA0_1#

D4
D5

[84] WCKA0_0
[84] WCKA0_0#

P4
P5

SEN
ZQ
MF
WCK1
WCK1#
WCK23
WCK23#

SG

SG

C8867
SC1U6D3V2KX-GP

SG

R8832
5K49R2F-GP

C8866
SC1U6D3V2KX-GP

SG

VREFD2_A0

SG

SGC8864
SC1U6D3V2KX-GP

VREFD1_A0

R8825
5K49R2F-GP

SG

C8865
SC1U6D3V2KX-GP

SG

2
1

VREFC_A0

R8822
5K49R2F-GP

R8829
2K37R2F-GP

A5
U5

SG

EDC0
EDC1
EDC2
EDC3

SG

[84] CKEA0

D2
D13
P13
P2

[84] DDBIA0_1
1D5V_VGA_S0
[84] DDBIA0_3
1D5V_VGA_S0
[84,89]

J2

MEM_RST
VRAM2_ZQ

MF=1
Mirror

C2
C13
R13
R2

EDCA0_2 [84]

1D5V_VGA_S0

J10
J13
J1

[84] WCKA0_0
[84] WCKA0_0#

D4
D5

[84] WCKA0_1
[84] WCKA0_1#

P4
P5

EDCA0_0 [84]

CK
CK#
CKE#
DBI0#
DBI1#
DBI2#
DBI3#
RESET#
SEN
ZQ
MF
WCK1
WCK1#
WCK23
WCK23#

SG

EDC0
EDC1
EDC2
EDC3

C2
C13
R13
R2

SGC8868
SC1U6D3V2KX-GP

SG

R8835
2K37R2F-GP

DQA0_29
DQA0_31
DQA0_26
DQA0_30
DQA0_27
DQA0_28
DQA0_24
DQA0_25

SG

SGC8870
SC1U6D3V2KX-GP

VREFC_A1

R8834
5K49R2F-GP

R8837
2K37R2F-GP

SG

SG

C8869
SC1U6D3V2KX-GP

SG

1D5V_VGA_S0

SGC8872
SC1U6D3V2KX-GP

R8833
2K37R2F-GP

1D5V_VGA_S0

1D5V_VGA_S0

VREFD1_A1

R8836
5K49R2F-GP

SG

SG

C8871
SC1U6D3V2KX-GP

VREFD2_A1

R8838
5K49R2F-GP

J12
J11
J3

[84] CLKA0
[84] CLKA0#

DQA0_0
DQA0_3
DQA0_1
DQA0_2
DQA0_6
DQA0_4
DQA0_7
DQA0_5

ABI#
RAS#
CS#
CAS#
WE#

DQA0_12
DQA0_13
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_15
DQA0_14

SG

SG
1

J4
G3
G12
L3
L12

ADBIA0
CASA0#
WEA0#
RASA0#
CSA0#_0

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

H11
K10
K11
H10

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

MAA0_4
MAA0_3
MAA0_2
MAA0_5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5

K4
H5
H4
K5
J5

[84]
[84]
[84]
[84]
[84]

MAA0_0
MAA0_6
MAA0_7
MAA0_1
MAA0_8

[84]

DQA0_22
DQA0_20
DQA0_23
DQA0_21
DQA0_19
DQA0_17
DQA0_16
DQA0_18

[84]

DQA0_[31..0]
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

DQA0_[31..0]

2 OF 2

VRAM2B

C8873
SC1U6D3V2KX-GP

DBI0#
DBI1#
DBI2#
DBI3#

J2

MEM_RST

SGC8863
SC1U6D3V2KX-GP

CK
CK#
CKE#

D2
D13
P13
P2

SG

[84] CKEA0
[84] DDBIA0_2
1D5V_VGA_S0
[84] DDBIA0_0
1D5V_VGA_S0

R8824
2K37R2F-GP

ABI#
RAS#
CS#
CAS#
WE#

J12
J11
J3

[84] CLKA0
[84] CLKA0#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

BA0/A2
BA1/A5
BA2/A4
BA3/A3

J4
G3
G12
L3
L12

ADBIA0
RASA0#
CSA0#_0
CASA0#
WEA0#

SGC8862
SC1U6D3V2KX-GP

SG

1D5V_VGA_S0

SG

H11
K10
K11
H10

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5

SG

[84]
[84]
R8810
[84]
120R2F-GP
[84]
[84]

MAA0_2
MAA0_5
MAA0_4
MAA0_3

VPP/NC#A5
VPP/NC#U5

R8823
2K37R2F-GP

1D5V_VGA_S0

1D5V_VGA_S0

K4
H5
H4
K5
J5

[84] MAA0_[8..0]

2 OF 2

VRAM1B
MAA0_7
MAA0_1
MAA0_0
MAA0_6
MAA0_8

VREFD
VREFD

1D5V_VGA_S0

H5GQ1H24AFR-T2L-GP

H5GQ1H24AFR-T2L-GP
[84] MAA0_[8..0]

VREFC

A10
U10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

J14

VREFD1_A1
VREFD2_A1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREFC_A1

A5
U5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

VREFD
VREFD

VPP/NC#A5
VPP/NC#U5

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREFC

1D5V_VGA_S0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A10
U10

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

J14

VREFD1_A0
VREFD2_A0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

VREFC_A0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1 OF 2

VRAM1A
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

1 OF 2

VRAM2A

1D5V_VGA_S0

1D5V_VGA_S0

R8809
120R2F-GP

1D5V_VGA_S0

SSID = VIDEO

EDCA0_1 [84]
EDCA0_3 [84]

H5GQ1H24AFR-T2L-GP

H5GQ1H24AFR-T2L-GP

Samsung = 72.20325.B0U
Hynix = 72.05224.00U
Hynix RTS = 72.05224.A0U
R8812 1

Use internal Vref memory voltage

R8811 1

SG

SG

2 120R2F-GP VRAM2_ZQ

2 120R2F-GP VRAM1_ZQ

SG

C8801
SC10U6D3V5KX-1GP

SG SG SG SG SG SG SG SG
C88382
SC1U6D3V2KX-GP
C88392
SC1U6D3V2KX-GP
C88402
SC1U6D3V2KX-GP
C88412
SC1U6D3V2KX-GP
C88422
SC1U6D3V2KX-GP
C88432
SC1U6D3V2KX-GP
C88442
SC1U6D3V2KX-GP
C88452
SC1U6D3V2KX-GP

1D5V_VGA_S0

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM1,2 (1/4)

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

88

of

105

SSID = VIDEO
1D5V_VGA_S0

VREFC_A2

J14

VREFD1_A2
VREFD2_A2

A10
U10

VREFC
VREFD
VREFD

VPP/NC#A5
VPP/NC#U5

A5
U5

VREFC_A3

J14

VREFD1_A3
VREFD2_A3

A10
U10

SG

VREFC
VREFD
VREFD

VPP/NC#A5
VPP/NC#U5

C8915
SC1U6D3V2KX-GP

R8955
5K49R2F-GP

SG

SG

SG

C8917
SC1U6D3V2KX-GP

SG
1

R8953
5K49R2F-GP

VREFD2_A2

C8911
SC1U6D3V2KX-GP

SG

SG

SGC8916
SC1U6D3V2KX-GP

SG

VREFD1_A2
2

VREFC_A2

R8949
5K49R2F-GP

R8954
2K37R2F-GP

SGC8914
SC1U6D3V2KX-GP

SG

R8952
2K37R2F-GP

SGC8936
SC1U6D3V2KX-GP

SG

1D5V_VGA_S0

R8946
2K37R2F-GP

1D5V_VGA_S0

1D5V_VGA_S0

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1D5V_VGA_S0

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

1D5V_VGA_S0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

1 OF 2

VRAM4A

1 OF 2

VRAM3A
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

1D5V_VGA_S0

A5
U5

SG

H5GQ1H24AFR-T2L-GP
H5GQ1H24AFR-T2L-GP

D2
D13
P13
P2

[84,88]

J2

MEM_RST
VRAM3_ZQ

J10
J13
J1

[84] WCKA1_1
[84] WCKA1#_1

D4
D5

[84] WCKA1_0
[84] WCKA1#_0

P4
P5

DBI0#
DBI1#
DBI2#
DBI3#
RESET#
SEN
ZQ
MF
WCK1
WCK1#
WCK23
WCK23#

SG

EDC0
EDC1
EDC2
EDC3

D2
D13
P13
P2

[84] DDBIA1_0
1D5V_VGA_S0
[84] DDBIA1_2
1D5V_VGA_S0
[84,88]

J2

MEM_RST
VRAM4_ZQ

MF=1
Mirror

C2
C13
R13
R2

EDCA1_3 [84]

1D5V_VGA_S0

J10
J13
J1

[84] WCKA1_0
[84] WCKA1#_0

D4
D5

[84] WCKA1_1
[84] WCKA1#_1

P4
P5

EDCA1_1 [84]

DBI0#
DBI1#
DBI2#
DBI3#
RESET#
SEN
ZQ
MF
WCK1
WCK1#
WCK23
WCK23#

SG

EDC0
EDC1
EDC2
EDC3

C2
C13
R13
R2

SG

SG

C8975
SC1U6D3V2KX-GP

SGC8978
SC1U6D3V2KX-GP

SG

R8943
2K37R2F-GP

1
VREFD1_A3

R8942
5K49R2F-GP

SG

SG

C8977
SC1U6D3V2KX-GP

VREFD2_A3

R8944
5K49R2F-GP

VREFC_A3

R8940
5K49R2F-GP

SGC8976
SC1U6D3V2KX-GP

DQA1_22
DQA1_20
DQA1_23
DQA1_21
DQA1_18
DQA1_19
DQA1_17
DQA1_16

SG
1

R8941
2K37R2F-GP

1D5V_VGA_S0

SGC8974
SC1U6D3V2KX-GP

SG

R8939
2K37R2F-GP

1D5V_VGA_S0

CK
CK#
CKE#

1D5V_VGA_S0

SG

SG
1

[84] CKEA1

[84]

J12
J11
J3

[84] CLKA1
[84] CLKA1#

DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_13
DQA1_14
DQA1_12
DQA1_15

ABI#
RAS#
CS#
CAS#
WE#

DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_7
DQA1_6
DQA1_5

C8979
SC1U6D3V2KX-GP

[84] CKEA1
[84] DDBIA1_3
1D5V_VGA_S0
[84] DDBIA1_1
1D5V_VGA_S0

CK
CK#
CKE#

J4
G3
G12
L3
L12

ADBIA1
CASA1#
WEA1#
RASA1#
CSA1#_0

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

J12
J11
J3

[84] CLKA1
[84] CLKA1#

[84]
[84]
[84]
[84]
[84]

H11
K10
K11
H10

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

ABI#
RAS#
CS#
CAS#
WE#

MAA1_4
MAA1_3
MAA1_2
MAA1_5

DQA1_[31..0]

2 OF 2

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5

J4
G3
G12
L3
L12

ADBIA1
RASA1#
CSA1#_0
CASA1#
WEA1#

BA0/A2
BA1/A5
BA2/A4
BA3/A3

DQA1_30
DQA1_29
DQA1_27
DQA1_26
DQA1_31
DQA1_28
DQA1_24
DQA1_25

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

K4
H5
H4
K5
J5

H11
K10
K11
H10

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

MAA1_0
MAA1_6
MAA1_7
MAA1_1
MAA1_8

MAA1_2
MAA1_5
MAA1_4
MAA1_3

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5

[84]

[84]
[84]
R8917
[84]
120R2F-GP
[84]
[84]

K4
H5
H4
K5
J5

SG SG

R8918
120R2F-GP

1D5V_VGA_S0

MAA1_7
MAA1_1
MAA1_0
MAA1_6
MAA1_8

DQA1_[31..0]

2 OF 2

VRAM3B

[84] MAA1_[8..0]

VRAM4B

[84] MAA1_[8..0]

EDCA1_0 [84]
EDCA1_2 [84]

H5GQ1H24AFR-T2L-GP

H5GQ1H24AFR-T2L-GP

Samsung = 72.20325.00U
Hynix = 72.05224.00U

R8914 1

Use internal Vref memory voltage

SG

2 120R2F-GP VRAM4_ZQ

SG

C8804
SC10U6D3V5KX-1GP

SG SG SG SG SG SG SG SG
C89852
SC1U6D3V2KX-GP
C89972
SC1U6D3V2KX-GP
C89802
SC1U6D3V2KX-GP
C89072
SC1U6D3V2KX-GP
C89902
SC1U6D3V2KX-GP
C89122
SC1U6D3V2KX-GP
C89012
SC1U6D3V2KX-GP
C88832
SC1U6D3V2KX-GP

1D5V_VGA_S0

2 120R2F-GP VRAM3_ZQ

SG

R8915 1

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM3,4 (2/4)
5

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

89

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

90

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved
5

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

91

of

105

SSID = PWR.Plane.Regulator_vga_core

3D3V_AUX_S5

5V_S5

DY PR9218
100KR2J-1-GP
1

PWR_VGA_CORE_EN_R#

VGA_CORE

PQ9206
DMN66D0LDW-7-GP

DY
2

X01 11/28

SG

SG

SG

PC9204
SC22U6D3V5MX-2GP
2
1

PC9203
SC22U6D3V5MX-2GP
2
1

5V_S5

PR9220
100R2J-2-GP

DY
1

SG

PC9202
SCD1U10V2KX-5GP

PC9201
SCD01U16V2KX-3GP
2

8209A_EN/DEM_VGA

DY

EC9203
SCD1U10V2KX-5GP

X03 2/16

PQ9206_3

PR9201
SG10R2J-2-GP

PWR_VGA_AVDD
PU9201

AGND_VGA
B3

SG

VT358FCX-ADJ-007-GP

X02 2/10

74.00358.A3Z

DGPU_PWROK

X03 2/16

[22,27,86,93]

PR9215
0R0402-PAD-2-GP
PG9201

PWRCNTL_0#

SG

DY

PG9203
PWR_VGA_VSENSE-

PWRCNTL_0_R

5V_S5

X03 2/16

4
2

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

SG
1

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

PU9208A
1

2
3

SG
7

3D3V_VGA_S0

TSLVC02APW-GP

PU9202_1
14
9

TSLVC02APW-GP

PQ9202_11

SG
PWRCNTL_0_R

PC9221
SCD01U50V2KX-1GP

VCC

SG

GND

PC9217

PR9217
3D3R5J-GP

SG

PR9216
3D3R5J-GP

PQ9203_D

PU9206_Y

74LVC1G32GW-1GP

SG

PQ9203
AO3404A-GP

84.03404.B31
2nd = 84.03404.C31

PU9208D

11
12

73.01G32.AHH
14

SG

52K3R2F-L-GP

SG

PC9223
SCD047U10V2KX-2GP

SG

10K7R2F-GP

10

PR9212
5K1R2F-2-GP

PU9206
1

SG
7

PU9208C

SG

SG SG

7
14

TSLVC02APW-GP

8
PWRCNTL_1_1

SG

SG

PC9220
SCD01U50V2KX-1GP

PR9222

DY

PQ9202_4

13

PQ9202_13

TSLVC02APW-GP

SG

PWRCNTL_0_D

PR9210

PWRCNTL_0_0

PQ9202_10

PR9211
100KR2J-1-GP

SG

PU9202_6

VGA_CORE

DY

83.R5003.G8H
2nd = 83.R5003.H8H

SG

SG

52K3R2F-L-GP

PC9222
SCD047U10V2KX-2GP

DY

PD9203
B0530WS-7-F-GP
K
A

SG

PWRCNTL_0_0
PWRCNTL_1_R

2
2

DY

10K7R2F-GP

PR9202
100KR2J-1-GP

PR9219

PR9207
5K1R2F-2-GP

PR9208

PWRCNTL_1_1

PU9208B

DY

5V_S5

PWRCNTL_1_D

DYA

VGA output

X03 2/16

PD9202
K

B0530WS-7-F-GP

Layout Note: Close

DY

SG

2N7002KDW-GP

PWRCNTL_0#

VGA_CORE

SCD1U10V2KX-5GP
1
2

PWRCNTL_1_R

PWRCNTL_1_1

PWRCNTL_1#

PWRCNTL_0 [85]

GAP-CLOSE-PWR-3-GP
6

2N7002KDW-GP

DY

PR9206
36K5R2F-GP

PC9215
SCD1U10V2KX-5GP

SG

14

SG SG

PWRCNTL_1#

PR9213
10KR2F-2-GP

SG

GAP-CLOSE-PWR-3-GP

PQ9204

[85] PWRCNTL_1

330KR2J-L1-GP
PR92231
2

DY

SC2200P50V2KX-2GP
PC9214

PR9224
360KR2F-GP

PQ9205
PWRCNTL_0_0

3D3V_VGA_S0

SG

SG

PG9202
PWR_VGA_VSENSE+
PWR_VGA_VDES

AGND_VGA

DY

SG

GAP-CLOSE-PWR-3-GP

PR9209
10KR2F-2-GP

SG

SG

SG

SG

X03 2/16

1
PC9219
SC100P50V2JN-3GP

DY

EC9202
SCD1U10V2KX-5GP

DY

SG

EC9201
SCD1U10V2KX-5GP

PWR_VGA_CORE_PGOOD

SG

PC9213
SC6800P25V2KX-1GP
2

SG

68.R2010.20A
2nd = 68.R2010.10P

PC9212
SCD1U10V2KX-5GP

COIL-D2UH-1-GP

PC9218
SC22U6D3V5MX-2GP
2
1

D1
D2
D3
D4
D5
F1
F2
F3
F4
F5

VX#D1
VX#D2
VX#D3
VX#D4
VX#D5
VX#F1
VX#F2
VX#F3
VX#F4
VX#F5

PC9211
SC22U6D3V5MX-2GP
2
1

SG

AGND_VGA

GND
GND
GND
GND
GND
GND
GND
GND
GND

PWR_VGA_VX

PC9210
SC22U6D3V5MX-2GP
2

C1
C2
C3
E1
E2
E3
G1
G2
G3

AGND

B1

PC9209
SC22U6D3V5MX-2GP
2

PC9216
SCD1U10V2KX-4GP

X01 11/28

VGA_CORE

PL9201

PC9261
SC22U6D3V5MX-2GP
2
1

AVDD

PWR_VGA_IRIPL

SG

DY

1
PR9205
36KR2F-GP

[86,93]

PC9208
SC22U6D3V5MX-2GP
2

8209A_EN/DEM_VGA

PC9205
SGSCD22U10V3KX-2GP

C4
C5
E5
G4
E4
G5

DY1

VDD
VDD
VDD
VDD
VDD
VDD

PC9207
SC22U6D3V5MX-2GP
2

CH551H-30PT-GP

BIAS
R_SEL/ILOAD
VDES
VSENSE+
OE
STAT
TEMP
IRIPL

PC9260
SC22U6D3V5MX-2GP
2
1

PD9201
[93] DGPU_PWR_EN

A1
A2
A3
A4
A5
B5
B4
B2

PC9262
SC22U6D3V5MX-2GP
2
1

8209A_EN/DEM_VGA
PWR_VGA_CORE_PGOOD

PC9259
SC22U6D3V5MX-2GP
2
1

PWR_VGA_BIAS
PWR_VGA_R_SEL/ILOAD

44K2R2D-GP
6K49R2F-1-GP

PC9264
SC22U6D3V5MX-2GP
2
1

SG22
SG

1
1

2
SG 10KR2J-3-GP

PC9206
SC22U6D3V5MX-2GP
2

PR9203
PR9204
1
PR9221

3D3V_VGA_S0

73.07402.EHB

VID0
GPIO15

Voltage

1V

0.9V

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VT357_+VGA_CORE

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

92

of

105

1D8V_S0 to 1D8V_VGA_S0 Transfer

AO4468, SO-8
Id=11.6A, Qg=9~12nC
Rdson=17.4~22m ohm

2 PR9301
0R2J-2-GP
3D3V_VGA_S0

[92] DGPU_PWR_EN
PR9305
1

3D3V_S0

SG

DGPU_PWR_EN

DGPU_PWR_EN

PC9330
SC10U6D3V3MX-GP

SG

SG

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

SG

20KR2F-L-GP

15V_S5

PC9329
SCD01U50V2KX-1GP

S G D

SG

PR9335
100KR2J-1-GP

1D8V_ENABLE

PD9303
CH551H-30PT-GP

83.R5003.C8F
2nd = 83.R5003.H8H

[92]

10KR2F-2-GP

X03 2/21
X01 11/28

SG

PR9333
2

1
2

SG

SCD1U10V2KX-5GP

DY

1D8V_ENABLE_RC

D G S

PQ9306
2N7002KDW-GP

PC9323

SC10U6D3V3MX-GP

1D8V_VGA_EN#

1D8V_VGA_EN

PR9320
0R0402-PAD-2-GP

PQ9303
2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

SG PC9331

5930_PGOOD_1V

SG

PR9334
100KR2J-1-GP

X03 2/13

1
2
3
4

[22]

S
S
G

AO4468-GP

DGPU_PWR_EN#

10KR2J-3-GP

SGS

84.04468.037
2nd = 84.04178.037
3rd = 84.02659.037

3D3V_AUX_S5
1

SG

PU9306
8 D
7 D
6 D
5 D

84.02130.031
2ND = 84.03413.A31

PC9324
SCD1U10V2KX-5GP
PR9319
PR9319_2
1
2

SG

PR9319_1

PQ9302
DMP2130L-7-GP

DY SG
2

SG

PR9316

SG 10KR2J-3-GP

1D8V_VGA_S0

3D3V_S0

1D8V_S0

X03 2/16
EC9302
SCD1U10V2KX-5GP

DY

3D3V_S0 to 3D3V_VGA_S0 Transfer

1

SSID = PWR.Plane.Regulator_3p3v_vga, 1p8v_vga, 1p5v_vga, 1v_vga

X01 11/28

PQ9304
[36,37]

PS_S3CNTRL

PS_S3CNTRL

G
D
S

Discharge Circuit

SG

X01 12/15

3D3V_VGA_S0

2N7002K-2-GP

1D8V_VGA_S0

SG

PR9314
470R2J-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

DGPU_PWR_EN#
L

IGPU

PR9337
470R2J-2-GP

SG
2

dGPU mode

IGPU with BACO

PQ9311
1

3.3V_RUN_VGA_1

PR9319_1

1D8V_VGA_EN#

DIS_1D8V_VGA_S0

SG

2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

APL5930 for 1V_VGA_S0

1D5V_S3

1D5V_S3

1
2
3
4

X01 11/28
PG9302
2

SG

[22,27,86,92]

SG

DGPU_PWROK

SG

X01 11/28

SC22U6D3V5MX-2GP

GAP-CLOSE-PWR-3-GP
SC22U6D3V5MX-2GP

1
2

2
1

4K99R2F-L-GP

PR9315

PC9316

Vout=0.8V*(R1+R2)/R2

Discharge Circuit

PR9327
20KR2J-L2-GP

1D5V_VGA_S0

X01 11/28

Discharge Circuit

PR9302

DIS_1D5V_VGA_S02

3D3V_AUX_S5

PR9336
470R2J-2-GP

SG

2 PWR_1V_EN#
A

100KR2J-1-GP

PQ9301
2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

PQ9307
G

1D5V_VGA_EN#

SG

<Core Design>

SG

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PR9303
PWR_1V_EN

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
4

SG

PC9318

DY

83.R5003.C8F
2nd = 83.R5003.H8H

PC9328
SCD47U25V3KX-1GP

SG

X01 11/28

83.R5003.C8F
2nd = 83.R5003.H8H

PR9311
0R0402-PAD-2-GP
PWR_1V_EN

PD9302
CH551H-30PT-GP

1D5V_ENABLE
1

1D5V_VGA_EN

SG

SG

[92] DGPU_PWR_EN

DY

8209A_EN/DEM_VGA

PR9331
100KR2J-1-GP

SG

DY

DY

PR9315_2

PC9317

PC9312

S G D

[86,92]

SG

PR9326
1
2
0R2J-2-GP

DGPU_PWROK

2 PWR_1V_PGOOD
100KR2J-1-GP

GAP-CLOSE-PWR-3-GP
PG9304
1
2

SG

SCD1U10V2KX-5GP

[92] DGPU_PWR_EN

[22,27,86,92]

74.05930.03D

SG

PR9312
100KR2J-1-GP

SG

PD9301
CH551H-30PT-GP
2

SG

APL5930KAI-TRG-GP

1V_VGA_S0

X03 2/16
PG9303

5
4
3
2
1

X02 2/13
5930_PGOOD_1V

X01 11/28

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

1
PR9304

3D3V_VGA_S0

SG

VCNTL
POK
EN
VIN#9

VIN#5
VOUT#4
VOUT#3
FB
GND

SCD01U16V2KX-3GP

D G S

DY

PC9326
SCD1U25V2KX-GP

PC9313

X03 2/16

X01 11/28

6
7
8
9

5V_S5

1K27R2F-L-GP

SG

10KR2J-3-GP

15V_S5

1V_PWR

PU9303

GAP-CLOSE-PWR-3-GP
PC9319
SC10U6D3V5KX-1GP

PR9322
1

1
PR9332

PQ9305
2N7002KDW-GP

1V_VGA
Design current =2.2A

GAP-CLOSE-PWR-3-GP

SC1U6D3V2KX-GP

SG
2 1D5V_VGA_EN#
SG 100KR2J-1-GP

SG SC10U6D3V3MX-GP

EC9301
SCD1U10V2KX-5GP

1
3D3V_AUX_S5

SG

X01 11/28

PR9330
1

PG9301
PC9332

AO4468-GP

84.04468.037
2nd = 84.04178.037
3rd = 84.02659.037

SC10U6D3V3MX-GP

SG

1V_VGA_S0_LDOIN

X03 2/16
1

S
G

PC9327

SG SS

1D5V_ENABLE_RC

AO4468, SO-8
Id=11.6A, Qg=9~12nC
Rdson=17.4~22m ohm

1D5V_VGA_S0
PU9305
8 D
7 D
6 D
5 D

1D5V_S3 to 1D5V_VGA_S0 Transfer

PQ9311_3 2

SG

Title

DISCRETE VGA POWER

1V_VGA_S0

470R2J-2-GP

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet

93

of

105

(Blanking)

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

94

of

105

(Blanking)

DMB40
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

A00

BMW Z4 DIS
Sheet
1

95

of

105

(Blanking)

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A3

Document Number

Date:

Friday, March 30, 2012

Reserved

Rev

A00

BMW Z4 DIS
Sheet
1

96

of

105

DY

DY

5V_S5
5V_S5

2
2

1D5V_S3

3D3V_S5

SG

1D5V_S3

VGA_CORE

EC9781
SCD1U10V2KX-5GP

EC9777
SCD1U10V2KX-5GP

1D5V_S3

2
EC9784
SCD1U10V2KX-5GP

EC9706
SCD1U25V2KX-GP

VGA_CORE

34.4UV01.001
2nd = 34.4UV01.101

Size
A2
Document Number

Date:
Friday, March 30, 2012
1

1D5V_S3

2
EC9783
SCD1U10V2KX-5GP

1D5V_S3

EC9785
SCD1U10V2KX-5GP

1D5V_S3

EC9788
SCD1U10V2KX-5GP

2
EC9782
SCD1U10V2KX-5GP

1D5V_S3

EC9787
SCD1U10V2KX-5GP

1
EC9704
SCD1U25V2KX-GP

HS5
STF237R148H67-GP
1

5V_S5
1

1D5V_S3

5V_S5

EC9786
SCD1U10V2KX-5GP

1D5V_S3

3D3V_AUX_S5

3D3V_AUX_S5

EC9724
SCD1U10V2KX-5GP

EC9731
SCD1U10V2KX-5GP

2
EC9718
SCD1U10V2KX-5GP

3D3V_S0

EC9719
SCD1U10V2KX-5GP

2
EC9716
SCD1U10V2KX-5GP

EC9725
SCD1U10V2KX-5GP

+DC_IN

EC9730
SCD1U10V2KX-5GP

5V_S5

EC9722
SCD1U10V2KX-5GP

3D3V_S5

EC9728
SCD1U10V2KX-5GP

5V_S5

3D3V_S5

SCD1U10V2KX-5GP

EC9733

DCBATOUT

3D3V_S0

3D3V_S0

SG2
2

2
EC9714
SCD1U10V2KX-5GP

+DC_IN

EC9776
SCD1U10V2KX-5GP

1
EC9707
SCD1U25V2KX-GP

5V_S5

3D3V_WWAN_AOAC

X03 2/16

DY
EC9732
SCD1U10V2KX-5GP

2
EC9740
SCD1U10V2KX-5GP

1D05V_PCH

EC9775
SCD1U10V2KX-5GP

2
EC9726
SCD1U10V2KX-5GP

2
EC9734
SCD1U10V2KX-5GP

EMI

EC9774
SCD1U10V2KX-5GP

EC9715
SCD1U10V2KX-5GP

A00 3/29

EC9773
SCD1U10V2KX-5GP

EC9701
SCD1U25V2KX-GP

DY

EC9768
SCD1U10V2KX-5GP

5V_S5

2
EC9790
SCD1U10V2KX-5GP

DY

3D3V_S0

EC9723
SCD1U10V2KX-5GP

DY

3D3V_S5

3D3V_S0

EC9767
SCD1U10V2KX-5GP

5V_S5

EC9720
SCD1U10V2KX-5GP

2
EC9742
SCD1U10V2KX-5GP

3D3V_S0

EC9766
SCD1U10V2KX-5GP

DY

DY

3D3V_S5

EC9727
SCD1U10V2KX-5GP

DY

5V_S5

3D3V_S5

EC9721
SCD1U10V2KX-5GP

5V_S5

DY

5V_S5

3D3V_S5

EC9765
SCD1U10V2KX-5GP

DY
1

5V_S5

5V_S5

EC9717
SCD1U10V2KX-5GP

DCBATOUT

DY

5V_S5
5V_S0

DY

DY

5V_S5

EC9764
SCD1U10V2KX-5GP

3D3V_S0
2

5V_S5

EC9710
SCD1U10V2KX-5GP

5V_S5

2
EC9789
SCD1U10V2KX-5GP

5V_S5

DCBATOUT

EC9736
SCD1U10V2KX-5GP

5V_S5
EC9735
SCD1U10V2KX-5GP

3D3V_S0

EC9737
SCD1U10V2KX-5GP

DY

EC9745
SCD1U10V2KX-5GP

DCBATOUT

5V_S5

EC9702
SCD1U25V2KX-GP

DCBATOUT

5V_S5
2

EC9756
SCD1U10V2KX-5GP

DCBATOUT

A00 3/27

EC9744
SCD1U10V2KX-5GP

5V_S5
1

DY

DCBATOUT
EC9703
SCD1U25V2KX-GP

DCBATOUT

X03 2/13

EC9743
SCD1U10V2KX-5GP

5V_S0

EC9708
SCD1U25V2KX-GP

EMI

EC9709
SCD1U25V2KX-GP

EC9757
SCD1U10V2KX-5GP

3D3V_S0

DVDDL
2

EC9754
SCD1U10V2KX-5GP

X01 12/09 For EMI

DY

3D3V_S0

X03 2/16

EC9741
SCD1U10V2KX-5GP

DY

EC9758
SCD1U10V2KX-5GP

DY

3D3V_S0

EC9746
SCD1U10V2KX-5GP

5V_S5

EC9739
SCD1U10V2KX-5GP

AVDDL

DY

EC9759
SCD1U10V2KX-5GP

RF

EC9738
SCD1U10V2KX-5GP

DCBATOUT
EC9755
SCD1U10V2KX-5GP

2
EC9747
SCD1U25V2KX-GP

RF

DY

DY

EC9772
SCD1U10V2KX-5GP

5V_S5

EC9760
SCD1U10V2KX-5GP

DY

EC9761
SCD1U10V2KX-5GP

3D3V_S5

3D3V_S5

DY

EC9762
SCD1U10V2KX-5GP

2
EC9752
SCD1U10V2KX-5GP

DCBATOUT

3D3V_S5

DY

5V_S0

EC9771
SCD1U10V2KX-5GP

2
EC9753
SCD1U10V2KX-5GP

2
EC9748
SCD1U25V2KX-GP

3D3V_S5

EC9763
SCD1U10V2KX-5GP

DY

2
EC9749
SCD1U25V2KX-GP

DY

DY

EC9770
SCD1U10V2KX-5GP

1D5V_S3

2
EC9750
SCD1U25V2KX-GP

DCBATOUT

EC9769
SCD1U10V2KX-5GP

2
EC9751
SCD1U25V2KX-GP

EC9705
SC4D7P50V2BN-GP

SSID = User.Interface

X03 2/21

SSID = Mechanical

On the TOP side

HS1
STF237R128H42-3-GP
H1
HT85BE95R29-U-5-GP

34.4UV01.001
2nd = 34.4UV01.101

HS2
STF237R128H42-3-GP
H2
HT85BE95R29-U-5-GP
D

34.4UV01.001
2nd = 34.4UV01.101

HS3
STF237R128H42-3-GP

34.4UV01.001
2nd = 34.4UV01.101

H3
HOLE256R115-GP

HS4
STF237R128H42-3-GP
H4
HOLE335R115-GP

H5
HT85BE95R29-U-5-GP

MSATA_WWAN

HS6
STF237R148H67-GP

Sheet
97

H6
HOLE256R115-GP

5V_S5

H7
HOLE256R115-GP

X01 12/15 For RF

X01 12/30

1D8V_S0
5V_S5

X01 12/23

X03 1/30
B

A
A

<Core Design>

Wistron Corporation

Title
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

UNUSED PARTS/EMI Capacitors

BMW Z4 DIS
of
Rev
105

A00

Huron River Platform Power Sequence

(AC mode)

(DC mode)

red word: KBC GPIO

+RTC_VCC

+RTC_VCC

t01 >9ms

DCBATOUT

DCBATOUT
Within logic high level and disable if
it is less than the logic low level.

3D3V_AUX_S5

3D3V_AUX_S5

KBC GPIO34 control power on by 3V_5V_EN

S5_ENABLE

Ta
V5REF_Sus must be powered up before
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.

t01 >9ms

RTC_RST#

RTC_RST#

red word: KBC GPIO

Sense the power button status

KBC_PWRBTN#

Press Power button

Platform to KBC PSL_IN2

5V_S5

EC_ENABLE#_1(GPIO31) keep low

Ta

3D3V_S5

3D3V_AUX_KBC

KBC GPIO34 control power on by 3V_5V_EN

+5VA_PCH_VCC5REFSUS

S5_ENABLE

KBC GPIO43 to PCH

PM_RSMRST#(EC Delay 40ms)

t05 >10ms

5V_S5

PCH to KBC GPIO00

PCH_SUSCLK_KBC

V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.

t07>5ms

KBC GPO84 to PCH

Not floating.

AC_PRESENT

Sense the power button status

AC KBC_PWRBTN#

0ms<t08a<90ms

+5V_ALW & +3.3V_ALW need meet 0.7V difference

+5VA_PCH_VCC5REFSUS

Ta

KBC GPIO20 to PCH

Press Power button

3D3V_AUX_KBC

+5V_ALW & +3.3V_ALW need meet 0.7V difference

3D3V_S5

PM_PWRBTN#

Platform to KBC PSL_IN2

This signal has an internal
pull-up resistor and has an
internal 16 ms de-bounce on the
input.

KBC GPIO43 to PCH

PM_RSMRST#

KBC GPIO20 to PCH

t05 >10ms

PCH to KBC GPIO00

AC PM_PWRBTN#

PCH_SUSCLK_KBC

AC PM_PWRBTN#

t07>5ms

DC PCH_RSMRST#
PCH to KBC GPIO44

PM_SLP_S4#

t10

t10

PCH to KBC GPIO01

>30us

PM_SLP_S3#

PCH to KBC GPIO44

PM_SLP_S4#

KBC GPIO23 to LAN

PM_LAN_ENABLE

PCH to KBC GPIO01

>30us

PM_SLP_S3#

KBC GPIO23 to LAN

PM_LAN_ENABLE

Enable by PM_SLP_S4#

Enable by PM_SLP_S4#

1D5V_S3
C

1D5V_S3

DDR_VREF_S3(0.75V)
Tb
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.

DDR_VREF_S3(0.75V)

+5V_RUN & +3.3V_RUN need meet 0.7V difference

5V_S0

+5V_RUN & +3.3V_RUN need meet 0.7V difference

5V_S0
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.

3D3V_S0
+5VS_PCH_VCC5REF

Tb

1D5V_S0

3D3V_S0
+5VS_PCH_VCC5REF

Tb

1D5V_S0

1D8V_S0

1D8V_S0

0D75V_S0

0D75V_S0

1D8V_S0 & 1D5V_S3 power ready

1D8V_S0 & 1D5V_S3 power ready

RUNPWROK

RUNPWROK

1D05V_PCH/VCCP_CPU

1D05V_PCH/VCCP_CPU

TPS51218 PGOOD

TPS51218 PGOOD

1D05VTT_PWRGD

1D05VTT_PWRGD

0D85V_S0

0D85V_S0
VCCSA_S0

VCCSA_S0

TPS51461RGER PGOOD

TPS51461RGER PGOOD

VCCSA_PWRGD

VCCSA_PWRGD
SetVID

CPU SVID BUS

ACK

50us< t36 <2000us

VCC_CORE

ACK

50us< t36 <2000us

VCC_CORE

VCC_GFXCORE

VCC_GFXCORE

t37
<5ms

IMVP_PWRGD

t37

ISL95831 PGOOD to system

<5ms

IMVP_PWRGD

CLK_EXP_P

ISL95831 PGOOD to system

CLK_EXP_P

This signal represents the Power

Good for all the non-CORE and
non-graphics power rails.

SetVID

CPU SVID BUS

ALL_SYS_PWRGD=VCCSA_PWRGD
t14 >99ms
PWROK
VCCSA_PWRGD
2ms<

KBC GPIO77 to PCH

t18 >0us

t17 <650ms

This signal represents the Power

Good for all the non-CORE and
non-graphics power rails.

VCCSA_PWRGD
2ms<

PCH to CPU

VDDPWRGOOD

ALL_SYS_PWRGD=VCCSA_PWRGD
t14 >99ms
PWROK

KBC GPIO77 to PCH

t18 >0us

t17 <650ms

PCH to CPU

VDDPWRGOOD

t19 >1ms
t20 >2ms
5ms< t13 <650ms

1D8V_S0

1D8V_S0

PCH to CPU

H_CPUPWRGD

H_CPUPWRGD

SYS_PWROK

SYS_PWROK

1ms<

t25 <100ms

PLT_RST#

t21+t22 >1ms+60us
PCH to all system

t19 >1ms
t20 >2ms
5ms< t13 <650ms

PCH to CPU

1ms<
PLT_RST#

t39 <200us

DMI

t25 <100ms

t21+t22 >1ms+60us
PCH to all system
t39 <200us

DMI

Thames PRO Power-Up/Down Sequence

3D3V_S0
DGPU_PWR_EN#(Discrete only)

PCH GPIO48 output

3D3V_VGA_S0(Discrete only)

3D3V_VGA_S0 above VT358 VIH

8209A_EN/DEM_VGA(Discrete only)
A

VGA_CORE(Discrete only)

Ta >0ms

1V_VGA_S0(Discrete only)

APL5930 PGOOD
5930_PGOOD_1V(Discrete only)

Tb >0ms

1D5V_VGA_S0(Discrete only)
Tc >0ms

VT358 PGOOD
DGPU_PWROK(Discrete only)
1D8V_VGA_S0(Discrete only)

DMB40

Wistron Corporation

Td <20ms

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

For power-down, reversing the ramp-up sequence is recommended.

Power Sequence
4

Size
A1

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS
1

A00
Sheet

98

of

105

Wistron CHIEF RIVER POWER UP SEQUENCE DIAGRAM

-6
AC
Adapter in

AD+

-3a

Page38

-3a

PWR_5V3D3V_ENC

-3a

3V_5V_EN

5V_S5

S5_ENABLE

3a

VDD

-3b

VOUT

-3c

15V_S5

PM_SLP_S4#

1D5V_S3

PWR_CHG_ACOK

SWITCH

ENC
LL1

Page40

LL2

5V_S5

PUMP

VT385

EN

RUNPWROK

3D3V_S5

PGD

Page46

SWITCH
Page40

VREG5

TPS51125RGER
DC/DC
(3V/5V)

-5

VREG3

5V_AUX_S5
3D3V_AUX_S5

-4
3

3V_5V_POK

DCBATOUT

VIN

PM_SLP_S4#

5V_S5

PGOOD

1D5V_S3

Page41

DC
Battery

BQ24727
Charger

BT+

5V_S0

PM_SLP_S3#

VDDP

3b

VIN

SWITCH

-3

Page39

Page36

3D3V_AUX_KBC

-3a

PM_SLP_S4#

3D3V_S0

Page40 ACOK

EN

SWITCH

S5_ENABLE

-6a

Page36

GPIO34

AC_IN#

GPIO70

RT9026

1D5V_S0
SWITCH

-1

Page36

DDR_VREF_S3

VTTREF

SLP_S4#

KBC
NPCE885

KBC_PWRBTN#

GPIO6

-2
9

PM_RSMRST#

GPIO43
GPIO44

0D75V_EN

GPIO20

GPIO01

PWRBTN#

SM_DRAMPWROK

DRAMPWRGD
H_CPUPWRGD

H_CPUPWRGD_R

PROCPWRGD

UNCOREPWRGOOD

Panther Point
PCH

Page27

S0_PWR_GOOD
Sequence:
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

Page46

VDDPWRGOOD
Y

PM_DRAM_PWRGD

2
GPIO77

4a

AND GATE
A

RSMRST#
PM_PWRBTN#

PM_SLP_S3#

PM_SLP_S3#
VTT_EN

Power Button

PM_SLP_S4#

0D75V_S0

VTT

SLP_S3#

10

5V_S5

Ivy Bridge
CPU

15

3D3V_S5

VDD

VIN
VOUT

1D8V_S0

APWROK
PM_SLP_S3#
PWROK

PLT_RST#

EN

BUF_CPU_RST#

PLTRST#

RT8068A

RSTIN#

RUNPWROK
SVID

SYS_PWROK

PGD

SYS_PWROK

Page47
SVID

14

5
11

5V_S5

V5IN

5V_S5

DCBATOUT

VIN
VOUT

1D05_PCH/VCCP_CPU

5a

11

VIN

OUTPUT
SVID

EN

1D05V_VTT_PWRGD
Page45

VCC_CORE

SVID

VT386

RUNPWROK

OUTPUT

12

VCC_GFXCORE

PGOOD

5b

D85V_PWRGD

7
IMVP_VR_ON

VT1318/VT1323/
VT1326
VR_ON

13
IMVP_PWRGD

14
SYS_PWROK

Page42 & 43 & 44 PGOOD

5V_S5 VCCP_CPU

-4
-7

VCNTL

VIN
VOUT

5b
A

0D85_S0

3D3V_AUX_S5

RTC_AUX_S5

5c

-8
+RTC_VCC

APL5916

1D05VTT_PWRGD
EN

D85V_PWRGD
Page48

PGOOD
RTC battery

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Power Up Sequence: -8 ~ 15
5

Title

Power Sequence Diagram

Size
A2

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS
Sheet
1

A00
99

of

105

AD+

Adapter

SI7121DN

DCBATOUT

3D3V_S5

TPS51225RUKR

SI7121DN
D

Charger

AO4468

AO3404A

AO3404A

RT8068AZQWID

PA102FMG

1D8V_S0

3D3V_LAN_S5

BQ24727
Battery

BT+
3D3V_S0

3D3V_WLAN_AOAC

15V_S5

3D3V_AUX_S5
(3D3V_PWR_2)

5V_PWR_2

G5285T11U

LCDVDD

DMP2130L

3D3V_WWAN_AOAC

RTS5179

3D3V_CARD_S0

DMP2130L

AO4468

3D3V_VGA_S0

1D8V_VGA_S0

For Discrete

AR8162L

DVDDL

For Discrete

3D3V_AUX_KBC

5V_S5

TPS2541RTER+
UP7534QRA8

USB30_VCCx

VT1318MFQ +
VT1326SFCX +
VT1323SFCX

VCC_CORE

VCC_GFXCORE

AO4468

VT358FCX

5V_S0

VGA_CORE

VT385FCX

VT386FCX

1D5V_S3

1D05V_PCH/VCCP_CPU

For Discrete
B

APL5916

0D85V_S0

RT9026PFP

0D75V_S0

TPCA8062

DDR_VREF_S3

1D5V_S0

AO4468

APL5930KAI

1V_VGA_S0

1D5V_VGA_S0

For Discrete

Power Shape

DMB40

Wistron Corporation
Regulator

LDO

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Switch
Title

Power Block Diagram

Size
A3

Document Number

Date:

Friday, March 30, 2012

BMW Z4 DIS

Rev

A00
Sheet
1

100

of

105

3D3V_S5

3D3V_S0

KBC SMBus Block Diagram

PCH SMBus Block Diagram

TP_VDD

3D3V_S0
SRN2K2J-1-GP

SRN2K2J-1-GP

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

DIMM 1

PCH_SMBCLK
PCH_SMBDATA

3D3V_S5

SRN10KJ-5-GP

SCL
SDA

SMBus Address:A0h

GPIO37/PSCLK1

TPCLK

GPIO35/PSDAT1

TPDATA

TouchPad Conn.

0R2J-2-GP
0R2J-2-GP

TPCLK_C

TPCLK

TPDATA_C

TPDATA

2N7002KDW

3D3V_AUX_KBC

DIMM 2
PCH_SMBCLK
PCH_SMBDATA

SRN2K2J-1-GP

SML0CLK

SML0_CLK

SML0DATA

SML0_DATA

SCL

SDA
SRN4K7J-8-GP

SMBus Address:A4h
3D3V_S5

PCH_SMBCLK
PCH_SMBDATA

Minicard
WLAN

GPIO17/SCL1/N2TCK

BAT_SCL

GPIO22/SDA1/N2TMS

BAT_SDA

SMB_CLK

33R2J-2-GP

33R2J-2-GP

Battery Conn.
PBAT_SMBCLK1
PBAT_SMBDAT1

SMBus address:16h

SMB_DATA

BQ24727

SRN2K2J-1-GP

SML1_DATA

GPIO73/SCL2

To KBC
GPIO74/SDA2

3D3V_VGA_S0

PCH_SMBCLK
PCH_SMBDATA

SRN4K7J-8-GP

SMB_CLK

SMB_DATA

SCL

KBC
NPCE885PA0DX

SDA

3D3V_S5

3D3V_S0

SMBus address:12h
SRN2K2J-1-GP

Minicard
W-WAN

PCH_SMBCLK

TouchPad
Conn.

SMB_CLK

PCH_SMBDATA SMB_DATA

GPIO_VGA_04_CLK

GPIO_4_SMBCLK

GPIO_VGA_03_DATA

To GPU

GPIO73/SCL2

SML1_CLK

GPIO74/SDA2

SML1_DATA

SML1_CLK

SML1DATA/GPIO75

SRN2K2J-1-GP

SML1CLK/GPIO58

THM_SML1_CLK

Thermal IC
NCT7718W
SCL

THM_SML1_DATA SDA

GPIO_3_SMBDATA

SMBus address:99h/98h(R/W)

2N7002KDW

SMBus Address:41h
2N7002KDW

PCH

PCH

SML1_CLK
SML1CLK/GPIO58
SML1_DATA SML1DATA/GPIO75

5V_S0

3D3V_S0

3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP

SDVO_CTRLCLK

PCH_HDMI_CLK

SDVO_CTRLDATA

PCH_HDMI_DATA

DDC_CLK_HDMI
DDC_DATA_HDMI

HDMI CONN

2N7002DW-1-GP

3D3V_S0

SRN2K2J-1-GP
SRN0J-6-GP

L_DDC_CLK

LVDS_DDC_CLK_R

LVDS_DDC_CLK_R_1

L_DDC_DATA

LVDS_DDC_DATA_R

LVDS_DDC_DATA_R_1

LCD CONN

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

SMBUS Block Diagram

Size
A2

Document Number

Date:

Friday, March 30, 2012

BMW Z4 DIS

Rev

A00
Sheet

101

of

105

Thermal Block Diagram

Audio Block Diagram

3D3V_S0
SRN2K2J-1-GP

SML1_CLK
SML1_DATA

PAGE28

SRN2K2J-1-GP

CPU/SYSTEM
Thermal
NCT7718W

D+

D-

THM_SML1_CLK

SCL

PAGE29
NCT7718_DXP
PMBS3904-1-GP
SC2200P50V2KX-2GP

SC470P50V3JN-2GP

NCT7718_DXN

PORTA_L

3D3V_S0

MIC_IN_L_R

3D3V_S5

MIC_JACK_R

PORTA_R

THM_SML1_DATA SDA

VREFOUT_A

HP/MIC
Combo

2K2R3F

AUD_VREFOUT_A

2K2R2F-3-GP
2N7002KDW

T_CRIT#

THERM_SYS_SHDN#

2N7002K D
S
G

GPIO73/SCL2

PURE_HW_SHUTDOWN#

AUD_HP1_JACK_L

PORTB_R

AUD_HP1_JACK_R

3V_5V_EN

3D3V_S0

GPIO74/SDA2

Codec
IDT
92HD94

PAGE27

PORTB_L

Digital
MIC

DMIC_CLK/GPIO1 AUD_DMIC_CLK_R
DMIC_0/GPIO2

KBC
NPCE885P

AUD_DMIC_IN0_R

GPIO4/AD5

GPIO56/TA1

FAN1_DAC

FAN_TACH1

GPIO94/DA0

PORTD_+L

AUD_SPK_L+

PORTD_-L

AUD_SPK_L-

PORTD_+R

AUD_SPK_R+

PORTD_-R

AUD_SPK_R-

SPEAKER

TACH

FAN
5V_S0

FAN_VCC

VIN

VIN

VSET

VOUT

FAN CONTROL

G991P11U
PAGE28

DMB40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Audio Block Diagram

Size
Document Number
Custom
A

Sheet

Friday, March 30, 2012

E

Rev

A00

BMW Z4 DIS

Date:

102

of

105

DATE

PAGE

Change Iteam

Owner

2011 11/28

92

Change VT358 AVDD power rail to 5V_S5 to avoide leakage

Power

Version

DATE

PAGE

X01

2011 12/09

Change Iteam

Owner

Version

27

Change AOAC_PCIE_WAKE# pull high to 3D3V_WLAN_AOAC and PCIE_WAKE# to 3D3V_LAN_S5

EE

X01

2011 11/28

92

Re-name Cap PC4663 to PC9218.

EE

X01

2011 12/09

66

Change WWAN power to 3D3V_S0

EE

X01

2011 11/28

85

Change U8506 power rail and select pin to 3D3V_VGA_S0 to avoid leakage

EE

X01

2011 12/09

Change VCC_CORE MLCC by power team request

Power

X01

2011 11/28

93

Change PU9303 to 74.05930.03D by design

EE

X01

2011 12/09

Change AXG_CORE MLCC by power team request

Power

X01

2011 11/28

93

POP PD9301, PD9302, PD9303, PD9304, PC9328, change PR9327 to 20K, PR9330 to 10K,
PC9326 to 0.1u, PR9312 to 100K, PR9312 re-connect to DGPU_PWR_EN,
PD9302 re-connect to DGPU_PWROK for GPU power sequence

EE

X01

2011 12/09

22

Reserved DGPU_HOLD_RST# & DGPU_PWR_EN# pull high and down

EE

X01

2011 12/09

97

Follow EMI request added Cap.

EMI

X01

2011 11/28

37

Change R3714 to 10K to fix step-like waveform

EE

X01

2011 12/09

20

Rename PCIE request pin

EE

X01

2011 11/28

84

DY R8408 cause GPU support PX5.0

EE

X01

2011 12/09

65

Add WLAN requirst circuit

EE

X01

2011 11/28

86

DY R8605, Q8602, R8603, R8604, U8601, U8602, U8603, U8604, cause GPU support PX5.0

EE

X01

2011 12/12

40

design change PU4001 by Power team request

Power

X01

2011 12/02

27

Reserved DGPU_PWROK signal to inform KBC

EE

X01

2011 12/12

41

design change PU4106 by Power team request

Power

X01

2011 12/02

62

POP R6208, DY R6201 for USB charging function.

EE

X01

2011 12/12

41

Change PU4102 to colay symbol by Power team request

Power

X01

2011 12/02

85

Change VRAM type setting.

EE

X01

2011 12/12

45

Change PU4501to VT386 by Power team request

Power

X01

2011 12/02

41

Change PT4101, PT4103, PT4104 to 77.52271.09L for design change

EE

X01

2011 12/12

46

Change PR4609 and PR4612 by Power team request

Power

X01

2011 12/02

27

Add R2737 for avoiding KBC power drop.

EE

X01

2011 12/12

48

Change PU4801 by Power team request

Power

X01

2011 12/02

37

Change R3719 to 0402 type

EE

X01

2011 12/12

43

Reserved PT4301 by Power team request

Power

X01

2011 12/02

69

Change TPAD1 conn by ME

ME

X01

2011 12/12

84

Change R8412 to 4.7k.

EE

X01

2011 12/02

82

Change LEDBD1 conn by ME

ME

X01

2011 12/12

27

Change U2701 to new P/N

EE

X01

2011 12/02

56

Change HDD1 conn by ME

ME

X01

2011 12/13

82

Add ER8201, ER8202, ER8203, ER8204 by EMI request.

EMI

X01

2011 12/02

68

Change PWSW1 conn by ME

ME

X01

2011 12/13

18

Reserved USB_PN13, USB_PP13 test point.

EE

X01

2011 12/02

27

Change RSTSW1 conn by ME

ME

X01

2011 12/13

62

Del USB3.0 Redriver circuit.

EE

X01

2011 12/02

39

Add BATSW1 and R3901 for avoiding MB crack on assembling.

ME

X01

2011 12/13

27

Change R2735 and R2737 to 20K for fix AUX power overshoot.

EE

X01

2011 12/02

60

Change RTC1 conn by ME

ME

X01

2011 12/13

41

Change PC4127 to 4.7uF for fix AUX power overshoot.

EE

X01

2011 12/02

39

DY D3901, D3902, D3903 cause the battery is internal type.

EE

X01

2011 12/13

82

Add ER8205, EC8206 by EMI request.

EMI

X01

2011 12/02

51

Re-name D5001 and F5001 to D5101 and F5101, and DY F5101 and add R5109
due to no current leakage problem

EE

X01

2011 12/13

46

Add EL4601, EL4602 by EMI request.

EMI

X01

2011 12/13

43

Add EG4301,EG4302EG4303,EG4304,EG4305,EG4306,EG4307 by EMI request.

EMI

X01

2011 12/02

14

Change DM1 conn by ME

ME

X01
2011 12/13

44

Add EG4401,EG4402,EG4403,EG4404,EG4405,EG4406,EG4407 by EMI request.

EMI

X01

2011 12/13

15

Change DM2 conn by ME request

ME

X01

2011 12/15

97

Add EC9736, EC9726, EC9750 EC9708, EC9709, EC9770, EC9705, EC9769 by RF request.

RF

X01

2011 12/15

56

Add EC5601 by RF request.

RF

X01

2011 12/15

46

Add EC4638 by RF request.

RF

X01

2011 12/15

31

Add EC3122 by RF request.

RF

X01

2011 12/02

27

Change R2724 to 20K for X01 version

EE

X01

2011 12/02

85

DY C8523, cause VGA temp detect by SMBUS.

EE

X01

2011 12/02

28

DY U2803, C2817, C2818 cause VGA temp detect by SMBUS.

EE

X01

2011 12/02

38

Del PR3812.

EE

X01

2011 12/02

49

Change LCD1 conn by ME

ME

X01

2011 12/02

60

POP U6001 and del ROMSK1 for X01 version

EE

X01

2011 12/02

65

Change R6507 to J type

EE

X01

2011 12/02

39

Change BATT1 conn by ME

ME

X01

2011 12/02

82

Change IOBD1 conn by ME

ME

X01

2011 12/02

68

Add WLAN/WWAN LED power control circuit

EE

X01

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Change History

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

103

of

105

DATE

PAGE

Change Iteam

Owner Version

DATE
2011 12/23

PAGE
62

Change Iteam

Owner Version

2011 12/15

14

Change DM1 P/N to 62.10017.S81

EE

X01

Swap USB0 signal to TR6204 for layout

EE

X01

2011 12/15

15

Change DM2 P/N to 62.10017.T01

EE

X01

2011 12/23

97

Del H8.

ME

X01

2011 12/15

62

Del R6201 change by USB detect function

EE

X01

2011 12/27

51

Pop D5101, DY R5109.

EE

X01

2011 12/15

65

DY R6507, U6501 for design change

EE

X01

2011 12/30

93

Change PD9301, PD9302, PD9303, PD9304's 2nd source to 83.R5003.H8H

EE

X01

2011 12/15

68

Add R6809, DY C6802, R6803, D6802, WLAN LED power control by AOAC_WLAN_EN#.

EE

X01

2011 12/30

31

Change U3101 to 71.08162.A03 due to vendor update new version.

EE

X01

2011 12/15

Change C825, C830, C831, C832 to 0805 type.

EE

X01

2011 12/30

97

Pop EC9738, EC9739, EC9741, EC9743, EC9744, EC9764, EC9765, EC9766, EC9767, EC9768

EMI

X01

2011 12/15

Change C906, C907, C908, C909, C910 to 0805 type.

EE

X01

2011 12/30

36, 93

2011 12/15

93

Del 1D8V_VGA_S0 power good circuit.

EE

X01

2011 12/30

49

2011 12/15

83

Del VGA_RST# circuit.

EE

X01

2012 01/09

15, 24

2011 12/15

86

Del 1D5V_VGA_S0 power good circuit.

EE

X01
2012 01/09

48

Change VCCSA to LDO type.

2011 12/15

31

Reserved EC3101 by RF request.

RF

X01
2012 01/09

51

2011 12/15

97

Reserved EC9771, EC9772 by RF request.

RF

X01
2012 01/30

2011 12/16

86

Change C8642, C8650, C8647 to 22u 0805 size.

EE

X01

2011 12/16

62

Pop TR6204, DY R6279, R6280.

EMI

X01

2011 12/16

49

Pop TR4902, DY R4903, R4906.

EMI

X01

2011 12/16

Change C847 to 22u 0805 size.

EE

X01

2011 12/16

68

Pop C6802, for soft start.

EE

X01

2011 12/19

38

Change PC3806 to 0805 type

Power

X01

2011 12/19

43

Del PT4301 cause no layout area.

Power

X01

2011 12/20

44

Change PWR_GFX to PWR_CPU

Power

X01

2011 12/20

18

Change touch panel USB signal to port 4.

EE

X01

2011 12/20

82

Reserved TPAN1, and swap IOBD1's main and 2nd source.

EE

X01

2011 12/20

49

Swap LCD1's main and 2nd source.

EE

X01

Power

X01

Change TR4902 to 69.10103.041

EMI

X01

DY C1507 and C2403 by PI testing result.

EE

X01

Power

X02

Change HDMI SMBUS pull up power to 5V_HDMI_S0_R

EE

X03

48

Reserved PC4818 PC4819 to prevent VCCSA power IC VID setting(PWM solution)

EE

X03

2012 01/30

68

Add D6803 to fix DW1703 BT LED behavior. and change WLAN LED power rail to 5V_S0.

EE

X03

2012 01/30

97, 38

Take off EC9704, del PS_ID_R.

EE

X03

2012 01/30

82

Move IO BD conn signal for coaxial cable

EE

X03

2012 01/30

66

DY R6615.

EE

X03

2012 01/30

40, 38

Change PR4004 to 3K and PR3816 to 3.3K for hiccup mode adaptor.

EE

X03

2012 01/30

62

Change U6201 to lastly version.

EE

X03

2012 01/30

31

Change L3101 to prevent the shortage problem.

EE

X03

2012 02/06

82

Change TPAN1 P/N by ME request and modify conn pin define.

EE

X03

Reserved C3110 for Lan IC.

EE

X03

EE

X03

Power

X03

EE

X03

Power

X03

EMI

X03

2012 02/06

2012 02/06
2011 12/20

14

Change R1401, R1402 to short pad

EE

X01

2011 12/20

15

Change R1502 to short pad

EE

X01

2011 12/20

39

Change R3902, R3903, R3904 to 100 ohm to avoid break KBC when battery in.

EE

X01

2011 12/20

27

Del RN2703, add R2714, R2715.

EE

X01

2011 12/21

48

POP PR4814, change PR4811 to 365ohm, PR4813 to 100Kohm

Power

X01

2011 12/21

21

Add R2115 and del R6001 for SPI louting setting

EE

X01

2012 02/13

2011 12/21

DY C807, C843, C824.

Power

X01

2012 02/13

2011 12/21

42

Change PR4236 to 374ohm, PR4249 to 7.68Kohm.

Power

X01

2011 12/21

43

Change PU4301 IC to lastly version.

Power

X01

2011 12/21

44

Change PU4401 IC to lastly version.

Power

X01

2011 12/21

40

Design change PU4002 by power request

Power

X01

2011 12/21

27

Add R2716 to modify PSL circuit.

EE

X01

2011 12/23

82

Swap USB1, USB10 signal to TR8202 TR8201 for layout

EE

X01

2012 02/10

2012 02/13
A

31

Change U3601 U3602 PU9305 PU9306 2nd to 84.04178.037

5, 8, 9, 14,
15, 19,
23, 24, 27,
28, 36, 37,
38, 49, 51,
62, 65, 66,
83, 85

Change R504, R812, R909, R1404, R1405, R1505, R1503, R1921, R1916, R1924, R1929,
R1925, R2304, R2301, R2307, R2306, R2308, R2403, R2404, R2412, R2402, R2702, R2765,
R2794, R2778, R2792, R2733, R2767, R2768, R2720, R2764, R2723, R2727, R2807, R3614,
R3710, PR3819, R4912, R4913, R5125, R5101,R5102, R5149, R5103, R5108, R5107, R5106,
R5105, R6202, R6203, R6204, R6205, R6505, R6502, R6616, R8322, R8504, R8506, R8507,
to short pad

41, 42, 45,

46, 47, 95

Change PR4127, PR4130, PR4133, PR4116, PR4251, PR4250, PR4212, PR4207, PR4228,
PR4523, PR4522, PR4510, PR4511, PR4626, PR4621, PR4622, PR4623, PR4611, PR4602,
PR4702 ,PR9215 to short pad

51
41, 42, 18
19, 28, 93
97

Change HDMI output power design

Change PR9311, PR9320, PR4116, PR4219, PR4223, PR4252, PR4254, PR4261, R1823, R1927
R2813 to short pad
Add EC9704, EC9706, EC9716, EC9718, EC9722, EC9724, EC9728, EC9730, EC9775, EC9776,
EC9773, EC9774,EC9701, EC9751, EL4901 by EMI required

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Change History

Size
A3

Document Number

Date:

Friday, March 30, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

104

of

105

DATE

PAGE

Change Iteam

Owner Version

2012 2/16

27

Change PCB version to X03, X02 is for VCCSA LDO version verify.

EE

X03

2012 2/16

97

Add EC9777, EC9778, EC9779, EC9780, EC9781, EC9782, EC9783, EC9784, EC9785, EC9786,
EC9787, EC9788 by EMI required

EMI

X03

2012 2/16

Del C819, add C815

EE

X03

Change Pad type, change to green cover type.

EE

X03

Add EL4501, EL4502 by EMI required.

EMI

X03

Reserved EC9201, EC9202, EC9203, EC9301, EC9302, EC9303 by RF required.

RF

X03

Add EC4901, EC4902, EC4904, EC4905, EC4906, EC4908, EC4909, EC4910, EC4911, EC1524,
EC1428, EC2409, EC2305, EC4528, EC4521, EC4507, EC9789, EC9790 by RF required.

RF

X03

Power

X03

EE

X03

Power

X03

DATE

PAGE

Change Iteam

Owner Version

2012 2/16

2012 2/16

45

2012 2/16

92, 93

2012 2/16

49

2012 2/20

40, 41, 42
43, 44, 45
46, 47, 48
92, 93

41, 43, 44

Add Power Gap PG4115, PG4116, PG4117 EG4308, EG4309, EG4310. EG4311, EG4408
EG4409, EG4410, EG4411 for power team

2012 2/21

93

Add PQ9304 for fine tune GPU sequence

2012 2/21

42

Change PR4236 to 953ohm, PR4239 to 300ohm

2012 2/21

14, 97

2012 2/29

59

2012 3/15

82, 85, 39

Change EC9778, EC9779, EC9780 to EC1406, EC1407, EC1408 by layout.

EE

X03

Change C5902 P/N.

EE

X03

DY R8501, R8204, TPAN1, R3901

EE

A00

2012 3/15

27

Change R2724 to 64.9k for A00 PCB version

EE

A00

2012 3/15

71, 82

Change DB1 and CRTBD1 to green cover type symbol.

EE

A00

2012 3/15

85

Pop R8535

EE

A00

2012 3/22

68

Del WLAN LED control power rail circuit.

EE

A00

Change ER8201, ER8202, ER8203, ER8204, R6503, R6506, R6601, R6602, ER8205, R2205, R3113,
R6281, R6282, R6283, R6284, R6616, PR4022, PR4801, PR4803, RN2012, RN2014, RN2017,
to short pad and del TR6501, TR6601, TR8201, TR8202, TR6205, TR6206.

EE

A00

2012 3/23
B

20, 22, 62
65, 48, 40
66, 82

2012 3/27

82, 97

Pop EC8207, EC9734, reserved ER1807 by EMI request.

EMI

A00

2012 3/27

49, 62

Del R6279, R6280, R4903, R4906 by PSE request

EE

A00

2012 3/27

69

Change R6909 to 0603 type.

EE

A00

2012 3/27

49

Change RN4902 to 100 Ohm.

EE

A00

2012 3/27

21

Change R2136 R8612 to short pad, and change RN2101 to R2116, R2121, R2127, R2128 short pad

EE

A00

2012 3/29

45, 97

Del EL4502 and EC9729 for layout.

EE

A00

2012 3/30

Del C819 for layout.

EE

A00

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Change History

Size
A3

Document Number

Date:

Monday, April 02, 2012

Rev

BMW Z4 DIS

A00
Sheet
1

105

of

105