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ESQUEMA ELÉTRICO DA PCI CPU MAMI NÚMERO – REV

AMD ALXD800 – GEODE LX


EE30184C
30-28700-0 PAGINA:1 de 26
30-28700-1

REGISTRO DE REVISÕES
REV. DATA DESCRIÇÃO BREVE DA REVISÃO
A 22.05.2009 Emissão Inicial
B 18.05.2010 Alteração do U16 de LP8340CLD-ADJ para LP38690,
R116 de 10K7 para 0R e R117 de 10K para NL.
C 12.07.2010 Alteração do R116 de 0R para 10K7 e R117 de NL
para 10K, para funcionamento com o Regulador
LP38690-ADJ.

PROJETO/ ADEP AP20204


ANÁLISE CRÍTICA Há necessidade de treinamento ? ( ) Sim ( X ) Não
DATA DE VIGÊNCIA 15.07.2010
ELABORADOR APROVADOR
Área P&D P&D
Data 22.06.2010 12.07.2010
Nome Igor N. Candiani Edward Maktura
Visto

ESQUEMA ELÉTRICO
DOCUMENTOS INCORPORADOS

1. EE30184C.dsn

DIXTAL
Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.
5 4 3 2 1

AMD Geode™ LX Ultra Value


D
Client RDK Schematic D

Page Index
------- ------------------------
1 COVER PAGE
2 REVISION HISTORY
3 BLOCK DIAGRAM
4 POWER ON & RESET SEQUENCE
NOTES:
5 PCI & JTAG BLOCK DIAGRAM
1) THIS SCHEMATIC IS TARGETED AT AN AMD GEODE™ LX PROCESSOR
(REV C0 OR HIGHER) AND AMD GEODE™ CS5536 COMPANION DEVICE 6 LX PROCESSOR DDR MEMORY
BASED DESIGN.
C 7 DDR SODIMM CONNECTOR C
2) UNLESS OTHERWISE SPECIFIED RESISTORS HAVE 1% TOLERANCE.

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


8 LX PROCESSOR DISPLAY
9 LX PROCESSOR PCI / SYSTEM
10 LX PROCESSOR POWER
11 CS5536 PCI / SYSTEM / PM / ROM
12 CS5536 IDE / USB / AC97 / LPC
13 CS5536 POWER & CLOCK GENERATOR
14 USB_PS2_CONNECTORS
B
15 AUDIO CODEC B

IMPORTANT NOTES ABOUT 16 ETHERNET - 10 / 100


THIS SCHEMATIC 17 IDE_CMPCT_FLSH_INVRSR_LCD
DESIGN NOTE: 1) DESIGN NOTES in 18 POWER SUPPLIES
Example text for the grey are information
design note to show the notes. 19 DDR_ONBOARD1
note inside the colored
box. 20 DDR_ONBOARD2
DESIGN NOTE: 2) DESIGN NOTES in
Example text for the yellow are notes of 21 LPC_ISA_MAMI
design note to show the caution.
note inside the colored 22 MAMI_RS485
A
box. A
DESIGN NOTE: 3) DESIGN NOTES in
23 PWR_SUPPLY_FPGA
Example text for the red are critical, and
design note to show the must be understood and
24 INTERFACE_ERT_SPO2 ITEM DOCUMENTO
note inside the colored followed.
box.
25 INTERFACE_IBP_NIBP_ETCO2 30-28700-0/1 EE30184C

PAGINA: 2 DE 26 COVER PAGE


5 4 3 2 1
5 4 3 2 1

REVISION HISTORY:

REV DATE NOTES


D
------- ----------------- -------------------------------------------------------------------------------------------------- D
A 08-02-2007 INITIAL RELEASE.

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


C C

B B

A A

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 3 DE 26 REVISION HISTORY


5 4 3 2 1
5 4 3 2 1

LVDS 18/24 BITS

ONBOARD DDR
SODIMM DDR
VGA MONITOR
CPU MEMORY BUS

AMD Geode™
D LX Processor D

PCI BUS(33MHz)

COMPACT FLASH 10/100


Ethernet

PRIMARY IDE ATA-66


Companion
Device
USB2.0 AMD Geode™
AC97
CS5536 AUDIO
CODEC

C C

LPC
MAMI FPGA RS485
XILINX INTERFACE
Flash XC3S500E
BIOS FT256 FRONT PANEL
INTERFACE

ERT
INTERFACE

SPO2
INTERFACE

NIBP
PCI(33 MHz) INTERFACE

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


B B
Clock 66 MHz
IBP
14.318 MHz Synthesizer INTERFACE
Crystal 48 MHz
REFCLK
ABS PRESSURE
INTERFACE

VCORE(1.2V to 1.4V) ETCO2


VMEM (2.5V or 2.6V) INTERFACE
3.3V, 5V DC/DC 1.225V
and
LDO POWER SUPPLY
INTERFACE

ANESTHESIA
INTERFACE
VCC_FPGA_3V3
VCC_FPGA_2V5
MEMORY
VCC_FPGA_1V2 STORAGE
5V
DC/DC
A A

3.3V
12V

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 4 DE 26 BLOCK DIAGRAM


5 4 3 2 1
5 4 3 2 1

D SYSTEM POWER D
AMD
Geode™ LX VCC=+5.0V
Processor VCC3=+3.30V

DESIGN NOTE: This design uses AMD Geode™LX


LVD to generate system reset. Processor
DESIGN NOTE: This design VCORE=+1.25V or +1.2V
PCIRST#
requires PWRBTN# to be asserted VCCMEM=+2.50V or +2.6V
after main power is applied to exit AMD RESET_WORK#
the S5 power state. MVREF=VCCMEM/2
Geode™ VIO=+3.30V
WORKING
CS5536
PWRBTN# AMD Geode™
LVD_EN# CS5536 POWER
C C

VCORE=+1.25V or +1.2V
VCORESB=VCORE
VIO=+3.30V

MEMORY POWER
VMEM=VCCMEM
MVREF=VCCMEM/2

B B

A A

ITEM DOCUMENTO
30-28700-0/1 EE30184C

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 5 DE 26 PWR ON RESET SEQUENCE
5 4 3 2 1
5 4 3 2 1

PCI MASTER CONFIGURATION


D D

REQ2#_IOC
AMD Geode™
AMD Geode™ GNT2#_IOC
CS5536
LX Processor REQ0#_LAN
GNT0#_LAN
ETHERNET
RTL8100C
SEL66_33# Function PCI CLOCK ROUTING
CLK_CPU AMD Geode™
1 PCI 66 MHz LX Processor
CLK_IOC AMD Geode™
C 0 PCI 33 MHz CS5536 C

CLK_LAN ETHERNET
DESIGN NOTE: PCI must SEL66_33#
be set to 33 MHz when CLOCK RTL8100C
using the RTL8100. CLK_IDE (66MHz)

GENERATOR CLK_LPC_IOC (33MHz) AMD Geode™


JTAG DAISY CHAIN MODE WITH AMD GEODE™ CLK_14_IOC (14.318MHz) CS5536
CS5536 COMPANION DEVICE
CLK_14_CODEC (14.318MHz) AUDIO CODEC
ALC203
CLK_LPC_48 (48MHz)
TCK LPC HEADER
B TCK TCK B
TMS
TMS TMS
CLK_LPC_FWH (33MHz)
TDI LPC ROM
TDI TDI

TDO TDO
TDO OTHER CLOCK ROUTING
TDEBUG_OUT
TDEBUG_OUT TDEBUG_OUT
TDEBUG_IN
TDEBUG_IN TDEBUG_IN
FS2 HEADER AMD GEODE™ LX PROCESSOR AMD GEODE™ CS5536

A A

ITEM DOCUMENTO
30-28700-0/1 EE30184C

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 6 DE 26 PCI & JTAG BLOCK DIAGRAM
5 4 3 2 1
5 4 3 2 1

U1A

RMDQS[7:0] 7 RMD[63:0] 7
MDQM0 M1 RMDQS0 RMD0
MDQM1 DQM0 DESIGN NOTE: RMDQS1 RMD1
G2 DQM1
MDQM2 D26 MBA0 MD1 RMD1 RMDQS2 RMD2
MDQM3
A6 DQM2 BA0 Layout must 8 1
B10 DQM3 BA1 C20 MBA1 MD21 8 1 RMD21 RN2 MD5 7 2 RMD5 RMDQS3 RMD3
MDQM4 A19 RN1 MD17 7 2 RMD17 adhere to the 33 MD4 6 3 RMD4 RMDQS4 RMD4
MDQM5 DQM4 33 MD16 RMD16 MD0 RMD0 RMDQS5 RMD5
MDQM6
C24 DQM5 TLA0 B15
MD20
6 3
RMD20
layout 5 4
RMDQS6 RMD6
H29 DQM6 TLA1 B13 5 4
MDQM7 N30 recommendations MD6 8 1 RMD6 RMDQS7 RMD7
D DQM7 MD22 RMD22 RN4 MD2 RMD2 RMD8 D
RN3 MD18
8 1
RMD18
(PID 32739). 33 MDQM0
7 2
RMDQM0 RMDQM[7:0] 7 RMD9
7 2 6 3
33 MDQM2 6 3 RMDQM2 MDQS0 5 4 RMDQS0 RMDQM0 RMD10
MCS0# B28 MDQS2 5 4 RMDQS2 RMDQM1 RMD11
MCS1# CS0# MD0 MD9 RMD9 RMDQM2 RMD12
F28 CS1# DQ0 P2 8 1
F29 N2 MD1 MD28 8 1 RMD28 RN6 MD8 7 2 RMD8 RMDQM3 RMD13
CS2# DQ1 MD2 RN5 MD24 RMD24 33 MD3 RMD3 RMDQM4 RMD14
D30 CS3# DQ2 M3 7 2 6 3
K2 MD3 33 MD19 6 3 RMD19 MD7 5 4 RMD7 RMDQM5 RMD15
DQ3
P3 MD4 MD23 5 4 RMD23 DESIGN NOTE: RMDQM6 RMD16
DQ4
MCKE0 E4 CKE0 DQ5 N1 MD5 Place DQ, DQS, MDQM1 8 1 RMDQM1 RMDQM7 RMD17
F4 L3 MD6 MDQM3 8 1 RMDQM3 RN8 MDQS1 7 2 RMDQS1 RMD18
CKE1 DQ6
K1 MD7 RN7 MDQS3 7 2 RMDQS3 and DQM series 33 MD13 6 3 RMD13 RMD19
DQ7 RMA[13:0] 7
DQ8 J2 MD8 33 MD25 6 3 RMD25 resistors as MD12 5 4 RMD12 RMD20
J1 MD9 MD29 5 4 RMD29 RMA0 RMD21
DQ9
F3 MD10 close to the MD11 8 1 RMD11 RMA1 RMD22
DQ10
MWE# C27 WE0# DQ11 E3 MD11 MD31 8 1 RMD31 processor as RN10 MD10 7 2 RMD10 RMA2 RMD23
A28 J3 MD12 RN9 MD27 7 2 RMD27 33 MD15 6 3 RMD15 RMA3 RMD24
WE1# DQ12
G1 MD13 33 MD26 6 3 RMD26 possible. MD14 5 4 RMD14 RMA4 RMD25
DQ13 MD14 MD30 RMD30 RMA5 RMD26
DQ14 F2 5 4
F1 MD15 RMA6 RMD27
MCAS# DQ15 MD16 MD37 RMD37 RMA7 RMD28
E28 CAS0# DQ16 D2 8 1
E29 B4 MD17 RN11 MD33 7 2 RMD33 RMA8 RMD29
MRAS# CAS1# DQ17 MD18 33 MD36 RMD36 RMA9 RMD30
C26 RAS0# DQ18 B6 6 3
C D27 C8 MD19 MD32 5 4 RMD32 RMA10 RMD31 C
RAS1# DQ19 MD20 RMA11 RMD32
DQ20 D1
A4 MD21 MD38 8 1 RMD38 RMA12 RMD33

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


DQ21 MD22 RN12 MD34 RMD34 RMA13 RMD34
M4 SDCLK0P DQ22 A7 7 2
7 SDCLK0 MD23 33 MDQM4 RMDQM4 MA13 RMA13 RMD35
J4 SDCLK1P DQ23 B7 6 3 1 8
M28 B9 MD24 MDQS4 5 4 RMDQS4 RN13 MCS1# 2 7 RMD36
7 SDCLK2 SDCLK2P DQ24 MD25 22 MCAS# RMCS1# 7 RMD37
J28 SDCLK3P DQ25 C10 3 6
MD26 MD44 RMD44 MCS0# RMCAS# 7 RMD38
D23 SDCLK4P DQ26 A12 8 1 4 5
7 SDCLK4 MD27 RN14 MD40 RMD40 RMCS0# 7 RMD39
D20 SDCLK5P DQ27 B12 7 2
A9 MD28 33 MD35 6 3 RMD35 MWE# 1 8 RMD40
DQ28 MD29 MD39 RMD39 RN15 MBA0 RMWE# 7 RMD41
DQ29 C9 5 4 2 7 RMBA0 7
C11 MD30 22 MRAS# 3 6 RMD42
DQ30 MD31 MDQM5 RMDQM5 MBA1 RMRAS# 7 RMD43
L4 SDCLK0N DQ31 A13 8 1 4 5
7 SDCLK0# MD32 RN16 MDQS5 RMDQS5 RMBA1 7 RMD44
H4 SDCLK1N DQ32 A15 7 2
L28 B17 MD33 33 MD41 6 3 RMD41 MA10 1 8 RMA10 RMD45
7 SDCLK2# SDCLK2N DQ33 MD34 MD45 RMD45 RN17 MA1 RMA1 RMD46
H28 SDCLK3N DQ34 B19 5 4 2 7
D24 B22 MD35 22 MA0 3 6 RMA0 RMD47
7 SDCLK4# SDCLK4N DQ35 MD36 MD47 RMD47 MA2 RMA2 RMD48
D21 SDCLK5N DQ36 B16 8 1 4 5
A17 MD37 RN18 MD43 7 2 RMD43 RMD49
DQ37 MD38 33 MD46 RMD46 MA3 RMA3 RMD50
DQ38 B20 6 3 1 8
A20 MD39 MD42 5 4 RMD42 RN19 MA4 2 7 RMA4 RMD51
DQ39 MD40 22 MA6 RMA6 RMD52
DQ40 A22 3 6
MDQS0 M2 A23 MD41 MD53 8 1 RMD53 MA5 4 5 RMA5 RMD53
MDQS1 DQS0 DQ41 MD42 RN20 MD52 RMD52 RMD54
H3 DQS1 DQ42 A25 7 2
B MDQS2 C6 A26 MD43 33 MD49 6 3 RMD49 MA8 1 8 RMA8 RMD55 B
MDQS3 DQS2 DQ43 MD44 MD48 RMD48 RN21 MA7 RMA7 RMD56
A10 DQS3 DQ44 C22 5 4 2 7
MDQS4 C19 C23 MD45 22 MA9 3 6 RMA9 RMD57
MDQS5 DQS4 DQ45 MD46 MD55 RMD55 MA11 RMA11 RMD58
B23 DQS5 DQ46 B25 8 1 4 5
MDQS6 J29 B26 MD47 RN22 MD54 7 2 RMD54 RMD59
MDQS7 DQS6 DQ47 MD48 33 MDQS6 RMDQS6 MA12 RMA12 RMD60
N31 DQS7 DQ48 D31 6 3 1 8
F31 MD49 MDQM6 5 4 RMDQM6 RN23 MCKE0 2 7 RMD61
DQ49 MD50 22 RMCKE0 7 RMD62
DQ50 K30 3 6
K31 MD51 MD61 8 1 RMD61 4 5 RMD63
DQ51 MD52 RN25 MD60 RMD60
DQ52 G30 7 2
MA0 C16 G31 MD53 33 MD51 6 3 RMD51
MA1 MA0 DQ53 MD54 MD50 RMD50
C17 MA1 DQ54 J31 5 4
MA2 C15 J30 MD55
MA3 MA2 DQ55 MD56 MDQS7 RMDQS7
C13 MA3 DQ56 M31 8 1
MA4 D13 M30 MD57 RN24 MDQM7 7 2 RMDQM7
MA5 MA4 DQ57 MD58 PT1 33 MD57 RMD57
D11 MA5 DQ58 R30 6 3
MA6 D12 R31 MD59 MD56 5 4 RMD56 DESIGN NOTE:
MA7 MA6 DQ59 MD60
D8 L29
MA8 D9
MA7 DQ60
M29 MD61 MD59 8 1 RMD59 Place the A, BA,
MA9 MA8 DQ61 MD62 RN26 MD58 RMD58
D6 MA9 DQ62 P30 7 2 CKE, CAS#,
MA10 D19 R29 MD63 VCCMEM 33 MD63 6 3 RMD63
MA11 D5
MA10 DQ63 MD62 5 4 RMD62 CS#, RAS#, and
MA12 MA11 R1
C5 MA12 WE# series
MA13 F30 3.40K
A MA13
P1 resistors as A
AMD GEODE™ MVREF DDRVREF7
close to the
DESIGN NOTE: See LX PROCESSOR C1 1%
R2 MVREF = VMEM/2 DRAM as
layout recommendations 0.1uF possible. ITEM DOCUMENTO
3.40K
(PID 32739) for latest 1%

instructions on memory 30-28700-0/1 EE30184C


routing. DGND PAGINA: 7 DE 26 LX PROCESSOR DDR MEMORY
5 4 3 2 1
5 4 3 2 1

JDIMM1A

6 SDCLK0 35 CK0
6 SDCLK0# 37 CK0#
160 PT2
6 SDCLK2 CK1
158 VCCMEM
6 SDCLK2# CK1#

6 RMCKE0 96 CKE0
95 CKE1 C2 C3 C4 C5
D 10uF 10uF 10uF 10uF D
RMD[63:0] 6
118 6.3V 6.3V 6.3V 6.3V
6 RMRAS# RAS#
120 5 RMD0
6 RMCAS# CAS# DQ00
119 7 RMD1
6 RMWE# WE# DQ01
13 RMD2
DQ02 RMD3
6 RMCS0# 121 S0# DQ03 17
122 6 RMD4 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
6 RMCS1# S1# DQ04
8 RMD5
6 RMDQS[7:0] DQ05
14 RMD6 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RMDQS0 DQ06 RMD7
11 DQS0 DQ07 18
RMDQS1 25 19 RMD8
RMDQS2 DQS1 DQ08 RMD9
47 DQS2 DQ09 23
RMDQS3 61 29 RMD10
RMDQS4 DQS3 DQ10 RMD11 DGND
133 DQS4 DQ11 31
RMDQS5 147 20 RMD12
RMDQS6 DQS5 DQ12 RMD13
169 DQS6 DQ13 24
RMDQS7 183 30 RMD14 JDIMM1B
DQS7 DQ14 RMD15
6 RMA[13:0] DQ15 32
41 RMD16 1
RMA0 DQ16 RMD17 6 DDRVREF VREF
112 A0 DQ17 43 2 VREF
RMA1 111 49 RMD18 VCCMEM
RMA2 A1 DQ18 RMD19
110 A2 DQ19 53
RMA3 109 42 RMD20 9 3
RMA4 A3 DQ20 RMD21 VDD VSS
C 108 A4 DQ21 44 10 VDD VSS 4 C
RMA5 107 50 RMD22 21 15
RMA6 A5 DQ22 RMD23 VDD VSS
106 A6 DQ23 54 22 VDD VSS 16
RMA7 105 55 RMD24 33 27

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


RMA8 A7 DQ24 RMD25 VDD VSS
102 A8 DQ25 59 34 VDD VSS 28
RMA9 101 65 RMD26 36 38
RMA10 A9 DQ26 RMD27 VDD VSS
115 A10/AP DQ27 67 45 VDD VSS 39
RMA11 100 56 RMD28 46 40
RMA12 A11 DQ28 RMD29 VDD VSS
99 A12 DQ29 60 57 VDD VSS 51
66 RMD30 58 52
6 RMDQM[7:0] DQ30 VDD VSS
68 RMD31 69 63
RMDQM0 DQ31 RMD32 VDD VSS
12 DM0 DQ32 127 70 VDD VSS 64
RMDQM1 26 129 RMD33 81 75
RMDQM2 DM1 DQ33 RMD34 VDD VSS
48 DM2 DQ34 135 82 VDD VSS 76
RMDQM3 62 139 RMD35 92 87
RMDQM4 DM3 DQ35 RMD36 VDD VSS
134 DM4 DQ36 128 93 VDD VSS 88
RMDQM5 148 130 RMD37 94 90
RMDQM6 DM5 DQ37 RMD38 VDD VSS
170 DM6 DQ38 136 113 VDD VSS 103
RMDQM7 184 140 RMD39 114 104
DM7 DQ39 RMD40 VDD VSS
DQ40 141 131 VDD VSS 125
145 RMD41 132 126
DQ41 RMD42 VDD VSS
6 RMBA0 117 BA0 DQ42 151 143 VDD VSS 137
116 153 RMD43 144 138
6 RMBA1 BA1 DQ43 VDD VSS
142 RMD44 155 149
DQ44 RMD45 VDD VSS
B
DQ45 146 156 VDD VSS 150 B
VCCMEM 194 152 RMD46 157 159
SA0 DQ46 RMD47 VDD VSS
196 SA1 DQ47 154 167 VDD VSS 161
R3 2.2K 198 163 RMD48 168 162
SA2 DQ48 RMD49 VDD VSS
DQ49 165 179 VDD VSS 173
R4 2.2K 171 RMD50 180 174
DGND DQ50 RMD51 VDD VSS
DQ51 175 191 VDD VSS 185
193 164 RMD52 192 186
12 SMB_SDA SDA DQ52 VDD VSS
195 166 RMD53
12 SMB_SCL SDL DQ53
172 RMD54
DQ54 RMD55 DGND
DQ55 176 197 VDDSPD
85 177 RMD56
RFU DQ56 RMD57
86 RFU/RESET DQ57 181
71 187 RMD58 SODIMM
CB0 DQ58 RMD59 <Mfr_Part_Number>
72 CB4 DQ59 189
73 178 RMD60
CB1 DQ60 RMD61
74 CB5 DQ61 182
77 188 RMD62
DQS8 DQ62 RMD63
78 DM8 DQ63 190
79 CB2
80 CB6
83 CB3
84 CB7
6 SDCLK4 89 CK2
A 91 A
6 SDCLK4# CK2
97 RFU1
98 RFU2
VCCMEM RMA13 123 RFU/A13
R5 10K
5%
124 RFU3 ITEM DOCUMENTO
199 VddID
200 RFU4
30-28700-0/1 EE30184C
SODIMM
<Mfr_Part_Number> PAGINA: 8 DE 26 DDR SODIMM CONNECTOR
2-1734073-1 NL
5 4 3 2 1
5 4 3 2 1

U1C
U2 VCC3 LVDS_AVCC3 LVDS_PVCC3
TFT_R0 51 34
RN27 22 TFT_R1 TXIN0 PLL_VCC
52 44
TFT_R1 T_R1 TFT_R2 TXIN1 LVDS_VCC PT3 PT5 PT7 PT9 PT11 PT23 VCC_LCD
8 1 AL12 AD4 LDEMOD_HSIP_VSYNC 26 54 26
TFT_R0 T_R0 VIPCLK LDEMOD/VIP_VSYNC TFT_R3 TXIN2 VCC
7 2 AL14 AE4 DISPEN 16 55 1
TFT_R2 T_R2 TFTCLK VIPSYNC DISPEN/VOP_BLANK TFT_R4 TXIN3 VCC PT4 PT6 PT8 PT10 PT12
TFT_R2 6 3 TFTCLK AE1 AE2 56 9 CN1
TFT_R3 T_R3 DOTCLK/VOPCLK VDDEN/VIP_HSYNC TFT_R5 TXIN4 VCC
TFT_R3 5 4 3 17 1
TFT_R6 TXIN6 VCC 1
50 2
RN28 22 T_B0 VSYNC TFT_R7 TXIN27 A0P 2
AH7 AD3 2 47 3
TFT_R4 T_R4 T_B1 DRGB0/VOP7 VSYNC/VOP_VSYNC HSYNC TXIN5 TA+ A0M 3
TFT_R4 8 1 AK6 AE3 48 4
TFT_R5 T_R5 T_B2 DRGB1/VOP6 HSYNC/VOP_HSYNC TFT_G0 TA- A0M 4
TFT_R5 7 2 AL6 4 5
TFT_R6 T_R6 T_B3 DRGB2/VOP5 TFT_G1 TXIN7 A1P A0P 5
TFT_R6 6 3 AJ7 6 45 6
TFT_R7 T_R7 T_B4 DRGB3/VOP4 TFT_G2 TXIN8 TB+ A1M 6
TFT_R7 5 4 AK7 7 46 7
T_B5 DRGB4/VOP3 TFT_G3 TXIN9 TB- A1M 7
AL7 11 8
RN29 22 T_B6 DRGB5/VOP2 TFT_G4 TXIN12 A2P A1P 8
AH8 12 41 9
TFT_G0 T_G0 T_B7 DRGB6/VOP1 TFT_G5 TXIN13 TC+ A2M 9
8 1 AJ8 14 42 10
TFT_G2 T_G2 T_G0 DRGB7/VOP0 CRT_RED TFT_G6 TXIN14 TC- A2M 10
TFT_G2 7 2 AJ2 W3 8 11
D
TFT_G1 T_G1 T_G1 DRGB8/VOP15 RED TFT_G7 TXIN10 A3P A2P 11 D
6 3 AK3 10 37 12
TFT_G5 T_G5 T_G2 DRGB9/VOP14 TXIN11 TD+ A3M 12
TFT_G5 5 4 AL3 38 13
T_G3 DRGB10/VOP13 TFT_B0 TD- CLKM 13
AH5 15 14
RN30 22 T_G4 DRGB11/VOP12 TFT_B1 TXIN15 CLKP CLKP 14
AJ4 19 39 15
TFT_G6 T_G6 T_G5 DRGB12/VOP11 CRT_GREEN TFT_B2 TXIN18 TCLK+ CLKM 15
TFT_G6 8 1 AL4 V2 20 40 16
TFT_G4 T_G4 T_G6 DRGB13/VOP10 GREEN TFT_B3 TXIN19 TCLK- A3M 16
TFT_G4 7 2 AK4 22 17
TFT_G7 T_G7 T_G7 DRGB14/VOP9 TFT_B4 TXIN20 A3P 17
TFT_G7 6 3 AJ5 23 35 18
TFT_G3 T_G3 T_R0 DRGB15/VOP8 TFT_B5 TXIN21 PLL_GND 18
TFT_G3 5 4 AF2 24 33 19
T_R1 DRGB16_VOP23 TFT_B6 TXIN22 PLL_GND PT24 19
AF1 16 49 20
RN31 22 T_R2 DRGB17_VOP22 CRT_BLUE TFT_B7 TXIN16 LVDS_GND 20
AG3 U2 18 43
TFT_B2 T_B2 T_R3 DRGB18_VOP21 BLUE TXIN17 LVDS_GND
8 1 AG4 36 JST
TFT_B1 T_B1 T_R4 DRGB19_VOP20 HSYNC LVDS_GND
TFT_B1 7 2 AH1 27 53
TFT_B5 T_B5 T_R5 DRGB20_VOP19 VSYNC TXIN24 GND
6 3 AH2 28 29
TFT_B4 T_B4 T_R6 DRGB21_VOP18 VCC3 LDEMOD_HSIP_VSYNC TXIN25 GND LVDS_PGND
TFT_B4 5 4 AH3 30 21
T_R7 DRGB22_VOP17 VCC3 TFTCLK TXIN26 GND DGND
AJ1 31 13
RN32 22 DRGB23_VOP16 DACVDD R6 1.0 CLKIN GND
AH11 W4 32 5
TFT_B3 T_B3 DRGB24/VID8 DAVDD PDWNX GND LDVS_AGND
TFT_B3 8 1 AJ11 V4 25
TFT_B0 T_B0 DRGB25/VID9 DAVDD TXIN23
TFT_B0 7 2 AK10 U1
TFT_B7 T_B7 DRGB26/VID10 DAVDD DS90CF383
TFT_B7 6 3 AL10 V1
TFT_B6 T_B6 DRGB27/VID11 DAVDD C18 C19 DGND
TFT_B6 5 4 AJ10
DRGB28/VID12 0.01uF 10uF R7 DGND
AH10
DRGB29/VID13 6.3V 10K
AL9
DRGB30/VID14
AK9 W2
DRGB31/VID15 DAVSS
Y2
DAVSS
AJ15 U3
VID0 DAVSS
DESIGN NOTE: VID[7:0] AK15
VID1 DAVSS
V3
AGND_VGA PT25 VCC3 LVDS_AVCC3 LVDS_PVCC3
AL15
and VIPCLK have AH13
VID2
U3
VID3 TFT_R2
internal pulldowns AJ13
VID4
44
TA0 PLL_VCC
29
AK13 W1 TFT_R3 45 37
VID5 DVREF TFT_R4 TA1 LVDS_VCC
AL13
VID6 AMD GEODE™ DRSET
Y1
TFT_R5
47
TA2 VCC
21
VCC_LCD
AK12 48 8 PT21
VID7 LX PROCESSOR R8 D1 TFT_R6 TA3 VCC PT13 PT15 PT17 PT19
1 43
1.21K C20 TFT_R7 TA4 NC PT14
3 CN2
1% 0.01uF TA5 A0PA PT16 PT18 PT20
40 1
LM4041 TFT_G2 TA+ A0MA 1
4 41 2
TFT_G3 TA6 TA- 2
6 3
TFT_G4 TB0 A1PA 3
C 7 38 4 C
TFT_G5 TB1 TB+ A1MA A0MA 4
9 39 5
TFT_G6 TB2 TB- A0PA 5
10 6
AGND_VGA TFT_G7 TB3 A2PA 6
12 34 7
TB4 TC+ A2MA A1MA 7
35 8
TFT_B2 TC- A1PA 8
13 9
TFT_B3 TB5 CLKPA 9
15 32 10
TFT_B4 TB6 TCLK+ CLKMA A2MA 10
16 33 11
TFT_B5 TC0 TCLK- A2PA 11
18 12
PT26 PT27 TFT_B6 TC1 12
19 28 13
VCC3 LVDS_PVCC3 VCC3 LVDS_AVCC3 VCC5 VCC3 TFT_B7 TC2 PLL_GND CLKMA 13
FB2 20 30 14
FB1 VCC_LCD TC3 PLL_GND CLKPA 14
FB3 36 15
HSYNC LVDS_GND 15
2 FERR 1 2 FERR 1 22 42 16
VSYNC TC4 LVDS_GND 16
1 2 2 FERR 1 23 31 17
FB/330/1.5A FB/330/1.5A LDEMOD_HSIP_VSYNC TC5 LVDS_GND PT22 17
R9 0 25 5 18
TC6 GND 18
1

C21 C22 C23 C24 C25 C29 FB/330/1.5A VCC3 TFTCLK 26 24 19

1
CLKIN GND 19
1 2 C26 C27 C28 27 11 20
10uF 0.1uF 0.01uF 10uF 0.1uF 0.01uF PDWNX GND 20
R10 0 NL 2 46
2

10uF 0.1uF 0.01uF RS GND


1 2 1 2 14 17 JST

2
R/F GND
R11 0 R12 0
DS90C363 LVDS_PGND DGND
DGND LVDS_PGND DGND LDVS_AGND
DGND LDVS_AGND
DGND
DGND
CONTROLE LVDS
VCC3 DESIGN NOTE: VCC5 VCC3 VCC5

Place the ESD TS1


protection 2 1
D2 D3 D4 D5 D6 D7 D8
components as close 50Wx80L_mil
to the VGA connector DGND AGND_VGA

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


B as possible. B

BAV99LT1 BAV99LT1 BAV99LT1 BAV99LT1 BAV99LT1 BAV99LT1 BAV99LT1 VCC5

R13 2.2K
L1 R14 2.2K
CRT_RED 1 2 DGND DGND
22nH CN22
HEADER 8X2
CRT_SDA 12
L2 MRED 1 2 HSYNC
CRT_GREEN 1 2 MGREEN MGREEN 3 4
22nH MBLUE 5 6 VSYNC
7 8 CRT_SDA
9 10 HSYNC
CRT_SCL 12
L3 11 12 VSYNC
CRT_BLUE 1 2 MBLUE 13 14 CRT_SCL
22nH 15 16

R15 R16 R17 C30 C31 C32


75 75 75 5pF 5pF 5pF C36 0.1uF
5% 5% 5% C33 C34 C35 AGND_VGA AGND_VGA
5pF 5pF 5pF
VCC5

FB4 FB5 FB/120/0.2A/0603


C37 0.1uF 1 FERR 2 1 FERR 2
AGND_VGA
AGND_VGA FB/120/0.2A/0603
DGND DGND CHASSIS

A
VGA A

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 9 DE 26 LX PROCESSOR DISPLAY


5 4 3 2 1
5 4 3 2 1

U1B
PCI_PAR 11,16

PAR AJ27

GNT0#_LAN AA28 PCI_AD[31:0] 11,16


16 GNT0#_LAN GNT0#
GNT1#_PCI0 AB30 AJ19 PCI_AD0 VCC3
GNT2#_IOC AC30 GNT1# AD0 PCI_AD1 RN33
11 GNT2#_IOC GNT2# AD1 AH19
AD2 AL20 PCI_AD2 4 3 2 1 CORE MEM JTAGTMS 1 8
AD3 AK20 PCI_AD3 --- --- --- --- --- --- TDBGI_CPU 2 7
DESIGN NOTE: REQ1# is AK19 PCI_AD4 Off Off Off Off 600 400 JTAGTDI 3 6
REQ0#_LAN AA29 AD4 PCI_AD5 JTAGTCK
D not used in this design. If 16 REQ0#_LAN REQ0# AD5 AH21 Off Off On Off 566 400 4 5
D
AB31 AJ21 PCI_AD6 Off On Off On 533 400
REQ1# is used a 10K REQ2#_IOC AB28 REQ1# AD6 PCI_AD7 4.7K
11 REQ2#_IOC REQ2# AD7 AL19 On Off Off Off 500 400
pullup needs to be added. AD8 AK22 PCI_AD8
AL22 PCI_AD9 On Off Off On 500 333
AD9 PCI_AD10 On On On On 433 333
AD10 AK23 DESIGN NOTE: Place
AJ22 AH22 PCI_AD11 VCC3
11,16 PCI_C/BE0# CBE0# AD11 PCI_AD12 JFS1
JTAG header on bottom
AL26 CBE1# AD12 AL23
11,16 PCI_C/BE1# PCI_AD13 side of board
AH27 CBE2# AD13 AL25 1 1 2 2
11,16 PCI_C/BE2# PCI_AD14 VCC3
11,16 PCI_C/BE3# AH31 CBE3# AD14 AH24 3 3 4 4 JTAGTCK 12
AJ24 PCI_AD15 5 6
AD15 5 6 JTAGTMS 12
AJ28 PCI_AD16 PW0 R18 10K 7 8 JTAGTDI
AD16 PCI_AD17 7 8
AD17 AK28 9 9 10 10 JTAGTDO 12
AL29 PCI_AD18 TDBGI_CPU 11 12
AD18 11 12 RST_WORK# 11
PCI_DEVSEL#AK25 PCI_AD19 R19 10K NL TDBGO_CPU
11,16 PCI_DEVSEL# DEVSEL# AD19 AJ30
PCI_AD20 SUSPA# R20 1.0K
Off 13 13 14 14

PCI_FRAME# AL28 AD20 AK29


AJ31 PCI_AD21
4 On H2x7 DESIGN NOTE: Add
11,16 PCI_FRAME# FRAME# AD21 PCI_AD22 R21 10K NL DGND DGND
AD22 AH30 Off "FS2" to the silkscreen.

PCI_IRDY#
AD23
AD24
AD25
AH29
AG29
AG28
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
3 GNT2#_IOC

GNT1#_PCI0
R22

R23
R24
1.0K

10K
1.0K NL
On
Off
JTAG HEADER
11,16 PCI_IRDY# PCI_TRDY#
AH25
AK26
IRDY# AD26 AF30
AE28 PCI_AD27
2 On
11,16 PCI_TRDY# TRDY# AD27 PCI_AD28 R25 10K NL
AD28 AF31
PCI_AD29 GNT0#_LAN R26 1.0K
Off
C
PCI_STOP# AJ25
AD29 AE30
AE31 PCI_AD30
1 On JDS1 C
11,16 PCI_STOP# STOP# AD30 PCI_AD31 H2X1 NL
11,12,15,16 PCI_RST# Y30 RESET# AMD GEODE™ AD31 AD29
VCC3 DGND
LX PROCESSOR
Debug VCC3
PCI_DEVSEL# R27 10K Stall

1
2
PCI_FRAME# R28 10K
PCI_TRDY# R29 10K DESIGN NOTE: Trace
PCI_IRDY# R30 10K DESIGN NOTE: Place
routing should be 1.0K
PCI_STOP# R31 10K R32 NL
JDS1 close to J2 and
optimized and 10K label and DEBUG STALL
REQ0#_LAN R33 10K
resistors condensed IRQ13 R34 10K in silk screen.
REQ2#_IOC R35 10K into a single RPACK.
DGND

U1D

PW0 AL18 PW0


13 SEL66_33# AJ17 PW1 PT28
W29 VCC3
CLPF COREPLLVDD R36 1.0
B
MLPF V29 B

VLPF AA3
AB1 C38 C39 C40
13 CLK_48_CPU DOTREF
Y31 0.01uF 0.01uF 10uF
13 CLK_CPU SYSREF C41 C42 C43 6.3V TS2
CAVDD W31 COREPLLVDD 220pF 220pF 220pF 2 1
CAVSS W30
IRQ13 AB29 PT29 50Wx80L_mil
11 IRQ13 IRQ13 VCC3 DGND
AD28 V31 GLPLLVDD GLPLLVDD R37 1.0
11,16 PCI_INTA# INTA# MAVDD
MAVSS V30
C44 C45 C46
0.01uF 0.01uF 10uF
AE29 AA1 DOTPLLVDD 6.3V TS3
11 CIS CIS VAVDD
VAVSS AA2 2 1
SUSPA# AC31
11 SUSPA# SUSPA# PT30 50Wx80L_mil
AMD GEODE™ VCC3 DGND
DOTPLLVDD R38 1.0
AL17
LX PROCESSOR AB3 JTAGTDI
TDP TDI JTAGTMS C47 C48 C49
AK17 TDN TMS AA4
AC1 0.01uF 0.01uF 10uF
TDO TDO_CPU 12
AC2 JTAGTCK 6.3V TS4
TDBGI_CPU TCLK
AB2 TDBGI 2 1
A TDBGO_CPU AB4 A
TDBGO 50Wx80L_mil
DGND

ITEM DOCUMENTO
30-28700-0/1 EE30184C
Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.
PAGINA: 10 DE 26 LX PROCESSOR PCI/SYSTEM
5 4 3 2 1
5 4 3 2 1
VCORE

VCORE

AH17

AH15

AH28
AF28
W19
W18
W14
W13

W17
AK5
U31
U30
U29
U28
R28

D15

N19
N18

N14
N13

D17

D14
D22
C21

D10
V28
V19
V18
V14
V13

P19
P18

P14
P13

Y28

A21
U4

R3

R4
VCC3

A1
E1
B2

A3
T3
T1

T4

T2
C50 C51 C52 C53

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
10uF 10uF 10uF 10uF
D 6.3V 6.3V 6.3V 6.3V D
AL11 VDDIO30 VSS16 B14
AG31 VDDIO29 VSS17 A16
AA31 VDDIO28 VSS18 D18
AC29 U1E
VDDIO27 VSS19 AJ16
AD31 VDDIO26 VSS20 V17
AJ3 C54 C55 C56 C57 C58 C59
VDDIO25 VSS21 AK2 1uF 1uF 1uF 1uF 1uF 1uF
AD1 VDDIO24 VSS22 V16
AC3 VDDIO23 VSS23 V15
AJ6 VDDIO22 VSS24 R15
AJ9 VDDIO21 R14
VSS25 R13
AJ12 VDDIO20 VSS26
AG1 VDDIO19 VSS27 P28
AF29 C60 C61 C62 C63 C64 C65 C66 C67
VDDIO18 VSS28 L2 0.01uF 0.01uF 0.01uF 0.01uF 1000pF 1000pF 1000pF 1000pF
AJ14 VDDIO17 VSS29 N16
AJ18 VDDIO15 VSS30 A31
AJ20 VDDIO14 VSS31 A27
AJ23 VDDIO13 VSS32 N15
AJ26 VDDIO12 VSS33 D16
Y3 VCC3
VDDIO11 VSS34 D7
AK1 VDDIO10 VSS35 N17
AJ29 VDDIO9 VSS36 N28
AF3 VDDIO8 VSS37 P15
AK31 VDDIO7 VSS38 P16
AL2 C68 C69 C70 C71 C72 C73
C VDDIO6 VSS39 P17 10uF 10uF 1uF 1uF 1uF 1uF
C
AL8 VDDIO5 VSS40 H2
AL24 6.3V 6.3V
VDDIO4 VSS41 A11
AL21 VDDIO3 VSS42 R16
VCCMEM
AL5 VSS43 R17

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


VDDIO2
AL27 VDDIO2 VSS44 R18
AL30 VDDIO1 VSS45 AH12
VSS46 Y29 C74 C75 C76 C77
D4 VMEM33 VSS47 AA30
C7 0.01uF 0.01uF 0.01uF 0.01uF
VMEM32 AMD GEODE™ VSS48 AD30
N4 VMEM31 VSS49 AG2
B11 VMEM30 LX PROCESSOR VSS50 AH9
H1 VMEM29 VSS51 AH4
L1 VMEM28 VSS52 AH6
B8 VMEM27 VSS53 AG30
A14 VCCMEM
VMEM26 VSS54 R19
B31 VMEM25 VSS55 AH20
C29 VMEM24 VSS56 C2
P29 VMEM23 VSS57 C4
B5 VMEM22 VSS58 A8
C14 C78 C79 C80 C81 C82 C83 C84 C85
VMEM21 VSS59 W16 10uF 10uF 1uF 1uF 1uF 1uF 1uF 1uF
K3 VMEM20 VSS60 W15
C18 6.3V 6.3V
VMEM19 VSS61 D25
A18 VMEM18 VSS62 B18
B B24 VMEM17 VSS63 AH14 B
C25 VMEM16 VSS64 A24
B27 VMEM15 VSS65 A29
D28 VMEM14 VSS66 B29
E30 C86 C87 C88 C89 C90 C91
VMEM13 VSS67 B30 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
G29 VMEM12 VSS68 C28
B21 VMEM11 VSS69 C30
H31 VMEM10 VSS70 C31
K29 VMEM9 VSS71 D29
L31 VMEM8 VSS72 E31
A30 VMEM7 VSS73 G28
N29 DGND
VMEM6 VSS74 K28
C3 VMEM5 VSS75 P31
A2 VMEM4 VSS76 W28
B1 VMEM3 VSS77 AC28
E2 VMEM2 VSS78 D3
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

G3 VSS79 A5
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80

VMEM1
AK8
AK18
AK16
AK14
AK11
AK21
AK24
AK27
AK30
AL1
AL16
AL31
R2
P4
C1
B3
AH16
AH18
AF4
AH26
AH23
C12
U19
U18
U17
U16
U15
U14
U13
T31
T30
K4
N3
T29
T28
T19
T18
T17
T16
T15
T14
L30
T13
H30
Y4
R1
AD2
AC4
G4

A A

ITEM DOCUMENTO
DGND
30-28700-0/1 EE30184C

PAGINA: 11 DE 26 LX PROCESSOR POWER


5 4 3 2 1
5 4 3 2 1

VCC3
VCC3
U4A
9,16 PCI_AD[31:0] R289 VCC3SB PME# R39 4.7K
PCI_CLK U4 CLK_IOC 13
PCI_AD0 R17 100
PCI_AD1 AD0 RST_WORK# WORK_AUX R40 10K PT32
T17 AD1 WORKING C5
PCI_AD2 R16 RST_STB# R41 4.7K
PCI_AD3 AD2 PWRBTN# TEST_MODE R42 1.0K
T16 AD3 GPIO28/PWR_BUT# A8 PWRBTN# 18
PCI_AD4 P16 D3 RN34 1K
PCI_AD5 AD4 GPIO5/MFGPT1_RS/MFGPT0_C1 PWRBTN# FUNC_TEST R43 1.0K
T15 AD5 1 8
PCI_AD6 R15 D2 MFGPT2_C1 RST_WORK# 2 7
D PCI_AD7 AD6 GPIO6/MFGPT0_RS/MFGPT1_C1/MFGPT2_C2 FLSH_FPGA_CLK SLP_CLK# D
P15 AD7 GPIO7/MFGPT2_C1/SLEEP_X C2 3 6
PCI_AD8 FLSH_FPGA_nCS PCI_INTA# DGND
T14 AD8 4 5
PCI_AD9 R14 E3
AD9 GPIO8/UART1_TX/UART1_IR_TX 5536_UART_TX 12
PCI_AD10 U13 D1 PT31 DESIGN NOTE:
AD10 GPIO9/UART1_RX/UART1_IR_RX 5536_UART_RX 12
PCI_AD11 T13
PCI_AD12 AD11 Place TP31 on the
R13 AD12 GPIO10/THRM_ALRM# C3
PCI_AD13 U12 A1 bottom side of VCC3
AD13 GPIO11/SLP_CLK_EN#/MFGPT1_C2 SLP_CLK# 13
PCI_AD14 T12 AD14
board clear of all SST LPC ROM: 49LF020A(2Mb)/040B(4Mb)/080A(8Mb)/160C(16Mb)
PCI_AD15 R12 C9 WORK_AUX obstructions.
PCI_AD16 AD15 GPIO24/WORK_AUX
U8 AD16 GPIO25/LOW_BAT#/MFGPT7_C2 A9 WINBOND LPC:W49V002A(2Mb)/004C(4Mb)/008A(8Mb)
PCI_AD17 T8
PCI_AD18 AD17 PME# C92
R8 AD18 GPIO26/MFGPT7_RS B7 PME# 12,16
PCI_AD19 U7 C8 DGND 1uF
AD19 GPIO27/MFGPT7_C1/32KHZ FLSH_FPGA_SDI
PCI_AD20 T7
PCI_AD21 AD20

32
25
R7 AD21 GPIO13/SLEEP_BUT F2
PCI_AD22 FLSH_FPGA_SDO DGND
PCI_AD23
U6 AD22 GPIO12/AC_S_IN2/SLEEP_Y J3 FLASH_DET 17 U5
T6 AD23
PCI_AD24 U5 A5 31 CLK
AD24 RESET_OUT# PCI_RST# 9,12,15,16 13 CLK_LPC_FWH
PCI_AD25 RST_STB# VCC3

VDD1
VDD2
T5 AD25 RESET_STAND# B8 MODE 29
PCI_AD26 R5 C6 PCI_RST# 2 RST# TBL# 8
AD26 RESET_WORK# RST_WORK# 9
PCI_AD27 T4 WP# 7
PCI_AD28 AD27
R4 AD28 SUSP#/CIS P3 12 LFRAME# 23 LFRAME# INIT# 24
PCI_AD29 CIS 9
U3 AD29 SUSPA# N1 SUSPA# 9 VPP 1
PCI_AD30 T3 17 LAD3
C AD30 12 LAD3 C
PCI_AD31 U1 15 LAD2 ID0 12
AD31 12 LAD2
12 LAD1 14 LAD1 ID1 11
U10 PAR IRQ13 K2 IRQ13 9 12 LAD0 13 LAD0 ID2 10
9,16 PCI_PAR
ID3 9
U14 C1 6 FGPI0 R44
9,16 PCI_C/BE0# C/BE0# MHZ14_CLK CLK_14_IOC 13
U11 A4 RTCXIN 5 FGPI1 4.7K
9,16 PCI_C/BE1# C/BE1# KHZ32_XCI RTCXOUT
T9 C/BE2# KHZ32_XCO B3 4 FGPI2
9,16 PCI_C/BE2#
R6 C/BE3# 3 FGPI3 RFU0 21
9,16 PCI_C/BE3#
30 FGPI4 RFU1 20
9,16 PCI_FRAME# U9 FRAME# USB_PTEST G15 RFU2 19
R10 IRDY# 26 NC RFU3 18
9,16 PCI_IRDY# DGND
R11 DEVSEL# 27 NC NC 22
9,16 PCI_DEVSEL#
T10 28

VSS2
NC
9,16 PCI_TRDY# PCI_INTA# TRDY# DGND
R2 GPIO0
9,16 PCI_INTA# AMD GEODE™ TEST_MODE
9,16 PCI_STOP# T11 STOP# TEST_MODE A6
B9 32PIN BIOS

16
LVD_TEST
9 GNT2#_IOC R1
T1
GNT# COMPANION F3 FUNC_TEST
9 REQ2#_IOC REQ# FUNC_TEST
DEVICE
DGND
CS5536
VCC5VSB PT33
B VCC5VSB B

DESIGN NOTE: GPIO24/WORK_AUX is an


SAVE TO RAM SUPPORT

1
C93
open drain output, which requires a pullup R45
resistor to achieve a high state. At initial 0.1uF 10K

2
PWR MANAGEMENT standby power application the

2
RTCXIN
GPIO24/WORK_AUX pin defaults to GPIO24 DGND INVERTER
PWRONX 23
GREEN

5
and the GPIO24 defaults as an input. This U6

1
RTCXOUT WORK_AUX 1 Q1 C94
VCC3
default combination will leave the pin in a R46 4.7K SI2308DS
4
PT36 R47 high state due to the pullup which is RST_WORK# 2 0.1uF

2
1M normally connected to VCC3SB. This circuit
R48 C95
works aournd that behaviour so that Save to

3
330 NC7SZ08/SC70 10uF
PT35 RAM will function correctly. 6.3V
C96 1pF PT34 DGND DGND

R49 22M 10% DGND


A

2 1
LD1
C97 C98 17-21SCR/TR8
A 22pF Y1 18pF A
32.768KHz
DGND DGND
K

MFGPT2_C1
ITEM DOCUMENTO
30-28700-0/1 EE30184C
Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.
PAGINA: 12 DE 26 CC5536/SYSTEM/PM/ROM
5 4 3 2 1
5 4 3 2 1

13 CLK_IDE
17 IDE_D[15:0]
VCC3
4 5 I_A0 RN36 10K
17 IDE_A0 I_A2 LAD0
17 IDE_A2 3 6 U4B 1 8
2 7 I_CS0# LAD1 2 7
17 IDE_CS0# I_CS1# LAD2
1 8 3 6
17 IDE_CS1# I_IRQ LAD3
B12 GPIO2/IDE_IRQ0 4 5
RN35 22 I_RST# F15
I_RDY IDE_RESET# RN38 10K
17 IDE_RDY 4 5 A10 MHZ66_CLK
3 6 I_A1 1 8
D 17 IDE_A1 D
2 7 I_IRQ I_A0 A11 LDRQ# 2 7
17 IDE_IRQ IDE_AD0/FLASH_AD25/AD0/FLASH_CLE
1 8 I_ACK# I_A1 A12 SERIRQ 3 6
17 IDE_ACK# I_A2 IDE_AD1/FLASH_AD26/AD1 LFRAME#
B11 IDE_AD2/FLASH_AD27/AD2 4 5
RN37 22 I_ACK# C12
I_DRQ# I_DRQ# IDE_DACK0#/FLASH_CS3#/FLASH_CE3# XCEN R50 1.0K
17 IDE_DRQ# 4 5 A14
IDE_D0 I_D0 I_IOR# IDE_DREQ0/FLASH_CS2#/FLASH_CE2# R51
3 6 B13 IDE_IOR0#/FLASH_RE#
17 IDE_IOR# 2 7 I_IOR# I_IOW# C13 1.0K NL
17 IDE_IOW# I_IOW# I_RDY IDE_IOW0#/FLASH_WE#
1 8 A13 IDE_RDY0/FLASH_IOCHRDY/FLASH_RDY/BUSY#
I_CS0# B10 TDBGI_IOC R52 4.7k DGND
RN39 22 I_CS1# IDE_CS0#/FLASH_CS0#/FLASH_CE0# IDE_RDY R53 10K
C10 IDE_CS1#/FLASH_CS1#/FLASH_CE1# IDE_IRQ R54 10K
RN40 22
H1 USB_OC# R55 10K
LPC_CLK CLK_LPC_IOC 13
IDE_D1 4 5 I_D1 I_D0 B14 H2 LAD0
IDE_DATA0/FLASH_AD10/IO0 LPC_AD0/GPIO16 LAD0 11
IDE_D14 3 6 I_D14 I_D1 A15 J2 LAD1 IDE_D7 R56 10K
IDE_DATA1/FLASH_AD11/IO1 LPC_AD1/GPIO17 LAD1 11
IDE_D2 2 7 I_D2 I_D2 C15 J1 LAD2 IDE_DRQ# R57 10K
IDE_DATA2/FLASH_AD12/IO2 LPC_AD2/GPIO18 LAD2 11
IDE_D15 1 8 I_D15 I_D3 C16 K1 LAD3 LVD_EN# R58 10K
IDE_DATA3/FLASH_AD13/IO3 LPC_AD3/GPIO19 LAD3 11
I_D4 B17 G1 LDRQ#
IDE_DATA4/FLASH_AD14/IO4 LPC_DRQ#/GPIO20 LDRQ# 11
RN41 22 I_D5 D15 H3 LFRAME#
IDE_DATA5/FLASH_AD15/IO5 LPC_FRAME#/GPIO22 LFRAME# 11
IDE_D11 1 8 I_D11 I_D6 E15 G2 SERIRQ DGND
IDE_DATA6/FLASH_AD16/IO6 LPC_SERIRQ/GPIO21/MFGPT2_RS SERIRQ 11
IDE_D5 2 7 I_D5 I_D7 E16 DESIGN NOTE: Trace
IDE_D10 I_D10 I_D8 IDE_DATA7/FLASH_AD17/IO7
3 6 E17
IDE_D6 4 5 I_D6 I_D[15:0] I_D9 D17
IDE_DATA8/FLASH_AD18/AD3 routing should be
I_D10 IDE_DATA9/FLASH_AD19/AD4
D16 IDE_DATA10/FLASH_AD20/AD5 optimized and 10K
RN42 22 I_D11 C17 G3
C IDE_DATA11/FLASH_AD21/AD6 GPIO14/SMB_CLK SMB_SCL 7 resistors condensed C
IDE_D9 1 8 I_D9 I_D12 A17 F1
IDE_DATA12/FLASH_AD22/AD7 GPIO15/SMB_DATA SMB_SDA 7
IDE_D7 2 7 I_D7 I_D13 B16 into one or more
IDE_D8 I_D8 I_D14 IDE_DATA13/FLASH_AD23/AD8
3 6 B15
4 5 I_RST# I_D15 C14
IDE_DATA14/FLASH_AD24/AD9
E1 RPACKs.
17 IDE_RST# IDE_DATA15/FLASH_ALE GPIO3/UART2_RX CRT_SCL 8
GPIO4/UART2_TX E2 CRT_SDA 8
RN43 22
IDE_D12 1 8 I_D12 K3
IDE_D13 I_D13 GPIO1/AC_BEEP/MFGPT0_C2
2 7
IDE_D4 3 6 I_D4 BITCLK M1 N2
AC_CLK TCK JTAGTCK 9
IDE_D3 4 5 I_D3 P1
TDI TDO_CPU 9
SYNC_BOS0 L3 P2
AC_S_SYNC/BOS0 TDO JTAGTDO 9
SDATA_IN L1 N3
AC_S_IN TMS JTAGTMS 9
SDATA_OUT_BOS1 L2 M2 TDBGI_IOC
AC_S_OUT/BOS1 T_DEBUG_IN
PCBEEP T_DEBUG_OUT M3

R59 CLK_48_DOT N17


DESIGN NOTE: This header may be used to
9 CLK_48_CPU MHZ48_CLK
LVD_EN# C7 LVD_EN# implement an SIO companion board or support
22/R0402 P17
N16
USB_PWR_EN1 debugging. Any attached device must limit its
USB_PWR_EN2
14 USB_OC#
USB_OC# N15 USB_OC_SENS#
VCC3 current to levels supported by the power supply.
K16 K15 USB_REXT
14 USB0+ USB1_DATPOS USB_REXT
K17 M15 CN21
14 USB0- USB1_DATNEG USB_VBUS
B 14 USB1+ L16 USB2_DATPOS B
L17 J15 XTALO_48 1 2
14 USB1- USB2_DATNEG MHZ48_XCO 13 CLK_LPC_SIO PCI_RST# 9,11,15,16
H17 H15 XTALI_48 3 4
14 USB2+
H16
USB3_DATPOS AMD GEODE™ MHZ48_XCI
F17 XCEN R60
13 CLK_LPC_48
5 6 LAD0 PME# 11,16
14 USB2- USB3_DATNEG MHZ48_XCEN
G17 3.40K 7 8 LAD1
14 USB3+ USB4_DATPOS
G16 COMPANION 1% 9 10 LAD2
14 USB3- USB4_DATNEG
11 12 LAD3
DEVICE 13 14 LDRQ# VCC5
11 5536_UART_TX
15 16 LFRAME#
11 5536_UART_RX
DGND 17 18
VCC3 19 20 SERIRQ
CS5536 PT38
R61 C99
22/R0402 CON20A 1uF
BITCLK XTALO_48 C100
AC97_BITCLK 15
SDATA_OUT_BOS1 R62 22/R0402 XTALI_48 1uF
SDATA_IN R63 22/R0402 AC97_DATA_OUT 15 PT37 DGND
AC97_DATA_IN 15
SYNC_BOS0 R64 22/R0402 Y2
AC97_SYNC 15 DGND
DESIGN NOTE: Place series R 1 2
DESIGN NOTE: Place DGND
near the audio CODEC. 48.0000MHz
series R near the IOC. C101 C102
DESIGN NOTE: IOC is configured 18pF 18pF

A to support LPC ROM. See A


R65 1.0K CS5536 databook (PID 33238) to DGND DGND

determine support for other


R66 1.0K configurations. ITEM DOCUMENTO
30-28700-0/1 EE30184C
DGND
Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 13 DE 26 CS5536 IDE/USB/AC97/LPC
5 4 3 2 1
5 4 3 2 1

PT39 R67
49.9
U4C
1 2

1B
1A
VCORESB VCORE R68 4.7 L15
BT1 NC21
A3 VBAT NC12 R9
NC11 U17

+
VCC3SB U16
NC10
A7 VCORE_VSB NC1 F16
J16 VCC3
NC2
B6 VIO_VSB NC3 M16
D D
NC6 U15
NC7 C11
C103 C104 C105 C106 C107 A16
10uF 0.01uF 0.01uF 1uF 0.01uF NC8 C108 C109
K14 VDDC_USB1 NC9 R3
VBH2032-1 6.3V H14 M17 10uF 10uF

2
VDDC_USB0 NC13 6.3V 6.3V
NC14 J17
D10 VCORE1 NC15 B5
D8 VCORE2 NC16 B4
DGND DGND H4 B1
VCORE VCORE3 NC17
K4 VCORE4 NC18 T2
P8 VCORE5 NC19 U2
P10 A2 C110 C111 C112 C113
VCORE6 NC20 1uF 1uF 1uF 1uF
NC4 C4
VCC3 VIOUSB B2
NC5
1 FERR 2 P14 VDDIO_USB0 VSSIO_USB0 L14
M14 VDDIO_USB1 VSSIO_USB1 J14
F14 VDDIO_USB2 VSSIO_USB2 G14
FB6 C114 C115 C116 C117 D14
FB/120/0.2A/0603 10uF 1000pF 1000pF 1000pF VDDIO_USB3 C118 C119 C120 C121
VSS N14
6.3V E14 0.01uF 0.01uF 0.01uF 0.01uF
VSS
VSS D13
VSS D11
VCC3 D7
C AMD GEODE™ VSS
D5
C

DGND VSS
D12 VIO VSS E4
D9 VIO COMPANION VSS G4
VCORE
D6 VIO VSS J4
D4 DEVICE L4
VIO VSS
F4 VIO VSS N4
M4 VIO VSS P5
P4 VIO VSS P7
P6 P11 C122 C123 C124 C125
VIO VSS 10uF 1uF 1uF 1uF
P9 VIO VSS P13
P12 6.3V
VIO

CS5536
DGND
VCC3

C126 C127 C128 C129


DESIGN NOTE: 0.01uF 0.01uF 0.01uF 0.01uF
Enables spread
C130 C131 C132 C133 spectrum. EMI PT42
12
19
25
28
4
8

10uF 0.01uF 0.01uF 0.01uF U7 mitigation technique


B 6.3V B
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6

14_CODEC_CLK R69 10K DGND

26 14_ISA_IOC_CLK
DGND REFCLK1 14_CODEC_CLK PT43 PT44 PT45 PT46 DGND
11 SLP_CLK# 17 PD# REFCLK0/SP# 27
RN44
48MHz 13
14 CLK_48_5536 14_CODEC_CLK 1 8
48MHz/TS# LPC_SIO_CLK CLK_14_CODEC 15
2 7
LPC_FWH_CLK CLK_LPC_SIO 12
3 6
IDE_CLK LPC_IOC_CLK CLK_LPC_FWH 11
9 SEL66_33# 10 SEL66/33# 66MHz 16 4 5
CLK_LPC_IOC 12
R70 10K PT47 PT48 PT49 PT50
LPC_IOC_CLK 22
LCLK2 9 RN45
5% 6 LPC_FWH_CLK
DGND LCLK1 LPC_SIO_CLK CPU_CLK
LCLK0 5 1 8
IOC_CLK CLK_CPU 9
2 7 CLK_IOC 11
LAN_CLK 3 6
CLKX1 CPU_CLK 14_ISA_IOC_CLK CLK_LAN 16
2 XTALIN PCICLK0 18 4 5
CLK_14_IOC 11
PCICLK1 20
Y3 23 IOC_CLK
CLKX2 PCICLK2 LAN_CLK 22 PT51 PT52
1 2 3 XTALOUT PCICLK3 24

PT40 14.31818MHz PT41 R71 22/R0402


GND6
GND5
GND4
GND3
GND2
GND1

A IDE_CLK A
CLK_IDE 12
R72 22/R0402 NL
MK1491-09F CLK_48_5536
CLK_LPC_48 12
1
7
11
15
21
22

C134
18pF
C135
18pF
ITEM DOCUMENTO
30-28700-0/1 EE30184C
DGND DGND

DGND Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 14 DE 26 CS5536 PWR & CLOCK GEN
5 4 3 2 1
5 4 3 2 1

D D

VCC5 VCC5
DESIGN NOTE: Some USB/PS2
Keyboard and Mouse devices
may not be detected correctly
without using a USB power
1

1
F1 switch. See FAQ225 for more D9
F2
1.10A, 8V 1.10A, 8V
details. FUSE2
2

2
12 USB_OC#
FB7 FB8
FUSE2 2 FERR 1 2 FERR 1

FB/330/1.5A FB/330/1.5A
1

1
+ C136 C137 BAT54A/SOT + C138 C139
C 100UF 10V 22uF 100UF 10V 22uF C
10V 10V CN13
2

2
HEADER 5X2
JUSB1
Common-Mode Choke Common-Mode Choke 1
1 2
2 FOR USE OF SSD
3 4
3 4 FLASH MODULE,
2

3
1 VCC-1 5 6
L4 L5 5 6 SEE LAYOUT
12 USB2- 2 DNEG-1
12 USB0- 7 8
7 8
3 DPOS-1 9
9 10
10 RECOMMENDATIONS
12 USB2+ 4 GND-1
12 USB0+
5 VCC-2 1 2
1

4
1 2
6 DNEG-2 3 4
3 4
7 DPOS-2 5 6
5 6
8 GND-2 7 8
2

3
7 8
9 10
9 10
1

1
L6 9 MH L7
12 USB3- D10 D11 D12 D13 12 USB1- D14 D15 D16 D17
FB9 10 MH FB10 CN14
FERR

FERR
11 MH HEADER 5X2
12 USB3+ 12 USB1+
12 MH
FB/330/1.5A FB/330/1.5A
1

2
USBAFDRD-SQBL5N0/DIP-8P
Common-Mode Choke Common-Mode Choke
PGB0010603 PGB0010603 PGB0010603 PGB0010603
PGB0010603 PGB0010603 PGB0010603 PGB0010603
LittleFuse: PGB Series LittleFuse: PGB Series

DESIGN NOTE: Place these DESIGN NOTE: Place these


components near the DGND CHASSIS components near the DGND

connectors. connectors.
C140 220pF
C141 220pF

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


B B
FB12
FB11 1 FERR 2
1 FERR 2
FB/120/0.2A/0603
FB/120/0.2A/0603 DGND CHASSIS
DGND CHASSIS

A A

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 15 DE 26 USB CONNECTORS

5 4 3 2 1
5 4 3 2 1

PT53
D D

VCC3
R73 4.7 VCC_AUD

DESIGN NOTE: Use 4.7 ohm resistor C142 C143 C144 1000pF R74
on ALC203 to insure that DVDD 0.01uF 10uF 0
powers up before AVDD due to device 6.3V
C145 1000pF
errata. GND_AUD
C146
1uF GND_AUD

25

26

27

28

29

30

31

32

33

34

35

36
U8

AVDD1

AVSS1

AFILT1

AFILT2

NC1

DCVOL

VREFOUT2

LINE-OUT-L

LINE-OUT-R
VREF

VREFOUT

VAUX
MICROPHONE IN
FRONT PANEL R75 24 37
4.7K LINE-IN-R MONO-O
23
LINE-IN-L AVDD2
38 HEADPHONE OUT
CN15 22 39 C147 1 100UF
2 10V FB14 FB/120/0.2A/0603 FRONT PANEL

+
FB13 MIC2 HP-OUT-L
1 1 FERR 2
AMP 4V 1 R76 1.0K C148 1uF
2 1 FERR 2 21 40 CN16
2 MIC1 NC2 VCC5V FB74 VCCAUD
3 1
3 FB/120/0.2A/0603 1 AMP 4V FB/120/0.2A/0603
4 20 41 1 2 1 2 2

+
4 CD-R HP-OUT-R FERR 2
3
C150 3
19 42 4 1 2

C
GND_AUD 220pF
18
CD-GND

CD-L
REALTEK AVSS2

GPIO0
43
C149
100UF 10V
FB15
FB/120/0.2A/0603
4 FERR

C
GND_AUD
17
JD1
ALC203-LF GPIO1
44 GND_AUD C323
0.01uF
C324
10uF
GND_AUD 16 45 6.3V
JD2 ID0#/JD0
15 46
AUX-R XTLSEL GND_AUD GND_AUD
DESIGN NOTE: ALC203 E version and later 14
AUX-L SPDIFI/EAPD
47

version will not support secondary mode due to

SDATA-OUT
13 48
PHONE SPDIFO
SDATA-IN

pin-45 is re-defined as Jack-Detect pin 0 (JD0)


PC-BEEP

XTL-OUT
RESET#

BIT-CLK DGND
DVDD2

DVDD1
DVSS2

DVSS1

XTL-IN
for auto MIC jack sensing.
SYNC

VCCAUD
12

11

10

1
VCC3 ALC203-LF R255 U57
0 NL AD5290-10K NL
AC97_PCBEEP 2 9
CPLD_BEEP B VDD
10 5 nCSB_SEL_2
W CS
1 6 SSPB_SCLK1
A CLK
7 SSPB_TXD
SDI
8
C151 C152 SDO
4
10uF 0.01uF TS5 R256 DGND VCCAUD C328
3
6.3V VSS 1000pF
2 1 0

50Wx80L_mil
DGND DGND GND_AUD GND_AUD GND_AUD DGND R257
DGND 100K
9,11,12,16 PCI_RST#
12 AC97_SYNC DGND DGND

6
12 AC97_DATA_IN U55
12 AC97_DATA_OUT
1 2 4 5

+
12 AC97_BITCLK
2
3 8
C153 C325 R258

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


B B
220pF 100UF 10V 10K C326 LM4861

7
1
0.1uF
FB75
FB/120/0.2A/0603
13 CLK_14_CODEC
DGND CN17
1 FERR 2 1
VCC5V GND_AUD 1 AMP 4V
2
R259 2
3
10K 3
1 FERR 2 4
4

FB76
FB/120/0.2A/0603

ENB_AUDIO
Q12
R260 BC817-40
1.0K

Buzzer VCC3 VCC3 GND_AUD


1

R283
2

10K
R284 BUZ1
NC1
+
2

Q16 10K DET801H


12 PCBEEP
NC2

SI2308DS
1

-
2

R285
22
R282 DGND
10K
A 2 1 AC97_PCBEEP A
1

C330
R286 C329
0.1uF NL 1.0K NL 0.1uF
2

DGND
ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 16 DE 26 AUDIO CODEC

5 4 3 2 1
5 4 3 2 1

PT54

XTAL1

PT55 LANLED_ACTIVE
Y4
1 2 XTAL2
R77
25.0000MHz 330
VCC3
C154 C155 LANLED_LINK
D 22pF 22pF U9 D

1 CS VCC 8

2
VCC3 R78 2 7
DGND DGND 330 SK NC C156
3 DI ORG 6
4 5 0.1uF

1
DO GND
2

2
VCC3 AT93C46A
C157 C158 C159 C160 C161 <Mfr_Part_Number>
10uF 0.1uF 0.1uF 0.1uF 0.1uF PCI_AD[31:0] DGND
1

6.3V 1

PCI_AD0
PCI_AD1
R79 5.60K 1%

DGND
VCC3

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
DGND U10 VCORE_ENET
FB16
1 2

EEDI
EESK

EECS
LWAKE
RSET
VSS17

NC27
NC26
VSS16
VSS15
XTAL2
XTAL1
NC25
VSS14
NC24
LED0
NC23
LED1
LED2
NC22
NC21

NC20

EEDO
VDD33_7

AD0
AD1
FERR
JLAN1 LAN CONNECTOR
2

FB/120/0.2A/0603
C162 C163 ENET_TX+ 1 102 PCI_AD2
0.1uF 0.1uF ENET_TX- TX+ AD2 ENET_TX+ RJ-1
2 101 1
1

TX- VSS13 TX+


3 AVDD33_1 VSS12 100
C 4 VSS1 VDD25_4 99 2 TXC C
DGND DGND ENET_RX+ 5 98 PCI_AD3
Q2 ENET_RX- RX+ AD3 PCI_AD4 ENET_TX- RJ-2
6 RX- AD4 97 3 TX-
3

2SB1188 7 96 PCI_AD5 R80 R81 R83 R82


AVDD33_2 AD5 PCI_AD6 49.9 49.9 49.9 49.9 ENET_RX+ RJ-3
1 8 CTRL25 AD6 95 4 RD+
9 94 1% 1% 1% 1%
PT56 NC1 VDD33_6 PCI_AD7
10 93 5
2

FB17 NC2 AD7 RDC


11 NC3 CBE0B 92 PCI_C/BE0# 9,11
VCORE_ENET 1 2 12 91 ENET_RX- 6 RJ-6
FERR AVDD25 VSS11 RD-
13 90 PCI_AD8
NC4 AD8
2

FB/120/0.2A/0603 14 89 PCI_AD9 75 OHM (x4)


C164 C165 C166 C167 NC5 AD9 C168 C169 C170 RJ-4
15 NC6 NC19 88 8 CGND
10uF 0.1uF 0.1uF 0.1uF 16 87 PCI_AD10 0.1uF 0.1uF 0.1uF RJ-5
1

6.3V NC7 AD10 PCI_AD11 1000PF/2KV RJ-7


17 VSS2 AD11 86
18 85 PCI_AD12 CHASSIS RJ-8
DGND NC8 RTL8100C AD12
19 NC9 VDD33_5 84 12 LED1+ NC 7
DGND 20 83 PCI_AD13 DGND VCC3 VCC3 GREEN
VCC3 AVDD33_3 AD13 PCI_AD14
21 VSS3 AD14 82 11 LED1- MH1 15
22 NC10 VSS10 81 MH2 16
R84 10K 23 80 10
ISOLATEB VSS9 PCI_AD15 LED2+ YELLOW
24 NC11 AD15 79 SH1 13
25 78 R85 R86 R87 9 14
9,11 PCI_INTA# INTAB VDD25_3 LED2- SH2
26 77 10K 10K 10K
VDD33_1 CBE1B PCI_C/BE1# 9,11
9,11,12,15 PCI_RST# 27 RSTB PAR 76 PCI_PAR 9,11 RJ-45-LED-MAG_0
B 28 75 LANLED_ACTIVE B
13 CLK_LAN CLK SERRB CHASSIS
9 GNT0#_LAN
9 REQ0#_LAN
29
30
GNTB
REQB
NC18
NC17
74
73 LANLED_LINK PINS 15 & 16
31 72
11,12 PME#
32
PMEB
VDD25_1
NC16
VDD33_4 71 ARE PLASTIC
PCI_AD31 33 70
PCI_AD30 AD31 PERRB
34 AD30 STOPB 69 PCI_STOP# 9,11
35 68 DESIGN NOTE: Place C171 2 1 0.1uF
VSS4 DEVSELB PCI_DEVSEL# 9,11
PCI_AD29 36 67
AD29 TRDYB PCI_TRDY# 9,11 capacitors under
PCI_AD28 37 66
AD28 VSS8 C172 2
38 65 connector 1 0.1uF
VDD33_2

VDD25_2

VDD33_3

VSS5 CLKRUNB
FRAMEB
CBE3B

CBE2B

9,11 PCI_AD[31:0]
IRDYB
IDSEL
NC12

NC13

VSS6
VSS7

NC14

NC15
AD27
AD26

AD25
AD24

AD23

AD22
AD21

AD20

AD19

AD18
AD17
AD16

DGND CHASSIS

<Mfr_Part_Number>
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PCI_AD27
PCI_AD26

PCI_AD25
PCI_AD24

PCI_AD23

PCI_AD22
PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18
PCI_AD17
PCI_AD16

PCI_IRDY# 9,11
PCI_FRAME# 9,11
DGND
A
PCI_C/BE2# 9,11 A

9,11 PCI_C/BE3#
R88 0 PCI_AD23 ITEM DOCUMENTO
30-28700-0/1 EE30184C

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 17 DE 26 ETHERNET CONTROLLER
5 4 3 2 1
5 4 3 2 1

12 IDE_D[15:0]
IDE CONNECTOR JHDD2
12 IDE_RST#
CF Connector AMP 788643-1
JHDD1
CARTUCHO INTERNO
1 2
IDE_D7 RST GND8 IDE_D8
3 4 1 26
IDE_D6 D7 D8 IDE_D9 IDE_D3 1 26 IDE_D11
5 6 2 27
IDE_D5 D6 D9 IDE_D10 IDE_D4 2 27 IDE_D12
7 8 3 28
IDE_D4 D5 D10 IDE_D11 IDE_D5 3 28 IDE_D13
9 10 4 29
IDE_D3 D4 D11 IDE_D12 VCC3 DGND IDE_D6 4 29 IDE_D14
11 12 5 30
D
IDE_D2 D3 D12 IDE_D13 IDE_D7 5 30 IDE_D15 D
13 14 6 31
IDE_D1 D2 D13 IDE_D14 6 31
15 16 12 IDE_CS0# 7 32 IDE_CS1# 12
IDE_D0 D1 D14 IDE_D15 7 32
17 18 8 33
D0 D15 C174 8 33
19 20 9 34
GND1 NC4 R89 0 NL C173 0.1uF 9 34 IDE_IOR# 12
21 22 10 35
12 IDE_DRQ# DRQ GND7 VCC5 1uF 10 35 WE1 IDE_IOW# 12
12 IDE_IOW# 23 24 11 36
IOW GND6 11 36 VCC5
12 IDE_IOR# 25 26 12 37 JDS2
IOR GND5 R90 470 12 37 IDE_IRQ 12
27 28 13 38
12 IDE_RDY
12 IDE_ACK# 29
NC1 ALE
30 14
13 38
39 CSEL1 1 CLOSED = FLASHCARD IDE SLAVE
DACK GND4 14 39
31 32 15 40 2
12 IDE_IRQ
12 IDE_A1 33
IRQ IOCS16
34 FLASH_DET 11 16
15 40
41 OPEN = FLASHCARD IDE MASTER
A1 NC3 16 41 IDE_RST# 12
12 IDE_A0 35 36 IDE_A2 12 17 42
A0 A2 17 42 IDE_RDY 12 H2X1
12 IDE_CS0# 37 38 IDE_CS1# 12 12 IDE_A2 18 43
CS0 CS1 R91 18 43 REG1 NL
39 40 12 IDE_A1 19 44
LED GND3 10K DGND 19 44
41 42 12 IDE_A0 20 45
VCC1 VCC2 IDE_D0 20 45
43 44 21 46 FLASH_DET 11
GND2 NC2 IDE_D1 21 46 IDE_D8
22 47
VCC5 H22X2/2mm IDE_D2 22 47 IDE_D9
23 48
23 48 IDE_D10
24 49
24 49
25 50
DGND 25 50
R92
C175 470
1uF
DGND

DGND R93 0 NL DGND


18 VDCIN
VCC5

1 8
2 7 REG1
3 6 WE1
4 5 CSEL1

C RN46 C
DGND 33

R94
4.7K
1 2

VCC5V

U11 TLV5626

2
1 8 C176
CTRSTDAT DIN VDD 0.1uF
2 7
CTRSTCLK SCLK OUTB
3 6

1
CTRSTCS CS REF
4 5
OUTA AGND
VCC5V VCC12V
VCC5V DGND

CONTROLE
2

1
VCC12V
R95 R96 R97 FB18 CN3
33K 33K 200K 2 FERR 1 1
DO U12A 2
1

8
FB/330/1.5A 2 AMP 6V
LM393 3
1 1

2
3
3 + FB19 4
4
INVERSOR R98 2 -
1 2 FERR

FB/330/1.5A
1 5
6
5
6
10K
1

2
FB20
4

JP2 R99 R100 2 1 C177 C178 C179


2

FERR
1 2 10K 10K 0.1uF 0.1uF 0.1uF

1
1 2 FB/330/1.5A
3 4
3 4

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


DGND FB21 CN4
2

2
B B
HEADER 2X2 2 FERR 1 1
DISPEN 1 AMP 4V
2
2

2
DGND DGND FB/330/1.5A 3
C180 3
4
0.1uF 4
FB22

1
2 FERR 1
VCC5V C181 1 2 0.1uF VCC12V VCC12V
R102 FB/330/1.5A
R101 680K 4.7K VCC5V
2

C182 JP3
1 2 0.1uF 1 2 1 2
1

1 2
1 2 3 4

1
R103 VCC12V R104 3 4
1

JP4
200K 10K R105 HEADER 2X2 R106 1 2
DGND 4.7K 1 2
3K92 3 4
3 4
2

1
VCC12V VCC12V D18 HEADER 2X2

2
8

DGND TL431 R107


14

14

5 U13A U13B 10K


+
7 1 5
6 3 4

2
-
VCC12V VCC12V 2 6
1

U12B
4

R108 LM393 4011 4011 DGND


7

7
2

200K C183 DGND


0.1uF DGND DGND
VCC12V
2

DGND
14

U13C
DGND DGND 8
10
9

VDD VCC12V 4011


7

DGND
VCC12V
DGND
14

A U13D A
12
11
13

4011
7

DGND
DGND

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 18 DE 26 IDE CONNEC_C0MPACT_FLSH


5 4 3 2 1
5 4 3 2 1

VCC5 17 VDCIN VCORE PT57


FB23 U15
1.25V@2A 3.30V
1 FERR 2 2 8 L8 2.2uH VCC3SB
VIN LX2 VCC5VSB PT60 PT61
120ohms, 3.5A , 0805 U14
LM317L
6 EN LX1 7
1 VIN VOUT 2
D C187 C186 R112 D
5 COMP FB 4 VOUT 3

1
+ 220uF 10uF R111 27K 5.62k + C184 5 6 C185
NC1 VOUT

ADJ
25V C189 3 1 1% C188 8 7 R109
AGND PGND 1uF NC2 VOUT 270 22uF
100UF 10V

2
1.5nF AOZ1010AI LM317L

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


2

12
DGND DGND R110 DGND
1.0K
R11410K 1%

2
DGND

1
DGND
R113
2K

2
DGND

C C

VCC3

2.60V@1A
U16
1

6
VCC3SB
PT58 +2.5VDDR VCCMEM
VIN1

VIN2

1
VOUT 5
C190 3 DESIGN NOTE: Replace R45 R115
10uF NC
ADJ 4 R116
with 10K8 1% to enable DDR400
470 1.225V
6.3V 10K7 PT59 VCORESB

2
GNDS

memory at 2.60V.
GND

1%
C191

1
10uF C192
2

LP38690ADJ/LLP R117 6.3V D19


10K 1uF

2
1% LM4041
B B

DGND
DGND DGND

DGND
MH1 MH3 MH4 MH5 MH7 MH6
M HOLE M HOLE M HOLE M HOLE M HOLE M HOLE

MH8 MH9 MH10 MH11 MH12 MH13 MH14 MH2


M HOLE M HOLE M HOLE M HOLE M HOLE M HOLE M HOLE M HOLE

MH15 MH16 MH17


M HOLE M HOLE M HOLE

R118 0 R119 0 R120 0 R121 0


A DGND A

R122 0 R123 0 R124 0 R125 0

ITEM DOCUMENTO
CHASSIS DGND CHASSIS DGND CHASSIS DGND CHASSIS DGND
30-28700-0/1 EE30184C

PAGINA: 19 DE 26 POWER SUPPLIES


5 4 3 2 1
OBM_MD[0..63]
OBM_MAA[0..12] OBM_MD[0..63]
7 RMA8 1 8OBM_MAA8
7 RMA7 2 7OBM_MAA7
3 6OBM_MAA9 RP1 +2.5VDDR +2.5VDDR
7 RMA9 OBM_MAA[0..12] +2.5VDDR +2.5VDDR
7 RMA11 4 5OBM_MAA11 22 OBM_MAA[0..12]
7 RMA3 1 8OBM_MAA3
7OBM_MAA4 U17 U19

61
55
15

15
55
61
7 RMA4 2

9
3

3
9
6OBM_MAA6 RP2 U20 U18

61
55
15

15
55
61
7 RMA6 3

9
3

3
9
4 5OBM_MAA5 22 OBM_MD3 2 1 1 2 OBM_MD0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
7 RMA5 DQ0 VDD VDD DQ0
1 8OBM_MAA10 OBM_MD7 5 18 18 5 OBM_MD4 OBM_MD11 2 1 1 2 OBM_MD8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
7 RMA10 DQ1 VDD VDD DQ1 DQ0 VDD VDD DQ0
7 RMA1 2 7OBM_MAA1 OBM_MD6 8 33 33 8 OBM_MD5 OBM_MD10 5 18 18 5 OBM_MD9
DQ2 VDD VDD DQ2 DQ1 VDD VDD DQ1
7 RMA0 3 6OBM_MAA0 RP3 OBM_MD2 11 11 OBM_MD1 OBM_MD15 8 33 33 8 OBM_MD12
DQ3 DQ3 DQ2 VDD VDD DQ2
7 RMA2 4 5OBM_MAA2 22 OBM_MD1 56 56 OBM_MD2 OBM_MD14 11 11 OBM_MD13
DQ4 DQ4 DQ3 DQ3
7 RMA12 2 1OBM_MAA12 OBM_MD5 59 29 OBM_MAA0 OBM_MAA0 29 59 OBM_MD6 OBM_MD13 56 56 OBM_MD14
OBM_MD4 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD7 OBM_MD12 DQ4 OBM_MAA0 OBM_MAA0 DQ4 OBM_MD15
62 30 30 62 59 29 29 59
R126 OBM_MD0 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD3 OBM_MD9 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD10
65 31 31 65 62 30 30 62
22/R0402 DQ7 A2 OBM_MAA3 OBM_MAA3 A2 DQ7 OBM_MD8 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD11
32 32 65 31 31 65
A3 OBM_MAA4 OBM_MAA4 A3 DQ7 A2 OBM_MAA3 OBM_MAA3 A2 DQ7
35 35 32 32
A4 OBM_MAA5 OBM_MAA5 A4 A3 OBM_MAA4 OBM_MAA4 A3
[6] DDRVREF 49 36 36 49 DDRVREF [6] 35 35
VREF A5 OBM_MAA6 OBM_MAA6 A5 VREF A4 OBM_MAA5 OBM_MAA5 A4
OBM_MD[0..63] 37 37 [6] DDRVREF 49 36 36 49 DDRVREF [6]
A6 A6 VREF A5 A5 VREF
7 RMD0 1 8OBM_MD0 38 OBM_MAA7 OBM_MAA7 38 37 OBM_MAA6 OBM_MAA6 37

1
A7 A7 A6 A6
7 RMD4 2 7OBM_MD4 C193 4 39 OBM_MAA8 OBM_MAA8 39 4 C194 38 OBM_MAA7 OBM_MAA7 38
NC4 A8 A8 NC4 A7 A7

1
7 RMD5 3 6OBM_MD5 RP4 0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF C195 4 39 OBM_MAA8 OBM_MAA8 39 4 C196
NC7 A9 A9 NC7 NC4 A8 A8 NC4
7 RMD1 4 5OBM_MD1 22 10 28 OBM_MAA10 OBM_MAA10 28 10 0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF

2
NC10 AP/A10 AP/A10 NC10 NC7 A9 A9 NC7
7 RMD2 1 8OBM_MD2 13 41 OBM_MAA11 OBM_MAA11 41 13 10 28 OBM_MAA10 OBM_MAA10 28 10

2
NC13 A11 A11 NC13 NC10 AP/A10 AP/A10 NC10
7 RMD6 2 7OBM_MD6 RP5 14 42 OBM_MAA12 OBM_MAA12 42 14 13 41 OBM_MAA11 OBM_MAA11 41 13
NC141 A12 A12 NC141 NC13 A11 A11 NC13
7 RMD7 3 6OBM_MD7 22 16 17 17 16 14 42 OBM_MAA12 OBM_MAA12 42 14
NC16 A13 A13 NC16 NC141 A12 A12 NC141
7 RMD3 4 5OBM_MD3 19 19 16 17 17 16
NC19 NC19 NC16 A13 A13 NC16
7 RMD8 1 8OBM_MD8 RMDX_WE# 20 20 19 19
NC20 NC20 NC19 NC19
7 RMD9 2 7OBM_MD9 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50 RMDX_WE# 20 20
NC50 WE WE NC50 NC20 NC20
7 RMD12 3 6OBM_MD12 RP6 RMDX_RAS# 53 22 RMDX_CAS# RMDX_CAS# 22 53 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50
NC53 CAS CAS NC53 NC50 WE WE NC50
7 RMD13 4 5OBM_MD13 22 RMDX_SCS0 54 23 RMDX_RAS# RMDX_RAS# 23 54 RMDX_RAS# 53 22 RMDX_CAS# RMDX_CAS# 22 53
NC54 RAS RAS NC54 NC53 CAS CAS NC53
7 RMD14 1 8OBM_MD14 RMDX_SCS1 57 57 RMDX_SCS0 54 23 RMDX_RAS# RMDX_RAS# 23 54
NC57 NC57 NC54 RAS RAS NC54
7 RMD15 2 7OBM_MD15 RP7 RMDX_BS0# 60 24 RMDX_SCS0 RMDX_SCS1 24 60 RMDX_SCS1 57 57
NC60 CS0 CS0 NC60 NC57 NC57
7 RMD10 3 6OBM_MD10 22 RMDX_BS1# 63 25 25 63 RMDX_BS0# 60 24 RMDX_SCS0 RMDX_SCS1 24 60
NC63 CS1/NC CS1/NC NC63 NC60 CS0 CS0 NC60
7 RMD11 4 5OBM_MD11 RMDX_CKE0 RMDX_BS1# 63 25 25 63
NC63 CS1/NC CS1/NC NC63
7 RMD20 1 8OBM_MD20 26 RMDX_BS0# RMDX_BS0# 26 RMDX_CKE0
BA0 BA0
7 RMD16 2 7OBM_MD16 27 RMDX_BS1# RMDX_BS1# 27 26 RMDX_BS0# RMDX_BS0# 26
BA1 BA1 BA0 BA0
7 RMD17 3 6OBM_MD17 RP8 27 RMDX_BS1# RMDX_BS1# 27
BA1 BA1
7 RMD21 4 5OBM_MD21 22 OBM_SDM0 6 44 RMDX_CKE0 RMDX_CKE0 44 6
VSSQ CKE0 CKE0 VSSQ
7 RMD18 1 8OBM_MD18 OBM_SDQS0 12 43 43 12 OBM_SDM1 6 44 RMDX_CKE0 RMDX_CKE0 44 6
VSSQ CKE1/NC CKE1/NC VSSQ VSSQ CKE0 CKE0 VSSQ
7 RMD22 2 7OBM_MD22 RP9 52 52 OBM_SDQS1 12 43 43 12
VSSQ VSSQ VSSQ CKE1/NC CKE1/NC VSSQ
7 RMD23 3 6OBM_MD23 22 MEMCLK0 58 45 MEMCLK0 MEMCLK0 45 58 52 52
VSSQ CK CK VSSQ VSSQ VSSQ
7 RMD19 4 5OBM_MD19 MEMCLK0# 64 46 MEMCLK0# MEMCLK0# 46 64 MEMCLK0 58 45 MEMCLK0 MEMCLK0 45 58
VSSQ CK CK VSSQ VSSQ CK CK VSSQ
7 RMD24 1 8OBM_MD24 MEMCLK0# 64 46 MEMCLK0# MEMCLK0# 46 64
VSSQ CK CK VSSQ
7 RMD28 2 7OBM_MD28 34 47 OBM_SDM0 OBM_SDM0 47 34
VSS DM DM VSS
7 RMD29 3 6OBM_MD29 RP10 48 48 34 47 OBM_SDM1 OBM_SDM1 47 34
VSS VSS VSS DM DM VSS
7 RMD25 4 5OBM_MD25 22 66 51 OBM_SDQS0 OBM_SDQS0 51 66 48 48
VSS DQS DQS VSS VSS VSS
7 RMD30 1 8OBM_MD30 66 51 OBM_SDQS1 OBM_SDQS1 51 66
VSS DQS DQS VSS
7 RMD26 2 7OBM_MD26 RP11 K4H560838H-UC/LCC K4H560838H-UC/LCC
7 RMD27 3 6OBM_MD27 22 DGND K4H560838H-UC/LCC K4H560838H-UC/LCC
7 RMD31 4 5OBM_MD31
7 RMD32 1 8OBM_MD32 OBM_MD[0..63]
7 RMD36 2 7OBM_MD36 OBM_MD[0..63]
7 RMD33 3 6OBM_MD33 RP12
7 RMD37 4 5OBM_MD37 22
1 8OBM_MD34 +2.5VDDR +2.5VDDR
7 RMD34 OBM_MAA[0..12] +2.5VDDR +2.5VDDR
7 RMD38 2 7OBM_MD38 RP13 OBM_MAA[0..12]
7 RMD39 3 6OBM_MD39 22
5OBM_MD35 U22 U24
61
55
15

15
55
61
7 RMD35 4 9
3

3
9
8OBM_MD40 U23 U21

61
55
15

15
55
61
7 RMD40 1

9
3

3
9
2 7OBM_MD44 OBM_MD19 2 1 1 2 OBM_MD20
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
7 RMD44 DQ0 VDD VDD DQ0
3 6OBM_MD45 RP14 OBM_MD23 5 18 18 5 OBM_MD16 OBM_MD31 2 1 1 2 OBM_MD24

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
7 RMD45 DQ1 VDD VDD DQ1 DQ0 VDD VDD DQ0
7 RMD41 4 5OBM_MD41 22 OBM_MD22 8 33 33 8 OBM_MD17 OBM_MD27 5 18 18 5 OBM_MD28
DQ2 VDD VDD DQ2 DQ1 VDD VDD DQ1
7 RMD42 1 8OBM_MD42 OBM_MD18 11 11 OBM_MD21 OBM_MD26 8 33 33 8 OBM_MD29
DQ3 DQ3 DQ2 VDD VDD DQ2
7 RMD46 2 7OBM_MD46 RP17 OBM_MD21 56 56 OBM_MD18 OBM_MD30 11 11 OBM_MD25
DQ4 DQ4 DQ3 DQ3
7 RMD43 3 6OBM_MD43 22 OBM_MD17 59 29 OBM_MAA0 OBM_MAA0 29 59 OBM_MD22 OBM_MD25 56 56 OBM_MD30
DQ5 A0 A0 DQ5 DQ4 DQ4
7 RMD47 4 5OBM_MD47 OBM_MD16 62 30 OBM_MAA1 OBM_MAA1 30 62 OBM_MD23 OBM_MD29 59 29 OBM_MAA0 OBM_MAA0 29 59 OBM_MD26
DQ6 A1 A1 DQ6 DQ5 A0 A0 DQ5
7 RMD48 1 8OBM_MD48 OBM_MD20 65 31 OBM_MAA2 OBM_MAA2 31 65 OBM_MD19 OBM_MD28 62 30 OBM_MAA1 OBM_MAA1 30 62 OBM_MD27
DQ7 A2 A2 DQ7 DQ6 A1 A1 DQ6
7 RMD49 2 7OBM_MD49 32 OBM_MAA3 OBM_MAA3 32 OBM_MD24 65 31 OBM_MAA2 OBM_MAA2 31 65 OBM_MD31
A3 A3 DQ7 A2 A2 DQ7
7 RMD52 3 6OBM_MD52 RP15 35 OBM_MAA4 OBM_MAA4 35 32 OBM_MAA3 OBM_MAA3 32
A4 A4 A3 A3
7 RMD53 4 5OBM_MD53 22
[6] DDRVREF 49 36 OBM_MAA5 OBM_MAA5 36 49 DDRVREF [6] 35 OBM_MAA4 OBM_MAA4 35
VREF A5 A5 VREF A4 A4
7 RMD54 1 8OBM_MD54 37 OBM_MAA6 OBM_MAA6 37 [6] DDRVREF 49 36 OBM_MAA5 OBM_MAA5 36 49 DDRVREF [6]
A6 A6 VREF A5 A5 VREF
7 RMD55 2 7OBM_MD55 RP16 38 OBM_MAA7 OBM_MAA7 38 37 OBM_MAA6 OBM_MAA6 37
A7 A7 A6 A6
1

1
7 RMD50 3 6OBM_MD50 22 C198 4 39 OBM_MAA8 OBM_MAA8 39 4 C199 38 OBM_MAA7 OBM_MAA7 38

1
NC4 A8 A8 NC4 A7 A7
7 RMD51 4 5OBM_MD51 0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF C197 4 39 OBM_MAA8 OBM_MAA8 39 4 C200
NC7 A9 A9 NC7 NC4 A8 A8 NC4
7 RMD62 1 8OBM_MD62 10 28 OBM_MAA10 OBM_MAA10 28 10 0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF
2

2
NC10 AP/A10 AP/A10 NC10 NC7 A9 A9 NC7
2 7OBM_MD63 13 41 OBM_MAA11 OBM_MAA11 41 13 10 28 OBM_MAA10 OBM_MAA10 28 10

2
7 RMD63 NC13 A11 A11 NC13 NC10 AP/A10 AP/A10 NC10
7 RMD58 3 6OBM_MD58 RP18 14 42 OBM_MAA12 OBM_MAA12 42 14 13 41 OBM_MAA11 OBM_MAA11 41 13
NC141 A12 A12 NC141 NC13 A11 A11 NC13
7 RMD59 4 5OBM_MD59 22 16 17 17 16 14 42 OBM_MAA12 OBM_MAA12 42 14
NC16 A13 A13 NC16 NC141 A12 A12 NC141
7 RMD60 1 8OBM_MD60 19 19 16 17 17 16
NC19 NC19 NC16 A13 A13 NC16
7 RMD61 2 7OBM_MD61 RMDX_WE# 20 20 19 19
NC20 NC20 NC19 NC19
7 RMD56 3 6OBM_MD56 RP19 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50 RMDX_WE# 20 20
NC50 WE WE NC50 NC20 NC20
7 RMD57 4 5OBM_MD57 22 RMDX_RAS# 53 22 RMDX_CAS# RMDX_CAS# 22 53 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50
RMDX_SCS0 NC53 CAS RMDX_RAS# RMDX_RAS# CAS NC53 RMDX_RAS# NC50 WE RMDX_CAS# RMDX_CAS# WE NC50
54 23 23 54 53 22 22 53
RMDX_SCS1 NC54 RAS RAS NC54 RMDX_SCS0 NC53 CAS RMDX_RAS# RMDX_RAS# CAS NC53
7 RMWE# 1 8 RMDX_WE# 57 57 54 23 23 54
RP20 RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57 RMDX_SCS1 NC54 RAS RAS NC54
7 RMBA0 2 7 RMDX_BS0# 60 24 24 60 57 57
22 RMDX_BS1# NC60 CS0 CS0 NC60 RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57
7 RMRAS# 3 6 RMDX_RAS# 63 25 25 63 60 24 24 60
RMDX_CKE0 NC63 CS1/NC CS1/NC NC63 RMDX_BS1# NC60 CS0 CS0 NC60
7 RMBA1 4 5 RMDX_BS1# 63 25 25 63
RMDX_BS0# RMDX_BS0# RMDX_CKE0 NC63 CS1/NC CS1/NC NC63
1 8 26 26
RP21 BA0 RMDX_BS1# RMDX_BS1# BA0 RMDX_BS0# RMDX_BS0#
7 RMCS1# 2 7 RMDX_SCS1 27 27 26 26
22 BA1 BA1 BA0 RMDX_BS1# RMDX_BS1# BA0
7 RMCAS# 3 6 RMDX_CAS# 27 27
OBM_SDM2 RMDX_CKE0 RMDX_CKE0 BA1 BA1
7 RMCS0# 4 5 RMDX_SCS0 6 44 44 6
OBM_SDQS2 VSSQ CKE0 CKE0 VSSQ OBM_SDM3 RMDX_CKE0 RMDX_CKE0
12 43 43 12 6 44 44 6
VSSQ CKE1/NC CKE1/NC VSSQ OBM_SDQS3 VSSQ CKE0 CKE0 VSSQ
7 RMCKE0 2 1 RMDX_CKE0 52 52 12 43 43 12
R127 22/R0402 MEMCLK0 VSSQ MEMCLK0 MEMCLK0 VSSQ VSSQ CKE1/NC CKE1/NC VSSQ
58 45 45 58 52 52
MEMCLK0# VSSQ CK MEMCLK0# MEMCLK0# CK VSSQ MEMCLK0 VSSQ MEMCLK0 MEMCLK0 VSSQ
64 46 46 64 58 45 45 58
VSSQ CK CK VSSQ VSSQ CK CK VSSQ
7 RMDQM0 2 1OBM_SDM0 MEMCLK0# 64 46 MEMCLK0# MEMCLK0# 46 64
R128 22/R0402 OBM_SDM2 OBM_SDM2 VSSQ CK CK VSSQ
34 47 47 34
VSS DM DM VSS
7 RMDQS0 2 1OBM_SDQS0 48 48 34 47 OBM_SDM3 OBM_SDM3 47 34
R129 22/R0402 VSS OBM_SDQS2 OBM_SDQS2 51 VSS VSS DM DM VSS
66 51 66 48 48
VSS DQS DQS VSS VSS OBM_SDQS3 OBM_SDQS3 51 VSS
66 51 66
VSS DQS DQS VSS
7 RMDQM1 2 1OBM_SDM1 K4H560838H-UC/LCC K4H560838H-UC/LCC
R130 22/R0402 K4H560838H-UC/LCC K4H560838H-UC/LCC
7 RMDQS1 2 1OBM_SDQS1
R131 22/R0402

7 RMDQM2 2 1OBM_SDM2
R132 22/R0402
7 RMDQS2 2 1OBM_SDQS2
R133 22/R0402

7 RMDQM3 2 1OBM_SDM3
R134 22/R0402 +2.5VDDR
7 RMDQS3 2 1OBM_SDQS3
R135 22/R0402

1
+2.5VDDR +2.5VDDR +2.5VDDR +2.5VDDR C315
MEMCLK0 U60
7 SDCLK0
2

100nF AT24C02N-10SC NL

2
1

R136 C201 C202 C203 C204


120/R0603 0.1uF 0.1uF 0.1uF 0.1uF 8 1
MEMCLK0# VCC3V A0
7 2
1

7 SDCLK0# WP A1
12 SMB_SCL 6 3
SCL A2
12 SMB_SDA 5 4
SDA GND

+2.5VDDR +2.5VDDR +2.5VDDR +2.5VDDR


1

C205 C206 C207 C208


0.1uF 0.1uF 0.1uF 0.1uF
2

ITEM DOCUMENTO
30-28700-0/1 EE30184C

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida. PAGINA: 20 DE 26 DDR_ONBOARD1


OBM_MD[0..63]
OBM_MD[0..63]

+2.5VDDR +2.5VDDR
RMDX_WE# OBM_MAA[0..12] +2.5VDDR +2.5VDDR
RMDX_CAS# OBM_MAA[0..12]
RMDX_RAS#
U26 U27

61
55
15

15
55
61
RMDX_SCS0

9
3

3
9
U25 U28

61
55
15

15
55
61
RMDX_SCS1

9
3

3
9
OBM_MD35 2 1 1 2 OBM_MD32

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RMDX_BS0# DQ0 VDD VDD DQ0
OBM_MD39 5 18 18 5 OBM_MD36 OBM_MD47 2 1 1 2 OBM_MD40

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RMDX_BS1# DQ1 VDD VDD DQ1 DQ0 VDD VDD DQ0
OBM_MD38 8 33 33 8 OBM_MD33 OBM_MD43 5 18 18 5 OBM_MD44
RMDX_CKE0 DQ2 VDD VDD DQ2 DQ1 VDD VDD DQ1
OBM_MD34 11 11 OBM_MD37 OBM_MD46 8 33 33 8 OBM_MD45
OBM_MD37 DQ3 DQ3 OBM_MD34 OBM_MD42 DQ2 VDD VDD DQ2 OBM_MD41
56 56 11 11
OBM_MD33 DQ4 OBM_MAA0 OBM_MAA0 DQ4 OBM_MD38 OBM_MD41 DQ3 DQ3 OBM_MD42
59 29 29 59 56 56
OBM_MD36 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD39 OBM_MD45 DQ4 OBM_MAA0 OBM_MAA0 DQ4 OBM_MD46
62 30 30 62 59 29 29 59
OBM_MD32 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD35 OBM_MD44 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD43
65 31 31 65 62 30 30 62
DQ7 A2 OBM_MAA3 OBM_MAA3 A2 DQ7 OBM_MD40 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD47
32 32 65 31 31 65
A3 A3 DQ7 A2 A2 DQ7
7 RMDQM4 2 1OBM_SDM4 35 OBM_MAA4 OBM_MAA4 35 32 OBM_MAA3 OBM_MAA3 32
R137 22/R0402 A4 OBM_MAA5 OBM_MAA5 A4 A3 OBM_MAA4 OBM_MAA4 A3
[6] DDRVREF 49 36 36 49 DDRVREF [6] 35 35
VREF A5 A5 VREF A4 A4
7 RMDQS4 2 1OBM_SDQS4 37 OBM_MAA6 OBM_MAA6 37 [6] DDRVREF 49 36 OBM_MAA5 OBM_MAA5 36 49 DDRVREF [6]
R138 22/R0402 A6 OBM_MAA7 OBM_MAA7 A6 VREF A5 OBM_MAA6 OBM_MAA6 A5 VREF
38 38 37 37

1
C209 A7 OBM_MAA8 OBM_MAA8 A7 C210 A6 OBM_MAA7 OBM_MAA7 A6
4 39 39 4 38 38
NC4 A8 A8 NC4 A7 A7

1
7 RMDQM5 2 1OBM_SDM5 0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF C211 4 39 OBM_MAA8 OBM_MAA8 39 4 C212
R139 22/R0402 NC7 A9 OBM_MAA10 OBM_MAA10 A9 NC7 0.1uF NC4 A8 OBM_MAA9 OBM_MAA9 A8 NC4 0.1uF
10 28 28 10 7 40 40 7

2
NC10 AP/A10 AP/A10 NC10 NC7 A9 A9 NC7
7 RMDQS5 2 1OBM_SDQS5 13 41 OBM_MAA11 OBM_MAA11 41 13 10 28 OBM_MAA10 OBM_MAA10 28 10

2
R140 22/R0402 NC13 A11 OBM_MAA12 OBM_MAA12 A11 NC13 NC10 AP/A10 OBM_MAA11 OBM_MAA11 AP/A10 NC10
14 42 42 14 13 41 41 13
NC141 A12 A12 NC141 NC13 A11 A11 NC13
7 RMDQM6 2 1OBM_SDM6 16 17 17 16 14 42 OBM_MAA12 OBM_MAA12 42 14
R141 22/R0402 NC16 A13 A13 NC16 NC141 A12 A12 NC141
19 19 16 17 17 16
NC19 NC19 NC16 A13 A13 NC16
7 RMDQS6 2 1OBM_SDQS6 RMDX_WE# 20 20 19 19
R142 22/R0402 RMDX_CAS# NC20 RMDX_WE# RMDX_WE# NC20 RMDX_WE# NC19 NC19
50 21 21 50 20 20
NC50 WE WE NC50 NC20 NC20
7 RMDQM7 2 1OBM_SDM7 RMDX_RAS# 53 22 RMDX_CAS# RMDX_CAS# 22 53 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50
R143 22/R0402 RMDX_SCS0 NC53 CAS RMDX_RAS# RMDX_RAS# CAS NC53 RMDX_RAS# NC50 WE RMDX_CAS# RMDX_CAS# WE NC50
54 23 23 54 53 22 22 53
NC54 RAS RAS NC54 NC53 CAS CAS NC53
7 RMDQS7 2 1OBM_SDQS7 RMDX_SCS1 57 57 RMDX_SCS0 54 23 RMDX_RAS# RMDX_RAS# 23 54
R144 22/R0402 RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57 RMDX_SCS1 NC54 RAS RAS NC54
60 24 24 60 57 57
RMDX_BS1# NC60 CS0 CS0 NC60 RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57
63 25 25 63 60 24 24 60
RMDX_CKE0 NC63 CS1/NC CS1/NC NC63 RMDX_BS1# NC60 CS0 CS0 NC60
63 25 25 63
RMDX_BS0# RMDX_BS0# RMDX_CKE0 NC63 CS1/NC CS1/NC NC63
26 26
BA0 RMDX_BS1# RMDX_BS1# BA0 RMDX_BS0# RMDX_BS0#
27 27 26 26
MEMCLK1 BA1 BA1 BA0 RMDX_BS1# RMDX_BS1# BA0
7 SDCLK2 27 27
2

OBM_SDM4 RMDX_CKE0 RMDX_CKE0 BA1 BA1


6 44 44 6
R145 OBM_SDQS4 VSSQ CKE0 CKE0 VSSQ OBM_SDM5 RMDX_CKE0 RMDX_CKE0
12 43 43 12 6 44 44 6
120/R0603 VSSQ CKE1/NC CKE1/NC VSSQ OBM_SDQS5 VSSQ CKE0 CKE0 VSSQ
52 52 12 43 43 12
MEMCLK1# MEMCLK1 VSSQ MEMCLK1 MEMCLK1 VSSQ VSSQ CKE1/NC CKE1/NC VSSQ
7 SDCLK2# 58 45 45 58 52 52
1

MEMCLK1# VSSQ CK MEMCLK1# MEMCLK1# CK VSSQ MEMCLK1 VSSQ MEMCLK1 MEMCLK1 VSSQ
64 46 46 64 58 45 45 58
VSSQ CK CK VSSQ MEMCLK1# VSSQ CK MEMCLK1# MEMCLK1# CK VSSQ
64 46 46 64
OBM_SDM4 OBM_SDM4 VSSQ CK CK VSSQ
34 47 47 34
VSS DM DM VSS OBM_SDM5 OBM_SDM5
48 48 34 47 47 34
VSS OBM_SDQS4 OBM_SDQS4 VSS VSS DM DM VSS
66 51 51 66 48 48
VSS DQS DQS VSS VSS OBM_SDQS5 OBM_SDQS5 51 VSS
66 51 66
VSS DQS DQS VSS
K4H560838H-UC/LCC NL K4H560838H-UC/LCC NL
K4H560838H-UC/LCC NL K4H560838H-UC/LCC NL

OBM_MD[0..63]
OBM_MD[0..63]

+2.5VDDR +2.5VDDR
OBM_MAA[0..12] +2.5VDDR +2.5VDDR
OBM_MAA[0..12]
U29 U30
61
55
15

15
55
61
9
3

3
9
U32 U31

61
55
15

15
55
61
9
3

3
9
OBM_MD51 2 1 1 2 OBM_MD48
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
OBM_MD50 DQ0 VDD VDD DQ0 OBM_MD49 OBM_MD59 OBM_MD61
5 18 18 5 2 1 1 2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
OBM_MD55 DQ1 VDD VDD DQ1 OBM_MD52 OBM_MD58 DQ0 VDD VDD DQ0 OBM_MD60
8 33 33 8 5 18 18 5
OBM_MD54 DQ2 VDD VDD DQ2 OBM_MD53 OBM_MD63 DQ1 VDD VDD DQ1 OBM_MD56
11 11 8 33 33 8
OBM_MD53 DQ3 DQ3 OBM_MD54 OBM_MD62 DQ2 VDD VDD DQ2 OBM_MD57
56 56 11 11
OBM_MD52 DQ4 OBM_MAA0 OBM_MAA0 DQ4 OBM_MD55 OBM_MD57 DQ3 DQ3 OBM_MD62
59 29 29 59 56 56
OBM_MD49 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD50 OBM_MD56 DQ4 OBM_MAA0 OBM_MAA0 DQ4 OBM_MD63
62 30 30 62 59 29 29 59
OBM_MD48 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD51 OBM_MD60 DQ5 A0 OBM_MAA1 OBM_MAA1 A0 DQ5 OBM_MD58
65 31 31 65 62 30 30 62
+2.5VDDR +2.5VDDR +2.5VDDR +2.5VDDR DQ7 A2 OBM_MAA3 OBM_MAA3 A2 DQ7 OBM_MD61 DQ6 A1 OBM_MAA2 OBM_MAA2 A1 DQ6 OBM_MD59
32 32 65 31 31 65
A3 OBM_MAA4 OBM_MAA4 A3 DQ7 A2 OBM_MAA3 OBM_MAA3 A2 DQ7
35 35 32 32
A4 OBM_MAA5 OBM_MAA5 A4 A3 OBM_MAA4 OBM_MAA4 A3
[6] DDRVREF 49 36 36 49 DDRVREF [6] 35 35
VREF A5 A5 VREF A4 A4
1

C213 C214 C215 C216 37 OBM_MAA6 OBM_MAA6 37 49 36 OBM_MAA5 OBM_MAA5 36 49


A6 A6 [6] DDRVREF VREF A5 A5 VREF DDRVREF [6]
0.1uF 0.1uF 0.1uF 0.1uF 38 OBM_MAA7 OBM_MAA7 38 37 OBM_MAA6 OBM_MAA6 37
1

1
C217 A7 OBM_MAA8 OBM_MAA8 A7 C220 A6 OBM_MAA7 OBM_MAA7 A6
4 39 39 4 38 38
2

NC4 A8 A8 NC4 A7 A7

1
0.1uF 7 40 OBM_MAA9 OBM_MAA9 40 7 0.1uF C218 4 39 OBM_MAA8 OBM_MAA8 39 4 C219
NC7 A9 OBM_MAA10 OBM_MAA10 A9 NC7 0.1uF NC4 A8 OBM_MAA9 OBM_MAA9 A8 NC4 0.1uF
10 28 28 10 7 40 40 7
2

2
NC10 AP/A10 OBM_MAA11 OBM_MAA11 AP/A10 NC10 NC7 A9 OBM_MAA10 OBM_MAA10 A9 NC7
13 41 41 13 10 28 28 10

2
NC13 A11 OBM_MAA12 OBM_MAA12 A11 NC13 NC10 AP/A10 OBM_MAA11 OBM_MAA11 AP/A10 NC10
14 42 42 14 13 41 41 13
+2.5VDDR +2.5VDDR +2.5VDDR +2.5VDDR NC141 A12 A12 NC141 NC13 A11 OBM_MAA12 OBM_MAA12 A11 NC13
16 17 17 16 14 42 42 14
NC16 A13 A13 NC16 NC141 A12 A12 NC141
19 19 16 17 17 16
RMDX_WE# NC19 NC19 NC16 A13 A13 NC16
20 20 19 19
NC20 NC20 NC19 NC19
1

C221 C222 C223 C224 RMDX_CAS# 50 21 RMDX_WE# RMDX_WE# 21 50 RMDX_WE# 20 20


0.1uF 0.1uF 0.1uF 0.1uF RMDX_RAS# NC50 WE RMDX_CAS# RMDX_CAS# WE NC50 RMDX_CAS# NC20 RMDX_WE# RMDX_WE# NC20
53 22 22 53 50 21 21 50
RMDX_SCS0 NC53 CAS RMDX_RAS# RMDX_RAS# CAS NC53 RMDX_RAS# NC50 WE RMDX_CAS# RMDX_CAS# WE NC50
54 23 23 54 53 22 22 53
2

RMDX_SCS1 NC54 RAS RAS NC54 RMDX_SCS0 NC53 CAS RMDX_RAS# RMDX_RAS# CAS NC53
57 57 54 23 23 54
RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57 RMDX_SCS1 NC54 RAS RAS NC54
60 24 24 60 57 57
RMDX_BS1# NC60 CS0 CS0 NC60 RMDX_BS0# NC57 RMDX_SCS0 RMDX_SCS1 NC57
63 25 25 63 60 24 24 60
RMDX_CKE0 NC63 CS1/NC CS1/NC NC63 RMDX_BS1# NC60 CS0 CS0 NC60
63 25 25 63

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


DGND RMDX_BS0# RMDX_BS0# RMDX_CKE0 NC63 CS1/NC CS1/NC NC63
26 26
BA0 RMDX_BS1# RMDX_BS1# BA0 RMDX_BS0# RMDX_BS0#
27 27 26 26
BA1 BA1 BA0 RMDX_BS1# RMDX_BS1# BA0
27 27
OBM_SDM6 RMDX_CKE0 RMDX_CKE0 BA1 BA1
6 44 44 6
OBM_SDQS6 VSSQ CKE0 CKE0 VSSQ OBM_SDM7 RMDX_CKE0 RMDX_CKE0
12 43 43 12 6 44 44 6
VSSQ CKE1/NC CKE1/NC VSSQ OBM_SDQS7 VSSQ CKE0 CKE0 VSSQ
52 52 12 43 43 12
MEMCLK1 VSSQ MEMCLK1 MEMCLK1 VSSQ VSSQ CKE1/NC CKE1/NC VSSQ
58 45 45 58 52 52
MEMCLK1# VSSQ CK MEMCLK1# MEMCLK1# CK VSSQ MEMCLK1 VSSQ MEMCLK1 MEMCLK1 VSSQ
64 46 46 64 58 45 45 58
VSSQ CK CK VSSQ MEMCLK1# VSSQ CK MEMCLK1# MEMCLK1# CK VSSQ
64 46 46 64
OBM_SDM6 OBM_SDM6 VSSQ CK CK VSSQ
34 47 47 34
VSS DM DM VSS OBM_SDM7 OBM_SDM7
48 48 34 47 47 34
VSS OBM_SDQS6 OBM_SDQS6 VSS VSS DM DM VSS
66 51 51 66 48 48
VSS DQS DQS VSS VSS OBM_SDQS7 OBM_SDQS7 51 VSS
66 51 66
VSS DQS DQS VSS
K4H560838H-UC/LCC NL K4H560838H-UC/LCC NL
K4H560838H-UC/LCC NL K4H560838H-UC/LCC NL

ITEM DOCUMENTO
30-28700-0/1 EE30184C

PAGINA: 21 DE 26 DDR_ONBOARD2
5 4 3 2 1

25 ANSTH_O1
25 ANSTH_O2
VCC_FPGA_3V3
25 ANSTH_O3
25 ANSTH_O4
25 ANSTH_O5

1
ANSTH_IB1
R301 VCC_FPGA_3V3 J2
ANSTH_IB2
3.92K U58 HEADER 9X1
ANSTH_IB3
PT72 14.7456MHz
ANSTH_IB4
ANSTH_IB5

2
25 SDCD1X 3 4
O +

9
8
7
6
5
4
3
2
1
25 SRXD1

G
VCC_FPGA_2V5
25 SDSR1X

9
8
7
6
5
4
3
2
1
2
25 SCTS1X
25 STXD1

FPGA_TMS

FPGA_TDO

FPGA_TCK
FPGA_TDI
2
1
D 25 SDTR1X D
25 SRTS1X DGND R147 VCC_FPGA_2V5
CLK_LPC_SIO
VCC_FPGA_3V3 330
CLK_LPC_48
CLK_LPC_IOC U59
PT73 8MHz R146
LAD0

1
2
4.7K
LAD1
LAD2 3 4
O +
LAD3

G
LFRAME#
DGND

2 22/R0402
2 22/R0402

2
PME# VCC_FPGA_3V3

22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402

2 22/R0402
2 22/R0402
2 22/R0402

22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
PCI_RST#
LDRQ#
SERIRQ DGND
CTRL_PWR_FLT

2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
STBY_MODULES R157 R158 R159
0 0 NL 0 NL PT63 PT65 PT67

1
1
VCC_FPGA_3V3 VCC_FPGA_2V5 VCC_FPGA_1V2 PT64 PT66

1
1
1
1
1
1
1
1
1
1
1

1
1
1

1
1
1
1
1

R288
R287
R277
R276
R148
R149
R150
R151
R152
R153
R154
R155
R156

R261
R262
R263

R264
R265
R266
R267
R268
17-21SCR/TR8
22/R0402 17-21SCR/TR8
22/R0402 R160 R161 R162 17-21SCR/TR8

M12
D11

C11

D10

C13
C12
D12

C10

D13

N13

C14
A12

B10

A14
B14
A13
B13
E11

B11

E10

A10

B12

A11

E12

A15

B15
F10

F16

T11

T15

T10
L16

M5
D9

D8
C8

C7

D7

D6
C6

C4
C5

C3

C9

D5

D4

N4

D3

R9
A7

B4
B6

E9
A9

E8

B7

E7

A4
A5

B3

A3

B8
A8
E6

B5

A6

E5

A2
22/R0402 17-21SCR/TR8

F9

F8

F7

F1

T6
L1

L9
0 NL 0 0
22/R0402 17-21SCR/TR8
22/R0402 R163 330 LD3
A K

I/O53
I/O54
I/O55
IP27
IP28
I/O_VREF11
I/O56
I/O57
I/O_VREF12
I/O58
I/O59
I/O60
I/O_VREF13
I/O61
I/O62
I/O63
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
I/O64
I/O65
I/O66
I/O67
I/O_VREF14
I/O68
I/O69
I/O70
I/O_VREF15
I/O71
I/O72
I/O73
I/O_DUAL27
I/O74
IP29
IP30
IP31
IP32
IP33
IP34
GCLK7
GCLK8
IP35
IP36

M0
M1
M2
TDI
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCO
VCCO
VCCO
VCCO

TDO
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX

PROG_B
DONE

TCK

TMS
Data
IBP_nPCS5 R293 1 2 22/R0402 R15 DGND DGND DGND R164 330 LD2
A K
R292 22/R0402 I/O_DUAL6 TransmiterEnabled
IBP_nPCS4 1 2 R16
R291 22/R0402 I/O_DUAL7 MM_DATA R165 330 LD4
ERT_IBP_D5 1 2 P15 B2 A K
R290 22/R0402 I/O_DUAL8 I/O26 MM_TRANSM_ENB Sync
ERT_IBP_D4 1 2 P16 B1
R269 22/R0402 I/O_DUAL9 BANK 0 I/O27 MM_SYNC R166 330 LD6
nCS_SEL_2 1 2 N15 C2 A K
R270 22/R0402 I/O_VREF5 I/O_VREF8 MM_BUSY Busy
SSP_SCLK1 1 2 N14 C1
R271 22/R0402 I/O12 I/O28 MM_QRSYNC R167 330 LD5
SSP_TXD 1 2 M16 E4 A K
R272 22/R0402 I/O_VREF6 I/O29 R168 1 QRSYNC
ENB_AUDIO 1 2 N16 E3 2 22/R0402 TCC0
R273 22/R0402 I/O13 I/O30 R169 1
CPLD_BEEP 1 2 L13 F4 2 22/R0402 TCC1
I/O14 I/O_VREF9 R170 1
L12 F3 2 22/R0402 TCC2 DGND
I/O15 I/O31 R171 1
C L15 E1 2 22/R0402 TCC3 C
PT74 PT75 PT76 PT77 I/O16 I/O32
L14 D1 TCCB4
I/O17 I/O33
K12 G4 TCCB5
I/O_DUAL10 I/O34
K13 G5 TCCB6
R179 22/R0402 I/O_DUAL11 I/O35
1 2 K14 G2 TCCB7
R252 22/R0402 I/O_VREF7 I/O36
1 2 K15 G3 SERINB
R253 22/R0402 I/O18 I/O37
1 2 J16 H6 SYNCINB
R254 22/R0402 I/O_DUAL12 I/O_LHCLK1
1 2 K16 H5 BUSYINB
I/O_DUAL13 I/O_LHCLK2
J13 H4 QRSYNCB
I/O_DUAL14 I/O_LHCLK3 R172 22/R0402
J14 H3 1 2 TRANSEN
R173 1 22/R0402 I/O_DUAL15 I/O_LHCLK4 R174 22/R0402
CTRSTDAT 2 H14 J3 1 2 SEROUT
R175 1 22/R0402 I/O_DUAL16 I/O_LHCLK5 R176 22/R0402
CTRSTCLK 2 H15 J2 1 2 SYNCEN
R177 1 22/R0402 I/O_DUAL17 I/O_LHCLK6 R178 22/R0402
CTRSTCS 2 H11 J4 1 2 SYNCOUT
I/O_DUAL18 I/O_LHCLK7 R180 22/R0402
H12 J5 1 2 BUSYEN
I/O_DUAL19 I/O_LHCLK8 R181 22/R0402 VCC_FPGA_3V3
FTEB_PWRFAIL G16 K1 1 2 BUSYOUT
R182 1 22/R0402 I/O_DUAL20 I/O38 R183 22/R0402
FTE_TXD5 2 G15 J1 1 2 QSDE
I/O_DUAL21 BANK 1 I/O39 R184 22/R0402
FTEB_RXD5 G14 K3 1 2 QSDI
I/O_DUAL22 I/O40

1
TCLDB_ENC1 G13 K2 R185 1 2 22/R0402 ERT_IBP_D0
I/O19 BANK 3 I/O41 R186 22/R0402 R302
TCLDB_ENC2 F15 L2 1 2 ERT_IBP_D1
I/O20 I/O_VREF10 R187 22/R0402
TCLDB_PRESS F14 L3 1 2 ERT_IBP_D2 3.92K
R188 1 22/R0402 I/O21 I/O42 R189 22/R0402
TCLD_LEDSTDB 2 F12 L5 1 2 ERT_IBP_D3
R190 1 22/R0402 I/O22 I/O43 R191 22/R0402
TCLD_LED2 2 F13 K5 1 2 ERT_nPCS6

2
R192 1 22/R0402 I/O23 I/O44 R193 22/R0402
TCLD_LED1 2 E16 N1 1 2 ERT_TMR0
I/O24 I/O45 R194 22/R0402
PNIB_RXD E13 M1 1 2 ERT_TMR1
I/O25 I/O46 R195 22/R0402
PNIB_nDRDY D14 L4 1 2 ERT_TXD1
I/O_DUAL23 I/O47
PNIB_nPROT D15 M4 ERTB_RXD
I/O_DUAL24 I/O48
C15 P1 SPO2B_RXD
I/O_DUAL25 I/O49
C16 P2 SPO2B_CLK_PWR
I/O_DUAL26 I/O50
B16 R1 SPO2B_TXD
IP10 I/O51
E14 R2 RD_IBPB_D0
IP11 I/O52
G12 D2
IP12 IP19
H16 F2
IP13 IP20
J11 F5
IP14 IP21
J12 H1
IP15 IP22
M13 J6
IP16 IP23
M14 K4
IP17 IP24
D16 M3
IP18 IP25
H13 N3
B IP_VREF1 IP26 B
E15 G1
VCCO IP_VREF2

Propriedade da DIXTAL. Informação confidencial. Divulgação ou reprodução proibida.


VCC_FPGA_3V3 G11 N2
VCCO IP_VREF3
K11 E2
VCCO BANK 2 VCCO VCC_FPGA_3V3
M15 G6
VCCO VCCO
K6
VCCO
I/O_GCLK1
I/O_GCLK2
I/O_GCLK3
I/O_GCLK4
I/O_GCLK5
I/O_GCLK6

I/O_GCLK7
I/O_VREF1
I/O_VREF2

I/O_VREF3

I/O_VREF4
I/O_DUAL1

I/O_DUAL2
I/O_DUAL3
I/O_DUAL4
I/O_DUAL5

M2
PT62 VCC_FPGA_3V3 VCCO

CSO_B

INIT_B
VCCO
VCCO
VCCO
VCCO

CSI_B
DOUT
CCLK
I/O10
I/O11

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VS0
VS1
VS2
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8

I/O9

DIN
IP1
IP2

IP3
IP4
IP5
IP6

IP7

IP8
IP9

VCC_FPGA_3V3
M7
T12
T8
P13
R4
T5
T4
N6
M6
P6
R6
P7
N7
L8
M8
P8
N8
N9
P9

R10
P10
M10
N10
P11
R11
N12
P12

T2
T14
R3
T3
T7
R7
T9
M11
N11
L7
L10
R5
R12

P14
R13
T13

M9
P3

N5
P5
P4

A1
A16
B9
F6
F11
G7
G8
G9
G10
H2
H7
H8
H9
H10
J7
J8
J9
J10
J15
K7
K8
K9
K10
L6
L11
R8
T1
T16
R14

U33
7
8

C225 U34 XC3S500E-FT256


R196
R197
R198
R199
R200
R201
R202

R203

R204
R205

R206
R207
R208
R209
R210
R211
R212
R213

0.1uF 93LC86 1 CS
VCC
PE

CS SK
2
SK
VCC_FPGA_3V3

VCC_FPGA_3V3 4 3 DI
GND

1
1
1
1
1
1
1

1
1

1
1
1
1
1
1
1
1

DO DI ORG VCC_FPGA_3V3
6
ORG R214 4.7K DGND VCC_FPGA_3V3
1

DGND 2 1
5

R303
2
2
2
2
2
2
2

2
2

2
2
2
2
2
2
2
2

3.92K
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402

22/R0402

22/R0402
22/R0402

22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402
22/R0402

DGND
1 8
2

nCS VCC
IBP_TMR0 2 7
SO nHOLD
IBP_TMR1 3 6
nWP SLK
4 5
IBPB_RXD VCC_FPGA_3V3 GND SI
IBP_TXD1
M25P40
IBP_nPCS
2 1 U35
SSP1_SCLK
DGND
nCS1_P_ABS
SSP1B_RXD R215
4.7K
CNTR_0
ETCO2B_RXD 2 1 R216
4.7K
ETCO2_TXD
SSP_SCLK VCC_FPGA_3V3
PNI_CLK
PNI_PWMVLV
A A
PNI_nCSPIC
PNI_EXAUST
PNI_SCADS R218 R219
PNI_PWMBMB
PNI_STSAUTO 0 0 NL 0
PNI_STSNEO

FLSH_FPGA_nCS 1 8
2 7
FLSH_FPGA_SDI
FLSH_FPGA_SDO 3 6
FLSH_FPGA_CLK 4 5 R220 R221 R222 ITEM DOCUMENTO
0 NL 0 0 NL
RP24
22 30-28700-0/1 EE30184C
DGND DGND DGND
PAGINA: 22 DE 26 LPC_ISA_MAMI
5 4 3 2 1
5 4 3 2 1

FB24
2 FERR 1 Q3
BC817-40 R223 1.0K
FB/330/1.5A 2 1 TCLD_LED1

FB25
2 FERR 1 Q4
BC817-40
FB/330/1.5A
TCLD_LED2

FTE_PWRFAIL
FB26
2 FERR 1 Q5
BC817-40 FTE_RXD5

1
FB/330/1.5A
C226 C227
RN47 0.01uF 0.01uF

2
D nCSB_SEL_2 D
FB27 1 8
SSPB_SCLK1 Q6
2 FERR 1 2 7
SSPB_TXD BC817-40 DGND DGND
3 6
RD_IBPB_D0 FB/330/1.5A LEDONLINE
4 5
TCLD_LEDSTDB
CN5
VCC_FPGA_3V3 VCC5VSB FB29 1K 1 2
VCC_FPGA_3V3 VCC5_MM 120ohms, 3.5A , 0805 1 2
FB28 3 4
Q7 3 4
1 FERR 2 2 FERR 1 5 6
FB30 BC817-40 5 6
7 8
7 8

1
C228 120ohms, 3.5A , 0805 FB/330/1.5A 9 10
0.1uF U36 9 10 C229
1 FERR 2
74LVCH16245A CN6 HEADER 5X2 0.01uF
18

42
31

2
7

FB31 FB/330/1.5A 1 2
DGND D20 MMBD4148 1 2 DGND LEDBAT1
1 2 FERR 1 3 4
VCC1
VCC1

VCC2
VCC2

1ATOB 3 4 DGND
48 5 6
n1OE D21 5 6 VCC5_MM VCC5_MM VCC5_MM
7 8
TCCB0 FB32 FB/330/1.5A 7 8
TCC0 2 47 9 10
1B1 1A1 9 10

7
TCC1 3 46 TCCB1 MMBD4148 2 FERR 1 FB33 11 12

1
1B2 1A2 TCCB2 D22 11 12
TCC2 5 44 2 FERR 1 13 14 2 DGND
1B3 1A3 TCCB3 FB34 FB/330/1.5A 13 14 R295 R296 R297
TCC3 6 43 15 16 3 FTE_TXD5
1B4 1A4 MMBD4148 FB/330/1.5A 15 16
IBPB_D0 8 41 2 FERR 1 17 18