http://hdlplanet.tripod.com/verilog/verilog-manual.

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1.SIMULATION OF LOGIC GATES

module logicgates(in1,in2,out1,out2,out3,out4,out5,out6,out7, out8);

input in1,in2;
output out1,out2,out3,out4,out5,out6,out7,out8;
assign out1=in1&in2;
assign out2=in1|in2;
assign out3=~(in1);
assign out4=~(in2);
assign out5=~(in1&in2);
assign out6=~(in1|in2);
assign out7=in1^in2;
assign out8=~(in1^in2);
endmodule

2.1. SYNTHESIS OF FULL ADDER

module fulladder(in1,in2,in3,sum,carry);
input in1,in2,in3;
output sum,carry;
assign sum=(in1^in2)^in3;

assign carry=((in1&in2)|(in1&in3)|(in2&in3));
endmodule
2.2. SYNTHESIS OF HALF ADDER

module halfadder(in1,in2,sum,carry);
input in1,in2;
output sum,carry;
assign sum=(in1^in2);
assign carry=in1&in2;
endmodule

3. 12 BIT SERIAL ADDER

module sadd(sum,carry);
output[11:0]sum;
output[3:0]carry;
reg[11:0]sum;
reg[3:0]carry;
reg[11:0]in1=12'b111100101100;//F2C
reg[11:0]in2=12'b110111000101;//DC5
reg[11:0]in3=12'b000100110011;//133
reg[11:0]in4=12'b010101101001;//569
reg[11:0]in5=12'b101001000111;//A47
reg[11:0]in6=12'b011010001101;//68D
reg[11:0]in7=12'b100111001111;//9CF
reg[11:0]in8=12'b111001110110;//E76
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
wire[11:0]sum1;
reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[2:0]car0=3'b000;
wire[2:0]car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12;
reg[14:0]c=15'b000000000000000;
reg[15:0]res=16'b0000000000000000;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
end

fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1);
fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2);
fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3);
fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4);
fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5);
fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6);
fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7);
fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8);
fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9);
fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10);
fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],car11);
fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],car12);
always@(car12,sum1,temp1,c,res)
begin
c<={car12,sum1};
res<=temp1-c;
sum<=res[11:0];
carry<=res[15:12];
end
endmodule
//fhadd(8 bit addition)
module fhadd(i1,i2,i3,i4,i5,i6,i7,i8,cp,s,c);
input i1,i2,i3,i4,i5,i6,i7,i8;
input [2:0]cp;

output s;
output [2:0]c;
reg s;
reg [2:0]c;
reg [3:0]s2;
wire [3:0]s1;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18;
wire ca1,ca2,ca3,ca4,ca5,ca6,ca7,ca8,ca9,ca10,ca11,ca12;
wire ca13,ca14,ca15,ca16,ca17,ca18,ca19,ca20,ca21,ca22;
hala ha1(i1,i2,x1,ca1);
hala ha2(x1,i3,x2,ca2);
hala ha3(x2,i4,x3,ca3);
hala ha4(x3,i5,x4,ca4);
hala ha5(x4,i6,x5,ca5);
hala ha6(x5,i7,x6,ca6);
hala ha7(x6,i8,s1[0],ca7);
hala ha8(ca1,ca2,x7,ca8);
hala ha9(ca3,x7,x8,ca9);
hala hal0(ca4,x8,x9,ca10);
hala hal1(ca5,x9,x10,ca11);
hala hal2(ca6,x10,x11,ca12);
hala hal3(ca7,x11,s1[1],ca13);
hala hal4(ca8,ca9,x12,ca14);
hala hal5(ca10,x12,x13,ca15);
hala hal6(ca11,x13,x14,ca16);
hala hal7(ca12,x14,x15,ca17);
hala hal8(ca13,x15,s1[2],ca18);
hala hal9(ca14,ca15,x16,ca19);
hala ha20(ca16,x16,x17,ca20);
hala ha21(ca17,x17,x18,ca21);
hala ha22(ca18,x18,s1[3],ca22);
always@(s1,cp,s2)
begin
s2<=s1+cp;
s<=s2[0];
c<=s2[3:1];

end
endmodule
// hala(2 bit addition)
module hala(a,b,s,c);
input a,b;
output s,c;
reg s,c;
always@(a,b)
begin
s=a^b;
c=a&b;
end
endmodule

4. 12 BIT PARALLEL ADDER

module paralleladder(sum,carry);
output[11:0] sum;
output[3:0] carry;
reg[11:0] sum;
reg[3:0] carry;
reg in1=12'b111100101100;
reg in2=12'b110111000101;
reg in3=12'b000100110011;
reg in4=12'b010101101001;
reg in5=12'b101001000111;
reg in6=12'b011010001101;
reg in7=12'b100111001111;
reg in8=12'b111101110110;
reg[12:0] temp=13'b1000000000000;
reg[11:0] a1,a2,a3,a4,a5,a6,a7,a8;
reg[14:0] c=15'b000000000000000;
reg[15:0] res=16'b0000000000000000;

reg[15:0] temp1=16'b1000000000000000;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp,c,res)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
c<=a1+a2+a3+a4+a5+a6+a7+a8;
res<=temp1-c;
sum<=res[11:0];
carry<=res[15:12];
end
endmodule
5. 12 BIT SERIAL SUBTRACTOR
module ssub(res);
output[15:0]res;
reg s_sign;
reg[15:0]res;
reg[11:0]in1=12'b111111111111;
reg[11:0]in2=12'b000000000101;
reg[11:0]in3=12'b000000000011;
reg[11:0]in4=12'b000000001001;
reg[11:0]in5=12'b000000000111;
reg[11:0]in6=12'b000000001101;
reg[11:0]in7=12'b000000001111;
reg[11:0]in8=12'b000000000110;
reg[12:0] a1,a2,a3,a4,a5,a6,a7,a8;
reg[12:0]temp1=13'b1000000000000;

wire[11:0] sum1;
wire[2:0] car0 = 3'b000;
wire[2:0] car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12;
reg[14:0] c = 15'b000000000000000;
reg[12:0]temp=13'b10000000000000;

always@(temp1,in1,in2,in3,in4,in5,in6,in7,in8)
begin
a1<={1'b0,in1};
a2<=temp1-in2;
a3<=temp1-in3;
a4<=temp1-in4;
a5<=temp1-in5;
a6<=temp1-in6;
a7<=temp1-in7;
a8<=temp1-in8;
end
fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1);
fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2);
fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3);
fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4);
fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5);
fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6);
fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7);
fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8);
fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9);
fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10);
fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],car11);
fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],car12);
always@(car12,sum1,temp)
begin
if (car12 == 3'b111)
begin
s_sign <= 1'b0; //(no carry)
res<= {4'b0000,sum1};
end
else
begin

s_sign <= 1'b1; //( carry)

res<= {3'b000,(temp-sum1)};
end
end
endmodule
6. 12 BIT PARALLEL SUBTRACTOR
module parallelsub(res);
output[15:0]res;
reg s_sign;
reg[15:0]res;
reg[11:0]in1=12'b111111111111;
reg[11:0]in2=12'b000000000101;
reg[11:0]in3=12'b000000000011;
reg[11:0]in4=12'b000000001001;
reg[11:0]in5=12'b000000000111;
reg[11:0]in6=12'b000000001101;
reg[11:0]in7=12'b000000001111;
reg[11:0]in8=12'b000000000110;
reg[16:0] store,res1;
reg[16:0]temp=17'b10000000000000000;
reg[16:0] p1,p2;

always@(in1,in2,in3,in4,in5,in6,in7,in8,temp,p1,p2,res1,store)
begin
//store<= {5'b00000,in1}+{5'b00000,in2}+{5'b00000,in3}+{5'b00000,in4}+{5'b00000,in5}+{5'b00000,in6}
//+{5'b00000,in7}+{5'b00000,in8};
store<= {5'b00000,in2}+{5'b00000,in3}+{5'b00000,in4}+{5'b00000,in5}+{5'b00000,in6}
+{5'b00000,in7}+{5'b00000,in8};
p1<= temp-store[15:0];
//p2<=p1;
p2<=in1+p1;

if(p2[16]==1'b1)
begin

res<=p2[15:0];
s_sign<=1'b0;
end

else
begin
res1<= temp-p2;
res<= res1[15:0];
s_sign<=1'b1;
end
end
endmodule
7. TRAFFIC LIGHT CONTROLLER IN VERILOG HDL
module tlc(clk,reset,p1,p2,p3,p4,pl);
input clk;
input reset;
output[4:0]p1;
output[4:0]p2;
output[4:0]p3;
output[4:0]p4;
output[3:0]pl;
reg[4:0]p1;
reg[4:0]p2;
reg[4:0]p3;
reg[4:0]p4;
reg[3:0]pl;
reg[5:0]sig;
always @(posedge clk or negedge reset)
begin
if(reset==1'b0)
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;

p4<=5'b00100;
pl<=4'b1111;
sig<=6'b000000;
end
else
begin
sig<=sig+1;
case(sig[5:0])
6'b000000:
begin
p1<=5'b10011;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b000100:
begin
p1<=5'b01000;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001000:
begin
p1<=5'b00100;
p2<=5'b10011;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001100:
begin
p1<=5'b00100;
p2<=5'b01000;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010000:
begin

p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;
p4<=5'b00100;
pl<=4'b1111;
end
6'b011000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;
pl<=4'b1111;
end
6'b011100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b01000;
pl<=4'b1111;
end
6'b100000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b0000;
end
6'b100100:sig<=6'b000000;
default:begin
end

endcase
end
end
endmodule

8. STUDY OF LED AND SWITCHES

module iotest(sw, led);
input [15:0] sw;
output [15:0] led;
assign led=sw;
endmodule
USER CONSTRIANT FILE
NET "sw<0>" LOC ="t14" ;
NET "sw<1>" LOC ="t12" ;
NET "sw<2>" LOC ="t9" ;
NET "sw<3>" LOC ="t7" ;
NET "sw<4>" LOC ="t2" ;
NET "sw<5>" LOC ="g12" ;
NET "sw<6>" LOC ="h1" ;
NET "sw<7>" LOC ="r3" ;
NET "sw<8>" LOC ="n11" ;
NET "sw<9>" LOC ="n3" ;
NET "sw<10>" LOC ="m13" ;
NET "sw<11>" LOC ="m7" ;
NET "sw<12>" LOC ="m3" ;
NET "sw<13>" LOC ="k4" ;
NET "sw<14>" LOC ="j12" ;
NET "sw<15>" LOC ="j11" ;
NET "led<0>" LOC ="r1" ;
NET "led<1>" LOC ="r2" ;
NET "led<2>" LOC ="k3" ;
NET "led<3>" LOC ="t4" ;
NET "led<4>" LOC ="t5" ;
NET "led<5>" LOC ="r6" ;
NET "led<6>" LOC ="t8" ;
NET "led<7>" LOC ="r10" ;

NET "led<8>" LOC ="n10" ;

NET "led<9>" LOC ="p12" ;
NET "led<10>" LOC ="n9" ;
NET "led<11>" LOC ="n12" ;
NET "led<12>" LOC ="p13" ;
NET "led<13>" LOC ="r13" ;
NET "led<14>" LOC ="t13" ;
NET "led<15>" LOC ="p14" ;
9. TRAFFIC LIGHT CONTROLLER IN FPGA BOARD
module tlc(clk,reset,p1,p2,p3,p4,p);
input clk;
input reset;
output[4:0]p1;
output[4:0]p2;
output[4:0]p3;
output[4:0]p4;
output[3:0]p;
reg[4:0]p1;
reg[4:0]p2;
reg[4:0]p3;
reg[4:0]p4;
reg[3:0]p;
reg[31:0]sig;
always @(posedge clk or negedge reset)
begin
if(reset==1'b0)
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
sig<=8'h0;
end
else
begin
sig<=sig+1;
case(sig[29:24])

6'b000000:
begin
p1<=5'b10011;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b000100:
begin
p1<=5'b01000;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b001000:
begin
p1<=5'b00100;
p2<=5'b10011;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b001100:
begin
p1<=5'b00100;
p2<=5'b01000;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b1111;
end
6'b010000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;
p4<=5'b00100;
p<=4'b1111;
end
6'b010100:
begin

p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;
p4<=5'b00100;
p<=4'b1111;
end
6'b011000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;
p<=4'b1111;
end
6'b011100:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b01000;
p<=4'b1111;
end
6'b100000:
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p<=4'b0000;
end
6'b100100:sig<=8'h0;
default:begin
end
endcase
end
end
endmodule

USER CONSTRIANT FILE

NET "clk" LOC = "a8";

NET "reset" LOC = "j6";
NET "p1<0>" LOC = "b14";
NET "p1<1>" LOC = "c16";
NET "p1<2>" LOC = "d15";
NET "p1<3>" LOC = "f14";
NET "p1<4>" LOC = "g14";
NET "p2<0>" LOC = "g16";
NET "p2<1>" LOC = "h15";
NET "p2<2>" LOC = "k15";
NET "p2<3>" LOC = "f15";
NET "p2<4>" LOC = "g15";
NET "p3<0>" LOC = "h14";
NET "p3<1>" LOC = "j16";
NET "p3<2>" LOC = "k16";
NET "p3<3>" LOC = "m16";
NET "p3<4>" LOC = "n16";
NET "p4<0>" LOC = "p16";
NET "p4<1>" LOC = "r16";
NET "p4<2>" LOC = "c15";
NET "p4<3>" LOC = "d14";
NET "p4<4>" LOC = "e16";
NET "p<0>" LOC = "l15";
NET "p<1>" LOC = "n15";
NET "p<2>" LOC = "p15";
NET "p<3>" LOC = "r15";

10. REAL TIME CLOCK ON FPGA

module realtimelock(clk,rst,sl,atoh);
input clk; // System Clock
input rst; // Reset(micro switch)
output[5:0] sl; // Segment Selection
output[7:0] atoh; // Segment Display Control Data
reg[5:0] sl;
reg[7:0] atoh;
reg[26:0] sig2;
reg[19:1] sig3;

reg[7:0] ssdigit1;
reg[7:0] ssdigit2;
reg[7:0] ssdigit3;
reg[7:0] ssdigit4;
reg[7:0] ssdigit5;
reg[7:0] ssdigit6;
integer digit1;
integer digit2;
integer digit3;
integer digit4;
integer digit5;
integer digit6;
always @ (posedge clk or negedge rst)
begin
if (rst == 1'b0) begin
sig2 = 0;
sig3 = 0;
digit1 = 0;
digit2 = 0;
digit3 = 0;
digit4 = 0;
digit5 = 0;
digit6 = 0;
end
else begin
sig2 = sig2 + 1;
case (sig2[24:23]) //RTC Function
2'b00 : begin
digit6 = digit6 + 1;
if (digit6 > 9) begin
digit6 = 0;
digit5 = digit5 + 1;
if (digit5 > 5) begin
digit5 =0;
digit4 = digit4 + 1;
if (digit4 >9 ) begin
digit4 = 0;
digit3 = digit3 + 1;
if (digit3 > 5) begin
digit3 = 0;

digit2 = digit2 + 1;
if (digit2 >9) begin
digit2 = 0;
digit1 = digit1 + 1; if ((digit1 >= 2) & (digit2 >= 4)) begin digit1 = 0;
digit2 = 0;
end
end
end
end
end
end
sig2[24:23] = 2'b01;
end
2'b11 : begin
if (sig2[22:19] == 4'b1001)
sig2 = 0;
end
default : begin
end
endcase
end
// Display Settings
sig3 = sig3 + 1;
case (sig3[17:15])
3'b000 : begin
sl = 6'b111110;
case (digit1)
0 : ssdigit1 = 8'b00111111;
1 : ssdigit1 = 8'b00000110;
2 : ssdigit1 = 8'b01011011;
default : ssdigit1 = 8'b00000000;
endcase
atoh = ssdigit1;
end
3'b001 : begin
sl = 6'b111101;
case (digit2)
0 : ssdigit2 = 8'b00111111;
1 : ssdigit2 = 8'b00000110;
2 : ssdigit2 = 8'b01011011;
3 : ssdigit2 = 8'b01001111;

4 : ssdigit2 = 8'b01100110;
5 : ssdigit2 = 8'b01101101;
6 : ssdigit2 = 8'b01111101;
7 : ssdigit2 = 8'b00000111;
8 : ssdigit2 = 8'b01111111;
9 : ssdigit2 = 8'b01101111;
default : ssdigit2 = 8'b00000000;
ndcase
atoh = ssdigit2;
end
3'b011 : begin
sl = 6'b111011;
case (digit3)
0 : ssdigit3 = 8'b00111111;
1 : ssdigit3 = 8'b00000110;
2 : ssdigit3 = 8'b01011011;
3 : ssdigit3 = 8'b01001111;
4 : ssdigit3 = 8'b01100110;
5 : ssdigit3 = 8'b01101101;
default : ssdigit3 = 8'b00000000;
endcase
atoh = ssdigit3;
end
3'b100 : begin
sl = 6'b110111;
case (digit4)
0 : ssdigit4 = 8'b00111111;
1 : ssdigit4 = 8'b00000110;
2 : ssdigit4 = 8'b01011011;
3 : ssdigit4 = 8'b01001111;
4 : ssdigit4 = 8'b01100110;
5 : ssdigit4 = 8'b01101101;
6 : ssdigit4 = 8'b01111101;
7 : ssdigit4 = 8'b00000111;
8 : ssdigit4 = 8'b01111111;
9 : ssdigit4 = 8'b01101111;
default : ssdigit4 = 8'b00000000;
endcase
atoh = ssdigit4;
end
3'b110 : begin
sl = 6'b101111;

case (digit5)
0 : ssdigit5 = 8'b00111111;
1 : ssdigit5 = 8'b00000110;
2 : ssdigit5 = 8'b01011011;
3 : ssdigit5 = 8'b01001111;
4 : ssdigit5 = 8'b01100110;
5 : ssdigit5 = 8'b01101101;
default : ssdigit5 = 8'b00000000;
endcase
atoh = ssdigit5;
end
3'b111 : begin
sl = 6'b011111;
case (digit6)
0 : ssdigit6 = 8'b00111111;
1 : ssdigit6 = 8'b00000110;
2 : ssdigit6 = 8'b01011011;
3 : ssdigit6 = 8'b01001111;
4 : ssdigit6 = 8'b01100110;
5 : ssdigit6 = 8'b01101101;
6 : ssdigit6 = 8'b01111101;
7 : ssdigit6 = 8'b00000111;
8 : ssdigit6 = 8'b01111111; 9 : ssdigit6 = 8'b01101111;
default : ssdigit6 = 8'b00000000;
endcase
atoh = ssdigit6;
end
endcase
end
end
endmodule
USER CONSTRIANT FILE
NET "clk" LOC = "a8";
NET "rst" LOC = "j6";
NET "atoh<0>" LOC = "p8" ;
NET "atoh<1>" LOC = "p10" ;
NET "atoh<2>" LOC = "p9" ;
NET "atoh<3>" LOC = "p6" ;
NET "atoh<4>" LOC = "p4" ;

NET "atoh<5>" LOC = "p5" ;

NET "atoh<6>" LOC = "p3" ;
NET "atoh<7>" LOC = "p11" ;
NET "sl<0>" LOC = "p1" ;
NET "sl<1>" LOC = "p2" ;
NET "sl<2>" LOC = "p7" ;
NET "sl<3>" LOC = "r4" ;
NET "sl<4>" LOC = "r11" ;
NET "sl<5>" LOC = "n14" ;

11. UP_DOWN COUNTER

//Following is the Verilog code for a 4-bit unsigned Up/Down counter with asynchronous reset.
module counter (clk,reset,up_down,Q);
input clk, reset, up_down;
output [3:0] Q;
reg [3:0] tmp;
always @ (posedge clk or posedge reset)
begin
if(reset==0)
tmp = 4'b0000;
else
if (up_down==1)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule
12. SHIFT REGISTER
module shiftreg(E,A,clk,reset);
output A;
input E,clk,reset;
reg A,B,C,D;

always@(posedge clk or negedge reset)

begin
if(reset==0)
begin
A=0;B=0;C=0;D=0;
end
else
begin
A<=B;
D<=E;
C<=D;
B<=C;
end
end
endmodule

13. SEVEN SEGMENT DISPLAY

module decoder (count,seven_seg);
input[3:0] count;
output[6:0] seven_seg;
reg[6:0]seven_seg;

//seven segment display pattern

parameter zero=7'b1000000;
parameter one=7'b1111001;
parameter two=7'b0100100;
parameter three=7'b0110000;
parameter four=7'b0011001;
parameter five=7'b0010010;
parameter six=7'b0000010;
parameter seven=7'b1111000;
parameter eight=7'b0000000;
parameter nine=7'b0010000;
parameter dash=7'b0111111;

//display count value on seven segment displays

always@(count)
case (count)
0:seven_seg= zero;
1:seven_seg= one;
2:seven_seg= two;
3:seven_seg= three;
4:seven_seg= four;
5:seven_seg= five;
6:seven_seg= six;
7:seven_seg= seven;
8:seven_seg= eight;
9:seven_seg= nine;
default:seven_seg= dash;
endcase
endmodule
14. MULTIPLEXER
module two_to_onemux(a,b,s,out);
input a,b,s;
output out;
wire sbar;
assign sbar=~(s);
assign out=(s&b)|(sbar&a);
end module
15. FOUR BIT ADDER
module fourbitadder(a,b,c,sum,carryout);
input[3:0]a,b;
output [3:0]sum;
input c;
output carryout;
wire [2:0]carry;

onebitadder ob1(a[0],b[0],c,sum[0],carry[0]);
onebitadder ob2(a[1],b[1],carry[0],sum[1],carry[1]);
onebitadder ob3(a[2],b[2],carry[1],sum[2],carry[2]);
onebitadder ob4(a[3],b[3],carry[2],sum[3],carryout);
endmodule
//onebit adder//
module onebitadder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=(a^b)^c;
assign carry=(a&b)|(a&c)|(b&c);
endmodule

Following is the Verilog code for flip-flop with a positive-edge clock.

module
input
output
reg

flop (clk, d, q);

clk, d;
q;
q;

always @(posedge clk)

begin
q <= d;
end
endmodule

Following is Verilog code for a flip-flop with a negative-edge clock and asynchronous clear.
module flop (clk, d, clr, q);
input clk, d, clr;
output q;
reg
q;
always @(negedge clk or posedge clr)
begin
if (clr)
q <= 1b0;
else
q <= d;
end
endmodule

Following is Verilog code for the flip-flop with a positive-edge clock and synchronous set.
module flop (clk, d, s, q);
input clk, d, s;
output q;
reg
q;
always @(posedge clk)
begin
if (s)
q <= 1b1;
else
q <= d;
end
endmodule

Following is Verilog code for the flip-flop with a positive-edge clock and clock enable.
module flop (clk, d, ce, q);
input clk, d, ce;
output q;
reg
q;
always @(posedge clk)
begin
if (ce)
q <= d;
end
endmodule

Following is Verilog code for a 4-bit register with a positive-edge clock, asynchronous set
and clock enable.
module flop (clk, d, ce, pre, q);
input
clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg
[3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4b1111;
else if (ce)
q <= d;
end
endmodule

Following is the Verilog code for a latch with a positive gate.

module latch (g, d, q);
input g, d;
output q;
reg
q;
always @(g or d)
begin
if (g)
q <= d;
end
endmodule

Following is the Verilog code for a latch with a positive gate and an asynchronous clear.
module latch (g, d, clr, q);
input g, d, clr;
output q;
reg
q;
always @(g or d or clr)
begin
if (clr)
q <= 1b0;
else if (g)
q <= d;
end
endmodule

Following is Verilog code for a 4-bit latch with an inverted gate and an asynchronous
preset.
module latch (g, d, pre, q);
input
g, pre;
input [3:0] d;
output [3:0] q;
reg
[3:0] q;
always @(g or d or pre)
begin
if (pre)
q <= 4b1111;
else if (~g)
q <= d;
end
endmodule

Following is Verilog code for a tristate element using a combinatorial process and always
block.
module three_st (t, i, o);
input t, i;
output o;
reg
o;
always @(t or i)
begin
if (~t)
o = i;
else
o = 1bZ;

end
endmodule

Following is the Verilog code for a tristate element using a concurrent assignment.
module three_st (t, i, o);
input t, i;
output o;
assign o = (~t) ? i: 1bZ;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear.
module counter (clk, clr, q);
input
clk, clr;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned down counter with synchronous set.
module counter (clk, s, q);
input
clk, s;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4b1111;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous load
from the primary input.
module counter (clk, load, d, q);
input
clk, load;
input [3:0] d;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with a synchronous load with
a constant.
module counter (clk, sload, q);
input
clk, sload;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= 4b1010;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous clear
and a clock enable.
module counter (clk, clr, ce, q);
input
clk, clr, ce;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)

tmp <= 4b0000;

else if (ce)
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up/down counter with an asynchronous
clear.
module counter (clk, clr, up_down, q);
input
clk, clr, up_down;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else if (up_down)
tmp <= tmp + 1b1;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset.
module counter (clk, clr, q);
input
clk, clr;
output signed [3:0] q;
reg
signed [3:0] tmp;
always @ (posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset and
a modulo maximum.

module counter (clk, clr, q);

parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);
input
clk, clr;
output [MAX_SQRT-1:0] q;
reg
[MAX_SQRT-1:0] cnt;
always @ (posedge clk or posedge clr)
begin
if (clr)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign q = cnt;
endmodule

Following is the Verilog code for a 4-bit unsigned up accumulator with an asynchronous
clear.
module accum (clk, clr, d, q);
input
clk, clr;
input [3:0] d;
output [3:0] q;
reg
[3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + d;
end
assign q = tmp;
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, serial
in and serial out.
module shift (clk, si, so);
input
clk,si;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock, a
clock enable, a serial in and a serial out.
module shift (clk, ce, si, so);
input
clk, si, ce;
output
so;
reg
[7:0] tmp;
always @(negedge clk)
begin
if (ce) begin
tmp
<= tmp << 1;
tmp[0] <= si;
end
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock,
asynchronous clear, serial in and serial out.
module shift (clk, clr, si, so);
input
clk, si, clr;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 8b00000000;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
synchronous set, a serial in and a serial out.
module shift (clk, s, si, so);
input
clk, si, s;
output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 8b11111111;

else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
serial in and a parallel out.
module shift (clk, si, po);
input
clk, si;
output [7:0] po;
reg
[7:0] tmp;
always @(posedge clk)
begin
tmp <= {tmp[6:0], si};
end
assign po = tmp;
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, an
asynchronous parallel load, a serial in and a serial out.
module shift (clk, load, si, d, so);
input
clk, si, load;
input [7:0] d;
output
so;
reg
[7:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, a
synchronous parallel load, a serial in and a serial out.
module shift (clk, sload, si, d, so);
input
clk, si, sload;
input [7:0] d;

output
so;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left/shift-right register with a positive-edge
clock, a serial in and a serial out.
module shift (clk, si, left_right, po);
input
clk, si, left_right;
output
po;
reg
[7:0] tmp;
always @(posedge clk)
begin
if (left_right == 1b0)
tmp <= {tmp[6:0], si};
else
tmp <= {si, tmp[7:1]};
end
assign po = tmp;
endmodule

Following is the Verilog code for a 4-to-1 1-bit MUX using an If statement.
module mux (a, b, c, d, s, o);
input
a,b,c,d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if (s == 2b00)
o = a;
else if (s == 2b01)
o = b;
else if (s == 2b10)
o = c;
else
o = d;
end
endmodule

Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input
a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
case (s)
2b00
: o = a;
2b01
: o = b;
2b10
: o = c;
default : o = d;
endcase
end
endmodule

Following is the Verilog code for a 3-to-1 1-bit MUX with a 1-bit latch.
module mux (a, b, c, d, s, o);
input
a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if (s == 2b00)
o = a;
else if (s == 2b01)
o = b;
else if (s == 2b10)
o = c;
end
endmodule

Following is the Verilog code for a 1-of-8 decoder.

module
input
output
reg
always

mux (sel, res);

[2:0] sel;
[7:0] res;
[7:0] res;
@(sel or res)

begin
case (sel)
3b000
3b001
3b010
3b011
3b100
3b101
3b110
default
endcase
end
endmodule

:
:
:
:
:
:
:
:

res
res
res
res
res
res
res
res

=
=
=
=
=
=
=
=

8b00000001;
8b00000010;
8b00000100;
8b00001000;
8b00010000;
8b00100000;
8b01000000;
8b10000000;

Following Verilog code leads to the inference of a 1-of-8 decoder.

module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg
[7:0] res;
always @(sel or res) begin
case (sel)
3b000 : res = 8b00000001;
3b001 : res = 8b00000010;
3b010 : res = 8b00000100;
3b011 : res = 8b00001000;
3b100 : res = 8b00010000;
3b101 : res = 8b00100000;
// 110 and 111 selector values are unused
default : res = 8bxxxxxxxx;
endcase
end
endmodule

Following is the Verilog code for a 3-bit 1-of-9 Priority Encoder.

module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg
[2:0] code;
always @(sel)
begin
if (sel[0])
code = 3b000;
else if (sel[1])
code = 3b001;
else if (sel[2])
code = 3b010;

else if
code
else if
code
else if
code
else if
code
else if
code
else
code

(sel[3])
= 3b011;
(sel[4])
= 3b100;
(sel[5])
= 3b101;
(sel[6])
= 3b110;
(sel[7])
= 3b111;
= 3bxxx;

end
endmodule

Following is the Verilog code for a logical shifter.

module lshift (di, sel, so);
input [7:0] di;
input [1:0] sel;
output [7:0] so;
reg
[7:0] so;
always @(di or sel)
begin
case (sel)
2b00
: so = di;
2b01
: so = di << 1;
2b10
: so = di << 2;
default : so = di << 3;
endcase
end
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry in.
module
input
input
input
output

adder(a, b, ci, sum);

[7:0] a;
[7:0] b;
ci;
[7:0] sum;

assign sum = a + b + ci;

endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry out.

module
input
input
output
output
wire

adder(a, b, sum, co);

[7:0] a;
[7:0] b;
[7:0] sum;
co;
[8:0] tmp;

assign tmp = a + b;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out.
module
input
input
input
output
output
wire

adder(a, b, ci, sum, co);

ci;
[7:0] a;
[7:0] b;
[7:0] sum;
co;
[8:0] tmp;

assign tmp = a + b + ci;

assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Following is the Verilog code for an unsigned 8-bit adder/subtractor.

module addsub(a, b, oper, res);
input
oper;
input [7:0] a;
input [7:0] b;
output [7:0] res;
reg
[7:0] res;
always @(a or b or oper)
begin
if (oper == 1b0)
res = a + b;
else
res = a - b;
end
endmodule

Following is the Verilog code for an unsigned 8-bit greater or equal comparator.
module compar(a, b, cmp);
input [7:0] a;
input [7:0] b;
output
cmp;
assign cmp = (a >= b) ?

1b1 : 1b0;

endmodule

Following is the Verilog code for an unsigned 8x4-bit multiplier.

module
input
input
output

compar(a, b, res);
[7:0] a;
[3:0] b;
[11:0] res;

assign res = a * b;
endmodule

Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as single registers.
module
input
input
input
output
reg
reg
wire
reg

mult(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_1, pipe_2, pipe_3;

assign mult_res = a_in * b_in;

always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
mult
<= pipe_3;

end
endmodule

Following Verilog template shows the multiplication operation placed inside the always
block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input
clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg
[35:0] mult;
reg
[17:0] a_in, b_in;
reg
[35:0] mult_res;
reg
[35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
mult_res <= a_in * b_in;
pipe_2
<= mult_res;
pipe_3
<= pipe_2;
mult
<= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as single registers.
module
input
input
input
output
reg
reg
wire
reg

mult(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_1, pipe_2, pipe_3;

assign mult_res = a_in * b_in;

always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;

mult
<= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed inside the always
block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input
clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg
[35:0] mult;
reg
[17:0] a_in, b_in;
reg
[35:0] mult_res;
reg
[35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in
<= a;
b_in
<= b;
mult_res <= a_in * b_in;
pipe_2
<= mult_res;
pipe_3
<= pipe_2;
mult
<= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed outside the always
block and the pipeline stages represented as shift registers.
module
input
input
input
output
reg
reg
wire
reg

mult3(clk, a, b, mult);
clk;
[17:0] a;
[17:0] b;
[35:0] mult;
[35:0] mult;
[17:0] a_in, b_in;
[35:0] mult_res;
[35:0] pipe_regs [3:0];

assign mult_res = a_in * b_in;

always @(posedge clk)
begin
a_in <= a;
b_in <= b;
{pipe_regs[3],pipe_regs[2],pipe_regs[1],pipe_regs[0]} <=
{mult, pipe_regs[3],pipe_regs[2],pipe_regs[1]};

end
endmodule

Following templates to implement Multiplier Adder with 2 Register Levels on Multiplier

Inputs in Verilog.
module mvl_multaddsub1(clk, a, b, c, res);
input
clk;
input [07:0] a;
input [07:0] b;
input [07:0] c;
output [15:0] res;
reg
[07:0] a_reg1, a_reg2, b_reg1, b_reg2;
wire
[15:0] multaddsub;
always @(posedge clk)
begin
a_reg1 <= a;
a_reg2 <= a_reg1;
b_reg1 <= b;
b_reg2 <= b_reg1;
end
assign multaddsub = a_reg2 * b_reg2 + c;
assign res = multaddsub;
endmodule

Following is the Verilog code for resource sharing.

module addsub(a, b, c, oper, res);
input
oper;
input [7:0] a;
input [7:0] b;
input [7:0] c;
output [7:0] res;
reg
[7:0] res;
always @(a or b or c or oper)
begin
if (oper == 1b0)
res = a + b;
else
res = a - c;
end
endmodule

Following templates show a single-port RAM in read-first mode.

module raminfr (clk, en, we, addr, di, do);

input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule

Following templates show a single-port RAM in write-first mode.

module raminfr (clk, we, en, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[4:0] read_addr;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule

Following templates show a single-port RAM in no-change mode.

module raminfr (clk, we, en, addr, di, do);
input
clk;
input
we;
input
en;

input [4:0] addr;

input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
else
do <= RAM[addr];
end
end
endmodule

Following is the Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule

Following is the Verilog code for a single-port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
do <= ram[a];

end
endmodule

Following is the Verilog code for a single-port RAM with synchronous read (read through).
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule

Following is the Verilog code for a single-port block RAM with enable.
module raminfr (clk, en, we, a, di, do);
input
clk;
input
en;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule

Following is the Verilog code for a dual-port RAM with asynchronous read.

module raminfr (clk, we, a, dpra, di, spo, dpo);

input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule

Following is the Verilog code for a dual-port RAM with false synchronous read.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[3:0] spo;
reg
[3:0] dpo;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
spo = ram[a];
dpo = ram[dpra];
end
endmodule

Following is the Verilog code for a dual-port RAM with synchronous read (read through).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;

input [3:0] di;

output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
reg
[4:0] read_dpra;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule

Following is the Verilog code for a dual-port RAM with enable on each port.
module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);
input
clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;
reg
[3:0] ram [31:0];
reg
[4:0] read_addra, read_addrb;
always @(posedge clk)
begin
if (ena) begin
if (wea) begin
ram[addra] <= dia;
end
end
end
always @(posedge clk)
begin
if (enb) begin
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule

Following is Verilog code for a ROM with registered output.

module rominfr (clk, en, addr, data);

input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4b0000: data
4b0001: data
4b0010: data
4b0011: data
4b0100: data
4b0101: data
4b0110: data
4b0111: data
4b1000: data
4b1001: data
4b1010: data
4b1011: data
4b1100: data
4b1101: data
4b1110: data
4b1111: data
default: data
endcase
end
endmodule

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

4b0010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4b1010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4bXXXX;

Following is Verilog code for a ROM with registered address.

module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
reg
[4:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end
always @(raddr)
begin
if (en)
case(raddr)
4b0000:
4b0001:
4b0010:
4b0011:
4b0100:
4b0101:

data
data
data
data
data
data

=
=
=
=
=
=

4b0010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;

4b0110:
4b0111:
4b1000:
4b1001:
4b1010:
4b1011:
4b1100:
4b1101:
4b1110:
4b1111:
default:
endcase

data
data
data
data
data
data
data
data
data
data
data

=
=
=
=
=
=
=
=
=
=
=

4b1100;
4b0000;
4b1010;
4b0010;
4b1110;
4b0010;
4b0100;
4b1010;
4b1100;
4b0000;
4bXXXX;

end
endmodule

Following is the Verilog code for an FSM with a single process.

module fsm (clk, reset, x1, outp);
input
clk, reset, x1;
output
outp;
reg
outp;
reg
[1:0] state;
parameter s1 = 2b00; parameter s2 = 2b01;
parameter s3 = 2b10; parameter s4 = 2b11;
always @(posedge clk or posedge reset)
begin
if (reset) begin
state <= s1; outp <= 1b1;
end
else begin
case (state)
s1: begin
if (x1 == 1b1) begin
state <= s2;
outp <= 1b1;
end
else begin
state <= s3;
outp <= 1b1;
end
end
s2: begin
state <= s4;
outp <= 1b0;
end
s3: begin
state <= s4;
outp <= 1b0;
end
s4: begin
state <= s1;
outp <= 1b1;
end

endcase
end
end
endmodule

Following is the Verilog code for an FSM with two processes.

module fsm (clk, reset, x1, outp);
input
clk, reset, x1;
output
outp;
reg
outp;
reg
[1:0] state;
parameter s1 = 2b00; parameter s2 = 2b01;
parameter s3 = 2b10; parameter s4 = 2b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else begin
case (state)
s1: if (x1 == 1b1)
state <= s2;
else
state <= s3;
s2: state <= s4;
s3: state <= s4;
s4: state <= s1;
endcase
end
end
always @(state) begin
case (state)
s1: outp = 1b1;
s2: outp = 1b1;
s3: outp = 1b0;
s4: outp = 1b0;
endcase
end
endmodule

Following is the Verilog code for an FSM with three processes.

module fsm (clk, reset, x1, outp);
input
clk, reset, x1;
output
outp;
reg
outp;
reg
[1:0] state;
reg
[1:0] next_state;

parameter s1 = 2b00; parameter s2 = 2b01;

parameter s3 = 2b10; parameter s4 = 2b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else
state <= next_state;
end
always @(state or x1)
begin
case (state)
s1: if (x1 == 1b1)
next_state = s2;
else
next_state = s3;
s2: next_state = s4;
s3: next_state = s4;
s4: next_state = s1;
endcase
end