Sistemas Digitais 2 Lista VHDL 1

Prof. Antonio Albiero

Frank F Freitas RA: 3783772357 ENG: eltrica 7Semestre
1. Porta NOT

Entity Fe is
port (A: in bit;
B: out bit);
end Fe;
architecture logica of Fe is
begin
B<= not A;
end lgica;
2. Porta AND

4 Uma porta AND.

entity nome_3 is
port (A,B,C,D: in bit;
g: out bit);
end nome_3;
architecture lgica of nome_3 is
begin
g<= A and B and
C and D;
end lgica;
5 Porta OR

Entity nome_1 is
port (a,b: in bit;
X: out bit);
end nome_1;
architecture lgica of nome_1 is
begin
X<= a and b;
end lgica;
3. Uma porta AND

entity nome_2 is
port (a,b,c: in bit;
y: out bit);
end nome_2;
architecture lgica of nome_2 is
begin
y<= a and b and
c;
end lgica;

entity nome_1 is
port (a,b: in bit;
X: out bit);
end nome_1;
architecture lgica of nome_1 is
begin
X<= a or b;
end lgica;

Sistemas Digitais 2 Lista VHDL 1

Prof. Antonio Albiero
Frank F Freitas RA: 3783772357 ENG: eltrica 7Semestre
6. Porta OR

entity nome_2 is
port (a,b,c: in bit;
y: out bit);
end nome_2;
architecture lgica of nome_2 is
begin
y<= a or b or c;
end lgica;
7. Porta NAND

8. Porta NAND.

entity none_2 is
port (a,b,c: in bit;
y: out bit);
end none_2;
architecture lgica of none_2 is
begin
y<= a nand b
nand c;
end lgica;
9. Porta NOR.

entity none_1 is
port (a,b: in bit;
X: out bit);
end none_1;
architecture lgica of none_1 is
begin
X<= a nand b;
end lgica;

entity nome_1 is
port (a,b: in bit;
X: out bit);
end nome_1;
architecture lgica of nome_1 is
begin
X<= a nor b;
end lgica;

Sistemas Digitais 2 Lista VHDL 1

Prof. Antonio Albiero
Frank F Freitas RA: 3783772357 ENG: eltrica 7Semestre
10. Uma porta NOR

entity nome_2 is
port (a,b,c: in bit;
y: out bit);
end nome_2;
architecture lgica of nome_2 is
begin
X<= a nor b nor
c;
end lgica;

11. Porta XOR

entity nome_1 is
port (a,b: in bit;
X: out bit);
end nome_1;
architecture lgica of nome_1 is
begin
X<= a xor b;
end lgica;

12. Porta XNOR

entity nome_1 is
port (a,b: in bit;
X: out bit);
end nome_1;
architecture lgica of nome_1 is
begin
X<= a xnor b;
end lgica;