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Wiley/Razavi/Fundamentals of Microelectronics
[Razavi.cls v. 2006]
119 (1)
120
Chap. 3
D1
Sec. 3.6
D1
Vout
Exame de Eletronica Aplicada
EE532
Chapter Summary
I in
R1
R 1 = 1 k!
Prof. Candido
V in
VB
10 deD julho
(a) de 2013
2
RD2
1
Nome:
RA:
(a)
R1
I in
1.1
(c)
119
R 1 = 1 k!
D2
Vout
D1
(b)
R2
VB
R1
R1
Vout
I in
R1
V in
Vout
D1
D1
V in
D1 R1
(d)
D2
Vout
R2
VB
V in
D1
(d)
Vout
1.3
(1.2) Existe umaD 1faixa de Vin para a qual apeD1
Figure
V in 3.80
V in
Vout
Voutao Vout = (Vin
nas D1 conduz,
quando ent
1.4
V
)[R
/(R
+
R
)].
D,on
2
1
2
2.1
R 1 = 1 k!
R 1 = 1 k!
D1
2.2
(1.3) Quando
V
>
2V
+ VB , D1 e D2 conin
V in
DD,on
2 V
2.3
duzem, e Vout = VB + VD,on .out
2.4
0.5 V
C1
(1.4) Quando Vin
(a)
(b)< 2VD,on +VB , D1 e D2 cortam,
3.1
e Vout = 0.
3.2
D1 R1
Figure 3.81
R1
o circuito a seguir. Vout
V in
V in
Vout 2. Considere
3.3
1 k!
1 k!
3.4
D2
D2
R2 2 k !
4.1
D3
D2
4.2
Vout
(c)
(d)
Vin
4.3
RL
Figure 3.78 4.4
D1
D
4.5
4
5.1
Figure
37. A 3-V adaptor
using
a 3.82
half-wave rectifier must supply a current of 0.5 A with a maximum
5.2
ripple of
300
mV.
For
a frequency of 60 Hz, compute
minimum
required
smoothing
5.3
(2.1) the
Durante
o ciclo
negativo
da entrada, D1 e
capacitor.
43. Suppose in Fig. 3.43, the diodes
a currenteofVout
5 mA
and the load, a current of 20 mA. If
5.4
D3carry
conduzem,
= 0.
38. Assume6.1
the input andthe
output
groundsincreases
in a full-wave
rectifier
areisshorted
together.
the
load current
to 21(2.2)
mA, what
theo change
in theDraw
total
across
Durante
ciclo negativo
davoltage
entrada,
D1 the
e three
output waveform
with
and
without
the
load
capacitor
and
explain
why
the
circuit
does
not
diodes?
Assume
is
much
greater
than
.
6.2
D2 conduzem, e Vout = Vin .
operate6.3
as a rectifier.
44. In this problem, we estimate the ripple seen by the load in Fig. 3.43 so as to appreciate
(2.3) Durante o ciclo positivo da entrada, D2 e
39. Plot the6.4
voltage across
diode in
Fig. 3.38(b)
a function
of time if neglect the load.. Also,
theeach
regulation
provided
by theasdiodes.
For simplicity,
Hz,
D cortam, e Vout = 0.
Assume a constant-voltage diodeF,model and
, and3 the.peak voltage
produced by the transformer is equal to 5
(2.4) Trata-se
de um retificador
de onda
Tabela
Quadro de arespostas.
V.full-wave rectifier, a student mistakenly
40.
While1:constructing
has swapped
the terminals
of completa,
assim chamado
por converter
ambos os mV,
ciclos
da
(a)3.82.
Assuming
carries
a relatively
constant current
and
estimate
the
as depicted in Fig.
Explain what
happens.
ripple amplitude across . entrada (positivo e negativo) numa mesma polari41. A full-wave rectifier is driven by a sinusoidal input
, where
V
dadeofde
da. determine the ripple amplitude across the
(b) Using the small-signal model
thesa
diodes,
and
. Assuming
mV, determine the ripple amplitude with a
load.
1000- F smoothing capacitor and a load resistance
of 30 . o circuito a seguir, no qual os transisto3. Considere
res t
em mesmo
e mesmo
IS .Plot the
42. Suppose the negative terminals of
and
in Fig.
3.38(b)
are shorted
together.
input-output characteristic assuming an ideal diode
model
and
explaining
why
thecomo
circuitfonte de cor(3.1) O transistor Q1 opera
does not operate as a full-wave rectifier.
rente.
(3.2) Desprezado o efeito Early, a impedancia (de
pequenos sinais) vista olhando-se para dentro da
base de Q2 (veja indicacao na figura) e aproximadamente 2r .
mentals of Microelectronics
[Razavi.cls v. 2006]
31. The op amp in Fig. 8.54 suffers from a finite gain. Calculate
in terms of
and .
369 (1)
32. Due to a manufacturing error, a parasitic resistance
has appeared in the adder of Fi
8.55. Calculate
in terms of
and
for
and
. (Note that
ca
RF
7.6
re 7.82
re 7.83
V1
V2
Chapter Summary
R2
X
Vout
369 A 0
R1
RP
VDD = 1.8 V
RG
Figure 8.55
RD
C2
C1
o amp-op
ter of
ganho
finito,
Valso
impedance
the op
amp.)a entrada inversora nao
out represent the input
M1
R2
V in
bos os
transistores e dada R pela
solucao da
(5.4) Considerando o ganho do amp-op infinito,
S Figure 8.56
equac
ao IC / = 2VT ln(IC /IS )/32k [VCC
a sada do circuito e Voutv.=
R [v1 /(R
||R ) +
BR
Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls
2006] F June
30,22007pat 13:42
696 (
2VT ln(IC /IS )]/18k.
v2 /(R
||R
)].
Basta
obter
o
equivalente
de shown in Fi
op amp exhibits a finite
input
impedance.
With
the
aid
of
the
op
amp
model
1
p
Th
eveninofparaand
cada .sinal de entrada e entao usar
8.43, determine
in terms
4. Considere o amplificador a seguir.
o
teorema
da
sobreposi
cao junto
comofaFig.
express
ao as a function
35. Plot the current flowing through
in the precision
rectifier
8.22(b)
conhecida
da
configura
c
a
o
inversora.
V for a sinusoidal input.
V = 1.8time
DD
R1
C1
RD
M1
V in
RS
V b1
V b1
Q3
V in
Q1
X
re 7.84
V in
D1
V out
Q3
Y
D1
Vout
o
Q
Q
se3
Figure 13.15
stage with realization
of 1current sources, (b) s
re 7.85
pende apenas de RD .
input. Use a constant-voltage
model(a)
forPush-pull
the diode.
guem
ao entre
of
.aproximadamente a mesma proporc
39. We
to improve as
thecorrentes
speed of the
rectifiercashown
in Fig.
8.22(b)
(4.3) O valor da corrente de polariza
c
ao wish
depende
de satura
o reversa
de D
. connecting a dio
1 e Q1by
from
node
to
ground.
Explain
how
this
can
be
accomplished.
de
R
,
mas
n
a
o
depende
de
R
nem
de
R
,
desde
S
D for both transistors
gain of 20 and a power budget
of 2 mW. Assume 1
(6.2) and
Em regime senoidal, a eficiencia desse amplique olevel
transistor
permane
ca saturado.
he maximum allowable
at the output
is 1.5
V (i.e.,
must remain
saturation
if from
40. Suppose
in in
Fig.
8.24 varies
V to que V.
Sketch
ficador
cresce
`a medida
aumentamos
aand
tens
ao as a function
V).
if the opeamp is ideal.
(4.4) A imped
ancia de entrada do amplificador
de
pico
da
carga.
circuit can be reduced to that shown in Fig. 13.16(a), revealing a strik
vez que
a corrente
de gate
Consider the circuit infinita,
shown inuma
Fig. 7.86,
where
is very
largedo
andtransis. que o sistema opere adequadamente, a
(6.3)VPara
V
tor e nula. Essa e a grande vantagem do transistor
corrente de polarizacao de Q3CCdeve ser pelo meMOS
em
rela
c
a
o
ao
bipolar.
(a) Calculate the voltage gain.
V b1 ao valor
nos igual
aximo da corrente na Vcarga
Q 3 m
Q3
b1
(b) Design the circuit
for a Os
voltage
gain of 15C1and
budget
of
3
mW.
Assume
(4.5)
capacitores
e aCpower
s
a
o
chamados
de
dividido
por
+
1,
e
a corrente de polarizac
ao de
S
1
Q
and the
dc level of de
the acoplamento,
output must be cuja
equalfun
to cao e evitar
.
capacitores
Q4 deve ser pelo menos igual1 ao modulo do valor
as incorporates
imped
anciasados
est
agios de
entrada
e sa
da
The CS stage of Fig.que
7.87
degenerated
PMOS
current
source.
Them
degenernimo da corrente na carga dividido por 2 + 1.
D1
amplificador
interfiram
no ponto
de polariza
ation must raise thedo
output
impedance
of the current
source
to aboutcao
such
that the
(6.4)
A aplicacao da entrada entre os diodos
D1
circuito.
voltage gain remainsdo
nearly
equal to the intrinsic gain of
. Assume
e for
naoboth
logo acima de D ou logo abaixo de D
1
(b)