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3
Introduo
A lei de Moore afirma que o nmero de transistores que podem ser colocados em
um circuito integrado dobra a cada 18 meses. Batizada em 1965 em homenagem a
seu criador, Gordon E. Moore, um dos fundadores da Intel, a lei vlida at hoje
graas produo de dispositivos cada vez menores.
4
Introduo
5
Estrutura e Operao Fsica do Dispositivo
0,1 m L 3 m Espessura
2 nm do oxido 50 nm
0,2 m W 100 m
Figure 4.1 Estrutura fssica do transistor NMOS tipo crescimento. : (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W
= 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. 6
Estrutura e Operao Fsica do Dispositivo
Operao sem tenso de porta ou de gate
Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate. 7
Estrutura e Operao Fsica do Dispositivo
Criando um canal para a circulao da corrente
Vt = 0,5 a 1 V
Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate. 8
Estrutura e Operao Fsica do Dispositivo
Aplicando um pequeno valor de VDS
Canal n induzido
VGS > Vt e
Condutncia controlada por VGS
VDS pequeno
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by
vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS. Note that the depletion
region is not shown (for simplicity). 9
Estrutura e Operao Fsica do Dispositivo
Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS,
is kept small. The device operates as a linear resistor whose value is controlled by vGS. 10
Estrutura e Operao Fsica do Dispositivo
A operao com um aumento de VDS
Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered
shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt. 11
Estrutura e Operao Fsica do Dispositivo
Corrente de dreno iD vs a tenso dreno-fonte vDS , para vGS > Vt
Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS >
Vt. 12
Estrutura e Operao Fsica do Dispositivo
Corrente de dreno iD vs a tenso dreno-fonte vDS , para vGS > Vt
vGD Vt
vGS vDS Vt
Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is pinched off
at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.
13
Estrutura e Operao Fsica do Dispositivo
Determinao da relao iD vs vDS
Cox ox Capacitncia por unidade de rea na regio do canal
tox
dq Cox (Wdx)[vGS v( x) Vt ]
dv( x )
E( x)
dx
15
Estrutura e Operao Fsica do Dispositivo
Determinao da relao iD vs vDS
O campo eltrico E(x) faz com que a carga dq se mova em direo ao dreno com uma
velocidade:
dx dv( x )
mn E ( x ) mn
dt dx
dq dq dx dv( x )
i mnCoxW [vGS v( x ) Vt ]
dt dx dt dx
dv( x )
iD i mnCoxW [vGS v( x ) Vt ]
dx
L vDS
i
0
D dx m C
0
n W [vGS v( x) Vt ]dv( x)
ox
W 1 2
iD ( mnCox )( )[(vGS Vt )vDS vDS ]
L 2
1 W
iD ( mnCox )( )(vGS Vt )2
2 L
17
Estrutura e Operao Fsica do Dispositivo
18
O MOSFET canal p
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known
as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown
are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.
19
As caractersticas de corrente-tenso
Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the
source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used
when the source is connected to the body or when the effect of the body on device operation is unimportant. 20
As caractersticas de iD x vDS
1 W
iD K n' ( )(vGS Vt )2
2 L
W 1 2
iD K n' ( ) (vGS Vt )vDS vDS
L 2
W
iD K n' ( )(vGS Vt )vDS
L
Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow
indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2. 21
As caractersticas de iD x vDS
1 W
iD K n' ( )(vGS Vt )2
2 L
W 1 2
iD K n' ( ) (vGS Vt )vDS vDS
L 2
W
iD K n' ( )(vGS Vt )vDS
L
1 1
rDS
W W
K n' (VGS Vt ) K n' VOV
L L
22
As caractersticas de iD x vDS
1 W
iD K n' ( )(vGS Vt )2
2 L
Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn W/L = 1.0 mA/V2).
23
As caractersticas de iD x vDS
Modelo equivalente de Circuito para grandes sinais do MOSFET
1 1
1 W
iD K n' ( )(vGS Vt )2 rDS
W ' W
2 L K (VGS Vt )
'
n K n VOV
L L
Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.
24
As caractersticas de iD x vDS
Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in
the saturation region. 25
A resistncia de sada finita na saturao
Resistncia de sada finita na saturao
1 ' W
iD K n ( )(vGS Vt )2
2 L
Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the
effective channel length (by DL). 26
A resistncia de sada finita na saturao
Resistncia de sada finita na saturao
L L L 1 ' W '
iD K n ( )1 vDS (vGS Vt ) 2
2 L L
1 ' W
iD K n ( )(vGS Vt ) 2
2 L L
'
1 ' W 1 L
iD K n ( ) (vGS Vt ) 2
2 L L
1 iD K n' ( )(vGS Vt ) 2 1 vDS
1 W
L 2 L
1 ' W L VA
1
iD K n ( )1 (vGS Vt ) 2
2 L L
L 1 1 ' W 1
L iD K n ( )(vGS Vt ) (1 vDS )
2
2 L VA
L 'vDS
27
A resistncia de sada finita na saturao
Tenso de Early (J. M. Early) = VA
VA VA
ro
I D 1 K ' (W )(v V )2
n GS t
2 L
1 W
I D K n' ( )(vGS Vt )2
2 L
ID 1 1 W 1
iD I D vDS I D (1 vDS ) K n' ( )(vGS Vt )2 (1 vDS )
VA VA 2 L VA
Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a
given process, is proportional to the channel length L. 28
A resistncia de sada finita na saturao
Tenso de Early (J. M. Early) = VA
VA VA
ro
I D 1 K ' (W )(v V )2
n GS t
2 L
Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The
output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22). 29
As caractersticas do MOSFET canal p
Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source
lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and
the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal. 30
As caractersticas do MOSFET canal p
' W 1 2
iD K p ( )[(vGS Vt )vDS vDS ]
L 2
1 ' W
iD K p ( )(vGS Vt ) 2 (1 vDS )
2 L
31
As caractersticas do MOSFET canal p
Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region
and in the saturation region.
32
As caractersticas do MOSFET canal p
Figure E4.8
33
A funo do substrato O efeito de corpo
34
O efeito da temperatura
Vt diminui ~ 2 mV para cada 1oC de aumento da temperatura.
35
Breakdown (Avalanche)
36
Sumrio das caractersticas corrente-tenso do MOSFET
Table 4.1
37
Exemplo 4.2
Projete o circuito de forma a que:
ID = 0,4 mA e VD = 0,5V
Dados do Tr. NMOS: Vt = 0,7 V; nCox = 100 A/V2; L = 1 m; W = 32 m
1 W 2 0,4
I D K n' ( )(vGS Vt )2 vGS vt
2 L 100 32
1
(vGS Vt ) 0,5V
VDD VD
RD 5k
ID
1 W
iD ( mnCox )( )(vGS Vt )2
2 L
2iD
(vGS Vt ) VOV 0,4V
W
( m nCox )( )
L
VGS Vt VOV 1V
VDD VD
RD 1k
ID
ID=80uA
Figure E4.12
40
Exemplo 4.4
Considerando VD = 0,1V, projete o circuito abaixo. Qual a resistncia entre dreno e
source neste ponto de operao?. Dados: Vt = 1 V; Kn(W/L) = 1 mA/V2
41
Exemplo 4.5
Exemplo 4.5: Faa a analise o circuito: Dados: Vt = 1 V; Kn(W/L) = 1 mA/V2
Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown. 42
Exemplo 4.6
Projetar o circuito com o transistor operando na regio de saturao com VD = 3 V e
ID = 0,5 mA.
Qual a mxima resistncia RD que ainda mantm o transistor na regio de saturao?
Dados: Vt = -1 V, Kp(W/L) = 1 mA/V2
Figure E4.16
45
O MOSFET: como amplificador e como chave
Caracterstica de Transferncia Operao em grandes sinais POLARIZAO
VDD 1
iD vDS
RD RD
Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of
the amplifier in (a). 46
Derivao grfica da caracterstica de transferncia
VDD 1
iD vDS
RD RD
dvo
Av
dt vi VIQ
Ganho do Amplificador
47
Expresses analticas para a caracterstica de transferncia
1 W
iD ( mnCox )( )(vI Vt ) 2
2 L
vO VDD RDiD
1 W
vO VDD RD ( mnCox )( )(vI Vt ) 2
2 L
dvo
Av
dt vi VIQ
48
Expresses analticas para a caracterstica de transferncia
W 1 2
vO VDD RD mnCox (
Iv Vt ) vo vO
L 2
W
vO VDD RD mnCox (vI Vt )vo
L
VDD
vO
W
1 RD m nCox (vI Vt )
L
1
rDS
W
m nCox (vI Vt )
L 49
Derivao grfica da caracterstica de transferncia
Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave
sufficient room for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close
to the boundary of the triode region and might not allow for sufficient negative signal swing.
50
Exemplo 4.8
Considerando VDD = 10V, RD=18 k, Vt = 1 V; Kn(W/L) = 1 mA/V2, analise o circuito.
1 W
I D mnCox (VGS Vt )2
2 L
Vt, Cox, W e L variam de transistor
para transistor da mesma famlia
Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2
represent extremes among units of the same type. 52
Polarizao de circuitos amplificadores MOS
Fixando a tenso VG e resistor de fonte RS
VG VGS
ID
RS
VG VGS I D RS
53
Polarizao de circuitos amplificadores MOS
Fixando a tenso VG e resistor de fonte RS
VSS VGS
ID
RS
Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic
arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a
signal source to the gate using a capacitor CC1; (e) practical implementation using two supplies. 54
Polarizao de circuitos amplificadores MOS: Exemplo 4.9
Projete o circuito para ter: ID = 0,5 mA. O circuito tem os seguintes valores: VDD = 15 V;
Vt = 1 V; Kn(W/L) = 1 mA/V2
Qual a variao de ID quando o MOSFET trocado por outro com Vt = 1,5 V?
VDD VGS
ID
RD
Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
56
Polarizao de circuitos amplificadores MOS
Polarizao com fonte de corrente constante
1 W
I D 2 K n' (VGS Vt )2
2 L 2
1 W
I D1 K n' (VGS Vt )2
2 L 1
(W / L )2
I D 2 I REF
(W / L )1
Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I
using a current mirror. 57
Operao em pequenos sinais e Modelos: Sinal de corrente no dreno
Anlise C.C.
1 W
I D K n' (VGS Vt )2 VD VGS Vt
2 L
1 W W 1 W
iD K n' (VGS Vt )2 K n' (VGS Vt )vgs K n' vgs 2
2 L L 2 L
Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier. 58
Operao em pequenos sinais e Modelos
K n'
W 1 W
(VGS Vt )vgs K n' vgs 2 vgs 2(VGS Vt ) vgs 2VOV
L 2 L
iD I D id
W
id K n' (VGS Vt )vgs g mvgs
L
W W
Ganho de transcondutncia g m K n' (VGS Vt ) K n' VOV
L L
59
Operao em pequenos sinais e Modelos
id
gm
vGS vGS VGS
1 W W
iD K n' (VGS vgs Vt )2 id K n' (VGS Vt )vgs g mvgs
2 L L
60
Operao em pequenos sinais e Modelos: Ganho de tenso
vD VDD RD ( I D id )
vd id RD g m RD vgs
id g mvgs
vd
Av g m RD
vgs
Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34. 61
Modelos equivalentes de circuitos para pequenos sinais
id g mvgs
i W 2I D VA VA
g m d K n' (VGS Vt ) ro
vgs L VGS Vt I D 1 K ' (W )(v V ) 2
n GS t
2 L
Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length modulation
effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID. 62
Exemplo 4.10
Analisar o circuito e determinar o ganho, resistncia de entrada e mxima excurso do
sinal de sada. Vt = 1,5 V; Kn(W/L) = 0,25 mA/V2 ; VA = 50V
63
Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.
Exemplo 4.10
VGS VD i vO g mvgs RD ro RL
RD 0
I D 0,125 VD 1,5 g m RD ro RL
vO vO
2
Av
vi vgs
VD 15 RD I D 15 10k I D Av 3,3 V V
I D 1,06mA e VD 4,4V
Rin = ?
ii vi vO RG 1 3,3
W vi
g m K n' (VGS Vt ) 0,725 mA
L V RG
vi RG
VA 50 Rin 2,33M
ro 47k ii 4,3
I D 1,06
64
O Modelo equivalente T
Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro 65
O Modelo equivalente T
66
Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model.
O Modelo considerando o efeito de corpo
iD
g mb
vBS vGS const . Transcondutncia do corpo
v DS const .
Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body. 67
O Modelo considerando o efeito de corpo
68
Modelos equivalentes
vbs 0
Table 4.2 69
Amplificadores MOS de um nico estgio
A topologia bsica Amplificadores MOS de um nico estgio
Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations. 70
Amplificadores MOS de um nico estgio
Determine VOV, VGS, VS, VD. Calcule gm e ro.
Considerando: Vt = 1,5 V; Kn(W/L) = 1 mA/V2; VA = 50V
Figure E4.30 71
Caractersticas dos Amplificadores
Table 4.3 72
Caractersticas dos Amplificadores circuitos equivalentes
73
Amplificador Fonte comum FC: ANLISE
1 Anlise do amplificador para
grandes sinais: polarizao do
ampli. Vsig=0, capacitores so
abertos;
2 Obter os valores de: ID, gm, ro
3 Anlise do amplificador em pq.
Sinais: Fontes VCC so aterradas e
as fontes ICC so abertas, cap. SC;
4 Substituir o transistor por seu
modelo em pq. sinal;
5 Obter: ganhos, Rin, Rout, etc.
Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. 74
Amplificador Fonte comum - FC
Figure 4.43 (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized. 75
Amplificador Fonte comum com resistncia de fonte
ro=
Figure 4.44 76
Amplificador Porta (Gate) comum - PC
Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). 77
Amplificador Gate comum - PC
Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model.. 79
Amplificador dreno comum ou seguidor de fonte
80
(c) Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower
Caractersticas dos amplificador MOSFET
Fonte comum
Table 4.4 81
Caractersticas dos amplificador MOSFET
Porta comum
Dreno comum
82
Cap. Internas do MOSFET Modelo para altas frequncias
Efeito capacitivo da porta
C gs 23 WLCox
Regio de saturao
C gd 0
C gs C gd 0
C gb WLCox Regio de corte
83
Cap. Internas do MOSFET Modelo para altas frequncias
Capacitncias de juno
Csb0
Csb
V
1 SB
V0
Cdb0
Cdb
V
1 DB
V0
84
Modelo para altas frequncias do MOSFET
Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is
connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis). 85
A frequncia de ganho unitrio do MOSFET (fT)
Ii gm
I O g m sCgdVgs Vgs T
s(C gs C gd ) (C gs C gd )
I O g mVgs Io
gm
fT
gm
I i s(C gs C gd ) 2 (C gs C gd )
Table 4.5 87
Resposta em frequncia do amp. FC MOSFET
VO RG
AM g m (ro RD RL )
Vsig RG Rsig
BW f H f L
Elementos que atuam
em altas freqncias
f L f H
BW f H
Amplificador genrico
88
Resposta em frequncia do amp. FC MOSFET
AM
L H
Faixa de passagem:
BW H L Funo Ganho A(s)
A(s) =AM.FL(s).FH(s)
Produto de ganho-faixa de passagem
PFB AM.H
89
Resposta em frequncia do amp. FC MOSFET
VO RG
AM g m (ro RD RL )
Vsig RG Rsig
BW f H f L
f L f H
BW f H
Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a)
delineating the three frequency bands of interest. 90
A resposta em alta frequncia
Figure 4.50 Determining the high-frequency response: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output; 91
A resposta em alta frequncia
Teorema de Miller
I1 I2
1 I1 Y I2 2
+ +
+ + Y1 Y2
V1 V2=K V1 V1 V2=K V1
- - - -
N 1
Y1V1 I1
I1 Y V1 V2 YV1 1 K
Y1 Y 1 K
N 2
Y2V2 I 2
I 2 Y V2 V1 YV2 1 1
K
Y2 Y 1 1
K
92
A resposta em alta frequncia
Aplicao do Teorema de Miller sobre Cgd
Vo g m vgs RL'
Vo
Av g m RL'
vgs
CT
Ceq C gd (1 K )
Ceq C gd (1 g m RL' ) C gd
'
CT C gs Ceq (1 g m RL' )
CT C gs C gd (1 g m RL' )
1 1
H ; AH AM
CT RS 1 s
H
93
A resposta em ALTA frequncia
Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq;
(d) the frequency response plot, which is that of a low-pass single-time-constant circuit. 94
A resposta em BAIXA frequncia
Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.
95
A resposta em BAIXA frequncia
RG RD
Vg ( s) Vsig I O ( s) I d
1
1 RD RL
RG Rsig sCC 2
sCC1
Vg ( s) Vsig
RG s VO I O RL
RG Rsig s 1
CC1 ( RG Rsig ) RD s
VO ( s) I d
RD RL s 1
1
P1 0 CC 2 RD RL
CC1 ( RG Rsig )
1
P3
Vg CC 2 RD RL
I d (s)
1 1
g m sCs
VO s s s
I d ( s) g mVg
s AO
g
s m
Vsig s P1 s P 2 s P 3
Cs
RG
P 2
g
m AO g ( R R )
R R m D L
Cs G sig
96
A resposta em BAIXA frequncia
Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are
sufficiently separated for their effects to appear distinct. 97
Inversor Lgico Digital CMOS
1
rDSN
' W
k
n L (VDD Vtn
)
n
Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b)
graphical construction to determine the operating point; (c) equivalent circuit. 99
Inversor Lgico Digital CMOS Operao do circuito - QP
1
rDSP
' W
(V
p DD tp
k V )
L p
Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical
construction to determine the operating point; (c) equivalent circuit. 100
Caractersticas de transferncia de tenso
Para QN
Para QP
Figure 4.56 The voltage transfer characteristic of the CMOS inverter. 101
Caractersticas de transferncia de tenso
Figure 4.56 The voltage transfer characteristic of the CMOS inverter. 102
Operao Dinmica
Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms;
(c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the
capacitor discharge. 103
Operao Dinmica
Figure 4.58 The current in the CMOS inverter versus the input voltage.
104
Sumrio das caractersticas do Inversor Lgico Digital CMOS
105
O MOSFET tipo Depleo
Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the
case the substrate (B) is connected to the source (S). 106
O MOSFET tipo Depleo
Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4 V and kn(W/L) = 2 mA/V2:
(a) transistor with current and voltage polarities indicated; (b) the iDvDS characteristics; (c) the iDvGS characteristic in saturation. 107
O MOSFET tipo Depleo
Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the
saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).
108
O MOSFET tipo Depleo
Figure 4.62 Sketches of the iDvGS characteristics for MOSFETs of enhancement and depletion types, of both polarities
(operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality
somewhat different values of |Vt| are shown for n-channel and p-channel devices.
109
O MOSFET tipo Depleo
Figure E4.51
110
O MOSFET tipo Depleo
Figure E4.52
111
Simulao para o
PSPICE
113
Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 mF and CS = 0 (i.e., CS removed). 114
Problemas sobre o MOSFET
Problema 4.16
Para um transistor NMOS com Vt = 0,8 V, operando com VGS na faixa de 1,5 a
4V, qual o maior valor de vDS para o qual o canal permanece contnuo?
115
Problemas sobre o MOSFET
Figure P4.18
116
Problemas sobre o MOSFET
Prob. 4.19
Para um determinado MOSFET operando na regio de saturao com vGS
constante, iD = 2 mA com vDS = 4V e 2,2 mA para vDS = 8V. Quais os valores
correspondentes de ro, VA e ?
VDS 84
ro 20k
iD vGSconst
2.2 2
VA+4=2mA x ro=40VVA=36V
117
4.16 Diversos transistores NMOS e PMOS foram medidos como mostrado na tabela a seguir. Para cada transistor, encontre o
valor de mCoxW/L e Vt que se aplicam e completam a tabela com V em volts, I em mA e mCoxW/L em mA/V2.
118
Problemas sobre o MOSFET
Figure P4.33
119
Problemas sobre o MOSFET
Prob. D4.36
O transistor PMOS da figura tem Vt = -0,7V, pCox = 60 A/V2, L = 0,8 m e = 0.
Determine os valores de W e R para estabelecer uma corrente de dreno de 115 A e
uma tenso VD = 3,5 V.
3,5
R 3,04k
0,115
W 4,8mm
Figure P4.36
120
Problemas sobre o MOSFET
Prob. D4.37
Os transistores NMOS da figura tem Vt = 1V, nCox = 120 A/V2, L1 = L2 = 1,0
m e = 0. Determine os valores de W 1, W2 e R para estabelecer a corrente e
tenses indicadas.
VGS1 1,5V ,
W1
120mA 0,5 x120 x (1,5 1) 2 W1 8mm
1
5 3,5
R 12,5k
0,120
Figure P4.37 121
Problemas sobre o MOSFET
Prob. D4.38
Os transistores NMOS da figura tem Vt = 1V, nCox = 120 A/V2, L1 = L2 = L3 = 1,0 m e
= 0. Determine W 1, W 2 e W 3 para estabelecer a corrente e tenses indicadas.
VGS1 1,5V ,
W1
120mA 0,5 x120 x (1,5 1) 2 W1 8mm
1
VGS 2 2V ,
W1
120mA 0,5 x120 x (2 1) 2 W1 2mm
1
VGS 3 1,5V ,
W1 8mm
Figure P4.38
122
Problemas sobre o MOSFET
Prob. D4.41
O transistor NMOS da figura tem Vt = 1V, nCox = 100 A/V2 e = 0. Determine os
valores de W/L e R para obter rDS = 50 e vo = 50 mV quando vI = VDD = 5V.
VDS 0,05
rDS 50 ID 1mA
VI VGS 5V ID 50
VO VDS 50mV 5 50mV
R 4,95k
I
W 1 2
iD K 'p ( )[(vGS Vt )vDS vDS ]
L 2
W 50mV 2
3
1 100 x10 (5 1) x50mV
L 2
W
50
L
Prob. 4.44 - Nos circuitos mostrados abaixo |Vt| = 1V, KW/L = 2 mA/V2 e = 0.
Encontre as tenses indicadas de V1 a V5.
V2 (5)
VGS 2 V2 , I 0,5 x 2 x(V2 1) 2
1k
V2 5 V22 2V2 1
V22 V2 4 V2 1,55V ou V2 2,56V
X ok!
V2 (5)
iD1 iD 2 0,5 x 2 x(5 V1 1) 2
1k
2,44 (4 V1 ) 2 V1 2,44V ou 5,56V
ok! X
Prob. 4.47 Para o circuito deste exerccio, |Vt| = 1V, nCox = 50 A/V2, = 0,
L = 1 m e W = 10 m. Determine V2 e I2. Como estes valores mudam se os
transistores Q3 e Q4 tem W = 100 m?
10
I1 12 50 (2,5 1) 2 562,5mA
1
VGS3=VGS1=2,5V
VGS3=VGS4=2,5V
I2=562,5uA
V2=5-2,5=2,5V
Figure P4.54
131
Problemas sobre o MOSFET
Prob. D4.61 - Projete o circuito da figura para que o transistor opere na saturao com
VD superior a 1V do limite da regio de triodo, com ID = 1 mA e VD = 3V, para cada um
dos seguintes dispositivos. Use uma corrente de 10 A no divisor de tenso.
| Vt | 1V e k 'pW / L 0,5mA / V 2
| Vt | 2V e k 'pW / L 1,25mA / V 2
Figure P4.61
132
Problemas sobre o MOSFET
Figure P4.66
133
Problemas sobre o MOSFET
Figure P4.74
134
Problemas sobre o MOSFET
Figure P4.75
135
Problemas sobre o MOSFET
Figure P4.77
136
Problemas sobre o MOSFET
Figure P4.86
137
Problemas sobre o MOSFET
Figure P4.87
138
Problemas sobre o MOSFET
Figure P4.88
139
Problemas sobre o MOSFET
Figure P4.97
140
Problemas sobre o MOSFET
Figure P4.99
141
Problemas sobre o MOSFET
Figure P4.101
142
Problemas sobre o MOSFET
Figure P4.104
143
Problemas sobre o MOSFET
Figure P4.117
144
Problemas sobre o MOSFET
Figure P4.120
145
Problemas sobre o MOSFET
Figure P4.121
146
Problemas sobre o MOSFET
Figure P4.123
147