VHDL

Parte 5
(Sequencial)
 FSM
• Usado para modelar um sistema que transita entre um
número finito de estados internos
• Transições dependem do estado atual e de entradas externas
• Na prática, a principal aplicação de uma máquina de
estados é:
• Controlar um sistema digital maior (complexo)
• Examina o estado do sistema e as entradas e ativa os
sinais de controle apropriados
108
Saídas Moore e Mealy
FSM

Mealy
INTRODUCTIONMealy109
output
- logic
output

- next-state d
> state
' state:eg "
input - logic state-next
-
i

register Moore
Moore
output
clk output
logic
mo: Moore output
me: Mealy output
Figure 5.1 Block diagram of a synchronous FSM.
state-name
Mealy output. The Moore and Mealy outputs
mo <=are
valuesimilar
but not identical. Understanding
their subtle differences is the key for a controller design. The example in Section 5.3.1
logic expression I me <= value logic expression I me <= value
illustrates the behaviors and constructions of the two types of outputs.

5.1.2 FSM representation to other state to other state

An FSM is usually specified by an abstract state diagram or ASM chart (algorithmic state
(a) Node
 state-name
mo <= value

logic expression I me <= value logic expression I me <= value

Saídas Moore e Mealy

to other state to other state

(a) Node

mo: Moore output

me: Mealy output

...........................
.................
r state entry

state box
state

mo <= value

I 7-- decision box

Boolean
conditional
output box

..................................
t-----
- exit to other ASM
block
'L exit to other ASM
block

(b) ASM block

The data type simply lists (i.e., enumerates) all symbolic values. Once the data type is end i f ;
defined, it can be used for the signals, as in when sl =>
s i g n a l s t a t e - r e g , s t a t e - n e x t : e g - s t a t e - t y p e ; 112
if ( a = ’ 1 ’ ) t
FSM
40 state-nex
During synthesis, software automatically maps the values in an enumerated data type to else

Exemplo FSM (Moore)

binary representations, a process known as state assignment. Although there is a mechanism
to perform this manually, it is rarely needed.
The complete code of the FSM is shown in Listing 5.1. It consists of segments for the
112 FSM
begin
case s t a t e - r e g i s
when S O = >
i f 45a = ’ 1 ’ t h e n
when s 2 =>
state-nex
end i f ;

state-next <
state register, next-state logic, Moore output logic, and Mealy output logic.
30 i f b = ’ lend ) t h ec na s e ;
begin
Listing 5.1 FSM example s t a t e -pnreoxcte s s<= ; s2;
c a s e s t a t e - r e g end is
else
library i e e e ; when S O = > -- M o o r e o u t p u t l o g i c
s tpartoec-enses x( ts t a<=
t e - sr le ;g )
use i e e e . s t d - l o g i c - 1 1 6 4 , a l l ; i f a = ’ 1 ’ t h e n
end bi fe g; i n
e n t i t y fsm-eg i s 30 i f50
b=’l) then
else
port ( s t a t e - cnaesxet <=
s t a t e - n e x t when
a t es- 2r e; g i s
s t<=
SsOo;l s 2 =>
5 c l k , r e s e t : in s t d - l o g i c ; ende l s ei f ;
a , b : in s t d - l o g i c ; when sl s=> t a t e - n e x t y<= l <=s l ;’ 0 ’ ;
when sl = >
y o , y l : out s t d - l o g i c i fend ( a =i f’ 1; ’ ) then
); 40 e l s e 5 5s t a t e - n e x t <=y lS O<= ;
’1’;
end c a s e ;
end f s m - e g ; e lsst ea t e - n e x t <= S O ;
10 end i sft;a t eend process;
- n e x t <= s l ;
a r c h i t e c t u r e m u l t - s e g - a r c h of fsm-eg i s when end sl => i f ;-- M e a l y o u t p u t l o g i c

...
type e g - s t a t e - t y p e i s ( s o , s l , s 2 ) ; i f (sa2= ’=>
when 1p ’ )r othen
cess ( s t a t e - r e g , a , b
s i g n a l s t a t e - r e g , s t a t e - n e x t : e g - s t a t e - t y p e ;40 45 s tsatMtaet-en-en bxeetgxitn<=<=S O S; O ;
begin end ceal s e ; case s t a t e - r e g i s
I5 -- s t a t e r e g i s t e r end p r o c e s ss ;t a t e - n e x t when <= s lS;O =>
process ( c l k , r e s e t ) -- M o o r eend o u tipf u;t l o g i c if ( a = ’ l ’ ) a
begin p r o c when
e s s ( s tsa2t e=> -reg) yo <= > 1 ’ ;
i f ( r e s e t = ’ l ’ ) then begin s t a t e - n e x t <= S O ; e l s e
50 65
45
s t a t e - r e g <= S O ; y o <= ) O ’ ;
endc a scea sset;a t e - r e g i s
20 e 1 s i f ( c l k ’ e v e n t and c l k = ’ 1 ’ ) t h e n end p r o cwhen e s s ; s o l s 2 => end i f ;
s t a t e - r e g <= s t a t e - n e x t ; y l <= l ’o0g’ i; c
-- M o o r e o u t p u t
when sl I s 2 = >
end i f ; p r o c e s s (when
s t a t e sl- r e =g>) yo <= ’ 0 ’ ;
end p r o c e s s ; 50
55
begin y l 70<= ’ 1 ’ ;end c a s e ;
-_ n e x t - s t a t e logic s e s ct aa ts ee -; r e g end
c a end is process;
25 p r o c e s s ( s t a t e - r e g , a ,b ) end p r o c e s s ; end m u l t - s e g - a r c h ;
when s o l s 2 =>
-- M e a l y o u t p u t l o g i c
y l <= ’ 0 ’ ;
p r o c e s s ( s t a t eThe-reg key, apart, b)is the next-state logic
 else
signal s t a t e - r e g , s t a t e - n e x t : eg-state-type; s t a t e - n e x t <= s l ;
end i f ;
During synthesis, software automatically maps the values in an enumerated data type to else
binary representations, a process known as state assignment. Although there is a mechanism s t a t e - n e x t <= S O ;
to perform this manually, it is rarely needed.

Exemplo FSM (Mealy)

end i f ;
The complete code of the FSM is shown in Listing 5.1. It consists of segments for when the sl =>
i f ( a = ’ 1 ’ ) then
state register, next-state logic, Moore output logic, and Mealy output logic.
40 112 FSM s t a t e - n e x t <= S O ;
Listing 5.1 FSM example else
begin s t a t e - n e x t <= s l ;
library i e e e ; c a s e ends t a t ief- ;r e g i s
use i e e e . s t d - l o g i c - 1 1 6 4 , a l l ; whens 2S O=>= >
when
e n t i t y fsm-eg i s 45 s t ai ft e -an=e’ x1 t’ t<= h e nS O ;
end c a s e ; i f b = ’ l ) t h e n
port ( 30
end p r o c e s s ; s t a t e - n e x t <= s 2 ;
5 c l k , r e s e t : in s t d - l o g i c ;
-- M o o r e o u t p u et l sleo g i c
a , b : in s t d - l o g i c ; p r o c e s s ( s t a t e - r e g s) t a t e - n e x t <= s l ;
y o , y l : out s t d - l o g i c 50 begin end i f ;
); c a s e s t a teel -s ree g i s
end f s m - e g ; when s o l s t2a t=> e - n e x t <= S O ;
10 y l end <= i’ f0 ;’ ;
whenwhensl sl= >=>

...
a r c h i t e c t u r e m u l t - s e g - a r c h of fsm-eg i s
y l i f<= ( a’=1 ’’ 1; ’ ) then
type e g - s t a t e - t y p e i s ( s o , s l , s 2 ) ; 55

end c a s e ; s t a t e - n e x t <= S O ;
signal s t a t e - r e g , s t a t e - n e x t : eg-state-type ;
40

end p r o c e s s e; l s e
begin -- M e a l y o u t p u st t altoeg- ince x t <= s l ;
I5 -- s t a t e r e g i s t e r p r o c e s s ( s t a tende - r eigf ;, a , b)
process ( c l k , r e s e t ) M begin when s 2 =>
begin 45 c a s e s t a tset a- rt e -gn e ixst <= S O ;
i f ( r e s e t = ’ l ’ ) then endwhenc a Ss Oe ; =>
s t a t e - r e g <= S O ; end p r o icfe s s( ;a = ’ l ’ ) and (b=)l’) t h e n
-- M o o r e yo o u t p<=u t >l1o’g;i c
20 e 1 s i f ( c l k ’ e v e n t and c l k = ’ 1 ’ ) t h e n
65 p r o c e s s e( sl st ae t e - r e g )
s t a t e - r e g <= s t a t e - n e x t ; 50 begin y o <= ) O ’ ;
end i f ; c a s e ends t a tief - ;r e g i s
end p r o c e s s ; whenwhensl s oI l ss22 => =>
-_ n e x t - s t a t e logic yo y <= l <=’ 0 ’ 0; ’ ;
25 p r o c e s s ( s t a t e - r e g , a ,b ) 70 end c when a s e ; sl = >
55 end p r o c e s sy; l <= ’ 1 ’ ;
end m u l t -end
s e g -caar sceh;;
end p r o c e s s ;
The key--partMise the
a l y next-state l o g i cIt uses a case statement with th
o u t p u t logic.
 FSM em VHDL

• Nos exemplos apresentados, a lógica de próximo

estado e de saída estavam separadas
• Alternativamente, pode-se realizar a
implementação combinando estes dois elementos
 s t a t e - r e g <= s t a t e - n e x t ;
end i f ;
end p r o c e s s ;
-_ n e x t - s t a t e / o u t p u t l o g i c
15 process ( s t a t e - r e g , a , b )
begin
s t a t e - n e x t <= s t a t e - r e g ; -- d e f a u l t b a c k t o s a m e s t a t e
y o <= ’ 0 ’ ; _- d e f a u l t 0
y l <= j 0 ’ ; __ d e f a u l t 0
case s t a t e - r e g is
when S O =>
i f a = ’ 1 ’ then
i f b = ’ l ’ then
s t a t e - n e x t <= s 2 ;
y o <= ’ 1 ’ ;
else
s t a t e - n e x t <= s l ;
end i f ;
-- no e l s e b r a n c h
30 end i f ;
when sl =>
y l <= ’ l > ;
i f ( a = ’ l ’ ) then
s t a t e - n e x t <= S O ;
35 -- no e l s e b r a n c h
end i f ;
when s 2 = >
s t a t e - n e x t <= S O ;
end c a s e ;
40 end p r o c e s s ;
end t w o - s e g - a r c h ;
 Exemplo interessante
• Circuito de debounce
• Botões tipo pushbuttons podem apresentar
oscilações mecânicas durante o uso - Glitches!!!
• Tempo de estabilização máximo em torno aos 20ms
119 DESIGN EXAMPLES

bounces bounces
(last less than 20 ms) (last less than 20 ms)
--
original
switch output
-- -

debounced output
(scheme 1) *Oms I 20 ms-
 2 possibilidades DESIGN EXAMPLES 119

bounces bounces
(last less than 20 ms) (last less than 20 ms)
--
original
switch output
-- -

debounced output
(scheme 1) *Oms I 20 ms-
L
I , 20ms
debounced output
(scheme 2)
- ; 20 ms

Figure 5.8 Original and debounced waveforms.

 I , 20ms
debounced output
(scheme 2)
- ; 20 ms

Solução 1
Figure 5.8 Original and debounced waveforms.

bounces
DESIGN EXAMPLES

bounces
119

(last less than 20 ms) (last less than 20 ms)

--
original
switch output
-- -

debounced output
(scheme 1) *Oms I 20 ms-
L
I , 20ms
debounced output
(scheme 2)
- ; 20 ms

Problema:
Figure 5.8 Original and debounced waveforms.

atraso na entrada
e na saída

Figure 5.9 State diagram of a debouncing circuit.

 Como ficaria o código
VHDL???

• Solução no livro...