1

Cover Sheet 1
Block Diagram/Clock Map/Power Map
Intel LGA775 CPU
2-4
5-7
MS-7592 Version 5.2

Intel Bearlake - MCH 8-11

CPU:
Intel ICH7 - PCI & DMI & CPU & IRQ 12 Intel Conroe (95W Dual core)
Intel ICH7 - LPC & ATA & USB & GPIO 13 System Chipset:

程
Intel ICH7 - POWER 14 Intel G41 - MCH (North Bridge)
Clock - RTM 875T-605 15 Intel ICH7R (South Bridge)
LPC I/O - Fintek 71889F
LAN Atheros AR8132M co-lay AR8131M

板
16
17
On Board Chipset:
BIOS -- SPI
工
機
DDR III DIMM A 18 HD --VT1708S
LPC Super I/O -- F718829G
DDR III DIMM B 19

主
LAN Atheros AR8132M co-lay AR8131M

-
DDR III CAP 20 CLOCK -- RTM875-605

I S
HD - VT1708S 21
Main Memory:

S
PCI EXPRESS X16 Slot 22
DDR III *2 (Max 4GB)

M 燕
A A

PCI Slot 1 & 2 23

Expansion Slots:
ATA33/66/100 IDE & SATA Connectors 24
PCI2.3 SLOT * 2

代
USB Connectors 25

謝 91225
PCI EXPRESS X16 SLOT
ATX Connetcor & Front Panel 26
ST PWM:
VGA Connector 27
Controller: 3 PHASES
UPI ACPI CONTROLLER 28

0
GMCH VCORE 29

20
PWM-UPI6206 30

MICRO-STAR INT'L CO.,LTD

MSI
MS-7592
Size Document Description Rev
Custom Cover Sheet 5.2

Date: Thursday, December 10, 2009 Sheet 1 of 33

1
 1

Block Diagram
VRM 10.1
UPI6206 Intel LGA775 Processor (95W)
3-Phase PWM

程
FSB 800/1066/1333

FSB
200/266
/333MHz

工
DDR3 800/1067
2DDR III
DIMM

板
RGB DDRIII Modules
Analog
Video G41
GMCH

機
Out 400/533
MHz

- 主
DMI

PCI Slot 1

PCI Slot 2
S
UltraDMA

I
33/66/100 PCI

IDE Primary

S
M 燕
SATA 0~3

USB Port 0~7

SATA

USB
ICH7
SPI
PCI EXPRESS X16 PCI EXPRESS
X16
Connector
A

SPI
代
謝 91225
HD
LPC Bus

VT1708S
PCI

LPC SIO
Fintek

0
AR8132M
F71889F
/AR8131M

20 TPM Keyboard

Mouse
Floopy Parallel Serial

MICRO-STAR INT'L CO.,LTD

MSI MS-7592
Size Document Description Rev
Custom BLOCK DIAGRAM 5.2

Date: Thursday, December 10, 2009 Sheet 2 of 33

1
 5 4 3 2 1

CLOCK MAP
D D

HCLK
LGA775

程
MCHCLK DDRCLKA

工
DOT96M G41 CH A CH B
DDRCLKB

板
PCIECLK

機
PCIECLK
C C
SATACLK

主
RTM875-605

-
ICHCLK
ICH7

S
USB48MHz

I
ICH14.318MHz

S
M 燕
SIO48MHz
33MHz Fintek SIO

代
HDCLK 24M

謝 91225
﹛ALC888
B B

TPMCLK_33M
TPM

0
PCIELAN_100M

0
RTL8111D

A
2 PCIEX16 100MHz

PCICLK[0..1]
33MHz
PCIE X 16

PCI1

PCI2
A

MICRO-STAR INT'L CO.,LTD

MSI MS-7592
Size Document Description Rev
Custom CLOCK MAP 5.2

Date: Thursday, December 10, 2009 Sheet 3 of 33

5 4 3 2 1
 5 4 3 2 1

Processor (95W) UPI6206 Regulator W83310DS Regula

1.15-1.5000V Core-70A VCCP VTT_DDR
1.2V FSB Vtt-5.8A
1.15-1.5000V 0.75V
VCCPLL
VCC-IOPLL & VCCA
D D

DDR3 DIMM conn(4) & term

0.75V SM Vtt-1.2A(S0)
G41 MCH 1.1V core 22A VTT Regulator 1.5V Vdd/vddq-4.7A(S0,S1)

V_FSB_VTT

程
1.2V FSB Vtt-0.9A
1.5V DDR3 I/O-4.4A(S0,S1) 1.2V PCIE X16 slot(1)
1.5V DDR3 I/O-25mA(S3) +12V-5.5A

工
0.75V DDR3 VREF-2mA +3.3Vaux-375mA(wake)
Divider uP6103 Regulator
0.75V DDR3 SB_VREF-10uA +3.3Vaux-20mA(no wake)
DDR3 Resister Comp V-36mA VCC_DDR +3.3V-3.0A
R

板
DDR3 Resis Comp SB_V-10uA 1.8V
1.1V Core-13.8A(Integrated) PCIE X1 slot(0)
1.1V Core-8.9A(Discrete) +12V-0.5A

機
1.5V PCI Express&DMI-0.68A V1.5 Regulator +3.3Vaux-375mA(wake)
1.1V PCIE&DMI PLL-41mA V_1P5_CORE +3.3Vaux-20mA(no wake)
1.5V HOST PLL-45mA +3.3V-3.0A

主
C C
1.5V
1.5V VCCA_DPLLA&B-55mA

-
1.5V MPLL-66mA PCI slot slot(2)

S
1.1V Regulator +3.3Vaux-375mA(wake)

I
1.1V Vcc-core 1.16A
+3.3Vaux-20mA(no wake)
V_1P1_Core

S
1.1V VCC_CL-3A +3.3V-5.6A
1.1V +5.0V-5.0A
+12V-0.5A

M 燕
-12V-0.1A
ICH7
1.2V VCC_CPU-14mA 1.05V Regulator
1.05V Core-0.86A V_1P05_CORE
VCC1_5 SATA/USB/PLL 1.65A USB
1.05V

代
VCC1_5B*-0.646A +5V-4A(S0,S1)
5VRef-6mA R

謝 91225
5VrefSus-10mA PS2
+3.3V-0.33A +5V-345mA(S0,S1)
B
RTC-6uA(G3) uP7706 Regulator uP7501 Regulator B

3.3V VccSus*-52mA 3VSB 5VDIMM CLKGEN

VccSus1_05V-See Note 1 3.3V 5V +3.3V-560mA
VccUSBPLL-10mA

0
VccDMIPLL-41mA L LAN
VccSATAIPLL-50mA 3VSB-

0
L

2
SIO SPI ROM
+3.3V
3VSB-
Battery

+12V +12V +5V +3.3V +5VSB Audio Codec

ATX
2x2 ATX POWER 1394
A A

MICRO-STAR INT'L CO.,LTD

MS-7592
MSI
Size Document Description Rev
Custom LGA775 - Signal 5.2

Date: Thursday, December 10, 2009 Sheet 4 of 33

5 4 3 2 1
 5 4 3 2 1

VCC_SENSE
VCC_SENSE 30

CPU SIGNAL BLOCK PULL HIGHT PULL DOWN

VSS_SENSE
VSS_SENSE 30
RN4
8P4R-680R0402-RH
VID[0..7] 30
VID5 1 2 VTT_OUT_RIGHT
8 H_A#[3..35]
VID4 3 4
VID2 5 6
VID0 7 8

H_A#10
H_A#35
H_A#34
H_A#33
H_A#32
H_A#31
H_A#30
H_A#29
H_A#28
H_A#27
H_A#26
H_A#25
H_A#24
H_A#23
H_A#22
H_A#21
H_A#20
H_A#19
H_A#18
H_A#17
H_A#16
H_A#15
H_A#14
H_A#13
H_A#12
H_A#11
D D

VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
H_A#8
H_A#7
H_A#6
H_A#5
H_A#4
H_A#3
H_A#9
RN3
8P4R-680R0402-RH
VID7 1 2
VTT_OUT_RIGHT VID3 3 4

AM7
AM5

AM3

AM2
AG5
AG4
AG6
AH5
AH4

AC5

AD6

AC2

AN3
AN4
AN5
AN6
AB4

AB5
AA5

AA4

AB6

AK3

AK4
AF4
AF5
VTT_OUT_RIGHT 6,7

AL4

AL6

AL5
AJ6
AJ5

AJ3
W6

W5

M4

M5
U4
U5

U6

R4
VID6

Y4
Y6

V4
V5

P6
T4

T5

L4

L5
5 6
CPU1A VID1 7 8
R75

VCC_SENSE
VSS_SENSE
VCC_MB_REGULATION
VSS_MB_REGULATION
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#

DBR#

ITP_CLK1
ITP_CLK0

RSVD/VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
680R1%0402

程
H_DBI#0 A8 RN5
8 H_DBI#[0..3] DBI0#
H_DBI#1 G11 AN7 8P4R-51R0402
DBI1# VID_SELECT VID_SEL 30
H_DBI#2 D19 H1 CPU_GTLREF0 H_BPM#1 1 2 VTT_OUT_RIGHT
DBI2# GTLREF0 CPU_GTLREF0 6
H_DBI#3 C20 H2 CPU_GTLREF1 H_BPM#0 3 4
DBI3# GTLREF1 CPU_GTLREF1 6
H29 H_BPM#5 5 6
GTLREF_SEL T6

工
AB2 E24 R188 X_0R0402 H_BPM#3 7 8
6 H_IERR# IERR# GTLREF2 CPU_MCH_GTLREF 8
AB3 F2 CPU_GTLREF1
MCERR# FC5/CPU_GTLREF2 CPU_GTLREF0 RN6
12 H_FERR# R3 FERR#/PBE# RSVD/CPU_GTLREF3 G10
M3 8P4R-51R0402
12 H_STPCLK# STPCLK#
AD3 AG3 H_BPM#5 H_TRST# 1 2
BINIT# BPM5#

板
P3 AF2 H_BPM#4 H_BPM#4 3 4
12 H_INIT# INIT# BPM4#
H4 AG2 H_BPM#3 H_TDO 5 6
RSP# BPM3# H_BPM#2 H_TCK
BPM2# AD2 7 8
B2 AJ1 H_BPM#1
8 H_DBSY# DBSY# BPM1#
C1 AJ2 H_BPM#0 RN7
8 H_DRDY# DRDY# BPM0# H_BPM#0 7

機
E3 8P4R-51R0402
8 H_TRDY# TRDY#
J6 H_REQ#4 H_TDI 1 2
REQ4# H_REQ#[0..4] 8
D2 K6 H_REQ#3 H_BPM#2 3 4
8 H_ADS# ADS# REQ3#
C3 M6 H_REQ#2 H_TMS 5 6
8 H_LOCK# LOCK# REQ2#
C C2 J5 H_REQ#1 7 8 C
8 H_BNR#

主
BNR# REQ1# H_REQ#0
8 H_HIT# D4 HIT# REQ0# K4

-
8 H_HITM# E4 HITM#
G8 W2 H_TESTHI12 RN9 8P4R-51R0402
8 H_BPRI# BPRI# TESTHI12 H_TESTHI12 7
G7 P1 DPSLP# H_TESTHI12 1 2 VTT_OUT_LEFT
8 H_DEFER# DEFER# TESTHI11 DPSLP# 13

S
H5 H_TESTHI10 H_TESTHI1 3 4
H_TDI TESTHI10 H_TESTHI9 R131 X_R/2 H_BPM#2 H_TESTHI10
AD1 G4 5 6

I
H_TDO TDI TESTHI9 H_TESTHI8 R133 X_R/2 H_BPM#3 C68
AF1 TDO TESTHI8 G3 7 8
H_TMS AC1 F24 C0.1u16Y0402
TMS TESTHI7

S
H_TRST# AG1 G24 Kentsfield
H_TCK TRST# TESTHI6
AE1 TCK TESTHI5 G26
PECI G5 G27
16 PECI PECI TESTHI4
VTIN1 AL1 G25
16 VTIN1 THERMDA TESTHI3
GNDHM H_TESTHI2_7 R162 51R0402 V_FSB_VTT

M 燕
16 GNDHM AK1 THERMDC TESTHI2 F25 V_FSB_VTT
H_TRMTRIP# M2 W3 H_TESTHI1 DEMO circuit DPSLP# pull high
12 H_TRMTRIP# THERMTRIP# TESTHI1
AE8 F26 H_TESTHI0 R161 51R0402
H_PROCHOT# GND/SKTOCC# TESTHI0 FORCEPH R87 X_130R1%0402VTT_OUT_RIGHT
6 H_PROCHOT# AL2 PROCHOT# FORCEPH AK6
H_IGNNE# N2 G6 RSVD_G6 R139 X_51R0402 VTT_OUT_LEFT DPSLP# R132 51R0402
12 H_IGNNE# IGNNE# RSVD#G6
ICH_H_SMI# P2 PM_SLP_N R127 51R0402
12 ICH_H_SMI# SMI#
H_A20M# K3 G28 CK_H_CPU# 15 H_COMP5 R113 49.9R1%0402
12 H_A20M# A20M# BCLK1#
R124 X_0R0402 L2 F28 CK_H_CPU 15
12 H_CPUSLP# TESTI_13 BCLK0#

代
AH2 A3 H_RS#2
8 PM_SLP_N RSVD#AH2 RS2# H_RS#[0..2] 8
N5 F5 H_RS#1
RESERVED0 RS1# H_RS#0
AE6 B3

謝 91225
H_BPM#1R86 X_R/2 H_TEST RESERVED1 RS0#
C9 RESERVED2 VTT_OUT_LEFT 6
D16 U3 TEST-U3
Kentsfield RESERVED4 AP1# TEST-U2 T2
A20 RESERVED5 AP0# U2 T1
R95 F3 C70
BR0# H_BR#0 6,8
B VTT_OUT_RIGHT X_1KR0402 Y1 T2 H_COMP5 R117 X_R/2 X_C0.1u16Y0402 B
BOOTSELECT COMP5 H_COMP5_R 8,13
V2 J2 H_COMP4 R125 X_49.9R1%0402 VTT_OUT_LEFT
R96 X_51R0402 LL_ID0 COMP4 H_COMP3
AA2 LL_ID1 COMP3 R1 1 2
G2 H_COMP2 3 4
COMP2 H_COMP1
15,16 CPU_BSEL0 G29 BSEL0 COMP1 T1 5 6
H30 A13 H_COMP0 R163 49.9R1%0402 7 8
15 CPU_BSEL1 BSEL1 COMP0 RN8 8P4R-49.9R1%-1
15 CPU_BSEL2 G30 BSEL2 TEST-J17

0
DP3# J17 T4
N1 H16 TEST-H16 H_TEST R135 X_51R0402 VTT_OUT_LEFT
6,12 H_PWRGD PWRGOOD DP2# T8
H15 TEST-H15

0
DP1# TEST-J16 T5
6,7,8 H_CPURST# G23 RESET# DP0# J16 T3 Kentsfield

2
8 H_D#[0..63] ADSTB1# AD5 H_ADSTB#1 8
H_D#63 B22 R6
D63# ADSTB0# H_ADSTB#0 8
H_D#62 A22 C17
D62# DSTBP3# H_DSTBP#3 8
H_D#61 A19 G19
D61# DSTBP2# H_DSTBP#2 8
H_D#60 B19 E12 FORCEPH R90 X_0R0402
D60# DSTBP1# H_DSTBP#1 8 VRM_HOT 30
H_D#59 B21 B9
D59# DSTBP0# H_DSTBP#0 8
H_D#58 C21 A16
D58# DSTBN3# H_DSTBN#3 8
H_D#57 B18 G20
D57# DSTBN2# H_DSTBN#2 8
H_D#56 A17 G12
D56# DSTBN1# H_DSTBN#1 8
H_D#55 B16 C8
D55# DSTBN0# H_DSTBN#0 8
H_D#54 C18 L1
D54# LINT1/NMI H_NMI 12
LINT0/INTR K1 H_INTR 12
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
H_D#53 B15
H_D#52 C14
H_D#51 C15
H_D#50 A14
H_D#49 D17
H_D#48 D20
H_D#47 G22
H_D#46 D22
H_D#45 E22
H_D#44 G21
H_D#43 F21
H_D#42 E21
H_D#41 F20
H_D#40 E19
H_D#39 E18
H_D#38 F18
H_D#37 F17
H_D#36 G17
H_D#35 G18
H_D#34 E16
H_D#33 E15
H_D#32 G16
H_D#31 G15
H_D#30 F15
H_D#29 G14
H_D#28 F14
H_D#27 G13
H_D#26 E13
H_D#25 D13
H_D#24 F12
H_D#23 F11
H_D#22 D10
H_D#21 E10
H_D#20 D7
H_D#19 E9
H_D#18 F9
H_D#17 F8
H_D#16 G9
H_D#15 D11
H_D#14 C12
H_D#13 B12
H_D#12 D8
H_D#11 C11
H_D#10 B10
H_D#9 A11
H_D#8 A10
H_D#7 A7
H_D#6 B7
H_D#5 B6
H_D#4 A5
H_D#3 C6
H_D#2 A4
H_D#1 C5
H_D#0 B4

ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
A A

MICRO-STAR INT'L CO.,LTD

MSI
MS-7592
Size Document Description Rev
Custom LGA775 - Signal 5.2

Date: Thursday, December 10, 2009 Sheet 5 of 33

5 4 3 2 1
 5 4 3 2 1

VCCP

AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30

AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30

AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AF21
AF22

AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26

AM8
AM9
AG8
AG9

AH8
AH9

AK8
AK9
AF8
AF9

AL8
AL9
AJ8
AJ9
CPU1B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
A23 H_VCCA
VCCA H_VSSA
AF19 VCC VSSA B23
D AF18 D23 H_VCCPLL D
VCC VCCPLL H_VCCA
AF15 VCC VCC-IOPLL C23
AF14 V_FSB_VTT
VCC
AF12 VCC
AF11 A25 V_FSB_VTT
VCC VTT
AE9 VCC VTT A26
AE23 VCC VTT A27

C10u10Y0805
C135

X_C10u10Y0805
C132
AE22 VCC VTT A28
AE21 VCC VTT A29
AE19 VCC VTT A30

程
AE18 VCC VTT B25
AE15 VCC VTT B26
AE14 VCC VTT B27
AE12 VCC VTT B28 CAPS FOR FSB GENERIC
AE11 VCC VTT B29

工
AD8 VCC VTT B30
AD30 VCC VTT C25
AD29 VCC VTT C26
AD28 VCC VTT C27
AD27 VCC VTT C28

板
AD26 VCC VTT C29
AD25 VCC VTT C30
AD24 VCC VTT D25
AD23 VCC VTT D26
AC8 VCC VTT D27

機
AC30 VCC VTT D28
AC29 VCC VTT D29
AC28 VCC VTT D30
AC27 AM6 VTT_PWG
VCC VTTPWRGD
C AC26 C

主
VCC VTT_OUT_RIGHT
AC25 VCC VTT_OUT_RIGHT AA1
VTT_OUT_LEFT

-
AC24 VCC VTT_OUT_LEFT J1
AC23 F27 VTT_SEL
VCC VTT_SEL VTT_SEL 28
AB8 VCC

S
AA8 VCC RSVD#F29 F29

I
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
S

AN26
AN25
Y8
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
W8
W30
W29
W28
W27
W26
W25
W24
W23
V8
U8
U30
U29
U28
U27
U26
U25
U24
U23
T8
T30
T29
T28
T27
T26
T25
T24
T23
R8
P8
N8
N30
N29
N28
N27
N26
N25
N24
N23
M8
M30
M29
M28
M27
M26
M25
M24
M23
L8
K8
K30
K29
K28
K27
K26
K25
K24
K23
J9
J8
J30
J29
J28
J27
J26
J25
J24
J23
J22
J21
J20
J19
J18
J15
J14
J13
J12
J11
J10
AN9
AN8
AN30
AN29
VCCP

M 燕
*GTLREF VOLTAGE SHOULD BE 0.67 * VTT = 0.8V (At VTT=1.2V)

代
R108 R110

謝 91225
VTT_OUT_RIGHT 57.6R1%0402-RH GTL_REF0 10R1%0402
CPU_GTLREF0 5 *PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
R120 X_0R0402 CPU_GTL_REF
R107 C62 C66
*TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MILS
B 100R1%/2 C1u16Y X_C220p50N0402 B

V_FSB_VTT V_1P5_CORE

L2 X_10u100mA_0805-RH CP2
R116 R126 1 2 H_VCCA H_VCCPLL
VTT_OUT_RIGHT 49.9R1%0402-RH GTL_REF1 10R1%0402
CPU_GTLREF1 5
C113 C117 C130

0
CP1 C108 C10u10Y0805 C116 X_C1u16Y C10u10Y0805
R123 C71 C75 C1u16Y X_C10u10Y0805

0
100R1%/2 C1u16Y X_C220p50N0402
H_VSSA

2
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
5VSB 5VSB

Address:60h
R85
10KR0402 U5 VTT_PWRGOOD
1 8 CPU_GTL_REF
VDD VOUT1 DIMM_MEM_REF
PLACE AT CPU END OF ROUTE 2
3
BUS_SELVOUT2 7
6 CPU_VRM_REF
DIMM_MEM_REF 18,19
GND VOUT3 CPU_VRM_REF 30
4 5 VTT_OUT_RIGHT
SDA SCL
VTT_OUT_RIGHT R98 130R1%0402 H_PROCHOT# UP6262M8_SOT23-8-RH VTT_PWG SPEC :
5,7 VTT_OUT_RIGHT H_PROCHOT# 5
C0.1u16Y0402
C57

R106 62R0402 H_IERR# R84 R88

H_IERR# 5 High > 0.9V
A 10KR0402 680R0402-RH A
SMBCLK_ISO 13,15,17,18,22,28
R137 62R0402 H_CPURST# Low < 0.3V
H_CPURST# 5,7,8 SMBDATA_ISO 13,15,17,18,22,28
VTT_OUT_LEFT R118 X_100R0402 H_PWRGD VTT_PWG
5 VTT_OUT_LEFT
R138 62R0402 H_BR#0
H_PWRGD 5,12 Trise < 150ns

C
H_BR#0 5,8
R79 1KR0402B
28,30 VID_GD#
Q11
C54 N-MMBT3904_NL_SOT23 MICRO-STAR INT'L CO.,LTD

E
X_C1u16Y

MSI
MS-7592
Size Document Description Rev
Custom LGA775 - Power 5.2
reserved
Date: Friday, December 18, 2009 Sheet 6 of 33
5 4 3 2 1
 5 4 3 2 1

X_0R0402

R30
R29
R28
R27
R26
R25
R24
R23

H28
H27
H26
H25
H24
H23
H22
H21
H20
H19
H18
H17
H14
H13
H12
H11
H10
V30

V29
V28
V27
V26
V25
V24
V23

P30
P29
P28
P27
P26
P25
P24
P23

L30

L29
L28
L27
L26
L25
L24
L23
W7
W4

M7
M1
U7

R7
R5

R2

N7
N6
N3

H9
H8
H7
H6
H3
R100 PSI#_N

Y7
Y5
Y2

V7
V6

V3

P7
P4

K7
K5
K2
T7
T6
T3

F7
L7
L6

L3

J7
J4
CPU1C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A12 VSS
A15 Y3 H_COMP6 R103 49.9R1%0402
VSS COMP6 VTT_OUT_RIGHT 5,6
D A18 AE3 H_COMP7 R102 X_49.9R1%0402 D
VSS COMP7 H_COMP8 R168 24.9R1%0402
A2 VSS RSVD/COMP8 B13
A21 VSS
A6 VSS RSVD#AE4 AE4
A9 VSS RSVD#D1 D1
AA23 VSS RSVD#D14 D14
AA24 VSS RSVD#E5 E5
AA25 VSS RSVD#E6 E6
AA26 VSS RSVD#E7 E7 T9
AA27 E23 R89
VSS RSVD#E23 T10

程
AA28 F23 X_0R0402
VSS RSVD#F23 T7
TP_MPG_NOBOOT_N
AA29 VSS RSVD AL3
AA3 VSS RSVD#J3 J3
AA30 VSS RSVD#N4 N4
AA6 VSS RSVD#P5 P5

工
AA7 VSS RSVD#AC4 AC4
AB1 VSS
AB23 F6 1505 R119 51R0402 For old CPU support
VSS IMPSEL# R115 51R0402
AB24 VSS MSID1 V1 1477
AB25 W1 1497 R112 51R0402
VSS MSID0

板
AB26 VSS
AB27 U1 FC28 R128 X_R/2 H_TESTHI12
VSS FC28 H_TESTHI12 5
AB28 G1 FC27 R129 X_R/2 H_BPM#0
VSS FC27 H_BPM#0 5
AB29 E29 R151 X_0R0402
VSS FC26 R152 X_1KR0402
AB30 VSS FC23 A24

機
AB7 VSS
AC3 VSS VSS F4 Kentsfield
AC6 VSS VSS F22
AC7 VSS VSS F19
C AD4 F16 C

主
VSS VSS
AD7 VSS VSS F13

-
AE10 VSS VSS F10
AE13 VSS VSS E8 MSID1 MSID0
AE16 VSS VSS E28

S
AE17 VSS VSS E27
AE2 E26

I
VSS VSS
AE20 VSS VSS E25 05 Per FMB 0 0
AE24 VSS VSS E20

S
AE25 VSS VSS E2
AE26 VSS VSS E17
AE27 VSS VSS E14 05 Value FMB 0 1
AE28 VSS VSS E11

M 燕
AE29 VSS VSS D9
AE30 VSS VSS D6
AE5 VSS VSS D5
AE7 VSS VSS D3
AF10 VSS VSS D24
AF13 VSS VSS D21
AF16 VSS VSS D18
AF17 VSS VSS D15
AF20 VSS VSS D12

代
AF23 VSS VSS C7
AF24 VSS VSS C4
AF25 C24

謝 91225
VSS VSS
AF26 VSS VSS C22
AF27 VSS VSS C19
AF28 VSS VSS C16 PSI# 30
AF29 VSS VSS C13
B AF3 VSS VSS C10 B
AF30 VSS VSS B8
AF6 VSS VSS B5
AF7 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
3
4

Q13

0
AG10
AG13
AG16
AG17
AG20
AG23
AG24
1
2
3
4

AH13
AH16
AH17
AH20
AH23
AH24
AG7
AH1
AH10

AH3
AH6
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28

AN13
AN16
AN17
AL7
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AN1
AN10

AN2
AN20
AN23
AN24
AN27
AN28
B1
B11
B14
B17
B20
B24
D
+12V R114 X_4.7KR0402 G R101
X_1KR0402

0
S
X_N-2N7002_SOT23
Q15

2
+12V R104 X_4.7KR0402 2 6
1
5,6,8 H_CPURST# R111 X_4.7KR0402 5 3
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH 4
(Place into CPU Socket Cavity)
VCCP
MLCC C63 X_NN-CMKT3904_SOT363-6-RH PSI#_N
X_C10u10Y0805

Q17
C89 C90 C81 C87 C91 C79 +12V R109 X_4.7KR0402 2 6
C22U6.3Y1206 X_C10U6.3Y1206 C22U6.3Y1206 X_C10U6.3Y1206 C22U6.3Y1206 X_C10U6.3Y1206 1
5,6,8 H_CPURST# R121 X_4.7KR0402 5 3
4
VCCP X_NN-CMKT3904_SOT363-6-RH
A A

C86 C83 C88 C78 C80 C82

C22U6.3Y1206 C22U6.3Y1206 X_C10U6.3Y1206 C22U6.3Y1206 X_C10U6.3Y1206 X_C10U6.3Y1206
MICRO-STAR INT'L CO.,LTD

MSI
MS-7592
Size Document Description Rev
Custom LGA775 - GND 5.2

Date: Thursday, December 10, 2009 Sheet 7 of 33

5 4 3 2 1
 5 4 3 2 1

D D

V_FSB_VTT

NB1A EAGLELAKE_DDR2

1
3
5
7
EAGLELAKE_DDR2
H_A#3 L36 F44 H_D#0 RN25 RN26 NB1E
5 H_A#[3..35] FSB_AB_3 FSB_DB_0 H_D#[0..63] 5
H_A#4 L37 C44 H_D#1 8P4R-470R0402 8P4R-10KR0402 HSYNC
FSB_AB_4 FSB_DB_1 HSYNC 27
H_A#5 J38 D44 H_D#2 1 2

2
4
6
8
FSB_AB_5 FSB_DB_2

程
H_A#6 F40 C41 H_D#3 16 MCH_BSEL0 3 4 MCH_BS0 F17 D14
H_A#7 FSB_AB_6 FSB_DB_3 H_D#4 BSEL0 CRT_HSYNC
H39 FSB_AB_7 FSB_DB_4 E43 16 MCH_BSEL1 5 6 MCH_BS1 G16 BSEL1 CRT_VSYNC C14 R no stuff for onbroad graphic
H_A#8 L38 B43 H_D#5 16 MCH_BSEL2 7 8 MCH_BS2 P15
H_A#9 FSB_AB_8 FSB_DB_5 H_D#6 BSEL2 VSYNC
L43 FSB_AB_9 FSB_DB_6 D40 M20 ALLZTEST VSYNC 27
H_A#10 N39 B42 H_D#7 DEMO BOARD CHANGE N17 B18
FSB_AB_10 FSB_DB_7 X_TP T13 XORTEST CRT_RED VGA_RED 27
H_A#11 N35 B38 H_D#8 R233 X_1KR0402 K16 D18
FSB_AB_11 FSB_DB_8 RSVD_36 CRT_GREEN VGA_GREEN 27
H_A#12 N37 H_D#9 R218 EXP_SLR
X_1KR0402

工
FSB_AB_12 FSB_DB_9 F38 F15 EXP_SLR CRT_BLUE C18 VGA_BLUE 27
H_A#13 J41 A38 H_D#10 G15 F13
H_A#14 N40 FSB_AB_13 FSB_DB_10 H_D#11 R205 X_R/2 EXP_EN RSVD_17 CRT_IRTN
FSB_AB_14 FSB_DB_11 B37 22 EXP16_PRSNT# H17 EXP_SM
H_A#15 M45 D38 H_D#12 R194 ITPM_EN
X_1KR0402 L17

VGA
H_A#16 R35 FSB_AB_15 FSB_DB_12 H_D#13 R198 X_1KR0402 ITPM_ENB
FSB_AB_16 FSB_DB_13 C37
H_A#17 T36 D37 H_D#14 M17 L15
FSB_AB_17 FSB_DB_14 G41 no suport ITPM RSVD_10 CRT_DDC_DATA MCH_DDC_DATA 27
H_A#18 R36 B36 H_D#15 MCH_TCEN J17 M15

板
FSB_AB_18 FSB_DB_15 0: enable NC: disable CEN CRT_DDC_CLK MCH_DDC_CLK 27
H_A#19 R34 E37 H_D#16 G20
H_A#20 R37 FSB_AB_19 FSB_DB_16 H_D#17 BSCANTEST
FSB_AB_20 FSB_DB_17 J35 J16 RSVD_12 DAC_IREF B15 DACREFSET
R213 1.02KR1%0402 R236 X_0R0402
H_A#21 R39 H35 H_D#18 remove test pad for layout, refer to DEMO board M16 R230 X_10KR0402 V_1P1_CORE
H_A#22 U38 FSB_AB_21 FSB_DB_18 H_D#19 RSVD_13
FSB_AB_22 FSB_DB_19 F37 X_TP T14 J15 RSVD_14 DPL_REFCLKINP E15 CK_96M_DREF 15
H_A#23 T37 G37 H_D#20 J20 D15
FSB_AB_23 FSB_DB_20 X_TP T12 RSVD_15 DPL_REFCLKINN CK_96M_DREF# 15
H_A#24 U34 J33 H_D#21 VCC3 R203 X_4.7KR0402 F20 G8
FSB_AB_24 FSB_DB_21 DUALX8_ENABLE DPL_REFSSCLKINP DPL_REFSSCLKIN_DP 15

機
H_A#25 U40 L33 H_D#22 G9
FSB_AB_25 FSB_DB_22 DPL_REFSSCLKINN DPL_REFSSCLKIN_DN 15
H_A#26 T34 G33 H_D#23 R243 X_0R0402
H_A#27 FSB_AB_26 FSB_DB_23 H_D#24 R249 X_10KR0402 V_1P1_CORE
Y36 FSB_AB_27 FSB_DB_24 L31
H_A#28 U35 M31 H_D#25 AY4 AN6
FSB_AB_28 FSB_DB_25 CL_DATA RSTINB PLTRST# 12,16
H_A#29 AA35 M30 H_D#26 AY2 AR4 CHIP_PWGD
FSB_AB_29 FSB_DB_26 CL_CLK PWROK CHIP_PWGD 13,28
H_A#30 U37 J30 H_D#27 CL_VREF_MCH AN13 K15 R227 X_R/2
FSB_AB_30 FSB_DB_27 CL_VREF ICH_SYNCB ICH_SYNC# 13
H_A#31 H_D#28 R245 0R0402 PLTRST_CLRSAW2 R228 X_1KR0402

主
C Y37 FSB_AB_31 FSB_DB_28 G31 12,16 PLTRST# CL_RSTB VCC3 C
H_A#32 Y34 K30 H_D#29 CHIP_PWGD R257 0R0402 AN8
H_A#33 FSB_AB_32 FSB_DB_29 H_D#30 CL_PWROK

-
Y38 FSB_AB_33 FSB_DB_30 M29 HDA_BCLK AU4
H_A#34 AA37 G30 H_D#31 AV4
H_A#35 AA36 FSB_AB_34 FSB_DB_31 H_D#32 R259 HDA_RSTB
FSB_AB_35 FSB_DB_32 J29 ITPM_ENB HDA_SDI AU2

MISC
F29 H_D#33 X_4.7KR0402 AR7 AV1

S
FSB_DB_33 JTAG_TDI HDA_SDO
5 H_REQ#[0..4]
H_REQ#0
H_REQ#1
G38 FSB_REQB_0 FSB_DB_34 H29 H_D#34
H_D#35
Itegrated TPM Enable: AN10 JTAG_TDO HDA_SYNC AU3
K35 L25 AN11

I
FSB_REQB_1 FSB_DB_35 JTAG_TCK
H_REQ#2 J39 FSB_REQB_2 FSB_DB_36 K26 H_D#36 0=Enable iTPM AN9 JTAG_TMS DDPC_CTRLCLK J11
H_REQ#3 C43 L29 H_D#37 F11
H_REQ#4 G39
FSB_REQB_3 FSB_DB_37
J26 H_D#38 1=Disable iTPM DDPC_CTRLDATA
P43 H_COMP5_R

S
FSB_REQB_4 FSB_DB_38 DPRSTPB

2
4
6
8
M26 H_D#39 AN17 P42 R172 X_R/2 R244
FSB_DB_39 H_D#40 NC_01 SLPB RN27
5 H_ADSTB#0 J40 FSB_ADSTBB_0 FSB_DB_40 H26 DualX8_Enable B45 NC_02
FSB

T39 F25 H_D#41 AW44 A45 X_R/2 X_8P4R-0R0402-2

5 H_ADSTB#1 FSB_ADSTBB_1 FSB_DB_41 NC_03 RSVD_18
F24 H_D#42 0=2X8 PCIe Ports Enable AN16 B2

1
3
5
7
FSB_DB_42 H_D#43 NC_04 RSVD_19
5 H_DSTBP#0 C39 FSB_DSTBPB_0 FSB_DB_43 G25 AD42 NC_05 RSVD_20 BE1
1=1X16 PCIe Port Enable

M 燕
B39 H24 H_D#44 W30 BE45
5 H_DSTBN#0 FSB_DSTBNB_0 FSB_DB_44 NC_06 RSVD_21
K31 L24 H_D#45 U32 R15 not support HDMI
5 H_DSTBP#1

PM_SLP_N
FSB_DSTBPB_1 FSB_DB_45 H_D#46 PIN H L Description NC_07 RSVD_25
5 H_DSTBN#1 J31 FSB_DSTBNB_1 FSB_DB_46 J24 R42 NC_08 RSVD_26 R14
J25 N24 H_D#47 BE44 T15
5 H_DSTBP#2 FSB_DSTBPB_2 FSB_DB_47 EXP_SLR Normal Reverse PCI_E Lane Reversal NC_09 RSVD_27
K25 C28 H_D#48 BE2 T14
5 H_DSTBN#2 FSB_DSTBNB_2 FSB_DB_48 NC_10 RSVD_28
C32 B31 H_D#49 EXP_EN Concurrent Non-concurrent PCI_E/SDVO co-existence BD45 AB15
5 H_DSTBP#3 FSB_DSTBPB_3 FSB_DB_49 MCH_TCEN Enable Disable TLS confidentiality NC_11 RSVD_29 H_COMP5_R 5,13
D32 F35 H_D#50 BD1 R32
5 H_DSTBN#3 FSB_DSTBNB_3 FSB_DB_50 NC_12 RSVD_30 PM_SLP_N 5
C35 H_D#51 A44 R31
H_DBI#0 FSB_DB_51 H_D#52 NC_13 RSVD_31
5 H_DBI#[0..3] B40 FSB_DINVB_0 FSB_DB_52 B35 AK15 NC_18 RSVD_32 U31 DEMO BOARD CHANGE
H_DBI#1 H_D#53 R214 X_0R0402 B14
H_DBI#2
F33
F26
FSB_DINVB_1 FSB_DB_53 D35
D31 H_D#54
Primary _PEG_Presence NC_19 RSVD_33 U30
L11
FSB_DINVB_2 FSB_DB_54 RSVD_34 T15 X_TP
H_DBI#3 D30 A34 H_D#55 Primary PCIe port Detect: L13 R225 X_10KR0402

代
FSB_DINVB_3 FSB_DB_55 RSVD_35 VCC3
B32 H_D#56
FSB_DB_56
FSB_DB_57 F31 H_D#57 0=PCIe Card is in Primary Slot
J42 D28 H_D#58

謝 91225
5 H_ADS# FSB_ADSB FSB_DB_58 1=PCIe Card is not in Primary Slot INTEL-AC82G41-A3-HF
L40 A29 H_D#59
5 H_TRDY# FSB_TRDYB FSB_DB_59
J43 C30 H_D#60
5 H_DRDY# FSB_DRDYB FSB_DB_60
G44 B30 H_D#61 EAGLELAKE_DDR2
5 H_DEFER# FSB_DEFERB FSB_DB_61
K44 E27 H_D#62 NB1B
5 H_HITM# FSB_HITMB FSB_DB_62
H45 B28 H_D#63 EXP_A_RXP_0 F6 C11 EXP_A_TXP_0
5 H_HIT# FSB_HITB FSB_DB_63 22 EXP_A_RXP_0 PEG_RXP_0 PEG_TXP_0 EXP_A_TXP_0 22
H40 EXP_A_RXN_0 G7 B11 EXP_A_TXN_0
5 H_LOCK# FSB_LOCKB 22 EXP_A_RXN_0 PEG_RXN_0 PEG_TXN_0 EXP_A_TXN_0 22
B 5,6 H_BR#0 L42 FSB_BREQ0B FSB_SWING B24 HXSWING 22 EXP_A_RXP_1
EXP_A_RXP_1 H6 PEG_RXP_1 PEG_TXP_1 A10 EXP_A_TXP_1
EXP_A_TXP_1 22 B
5 H_BNR# J44 FSB_BNRB FSB_RCOMP A23 HXRCOMP 22 EXP_A_RXN_1
EXP_A_RXN_1 G4 PEG_RXN_1 PEG_TXN_1 B9 EXP_A_TXN_1
EXP_A_TXN_1 22
H37 EXP_A_RXP_2 J6 C9 EXP_A_TXP_2
5 H_BPRI# FSB_BPRIB 22 EXP_A_RXP_2 PEG_RXP_2 PEG_TXP_2 EXP_A_TXP_2 22
H42 C22 MCH_GTLREF EXP_A_RXN_2 J7 D8 EXP_A_TXN_2
5 H_DBSY# FSB_DBSYB FSB_DVREF 22 EXP_A_RXN_2 PEG_RXN_2 PEG_TXN_2 EXP_A_TXN_2 22 V_1P1_CORE
H_RS#0 G43 B23 EXP_A_RXP_3 L6 B8 EXP_A_TXP_3
5 H_RS#[0..2] FSB_RSB_0 FSB_ACCVREF 22 EXP_A_RXP_3 PEG_RXP_3 PEG_TXP_3 EXP_A_TXP_3 22
H_RS#1 L44 EXP_A_RXN_3 L7 C7 EXP_A_TXN_3
FSB_RSB_1 22 EXP_A_RXN_3 PEG_RXN_3 PEG_TXN_3 EXP_A_TXN_3 22
H_RS#2 G42 P29 CK_H_MCH 15 EXP_A_RXP_4 N9 B7 EXP_A_TXP_4 Close to MCH A.S.A.P
FSB_RSB_2 HPL_CLKINP 22 EXP_A_RXP_4 PEG_RXP_4 PEG_TXP_4 EXP_A_TXP_4 22
D27 P30 CK_H_MCH# 15 EXP_A_RXN_4 N10 B6 EXP_A_TXN_4 R481 X_5.1KR1%0402 DMI_MCH_IT_MR_0_DP
FSB_CPURSTB HPL_CLKINN 22 EXP_A_RXN_4 PEG_RXN_4 PEG_TXN_4 EXP_A_TXN_4 22
EXP_A_RXP_5 N7 B3 EXP_A_TXP_5 R479 X_5.1KR1%0402 DMI_MCH_IT_MR_1_DP

0
5,6,7 H_CPURST# 22 EXP_A_RXP_5 PEG_RXP_5 PEG_TXP_5 EXP_A_TXP_5 22
N25 EXP_A_RXN_5 N6 B4 EXP_A_TXN_5 R480 X_5.1KR1%0402 DMI_MCH_IT_MR_2_DP
RSVD_05 22 EXP_A_RXN_5 PEG_RXN_5 PEG_TXN_5 EXP_A_TXN_5 22
EXP_A_RXP_6 R7 D2 EXP_A_TXP_6 R478 X_5.1KR1%0402 DMI_MCH_IT_MR_3_DP
22 EXP_A_RXP_6 PEG_RXP_6 PEG_TXP_6 EXP_A_TXP_6 22
EXP_A_RXN_6 R6 C2 EXP_A_TXN_6

0
22 EXP_A_RXN_6 PEG_RXN_6 PEG_TXN_6 EXP_A_TXN_6 22

PCIE
EXP_A_RXP_7 R9 H2 EXP_A_TXP_7
INTEL-AC82G41-A3-HF 22 EXP_A_RXP_7 PEG_RXP_7 PEG_TXP_7 EXP_A_TXP_7 22
EXP_A_RXN_7 R10 G2 EXP_A_TXN_7
22 EXP_A_RXN_7 PEG_RXN_7 PEG_TXN_7 EXP_A_TXN_7 22
GTLREF VOLTAGE SHOULD BE 0.67*VTT=0.804V EXP_A_RXP_8 U10 J2 EXP_A_TXP_8

2
22 EXP_A_RXP_8 PEG_RXP_8 PEG_TXP_8 EXP_A_TXP_8 22
EXP_A_RXN_8 U9 K2 EXP_A_TXN_8
V_FSB_VTT V_FSB_VTT 22 EXP_A_RXN_8 PEG_RXN_8 PEG_TXN_8 EXP_A_TXN_8 22
EXP_A_RXP_9 U6 K1 EXP_A_TXP_9
22 EXP_A_RXP_9 PEG_RXP_9 PEG_TXP_9 EXP_A_TXP_9 22
HXSWING S/B 1/4*VTT +/- 2% EXP_A_RXN_9 U7 L2 EXP_A_TXN_9
CPU_MCH_GTLREF 5 22 EXP_A_RXN_9 PEG_RXN_9 PEG_TXN_9 EXP_A_TXN_9 22
EXP_A_RXP_10 AA9 P2 EXP_A_TXP_10
22 EXP_A_RXP_10 PEG_RXP_10 PEG_TXP_10 EXP_A_TXP_10 22
EXP_A_RXN_10 AA10 M2 EXP_A_TXN_10
22 EXP_A_RXN_10 PEG_RXN_10 PEG_TXN_10 EXP_A_TXN_10 22
R189 R186 EXP_A_RXP_11 R4 T2 EXP_A_TXP_11
22 EXP_A_RXP_11 PEG_RXP_11 PEG_TXP_11 EXP_A_TXP_11 22
300R1%0402 57.6R1%0402-RH EXP_A_RXN_11 P4 R1 EXP_A_TXN_11
22 EXP_A_RXN_11 PEG_RXN_11 PEG_TXN_11 EXP_A_TXN_11 22
EXP_A_RXP_12 AA7 U2 EXP_A_TXP_12
22 EXP_A_RXP_12 PEG_RXP_12 PEG_TXP_12 EXP_A_TXP_12 22
R193 49.9R1%0402 HXSWING R201 49.9R1%0402 MCH_GTLREF EXP_A_RXN_12 AA6 V2 EXP_A_TXN_12
22 EXP_A_RXN_12 PEG_RXN_12 PEG_TXN_12 EXP_A_TXN_12 22
EXP_A_RXP_13 AB10 W4 EXP_A_TXP_13
22 EXP_A_RXP_13 PEG_RXP_13 PEG_TXP_13 EXP_A_TXP_13 22
EXP_A_RXN_13 AB9 V3 EXP_A_TXN_13
22 EXP_A_RXN_13 PEG_RXN_13 PEG_TXN_13 EXP_A_TXN_13 22
R191 C176 R197 C173 C184 EXP_A_RXP_14 AB3 AA4 EXP_A_TXP_14
22 EXP_A_RXP_14 PEG_RXP_14 PEG_TXP_14 EXP_A_TXP_14 22
100R1%/2 C0.1U16Y0402 100R1%/2 C1u16Y C220p16X0402 EXP_A_RXN_14 AA2 Y4 EXP_A_TXN_14
22 EXP_A_RXN_14 PEG_RXN_14 PEG_TXN_14 EXP_A_TXN_14 22
EXP_A_RXP_15 AD10 AC1 EXP_A_TXP_15
22 EXP_A_RXP_15 PEG_RXP_15 PEG_TXP_15 EXP_A_TXP_15 22
EXP_A_RXN_15 AD11 AB2 EXP_A_TXN_15
22 EXP_A_RXN_15 PEG_RXN_15 PEG_TXN_15 EXP_A_TXN_15 22
DMI_MCH_IT_MR_0_DP AD7 AC2
12 DMI_MCH_IT_MR_0_DP DMI_RXP_0 DMI_TXP_0 DMI_ICH_MT_IR_0_DP 12
DMI_MCH_IT_MR_0_DN AD8 AD2
V_1P1_CORE 12 DMI_MCH_IT_MR_0_DN DMI_RXN_0 DMI_TXN_0 DMI_ICH_MT_IR_0_DN 12
DMI_MCH_IT_MR_1_DP AE9 AD4
12 DMI_MCH_IT_MR_1_DP DMI_RXP_1 DMI_TXP_1 DMI_ICH_MT_IR_1_DP 12
DMI_MCH_IT_MR_1_DN AE10 AE4
12 DMI_MCH_IT_MR_1_DN DMI_RXN_1 DMI_TXN_1 DMI_ICH_MT_IR_1_DN 12
DMI

HXRCOMP DMI_MCH_IT_MR_2_DP AE6 AE2

12 DMI_MCH_IT_MR_2_DP DMI_RXP_2 DMI_TXP_2 DMI_ICH_MT_IR_2_DP 12
R195 DMI_MCH_IT_MR_2_DN AE7 AF2
12 DMI_MCH_IT_MR_2_DN DMI_RXN_2 DMI_TXN_2 DMI_ICH_MT_IR_2_DN 12
16.5R1%/2 DMI_MCH_IT_MR_3_DP AF9 AF4
12 DMI_MCH_IT_MR_3_DP DMI_RXP_3 DMI_TXP_3 DMI_ICH_MT_IR_3_DP 12
A C175 R275 DMI_MCH_IT_MR_3_DN AF8 AG4 A
12 DMI_MCH_IT_MR_3_DN DMI_RXN_3 DMI_TXN_3 DMI_ICH_MT_IR_3_DN 12
X_C2.7P/25N/2 1KR0402
15 CK_PE_100M_MCH CK_PE_100M_MCH D9 Y7 GRCOMP R255 49.9R1%0402 V_1P1_CORE
V_FSB_VTT CL_VREF_MCH CK_PE_100M_MCH# EXP_CLKP EXP_RCOMPO
15 CK_PE_100M_MCH# E9 EXP_CLKN EXP_COMPI Y8
SDVOCTRLDATA Bottom side
22 SDVOCTRLDATA
SDVOCTRLCLK
J13
G13
SDVO_CTRLDATA EXP_ICOMPO Y6
AG1 R241 X_750R1%0402 V_1P1_CORE MSI MICRO-STAR INt'L CO., LTD.
22 SDVOCTRLCLK SDVO_CTRLCLK EXP_RBIAS
R274 C232 AB13
464R1%0402 C0.1U16Y0402 RSVD_23 R250 750R1%0402 Title
AD13 RSVD_22
C174 C125 C137 Intel Bearlake G41 - CPU Signals
C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402
SDVOCTRLDATA R253 X_2.2KR0402 VCC3 Size Document Number Rev
SDVOCTRLCLK R252 X_2.2KR0402
INTEL-AC82G41-A3-HF MS-7592 5.2
Date: Friday, December 18, 2009 Sheet 8 of 33

5 4 3 2 1
 5 4 3 2 1

EAGLELAKE_DDR2
X_TP EAGLELAKE_DDR2 MAA_B[0..14] NB1D
T20 19 MAA_B[0..14]
NB1C MAA_B0 BD24 AW8 DQS_B0
MAA_A[1..14] DDR_B_MA_0 DDR_B_DQS_0 DQS_B0 19
TP_MAA_A0 BC41 BC5 DQS_A0 MAA_B1 BB23 AW9 DQS_B#0
18 MAA_A[1..14] DDR_A_MA_0 DDR_A_DQS_0 DQS_A0 18 DDR_B_MA_1 DDR_B_DQSB_0 DQS_B#0 19
MAA_A1 BC35 BD4 DQS_A#0 MAA_B2 BB24 AT15 DQS_B1
DDR_A_MA_1 DDR_A_DQSB_0 DQS_A#0 18 DDR_B_MA_2 DDR_B_DQS_1 DQS_B1 19
MAA_A2 BB32 BB9 DQS_A1 MAA_B3 BD23 AU15 DQS_B#1
DDR_A_MA_2 DDR_A_DQS_1 DQS_A1 18 DDR_B_MA_3 DDR_B_DQSB_1 DQS_B#1 19
MAA_A3 BC32 BC9 DQS_A#1 MAA_B4 BB22 AR20 DQS_B2
DDR_A_MA_3 DDR_A_DQSB_1 DQS_A#1 18 DDR_B_MA_4 DDR_B_DQS_2 DQS_B2 19
MAA_A4 BD32 BD15 DQS_A2 MAA_B5 BD22 AR17 DQS_B#2
DDR_A_MA_4 DDR_A_DQS_2 DQS_A2 18 DDR_B_MA_5 DDR_B_DQSB_2 DQS_B#2 19
MAA_A5 BB31 BB15 DQS_A#2 MAA_B6 BC22 AU26 DQS_B3
DDR_A_MA_5 DDR_A_DQSB_2 DQS_A#2 18 DDR_B_MA_6 DDR_B_DQS_3 DQS_B3 19
MAA_A6 AY31 AR22 DQS_A3 MAA_B7 BC20 AT26 DQS_B#3
DDR_A_MA_6 DDR_A_DQS_3 DQS_A3 18 DDR_B_MA_7 DDR_B_DQSB_3 DQS_B#3 19
MAA_A7 BA31 AT22 DQS_A#3 MAA_B8 BB20 AR38 DQS_B4
DDR_A_MA_7 DDR_A_DQSB_3 DQS_A#3 18 DDR_B_MA_8 DDR_B_DQS_4 DQS_B4 19
MAA_A8 BD31 AH43 DQS_A4 MAA_B9 BD20 AR37 DQS_B#4
DDR_A_MA_8 DDR_A_DQS_4 DQS_A4 18 DDR_B_MA_9 DDR_B_DQSB_4 DQS_B#4 19
MAA_A9 BD30 AH42 DQS_A#4 MAA_B10 BC26 AK34 DQS_B5
DDR_A_MA_9 DDR_A_DQSB_4 DQS_A#4 18 DDR_B_MA_10 DDR_B_DQS_5 DQS_B5 19
D MAA_A10 AW43 AD43 DQS_A5 MAA_B11 BD19 AL34 DQS_B#5 D
DDR_A_MA_10 DDR_A_DQS_5 DQS_A5 18 DDR_B_MA_11 DDR_B_DQSB_5 DQS_B#5 19
MAA_A11 BC30 AE42 DQS_A#5 MAA_B12 BB19 AF37 DQS_B6
DDR_A_MA_11 DDR_A_DQSB_5 DQS_A#5 18 DDR_B_MA_12 DDR_B_DQS_6 DQS_B6 19
MAA_A12 BB30 Y43 DQS_A6 MAA_B13 BE38 AF36 DQS_B#6
DDR_A_MA_12 DDR_A_DQS_6 DQS_A6 18 DDR_B_MA_13 DDR_B_DQSB_6 DQS_B#6 19
MAA_A13 AM42 Y42 DQS_A#6 MAA_B14 BA19 AB35 DQS_B7
DDR_A_MA_13 DDR_A_DQSB_6 DQS_A#6 18 DDR_B_MA_14 DDR_B_DQS_7 DQS_B7 19
MAA_A14 BD28 T44 DQS_A7 AD35 DQS_B#7
DDR_A_MA_14 DDR_A_DQS_7 DQS_A7 18 DDR_B_DQSB_7 DQS_B#7 19
T43 DQS_A#7 WE_B# BD36
DDR_A_DQSB_7 DQS_A#7 18 19 WE_B# DDR_B_WEB
X_TPTP_WE_A# AW42 CAS_B# BC37
T11 DDR_A_WEB DQM_A[0..7] 19 CAS_B# DDR_B_CASB DQM_B[0..7]
CAS_A# AU42 BC3 DQM_A0 RAS_B# BD35 AY6 DQM_B0
18 CAS_A# DDR_A_CASB DDR_A_DM_0 DQM_A[0..7] 18 19 RAS_B# DDR_B_RASB DDR_B_DM_0 DQM_B[0..7] 19
RAS_A# AV42 BD9 DQM_A1 AR15 DQM_B1
18 RAS_A# DDR_A_RASB DDR_A_DM_1 DQM_A2 SBS_B0 DDR_B_DM_1 DQM_B2
DDR_A_DM_2 BD14 19 SBS_B0 BD26 DDR_B_BS_0 DDR_B_DM_2 AU17

程
SBS_A0 AV45 AV22 DQM_A3 SBS_B1 BB26 AV25 DQM_B3
18 SBS_A0 SBS_A1 DDR_A_BS_0 DDR_A_DM_3 DQM_A4 19 SBS_B1 SBS_B2 DDR_B_BS_1 DDR_B_DM_3 DQM_B4
18 SBS_A1 AY44 DDR_A_BS_1 DDR_A_DM_4 AK42 19 SBS_B2 BD18 DDR_B_BS_2 DDR_B_DM_4 AU39
SBS_A2 BC28 AE45 DQM_A5 AL37 DQM_B5
18 SBS_A2 DDR_A_BS_2 DDR_A_DM_5 DQM_A6 SCS_B#0 DDR_B_DM_5 DQM_B6
DDR_A_DM_6 AA45 19 SCS_B#0 BB35 DDR_B_CSB_0 DDR_B_DM_6 AJ35
SCS_A#0 AU43 T42 DQM_A7 SCS_B#1 BD39 AD37 DQM_B7
18 SCS_A#0 DDR_A_CSB_0 DDR_A_DM_7 19 SCS_B#1 DDR_B_CSB_1 DDR_B_DM_7

工
TP_SCS_A#1 AR40 BB37
T18 DDR_A_CSB_1 DATA_A[0..63] DDR_B_CSB_2 DATA_B[0..63]
AU44 BC2 DATA_A0 BD40
DDR_A_CSB_2 DDR_A_DQ_0 DATA_A[0..63] 18 DDR_B_CSB_3 DATA_B[0..63] 19
X_TP AM43 BD3 DATA_A1 AV7 DATA_B0
DDR_A_CSB_3 DDR_A_DQ_1 DATA_A2 SCKE_B0 DDR_B_DQ_0 DATA_B1
DDR_A_DQ_2 BD7 19 SCKE_B0 BC18 DDR_B_CKE_0 DDR_B_DQ_1 AW4
SCKE_A0 BB27 BB7 DATA_A3 SCKE_B1 AY20 BA9 DATA_B2
18 SCKE_A0 DDR_A_CKE_0 DDR_A_DQ_3 19 SCKE_B1 DDR_B_CKE_1 DDR_B_DQ_2

板
SCKE_A1 BD27 BB2 DATA_A4 BE17 AU11 DATA_B3
18 SCKE_A1 DDR_A_CKE_1 DDR_A_DQ_4 DATA_A5 DDR_B_CKE_2 DDR_B_DQ_3 DATA_B4
BA27 DDR_A_CKE_2 DDR_A_DQ_5 BA3 BB18 DDR_B_CKE_3 DDR_B_DQ_4 AU7
AY26 BE6 DATA_A6 AU8 DATA_B5
DDR_A_CKE_3 DDR_A_DQ_6 DATA_A7 ODT_B0 DDR_B_DQ_5 DATA_B6
DDR_A_DQ_7 BD6 19 ODT_B0 BD37 DDR_B_ODT_0 DDR_B_DQ_6 AW7
ODT_A0 AR42 BB8 DATA_A8 ODT_B1 BC39 AY9 DATA_B7
18 ODT_A0 DDR_A_ODT_0 DDR_A_DQ_8 19 ODT_B1 DDR_B_ODT_1 DDR_B_DQ_7

機
ODT_A1 AM44 AY8 DATA_A9 BB38 AY13 DATA_B8
18 ODT_A1 DDR_A_ODT_1 DDR_A_DQ_9 DATA_A10 DDR_B_ODT_2 DDR_B_DQ_8 DATA_B9
AR44 DDR_A_ODT_2 DDR_A_DQ_10 BD11 BD42 DDR_B_ODT_3 DDR_B_DQ_9 AP15
AL40 BB11 DATA_A11 AW15 DATA_B10
DDR_A_ODT_3 DDR_A_DQ_11 DATA_A12 P_DDR0_B DDR_B_DQ_10 DATA_B11
DDR_A_DQ_12 BC7 19 P_DDR0_B AY33 DDR_B_CK_0 DDR_B_DQ_11 AT16
C P_DDR0_A AY37 BE8 DATA_A13 N_DDR0_B AW33 AU13 DATA_B12 C
18 P_DDR0_A

主
N_DDR0_A DDR_A_CK_0 DDR_A_DQ_13 DATA_A14 19 N_DDR0_B DDR_B_CKB_0 DDR_B_DQ_12 DATA_B13
18 N_DDR0_A BA37 DDR_A_CKB_0 DDR_A_DQ_14 BD10 AV31 DDR_B_CK_1 DDR_B_DQ_13 AW13
DATA_A15 DATA_B14

-
AW29 DDR_A_CK_1 DDR_A_DQ_15 AY11 AW31 DDR_B_CKB_1 DDR_B_DQ_14 AP16
AY29 BB14 DATA_A16 P_DDR2_B AW35 AU16 DATA_B15
P_DDR2_A DDR_A_CKB_1 DDR_A_DQ_16 DATA_A17 19 P_DDR2_B N_DDR2_B DDR_B_CK_2 DDR_B_DQ_15 DATA_B16
18 P_DDR2_A AU37 DDR_A_CK_2 DDR_A_DQ_17 BC14 19 N_DDR2_B AY35 DDR_B_CKB_2 DDR_B_DQ_16 AY17

S
N_DDR2_A AV37 BC16 DATA_A18 AT31 AV17 DATA_B17
18 N_DDR2_A DDR_A_CKB_2 DDR_A_DQ_18 DATA_A19 DDR_B_CK_3 DDR_B_DQ_17 DATA_B18
AU33 BB16 AU31 AR21

I
DDR_A_CK_3 DDR_A_DQ_19 DATA_A20 DDR_B_CKB_3 DDR_B_DQ_18 DATA_B19
AT33 DDR_A_CKB_3 DDR_A_DQ_20 BC11 AP31 DDR_B_CK_4 DDR_B_DQ_19 AV20
AT30 BE12 DATA_A21 AP30 AP17 DATA_B20
DDR_A_CK_4 DDR_A_DQ_21 DDR_B_CKB_4 DDR_B_DQ_20

S
AR30 BA15 DATA_A22 AW37 AW16 DATA_B21
DDR_A_CKB_4 DDR_A_DQ_22 DATA_A23 DDR_B_CK_5 DDR_B_DQ_21 DATA_B22
AW38 DDR_A_CK_5 DDR_A_DQ_23 BD16 AV35 DDR_B_CKB_5 DDR_B_DQ_22 AT20
AY38 AW21 DATA_A24 AN20 DATA_B23
DDR_A_CKB_5 DDR_A_DQ_24 DATA_A25 DDR_B_DQ_23 DATA_B24
DDR_A_DQ_25 AY22 DDR_B_DQ_24 AT25
DATA_A26 DATA_B25

M 燕
DDR_A_DQ_26 AV24 DDR_B_DQ_25 AV26
AY24 DATA_A27 AU29 DATA_B26
DDR_A_DQ_27 DATA_A28 DDR_B_DQ_26 DATA_B27
DDR_A_DQ_28 AU21 DDR_B_DQ_27 AV29
AT21 DATA_A29 AW25 DATA_B28
DDR_A_DQ_29 DATA_A30 DDR_B_DQ_28 DATA_B29
DDR_A_DQ_30 AR24 DDR_B_DQ_29 AR25
AU24 DATA_A31 AP26 DATA_B30
DDR_A_DQ_31 DATA_A32 DDR_B_DQ_30 DATA_B31
DDR_A_DQ_32 AL41 DDR_B_DQ_31 AR29
AK43 DATA_A33 AR36 DATA_B32
DDR_A_DQ_33 DATA_A34 VCC_DDR DDR_B_DQ_32 DATA_B33
DDR_A_DQ_34 AG42 DDR_B_DQ_33 AU38

代
AG44 DATA_A35 AN35 DATA_B34
DDR_A_DQ_35 DATA_A36 DDR_B_DQ_34 DATA_B35
DDR_A_DQ_36 AL42 DDR_B_DQ_35 AN37
AK44 DATA_A37 DATA_B36
DDR_B AV39

謝 91225
DDR3_RST# DDR_A_DQ_37 DATA_A38 DDR_B_DQ_36 DATA_B37
18,19 DDR3_RST# BC24 DDR3_DRAMRSTB DDR_A_DQ_38 AH44