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Verilog
Verilog
// Mdulo Porta_XOR
module Porta_XOR(S, A, B, C);
input A, B, C;
output S;
assign S = A^B^C;
endmodule
// Mdulo Somador/Subtrator de 2 bits
module Soma_Sub (SW, LEDR);
input [4:0] SW;
output [2:0] LEDR;
wire A1, A0, B1, B0, S1, S0, C, m, x, y, z, t, u, v;
assign B0 = SW[0];
assign B1 = SW[1];
assign A0 = SW[2];
assign A1 = SW[3];
assign m = SW[4]
assign LEDR[0] = S0;
assign LEDR[1] = S1;
assign LEDR[2] = C;
// Determinao de S0
Porta_XOR U1(S0, A0, B0, 0);
// Determinao de S1
Porta_XOR U2(x, A0, m, 0);
Porta_XOR U3(y, A1, m, 0);
Porta_AND U4(z, x, B0, 1);
Porta_XOR U5(S1, A1, B1, z);
// Determinao de C
Porta_AND U6(t, y, B1, 1);
Porta_AND U7(u, x, y, B0);
Porta_AND U8(v, x, B1, B0);
Porta_OR U9(C, t, u, v);
endmodule
//Mdulo do Flip-Flop D
module FlipFlopD(Q, D, CK, CLR);
input D, CK, CLR;
output Q;
reg Q;
always @(negedge CK or negedge CLR)
begin
if(!CLR) Q = 0;
else Q = D;
end
endmodule
//Mdulo do Flip-Flop JK
module FlipFlopJK(Q, J, K, CK, CLR);
input J, K, CK, CLR;
output Q;
reg Q;
always @(negedge CK or negedge CLR)
begin
if(!CLR) Q = 0;
else
begin
case ({J, K})
0: Q =
1: Q =
2: Q =
3: Q =
endcase
end
end
endmodule
//Mdulo da porta NAND
module porta_NAND(S, A, B);
input A, B;
output S;
Q;
0;
1;
~Q;
assign S = ~(A&B);
endmodule
// Registrador entrada paralela / sada serial de 4 bits
wire Q, E, CK, CLR;
wire[3:0] I, x;
wire [2:0] y;
assignI [3:0] = SW [3:0]
assignE = SW[4];
assign CLR = SW[5];
assign CK = CLOCK_27;
porta_NAND U0( x[3], I[3], E);
porta_NAND U1( x[2], I[2], E);
porta_NAND U2( x[1], I[1], E);
porta_NAND U3( x[0], I[0], E);
FlipFlopD_PR U4( y[2], 0, CK, CLR, x[3] );
FlipFlopD_PR U5( y[1], y[2], CK, CLR, x[2] );
FlipFlopD_PR U6( y[0], y[1], CK, CLR, x[1] );
FlipFlopD_PRU7(Q, y[0], CK, CLR, x[0] );
assign LEDR[0] = Q;
endmodule
//Mdulo do Flip-Flop D com entrada PR
module FlipFlopD_PR(Q, D, CK, CLR, PR);
input D, CK, CLR, PR;
output Q;
reg Q;
always @(negedge CK or negedge CLR or negedge PR)
begin
if(!CLR) Q = 0;
else if(!PR) Q = 1;
else Q = D;
end
endmodule
// Registrador de deslocamento direita/esquerda de 4 bits
wire [3:0] q, x;
wire [1:0] y;
wire D, CK, CLR;
assign D = SW [0];
assign CLR = SW[1];
assign y[1:0] = SW[3:2];
assign CK = KEY[0];
MUX2x1 U3( x[3], D, q[2], y[1]);
FlipFlopD W3( q[3], x[3], CK, CLR);
MUX2x1 U2( x[2], D, q[1], q[3]);
FlipFlopD W2( q[2], x[2], CK, CLR);
MUX2x1 U1( x[1], D, q[0], q[2]);
FlipFlopD W1( q[1], x[1], CK, CLR);
MUX2x1 U0( x[0], D, y[0], q[1]);
FlipFlopD W0( q[0], x[0], CK, CLR);
assign LEDR [3:0] = q[3:0];
endmodule
//Mdulo do MUX 2x1
module MUX2x1(S, D, I0, I1);
input I0, I1, D;
output S;
reg S;
always @( I0 or I1 or D)
begin
case(D)
0: S = I0;
1: S = I1;
end
endmodule
endcase
decrescente
K[2]);
K[1]);
K[0]);