Foxcom M61PMV

5 4 3 2 1
Foxconn MCP61M05
Fab :A
D D
nVIDIA MCP61 Chipset for AMD M2 CPU

(3/31/2008)
PAGE CONTENT PAGE CONTENT

1 01. COVER 25 25. USB CONNECTORS
2 02. BLOCK DIAGRAM 26 26. LAN
3 03. RESET MAP 27 27. PWR CONN / FNT PNL / VBAT
4 04. CLOCK DISTRIBUTION 28 28. ACPI VREG
C C
5 05. PCI DEVICE / VID TABLE 29 29. MCP61 CORE POWER

6 06. M2-1 Hyper Transport 30 30. VRM
7 07. M2-2 DDRII -1 31 31. LAN CONN
8 08. M2-2 DDRII -2 32 32. AUDIO ALC888/ALC662
9 09. M2-3 MISC 33 33. Power Map
10 10. M2-4 Power 34 34. Modify List
11 11. DDRII SDRAM DIMM1-2 35 35. Optional Part
12 12. DDRII Terminator
13 13. MCP61_HT
B
14 14. MCP61_PCI-E_RGM_VGA B
15 15. MCP61_POWER
16 16. MCP61_PCI
17 17. MCP61_SATA_IDE
18 18. MCP61_HDA_USB
19 19. PCI_E X16 Slot
20 20. PCI SLOT 1 2 3
21 21. SIO IT8716F
22 22. IDE / Floppy / PS2
A
23 23. PLT / COM A
24 24. FAN / HARDWARE MONITOR /VID

LEADTEK RESEARCH INC. ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS. FOXCONN PCEG
THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. Title
Cover
COPYRIGHT 2002 LEADTEK RESEARCH INC. . Size Document Number Rev
C MCP61M05 A
Date: Friday, June 27, 2008 Sheet 1 of 35

5 4 3 2 1
5 4 3 2 1
D D
MCP61M05 Block Diagram
64-BIT 800/667/533/400MHZ
SOCKET M2
POWER 60 Amp DDRII Memory CH:A DDRII SDRAM CONN 1
SUPPLY
CONNECTOR VREG -> ISL6566 => 3 phase
2*12 = 24 pin DDRII Memory CH:B DDRII SDRAM CONN 2
2*2 = 4 pin (12V)
PWRBTN# S I/O PANSWHJ SW
HT 16X16 2GT/S
CPU_VLD
PCI EXPRESS Lane * 16
C C
PCI Express X16 HT_VLD
PCI_RESET0*
SB PS_ON# ACPI PS_OUT#
NFORCE
PCI EXPRESS Lane * 1
SLP_S5*
PCI Express X1 SLP_S3* PWRGD_PS
VRM_EN ATX POWER
PCI SLOT 1
VRM PWM_GD
MCP61
PCI V2.3 / 33MHZ

PCI SLOT 2
ATA 133
PRIMARY IDE 692 Ball BGA
HDA
Azalia / ALC888 (7.1 Audio)
INTEGRATED SATA
SATA-II CONN * 4
B B
BACK PANEL CONN => 4 Port
X8 USB ( V2.0 EHCI / V1.1 OHCI ) USB2 PORTS 7,8
USB2 PORTS 1,6

10/100Mb (Giga-Bit )LAN PHY
FLOPPY CONN
PS2/KB CONN
LPC BUS V1.0 / 33MHZ
FRONT PANEL Header * 2 => 4 Port
SIO
PARALLEL CONN USB2 PORTS 2,3
ITE IT8716F/FX
USB2 PORTS 4,5
SERIAL CONN (COM1)
SERIAL Header (COM2)

RGMII/MII
4MB FLASH AC131
A A
FOXCONN PCEG
Title
Block Diagram
Size Document Number Rev
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
RESET MAP
CPU RST*
D D
K8 Socket M2
CPU PWRGD
MCP61
HT_CPU_PWRGD
HT CPU PWRGD
PE_RESET*
HT_CPU_RST*
HT CPU RST*
PEX X16
PEX X1
PWR SWTCH
PWR CONN PWRBTN*

PWR BUTTON
C C
SLP_S3* PCIRST_SLOT1*
PS ON SLP S3* PCI RST0*
PCIRST_SLOT2*
PCI RST1*
PWR GOOD POWER_GOOD PWRGD
PCIRST_SLOT3*
PCI RST2*
PCI RST3* PCIRST_IDE*
LPC_RST* LPCRST_FLASH*
PWRGD SB PWRGD_SB PWRGD_SB
LPCRST_SIO*
CIRCUIT
GPIO_AUX* AC_RESET*
SIO FLASH PRI IDE VT6307 PCI SLOT 2 PCI SLOT 1
SEC IDE
LAN_PHY AUDIO_PHY
RESET* RESET*
PWM_GD VRM
PWM_GD PGOOD
TIGER ONE (8)
(35)
B B
PWRGD_PS
PWR_OK ALL_PWR_OK VRM_EN
POWER ON SCHEME VRM_EN ENLL
(46) (1) (9) (37)
HT_VLD
MCP61
SLP_S3#
PWBTN# SLP_S5#
PWRBTN#
HT_VLD
PWRON# PSIN ATX
(72) (71) TIGER ONE Power
Supply MCP61 CPU
PWRGD_PS ALL_PWROK
IT8716F PSON# PWROK PWRGD PWROK
PS_ON_OUT#
PANSWHJ PS_ON_IN#
Power button input PANSWH# PSON# (7)
(75) (76) (6)
A A
FOXCONN PCEG
Title
Reset Map MCP61M05
C A

5 4 3 2 1
5 4 3 2 1
K8 M2 CPU
D D
HT_CPU_TXCLK0
HT_CPU_TXCLK0*
MEMCLK_L[0,5,7] DIMM 0
HT_CPU_RXCLK0 MEMCLK_H[0,5,7] CHANNEL A1 0-63
HT_CPU_RXCLK0*
MEMCLK_L[2,3]
HT_CPU_TXCLK1 MEMCLK_H[2,3] NC
HT_CPU_TXCLK1*
HT_CPU_RXCLK1 MEMCLK_L[1,4,6] DIMM 1

HT_CPU_RXCLK1* MEMCLK_H[1,4,6] CHANNEL B1 0~63
CPUCLK_IN*
CPUCLK_IN
MCP61
CLKOUT_200MHZ
CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
PE0_REFCLK PEX X16
PE0_REFCLK*
HT_CPU_TXCLK1*
C HT_CPU_TXCLK1 C
PE1_REFCLK PEX X1
HT_CPU_RXCLK0* PE1_REFCLK*
HT_CPU_RXCLK0
HT_CPU_TXCLK0* PE2_REFCLK
HT_CPU_TXCLK0 PE2_REFCLK*
14MHZ OR 24MHZ
BUF_SIO
SUSCLK SIO
LPC_CLK0 PCI SLOT 1
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3 PCI SLOT 2
PCI_CLK4
PCI_CLK_FB
LPC_CLK1 PCI SLOT 3
32.768 KHZ RTC_XTAL FLASH LPC

AC_BITCLK HEADER
XTAL_IN
AZALIA
25 MHZ
BUF_25MHZ CODEC
B XTAL_OUT B
LAN
PHY
A A
FOXCONN PCEG
Title
Clock Distribution
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
PCI INTERRUPT/IDSEL MAP

D
CPU VID TABLE D
BACK PANEL PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT PCI SLOT PCI SLOT REQ/GNT
VID [4..0] VDD VID [4..0] VDD
SLOT INTA* INTB* INTC* INTD*
0X00000 1.550V 0X10000 1.150V

VT6308 01 0X06 22 P_INTZ* 1/1
0X00001 1.525V 0X10001 1.125V
PCI 2 01 0X08 23 P_INTW* P_INTX* P_INTY* P_INTZ* 2/2
0X00010 1.500V 0X10010 1.100V
PCI 1 01 0X09 24 P_INTX* P_INTY* P_INTZ* P_INTW* 3/3
0X00011 1.475V 0X10011 1.075V
0X00100 1.450V 0X10100 1.050V
0X00101 1.425V 0X10101 1.025V
0X00110 1.400V 0X10110 1.000V
0X00111 1.375V 0X10111 0.975V
0X01000 1.350V 0X11000 0.950V
0X01001 1.325V 0X11001 0.925V
0X01010 1.300V 0X11010 0.900V
0X01011 1.275V 0X11011 0.875V
0X01100 1.250V 0X11100 0.850V PCI DEVICE MAP

0X01101 1.225V 0X11101 0.825V
0X01110 1.200V 0X11110 0.800V

DEVICE PCI BUS# DEVICE# FUNCTION DEVICE ID SOT23 SOT23-5/SC70
MCP51 LOGICAL SOT89-5
C
0X01111 1.175V 0X11111 OFF MCP 61 PCI BUS 0 0X01-0X0F -- --
C
MAC /MAC 0 XA 0 0X56/57 3 5 4
PCI-PCI BRIDGE 0 X9 0 0X005C
SATA1 0 X8 0 0X0055
SMBUS ADDRESS MAP SATA0 0 X8 0 0X0054
IDE 0 X6 0 0X0053
DEVICE SMBUS # ADDRESS MODEM CODEC 0 X4 1 0X0058

1 2
DIMM 0 0 1010 000 = 0X50
AUDIO CODEC 0 X4 0 0X0059 1 2 3
USB 2.0 0 X2 1 0X005B
DIMM 1 0 1010 001 = 0X51
USB 1.1 0 X2 0 0X005A
DIMM 2 0 1010 010 = 0X52
SHAPE TRIM 0 X1 2 0X005F
DIMM 3 0 1010 011 = 0X53
LDT 0 X0 0 0X005E
SIO 1 0101 101 = 0X2D
SMBUS2 0 X1 1 0X0052 SOT23-6
PCI SLOT 1 1 ARP SOT223
LEGACY SLAVE 0 ? ? 0X00D3
PCI SLOT 2 1 ARP
1394 1 ARP
LPC 0 X1 0 0X0050/51 6 5 4 4
LOGICAL PCI BUS 1 ? ? ?
A ? PCI SLOT 1
DDC BUS
B ? PCI SLOT 2
DDC BUS
PCI SLOT 3
B PCI SLOT 4 B
PCI SLOT 5 1 2 3
1 2 3
A A
FOXCONN PCEG
Title
PCI Device / VID Table
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
D D
U9A
HYPERTRANSPORT
13 HT_RC_CPU_CLK_H1 N6 L0_CLKIN_H(1) L0_CLKOUT_H(1) AD5 HT_CPU_RC_CLK_H1 13
13 HT_RC_CPU_CLK_L1 P6 L0_CLKIN_L(1) L0_CLKOUT_L(1) AD4 HT_CPU_RC_CLK_L1 13
13 HT_RC_CPU_CLK_H0 N3 L0_CLKIN_H(0) L0_CLKOUT_H(0) AD1 HT_CPU_RC_CLK_H0 13
+1.2V_HT N2 AC1 HT_CPU_RC_CLK_L0 13
13 HT_RC_CPU_CLK_L0 L0_CLKIN_L(0) L0_CLKOUT_L(0)
**
R150 49.9 +/-1% HT_CPU_CTLIN_H1 V4 Y6 HT_CPU_CTLOUT_H1 1 TP14

R149 49.9 +/-1% HT_CPU_CTLIN_L1
L0_CTLIN_H(1) L0_CTLOUT_H(1) HT_CPU_CTLOUT_L1 TP12
C V5 L0_CTLIN_L(1) L0_CTLOUT_L(1) W6 1 C
13 HT_RC_CPU_CTL_H0 U1 L0_CTLIN_H(0) L0_CTLOUT_H(0) W2 HT_CPU_RC_CTL_H0 13

13 HT_RC_CPU_CTL_L0 V1 L0_CTLIN_L(0) L0_CTLOUT_L(0) W3 HT_CPU_RC_CTL_L0 13
HT_RC_CPU_CAD_H15 U6 Y5 HT_CPU_RC_CAD_H15
13 HT_RC_CPU_CAD_H[15..0] L0_CADIN_H(15) L0_CADOUT_H(15) HT_CPU_RC_CAD_H[15..0] 13
HT_RC_CPU_CAD_L15 V6 Y4 HT_CPU_RC_CAD_L15
13 HT_RC_CPU_CAD_L[15..0] L0_CADIN_L(15) L0_CADOUT_L(15) HT_CPU_RC_CAD_L[15..0] 13
HT_RC_CPU_CAD_H14 T4 AB6 HT_CPU_RC_CAD_H14
HT_RC_CPU_CAD_L14
L0_CADIN_H(14) L0_CADOUT_H(14) HT_CPU_RC_CAD_L14
T5 L0_CADIN_L(14) L0_CADOUT_L(14) AA6
HT_RC_CPU_CAD_H13 R6 AB5 HT_CPU_RC_CAD_H13
HT_RC_CPU_CAD_L13
T6 L0_CADIN_L(13) L0_CADOUT_L(13) AB4
HT_RC_CPU_CAD_H12 P4 AD6 HT_CPU_RC_CAD_H12
HT_RC_CPU_CAD_L12
P5 L0_CADIN_L(12) L0_CADOUT_L(12) AC6
HT_RC_CPU_CAD_H11 M4 AF6 HT_CPU_RC_CAD_H11
HT_RC_CPU_CAD_L11
M5 L0_CADIN_L(11) L0_CADOUT_L(11) AE6
HT_RC_CPU_CAD_H10 L6 AF5 HT_CPU_RC_CAD_H10
HT_RC_CPU_CAD_L10
M6 L0_CADIN_L(10) L0_CADOUT_L(10) AF4
HT_RC_CPU_CAD_H9 K4 AH6 HT_CPU_RC_CAD_H9
HT_RC_CPU_CAD_L9
K5 L0_CADIN_L(9) L0_CADOUT_L(9) AG6
HT_RC_CPU_CAD_H8 J6 AH5 HT_CPU_RC_CAD_H8
HT_RC_CPU_CAD_L8
K6 L0_CADIN_L(8) L0_CADOUT_L(8) AH4
HT_RC_CPU_CAD_H7 U3 Y1 HT_CPU_RC_CAD_H7
HT_RC_CPU_CAD_L7
U2 L0_CADIN_L(7) L0_CADOUT_L(7) W1
HT_RC_CPU_CAD_H6 R1 AA2 HT_CPU_RC_CAD_H6
HT_RC_CPU_CAD_L6
T1 L0_CADIN_L(6) L0_CADOUT_L(6) AA3
HT_RC_CPU_CAD_H5 R3 AB1 HT_CPU_RC_CAD_H5
HT_RC_CPU_CAD_L5
R2 L0_CADIN_L(5) L0_CADOUT_L(5) AA1
HT_RC_CPU_CAD_H4 N1 AC2 HT_CPU_RC_CAD_H4
HT_RC_CPU_CAD_L4
P1 L0_CADIN_L(4) L0_CADOUT_L(4) AC3
HT_RC_CPU_CAD_H3 L1 AE2 HT_CPU_RC_CAD_H3
HT_RC_CPU_CAD_L3
M1 L0_CADIN_L(3) L0_CADOUT_L(3) AE3
HT_RC_CPU_CAD_H2 L3 AF1 HT_CPU_RC_CAD_H2
HT_RC_CPU_CAD_L2
L2 L0_CADIN_L(2) L0_CADOUT_L(2) AE1
HT_RC_CPU_CAD_H1 J1 AG2 HT_CPU_RC_CAD_H1
HT_RC_CPU_CAD_L1
K1 L0_CADIN_L(1) L0_CADOUT_L(1) AG3
HT_RC_CPU_CAD_H0 J3 AH1 HT_CPU_RC_CAD_H0
HT_RC_CPU_CAD_L0
J2 L0_CADIN_L(0) L0_CADOUT_L(0) AG1
B B
Layout: Add stitching caps if crossing plane split
A A
FOXCONN PCEG
Title
M2 HyperTransport
C MCP61M05 A
5 4 3 2 1
5 4 3 2 1
U9B
MEMORY INTERFACE A
11,12 MEM_MA0_CLK_H2 AG21 MA0_CLK_H(2) MA_DATA(63) AE14 MEM_MA_DATA63 MEM_MA_DATA[63..0] 11
11,12 MEM_MA0_CLK_L2 AG20 MA0_CLK_L(2) MA_DATA(62) AG14 MEM_MA_DATA62
11,12 MEM_MA0_CLK_H1 G19 MA0_CLK_H(1) MA_DATA(61) AG16 MEM_MA_DATA61
11,12 MEM_MA0_CLK_L1 H19 MA0_CLK_L(1) MA_DATA(60) AD17 MEM_MA_DATA60
11,12 MEM_MA0_CLK_H0 U27 MA0_CLK_H(0) MA_DATA(59) AD13 MEM_MA_DATA59
11,12 MEM_MA0_CLK_L0 U26 MA0_CLK_L(0) MA_DATA(58) AE13 MEM_MA_DATA58
MA_DATA(57) AG15 MEM_MA_DATA57
11,12 MEM_MA0_CS_L1 AC25 MA0_CS_L(1) MA_DATA(56) AE16 MEM_MA_DATA56
11,12 MEM_MA0_CS_L0 AA24 MA0_CS_L(0) MA_DATA(55) AG17 MEM_MA_DATA55
MA_DATA(54) AE18 MEM_MA_DATA54
11,12 MEM_MA0_ODT0 AC28 MA0_ODT(0) MA_DATA(53) AD21 MEM_MA_DATA53
D MA_DATA(52) AG22 MEM_MA_DATA52 D
AE20 MA1_CLK_H(2) MA_DATA(51) AE17 MEM_MA_DATA51
AE19 MA1_CLK_L(2) MA_DATA(50) AF17 MEM_MA_DATA50
G20 MA1_CLK_H(1) MA_DATA(49) AF21 MEM_MA_DATA49
G21 MA1_CLK_L(1) MA_DATA(48) AE21 MEM_MA_DATA48
V27 MA1_CLK_H(0) MA_DATA(47) AF23 MEM_MA_DATA47
W27 MA1_CLK_L(0) MA_DATA(46) AE23 MEM_MA_DATA46
MA_DATA(45) AJ26 MEM_MA_DATA45
AD27 MA1_CS_L(1) MA_DATA(44) AG26 MEM_MA_DATA44
AA25 MA1_CS_L(0) MA_DATA(43) AE22 MEM_MA_DATA43
MA_DATA(42) AG23 MEM_MA_DATA42
AC27 MA1_ODT(0) MA_DATA(41) AH25 MEM_MA_DATA41
MA_DATA(40) AF25 MEM_MA_DATA40
11,12 MEM_MA_CAS_L AB25 MA_CAS_L MA_DATA(38) AJ29 MEM_MA_DATA38
11,12 MEM_MA_WE_L AB27 MA_WE_L MA_DATA(37) AF29 MEM_MA_DATA37
11,12 MEM_MA_RAS_L AA26 MA_RAS_L MA_DATA(36) AE26 MEM_MA_DATA36
11,12 MEM_MA_BANK2 N25 MA_BANK(2) MA_DATA(34) AH27 MEM_MA_DATA34
11,12 MEM_MA_BANK1 Y27 MA_BANK(1) MA_DATA(33) AG29 MEM_MA_DATA33
11,12 MEM_MA_BANK0 AA27 MA_BANK(0) MA_DATA(32) AF27 MEM_MA_DATA32
MA_DATA(31) E29 MEM_MA_DATA31
L27 MA_CKE(1) MA_DATA(30) E28 MEM_MA_DATA30
11,12 MEM_MA_CKE0 M25 MA_CKE(0) MA_DATA(29) D27 MEM_MA_DATA29
MA_DATA(28) C27 MEM_MA_DATA28
MEM_MA_ADD15 M27 G26 MEM_MA_DATA27
11,12 MEM_MA_ADD[15..0] MA_ADD(15) MA_DATA(27)
MEM_MA_ADD14 N24 F27 MEM_MA_DATA26
MEM_MA_ADD13 AC26
MA_ADD(14) MA_DATA(26)
MA_ADD(13) MA_DATA(25) C28 MEM_MA_DATA25
MEM_MA_ADD12 N26 E27 MEM_MA_DATA24
MEM_MA_ADD11 P25
MA_ADD(11) MA_DATA(23) F25 MEM_MA_DATA23
MEM_MA_ADD10 Y25 E25 MEM_MA_DATA22
MEM_MA_ADD9
N27 MA_ADD(9) MA_DATA(21) E23 MEM_MA_DATA21
MEM_MA_ADD8 R24 D23 MEM_MA_DATA20
MEM_MA_ADD7
P27 MA_ADD(7) MA_DATA(19) E26 MEM_MA_DATA19
MEM_MA_ADD6 R25 C26 MEM_MA_DATA18
MEM_MA_ADD5
R26 MA_ADD(5) MA_DATA(17) G23 MEM_MA_DATA17
MEM_MA_ADD4 R27 F23 MEM_MA_DATA16
MEM_MA_ADD3
T25 MA_ADD(3) MA_DATA(15) E22 MEM_MA_DATA15
C MEM_MA_ADD2 U25 E21 MEM_MA_DATA14 C
MEM_MA_ADD1
T27 MA_ADD(1) MA_DATA(13) F17 MEM_MA_DATA13
MEM_MA_ADD0 W24 G17 MEM_MA_DATA12
MA_DATA(11) G22 MEM_MA_DATA11
MEM_MA_DQS_H7AD15 F21 MEM_MA_DATA10
11 MEM_MA_DQS_H[7..0] MA_DQS_H(7) MA_DATA(10)
MEM_MA_DQS_L7AE15 G18 MEM_MA_DATA9
11 MEM_MA_DQS_L[7..0] MA_DQS_L(7) MA_DATA(9)
MEM_MA_DQS_H6AG18 E17 MEM_MA_DATA8
MEM_MA_DQS_L6AG19
MA_DQS_H(6) MA_DATA(8)
MA_DQS_L(6) MA_DATA(7) G16 MEM_MA_DATA7
MEM_MA_DQS_H5AG24 E15 MEM_MA_DATA6
MEM_MA_DQS_L5AG25
MA_DQS_L(5) MA_DATA(5) G13 MEM_MA_DATA5
MEM_MA_DQS_H4AG27 H13 MEM_MA_DATA4
MEM_MA_DQS_L4AG28
MA_DQS_L(4) MA_DATA(3) H17 MEM_MA_DATA3
MEM_MA_DQS_H3 D29 E16 MEM_MA_DATA2
MEM_MA_DQS_L3 C29
MA_DQS_L(3) MA_DATA(1) E14 MEM_MA_DATA1
MEM_MA_DQS_H2 C25 G14 MEM_MA_DATA0
MEM_MA_DQS_L2 D25
MEM_MA_DQS_H1 E19
MA_DQS_L(2)
MA_DQS_H(1) MA_DQS_H(8) J28 MEM_MA_DQS_H8 11
MEM_MA_DQS_L1 F19 J27
MA_DQS_L(1) MA_DQS_L(8) MEM_MA_DQS_L8 11
MEM_MA_DQS_H0 F15
MEM_MA_DQS_L0 G15
MA_DQS_H(0)
MA_DQS_L(0) MA_DM(8) J25 MEM_MA_DM8 11
MEM_MA_DM7 AF15 K25 MEM_MA_CHECK7
11 MEM_MA_DM[7..0] MA_DM(7) MA_CHECK(7) MEM_MA_CHECK[7..0] 11
MEM_MA_DM6 AF19 J26 MEM_MA_CHECK6
MEM_MA_DM5 AJ25
MA_DM(6) MA_CHECK(6) MEM_MA_CHECK5
MA_DM(5) MA_CHECK(5) G28
MEM_MA_DM4AH29 G27 MEM_MA_CHECK4
MEM_MA_DM3 B29
MA_DM(3) MA_CHECK(3) L24
MEM_MA_DM2 E24 K27 MEM_MA_CHECK2
MEM_MA_DM1 E18
MA_DM(1) MA_CHECK(1) H29
MEM_MA_DM0 H15 H27 MEM_MA_CHECK0
MA_DM(0) MA_CHECK(0)
B B
A A
FOXCONN PCEG
Title
M2- 2 DDR -1
C MCP61M05 A
5 4 3 2 1
5 4 3 2 1
D D
U9C
MEMORY INTERFACE B
11,12 MEM_MB0_CLK_H2 AJ19 MB0_CLK_H(2) MB_DATA(63) AH13 MEM_MB_DATA63 MEM_MB_DATA[63..0] 11
11,12 MEM_MB0_CLK_L2 AK19 MB0_CLK_L(2) MB_DATA(62) AL13 MEM_MB_DATA62
11,12 MEM_MB0_CLK_H1 A18 MB0_CLK_H(1) MB_DATA(61) AL15 MEM_MB_DATA61
11,12 MEM_MB0_CLK_L1 A19 MB0_CLK_L(1) MB_DATA(60) AJ15 MEM_MB_DATA60
11,12 MEM_MB0_CLK_H0 U31 MB0_CLK_H(0) MB_DATA(59) AF13 MEM_MB_DATA59
11,12 MEM_MB0_CLK_L0 U30 MB0_CLK_L(0) MB_DATA(58) AG13 MEM_MB_DATA58
MB_DATA(57) AL14 MEM_MB_DATA57
11,12 MEM_MB0_CS_L1 AE30 MB0_CS_L(1) MB_DATA(56) AK15 MEM_MB_DATA56
11,12 MEM_MB0_CS_L0 AC31 MB0_CS_L(0) MB_DATA(55) AL16 MEM_MB_DATA55
11,12 MEM_MB0_ODT0 AD29 MB0_ODT(0) MB_DATA(53) AK21 MEM_MB_DATA53
AL19 MB1_CLK_H(2) MB_DATA(51) AH15 MEM_MB_DATA51
AL18 MB1_CLK_L(2) MB_DATA(50) AJ16 MEM_MB_DATA50
C19 MB1_CLK_H(1) MB_DATA(49) AH19 MEM_MB_DATA49
D19 MB1_CLK_L(1) MB_DATA(48) AL20 MEM_MB_DATA48
W29 MB1_CLK_H(0) MB_DATA(47) AJ22 MEM_MB_DATA47
W28 MB1_CLK_L(0) MB_DATA(46) AL22 MEM_MB_DATA46
AE29 MB1_CS_L(1) MB_DATA(44) AK25 MEM_MB_DATA44
AB31 MB1_CS_L(0) MB_DATA(43) AJ21 MEM_MB_DATA43
MB_DATA(42) AH21 MEM_MB_DATA42
AD31 MB1_ODT(0) MB_DATA(41) AH23 MEM_MB_DATA41
MB_DATA(40) AJ24 MEM_MB_DATA40
11,12 MEM_MB_CAS_L AC29 MB_CAS_L MB_DATA(38) AK27 MEM_MB_DATA38
11,12 MEM_MB_WE_L AC30 MB_WE_L MB_DATA(37) AH31 MEM_MB_DATA37
11,12 MEM_MB_RAS_L AB29 MB_RAS_L MB_DATA(36) AG30 MEM_MB_DATA36
11,12 MEM_MB_BANK2 N31 MB_BANK(2) MB_DATA(34) AL26 MEM_MB_DATA34
11,12 MEM_MB_BANK1 AA31 MB_BANK(1) MB_DATA(33) AJ30 MEM_MB_DATA33
C 11,12 MEM_MB_BANK0 AA28 MB_BANK(0) MB_DATA(32) AJ31 MEM_MB_DATA32 C
MB_DATA(31) E31 MEM_MB_DATA31

M31 MB_CKE(1) MB_DATA(30) E30 MEM_MB_DATA30
11,12 MEM_MB_CKE0 M29 MB_CKE(0) MB_DATA(29) B27 MEM_MB_DATA29
MB_DATA(28) A27 MEM_MB_DATA28
MEM_MB_ADD15 N28 F29 MEM_MB_DATA27
11,12 MEM_MB_ADD[15..0] MB_ADD(15) MB_DATA(27)
MEM_MB_ADD14 N29 F31 MEM_MB_DATA26
MEM_MB_ADD13
MB_ADD(14) MB_DATA(26)
AE31 MB_ADD(13) MB_DATA(25) A29 MEM_MB_DATA25
MEM_MB_ADD12 N30 A28 MEM_MB_DATA24
MEM_MB_ADD11
P29 MB_ADD(11) MB_DATA(23) A25 MEM_MB_DATA23
MEM_MB_ADD10 AA29 A24 MEM_MB_DATA22
MEM_MB_ADD9
P31 MB_ADD(9) MB_DATA(21) C22 MEM_MB_DATA21
MEM_MB_ADD8 R29 D21 MEM_MB_DATA20
MEM_MB_ADD7
R28 MB_ADD(7) MB_DATA(19) A26 MEM_MB_DATA19
MEM_MB_ADD6 R31 B25 MEM_MB_DATA18
MEM_MB_ADD5
R30 MB_ADD(5) MB_DATA(17) B23 MEM_MB_DATA17
MEM_MB_ADD4 T31 A22 MEM_MB_DATA16
MEM_MB_ADD3
T29 MB_ADD(3) MB_DATA(15) B21 MEM_MB_DATA15
MEM_MB_ADD2 U29 A20 MEM_MB_DATA14
MEM_MB_ADD1
U28 MB_ADD(1) MB_DATA(13) C16 MEM_MB_DATA13
MEM_MB_ADD0 AA30 D15 MEM_MB_DATA12
MB_DATA(11) C21 MEM_MB_DATA11
MEM_MB_DQS_H7AK13 A21 MEM_MB_DATA10
11 MEM_MB_DQS_H[7..0] MB_DQS_H(7) MB_DATA(10)
MEM_MB_DQS_L7AJ13 A17 MEM_MB_DATA9
11 MEM_MB_DQS_L[7..0] MB_DQS_L(7) MB_DATA(9)
MEM_MB_DQS_L6AJ17
MB_DQS_H(6) MB_DATA(8)
MB_DQS_L(6) MB_DATA(7) B15 MEM_MB_DATA7
MEM_MB_DQS_L5AL23
MB_DQS_L(5) MB_DATA(5) E13 MEM_MB_DATA5
MEM_MB_DQS_H4AL28 F13 MEM_MB_DATA4
MEM_MB_DQS_L4AL29
MB_DQS_L(4) MB_DATA(3) C15 MEM_MB_DATA3
MEM_MB_DQS_H3 D31 A15 MEM_MB_DATA2
MEM_MB_DQS_L3 C31
MB_DQS_L(3) MB_DATA(1) A13 MEM_MB_DATA1
MEM_MB_DQS_H2 C24 D13 MEM_MB_DATA0
MEM_MB_DQS_L2 C23
MEM_MB_DQS_H1 D17
MB_DQS_L(2)
MB_DQS_H(1) MB_DQS_H(8) J31 MEM_MB_DQS_H8 11
MEM_MB_DQS_L1 C17 J30
MB_DQS_L(1) MB_DQS_L(8) MEM_MB_DQS_L8 11
MEM_MB_DQS_H0 C14
MEM_MB_DQS_L0 C13
MB_DQS_H(0)
B MB_DQS_L(0) MB_DM(8) J29 MEM_MB_DM8 11 B
MEM_MB_DM7 AJ14 K29 MEM_MB_CHECK7
11 MEM_MB_DM[7..0] MB_DM(7) MB_CHECK(7) MEM_MB_CHECK[7..0] 11
MEM_MB_DM6 AH17 K31 MEM_MB_CHECK6
MEM_MB_DM5
MB_DM(6) MB_CHECK(6) MEM_MB_CHECK5
AJ23 MB_DM(5) MB_CHECK(5) G30
MEM_MB_DM4 AK29 G29 MEM_MB_CHECK4
MEM_MB_DM3
C30 MB_DM(3) MB_CHECK(3) L29
MEM_MB_DM2 A23 L28 MEM_MB_CHECK2
MEM_MB_DM1
B17 MB_DM(1) MB_CHECK(1) H31
MEM_MB_DM0 B13 G31 MEM_MB_CHECK0
MB_DM(0) MB_CHECK(0)
A A
FOXCONN PCEG
Title
M2- 2 DDR -2
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
Level translation buffers

Assuming system devices +2.5V modify 8/20
Do not provide VDDIO
compatible voltage levels CPU_VDDA_RUN
C199 C211 C200 C201

* 22uF
* 4.7uF
* 3.3nF
* 0.22uF
+80/-20%
+/-10%
6.3V, Y5V, +80%/-20%
10V, X7R, +/-10%

Required for compatibility
with future processors
+1.8V_SUS
Keep trace to resistor
+1.8V_SUS
less than 600mils from CPU pin and
D D
trace to AC caps less than 1250mils
C191
RN24 3.9nF U9D
*
+/-10% R170
MISC
* *R174 *R175
1
3
5
7
*
13 CPU_CLKIN_H 300 300 300
C10 VDDA1
R154 D10 +/-5% +/-5% +/-5%
* VDDA2
2
4
6
8
C188 169 Ohm
3.9nF+/-1% CPU_CLKIN_SC_H A8
300 +/-10% CPU_CLKIN_SC_L
CLKIN_H
B8
*
+/-5% 13 CPU_CLKIN_L CLKIN_L
13 CPU_ALL_PWROK CPU_ALL_PWROK C9 D2 CPU_VID5 1 TP7

CPU_LDTSTOP_L
PWROK VID(5) CPU_VID4
13 CPU_LDTSTOP_L D8 LDTSTOP_L VID(4) D1 VREG_VID4 30
CPU_HT_RESET_L C7 C1 CPU_VID3
13 CPU_HT_RESET_L RESET_L VID(3) VREG_VID3 30
C190 E3 CPU_VID2
VID(2) VREG_VID2 30
* 0.22uF
+1.8V_SUS
CPU_PRESENT_L AL3 CPU_PRESENT_L VID(1)
VID(0)
E2
E1
CPU_VID1
CPU_VID0
VREG_VID1
VREG_VID0
30
30
near CPU Dummy
R164 R162 CPU_SIC AL6 AK7CPU_THERMTRIP_L CPU_THERMTRIP* 13,21
300 300 CPU_SID SIC THERMTRIP_L
* * AK6 SID PROCHOT_L AL7CPU_PROCHOT_L_1.8 CPU_PROCHOT_L_1.8 13
+/-5% +/-5%
CPU_TDI AL10 CPU_TDO
AK10
CPU_TRST_L
TDI TDO
18 CPU_SIC AJ10 TRST_L
CPU_TCK AH10
18 CPU_SID CPU_TMS
TCK
AL9 TMS
*R161
300
Dummy CPU_DBREQ_L A5 DBREQ_L DBRDY B6 CPU_DBRDY
U9E +/-5%
INTERNAL MISC 30 CPU_VDD_RUN_FB_H G2 VDD_FB_H VDDIO_FB_H AK11 CPU_VDDIO_SUS_FB_H
L25 E20 G1 CPU_VDDIO_SUS_FB_L
AL11
RSVD1 RSVD17 30 CPU_VDD_RUN_FB_L VDD_FB_L VDDIO_FB_L
L26 RSVD2 RSVD18 B19
L31 TP26 1 CPU_VTT_SUS_SENSE E12 F1 CPU_PSI_L 1 TP8 +1.2V_HT
RSVD3 VTT_SENSE PSI_L
L30 RSVD4 RSVD19 AL4
AK4 +1.8V_SUS CPU_M_VREF_SUS
Keep trace to resistors
**
RSVD20 CPU_HTREF1 R160 44.2Ohm +/-1%
AK3 F12 V8
**
RSVD21 R179 39.2 +/-1% M_VREF HTREF1 R157 44.2Ohm +/-1%
F2 R180 39.2 +/-1%
M_ZN
M_ZP
AH11
AJ11
M_ZN HTREF0 V7 CPU_HTREF0
less than 1.5" from CPU pin
RSVD22 M_ZP
RSVD23 F3
C W26 CPU_TEST25_H A10 C11 CPU_TEST29_H C
RSVD5 CPU_TEST25_L
TEST25_H TEST29_H CPU_TEST29_L
W25 G4 B10 D11
**
RSVD6 RSVD24 R168 300 +/-5% TEST25_L TEST29_L
AE27
U24
RSVD7
RSVD8
RSVD25
RSVD26
G3
G5 R167 300 +/-5%
F10
E9
TEST19
TEST18
*R173
80.6
Route as 80-Ohm differential impedance
V24 AJ7 +/-1%
RSVD9 TEST13
AE28 RSVD10 RSVD27 AD25
AE24
F6 TEST9 Keep trace to resistor less than 1" from CPU pin
RSVD28 TP16 CPU_TEST17
RSVD29 AE25 1 D6 TEST17 TEST24 AK8
AJ18 TP15 1 CPU_TEST16 E7 AH8 CPU_TEST23 1 TP17
TEST16 TEST23 CPU_TEST22 TP19
RSVD31 AJ20 1 F8 TEST15 TEST22 AJ9 1
C18 TP13 1 CPU_TEST14 C5 AL8 CPU_TEST21
TEST14 TEST21
Y31 RSVD11 RSVD33 C20 1 AH9 TEST12 TEST20 AJ8
Y30 RSVD12 RSVD34 G24
AG31 RSVD13 RSVD35 G25 E5 TEST7 TEST28_H J10
V31 RSVD14 RSVD36 H25 AJ5 TEST6 TEST28_L H9
W31 V29 CPU_THERMDC AG9 AK9
RSVD15 RSVD37 24 CPU_THERMDC CPU_THERMDA
THERMDC TEST27 CPU_TEST26 +1.8V_SUS
AF31 RSVD16 RSVD38 W30 24 CPU_THERMDA AG8 THERMDA TEST26 AK5
AH7 TEST3 TEST10 G7
AJ6 TEST2 TEST8 D4
HDT
HHS2X13JZO25H70 CPU_VDDA_RUN
1 1 2 2
3 4 1 TP21
5 6
CPU_DBREQ_L 7 8 CPU_CLKIN_H 1 TP4
CPU_DBRDY 9 10 CPU_CLKIN_L 1 TP3
CPU_TCK 11 11 12 12
CPU_TMS 13 14 CPU_VDD_RUN_FB_H 1 TP6
CPU_TDI 15 16 CPU_VDD_RUN_FB_L 1 TP5
CPU_TRST_L 17 18
CPU_TDO 19 20 CPU_TEST29_H 1 TP22
21 21 22 22 CPU_TEST29_L 1 TP25
23 24 CPU_HT_RESET_L
26 26 CPU_VDDIO_SUS_FB_H 1 TP24
CPU_VDDIO_SUS_FB_L 1 TP23
0.050IN
DUMMY CPU_ALL_PWROK 1 TP11

B B
CPU_LDTSTOP_L 1 TP10
CPU_HT_RESET_L 1 TP9
TP27
Erratum 133, Revision Guide for CPU_THERMTRIP_L 1
CPU_M_VREF_SUS AMD NPT 0Fh Processors

R177 +1.8V_SUS
* * * ** * *
CPU_DBREQ_L 300
+1.8V_SUS Dummy +/-5%
CPU_TEST26 R158 300 +/-5%
*R172
16.9 Ohm CPU_PRESENT_L R159 1K +/-5%
+/-1% CPU_M_VREF_SUS CPU_TEST25_H R166 510 Ohm
+/-5%
CPU_TEST25_L R165 510 Ohm
U9J +/-5%
R171 C196
* 16.9 Ohm
* C197
* 1nF CPU_TEST21 R178 300 +/-5%
+/-1% 100nF R176
5 21
Layout: Place near CPU socket CPU_TEST22 300
MTG1 MTG3
6 MTG1 22
MTG3 Dummy +/-5%
7 MTG1 23
MTG3
8
9
MTG1 24
MTG3
25
Erratum 133, Revision Guide for
MTG1 MTG3
10 MTG1 26
MTG3 AMD NPT 0Fh Processors
11 MTG1 27
MTG3
12 MTG1 28
MTG3
1 EMI EMI3
2 EMI EMI4
13 MTG2 29
MTG4
14 MTG2 30
MTG4
15 MTG2 31
MTG4
16 MTG2 32
MTG4
A 17 MTG2 33
MTG4
A
18 MTG2 34
MTG4
19 MTG2 35
MTG4
20 MTG2 36
MTG4
FOXCONN PCEG
GND Title
M2- 3 MISC
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
Processor Power & Ground

D D
VLDT_RUN_B is connected to the VLDT_RUN power

supply through the package or on the die. It is only connected
+V_CPU on the board to decoupling near the CPU package.
U9F
VDD1 +V_CPU U9I VLDT_RUN_B
A4 A3 U9G +V_CPU U9H +1.2V_HT VDDIO
VDD1 VSS1
A6 VDD2 VSS2 A7 VDD2 VDD3 AJ4 VLDT_A1 VLDT_B1 H6
AA8 VDD3 VSS3 A9 L14 VDD1 VSS1 AK20 AA20 VDD1 VSS1 N17 AJ3 VLDT_A2 VLDT_B2 H5
AA10 A11 L16 AK22 AA22 N19 AJ2 H2 * C173
VDD4 VSS4 VDD2 VSS2 VDD2 VSS2 VLDT_A3 VLDT_B3
Bottomside Decoupling
AA12 AA4 L18 AK24 AB13 N21 AJ1 H1 +80/-20%
VDD5 VSS5 VDD3 VSS3 VDD3 VSS3 VTT_DDR_SUS VLDT_A4 VLDT_B4 VTT_DDR_SUS 4.7uF
AA14 VDD6 VSS6 AA5 M2 VDD4 VSS4 AK26 AB15 VDD4 VSS4 N23
AA16 VDD7 VSS7 AA7 M3 VDD5 VSS5 AK28 AB17 VDD5 VSS5 P2 D12 VTT1 VTT5 AK12
GND
AA18 VDD8 VSS8 AA9 M7 VDD6 VSS6 AK30 AB19 VDD6 VSS6 P3 C12 VTT2 VTT6 AJ12
AB7 VDD9 VSS9 AA11 M9 VDD7 VSS7 AL5 AB21 VDD7 VSS7 P8 B12 VTT3 VTT7 AH12
AB9 AA13 M11 B4 AB23 P10 +1.8V_SUS A12 AG12
VDD10 VSS10 VDD8 VSS8 VDD8 VSS8 VTT4 VTT8 +V_CPU
AB11 VDD11 VSS11 AA15 M13 VDD9 VSS9 B9 AC12 VDD9 VSS9 P12 VTT9 AL12
AC4 VDD12 VSS12 AA17 M15 VDD10 VSS10 B11 AC14 VDD10 VSS10 P14 AB24 VDDIO1 modify 8/16
AC5 VDD13 VSS13 AA19 M17 VDD11 VSS11 B14 AC16 VDD11 VSS11 P16 AB26 VDDIO2 VSS1 K24
AC8 AA21 M19 B16 AC18 P18 AB28 K26 C490 C502 C492 C491 C499 C498 C497 C496 C487 C489 C500 C488 C501 C495 C503
VDD14 VSS14 VDD12 VSS12 VDD12 VSS12 VDDIO3 VSS2
AC10
AD2
VDD15 VSS15 AA23
AB2
N8
N10
VDD13 VSS13 B18
B20
AC20
AC22
VDD13 VSS13 P20
P22
AB30
AC24
VDDIO4 VSS3 K28
K30
* 22uF
* 10uF
+/-10% * 22uF
* 10uF 22uF
+/-10% * * 10uF
+/-10% * 10uF
+/-10% * 10uF
+/-10% * 10uF
+/-10%* 10uF
*
+/-10%
10uF
*
+/-10%
22uF
* 22uF
* 10uF
*
+/-10%
10uF
+/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%

AD3 AB3 N12 B22 AD11 R7 AD26 L7
6.3V, X5R, +/-10%

AD7 VDD18 VSS18 AB8 N14 VDD16 VSS16 B24 AD23 VDD16 VSS16 R9 AD28 VDDIO7 VSS6 L9
AD9 VDD19 VSS19 AB10 N16 VDD17 VSS17 B26 AE12 VDD17 VSS17 R11 AD30 VDDIO8 VSS7 L11
AE10 VDD20 VSS20 AB12 N18 VDD18 VSS18 B28 AF11 VDD18 VSS18 R13 AF30 VDDIO29 VSS8 L13
GND
AF7 VDD21 VSS21 AB14 P7 VDD19 VSS19 B30 L20 VDD19 VSS19 R15 M24 VDDIO9 VSS9 L15
AF9 VDD22 VSS22 AB16 P9 VDD20 VSS20 C3 L22 VDD20 VSS20 R17 M26 VDDIO10 VSS10 L17
AG4 VDD23 VSS23 AB18 P11 VDD21 VSS21 D14 M21 VDD21 VSS21 R19 M28 VDDIO11 VSS11 L19
C AG5 VDD24 VSS24 AB20 P13 VDD22 VSS22 D16 M23 VDD22 VSS22 R21 M30 VDDIO12 VSS12 L21 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy C
AG7 VDD25 VSS25 AB22 P15 VDD23 VSS23 D18 N20 VDD23 VSS23 R23 P24 VDDIO13 VSS13 L23
AH2 AC7 P17 D20 N22 T8 P26 M8 +V_CPU
AH3 VDD27 VSS27 AC9 P19 VDD25 VSS25 D22 P21 VDD25 VSS25 T10 P28 VDDIO15 VSS15 M10
B3 VDD28 VSS28 AC11 R4 VDD26 VSS26 D24 P23 VDD26 VSS26 T12 P30 VDDIO16 VSS16 M12
B5 AC13 R5 D26 R22 T14 T24 M14 C486 C504 C493 C133 C494
B7 VDD30 VSS30 AC15 R8 VDD28 VSS28 D28 T23 VDD28 VSS28 T16 T26 VDDIO18 VSS18 M16
* 0.22uF
* 0.22uF
* 0.22uF
* 10nF
* 180pF
50V, NPO, +/-5%
25V, X7R, +/-10%

C2 VDD31 VSS31 AC17 R10 VDD29 VSS29 D30 U22 VDD29 VSS29 T18 T28 VDDIO19 VSS19 M18
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%

C4 VDD32 VSS32 AC19 R12 VDD30 VSS30 E11 V23 VDD30 VSS30 T20 T30 VDDIO20 VSS20 M20
C6 VDD33 VSS33 AC21 R14 VDD31 VSS31 F4 W22 VDD31 VSS31 T22 V25 VDDIO21 VSS21 M22
C8 VDD34 VSS34 AC23 R16 VDD32 VSS32 F14 Y23 VDD32 VSS32 U4 V26 VDDIO22 VSS22 N4
D3 VDD35 VSS35 AD8 R18 VDD33 VSS33 F16 VSS33 U5 V28 VDDIO23 VSS23 N5
Dummy Dummy GND
D5 VDD36 VSS36 AD10 R20 VDD34 VSS34 F18 VSS34 U7 V30 VDDIO24 VSS24 N7
D7 VDD37 VSS37 AD12 T2 VDD35 VSS35 F20 VSS35 U9 Y24 VDDIO25 VSS25 N9
D9 VDD38 VSS38 AD14 T3 VDD36 VSS36 F22 VSS36 U11 Y26 VDDIO26 VSS26 N11
E4 VDD39 VSS39 AD16 T7 VDD37 VSS37 F24 VSS37 U13 Y28 VDDIO27 VSS27 N13
E6 AD20 T9 F26 U15 Y29 N15 +1.8V_SUS modify 8/16
VDD40 VSS40 VDD38 VSS38 VSS38 VDDIO28 VSS28
E8 VDD41 VSS41 AD22 T11 VDD39 VSS39 F28 VSS39 U17
E10 VDD42 VSS42 AD24 T13 VDD40 VSS40 F30 VSS40 U19
F5 AE4 T15 G9 U21 C505 C506 C509 C508 C507 C511 C510 C513 C512
VDD43 VSS43 VDD41 VSS41 VSS41 GND
F7 VDD44 VSS44 AE5 T17 VDD42 VSS42 G11 VSS42 U23
* 10uF
* 10uF
* 4.7uF
* 4.7uF
* 0.22uF
* 0.22uF
* 0.22uF
* 10nF
* 180pF
+80/-20%
+80/-20%
F9 AE9 T19 H8 V2 +/-10% +/-10% 50V, NPO, +/-5%
25V, Y5V, +80%/-20%

VDD45 VSS45 VDD43 VSS43 VSS43
10V, X7R, +/-10%
10V, X7R, +/-10%
10V, X7R, +/-10%

F11 VDD46 VSS46 AE11 T21 VDD44 VSS44 H10 VSS44 V3
G6 VDD47 VSS47 AF2 U8 VDD45 VSS45 H12 VSS45 V10
GND
H7 VDD51 VSS51 AF12 U16 VDD49 VSS49 H22 VSS49 V18
J8 VDD54 VSS54 AF18 V9 VDD52 VSS52 H28 VSS52 W9
J12 VDD55 VSS55 AF20 V11 VDD53 VSS53 H30 VSS53 W11
J14 VDD56 VSS56 AF22 V13 VDD54 VSS54 J4 VSS54 W13
J22 VDD60 VSS61 AG10 V21 VDD58 VSS58 J11 VSS58 W21
B
J24
K7
VDD61
VDD62
VSS62
VSS63
AG11
AH14
W4
W5
VDD59
VDD60
VSS59
VSS60
J13
J15
VSS59
VSS60
W23
Y8
Decoupling Between Processor and DIMMs B
K9 AH16 W8 J17 Y10

K11
K13
VDD63
VDD64
VSS64
VSS65 AH18
AH20
W10
W12
VDD61
VDD62
VSS61
VSS62 J19
J21
VSS61
VSS62 Y12
W7
Place as close to processor as possible. Decoupling Between Processor and DIMMs
K15 VDD66 VSS67 AH22 W14 VDD64 VSS64 J23 VSS64 Y20
K17 AH24 W16 K2 Y22 +1.8V_SUS
K19 VDD68 VSS69 AH26 W18 VDD66 VSS66 K3
K21 VDD69 VSS70 AH28 W20 VDD67 VSS67 K8
GND C357 C342 C346 C334
K23 VDD70 VSS71 AH30 Y2 VDD68 VSS68 K10
L4 VDD71 VSS72 AK2 Y3 VDD69 VSS69 K12
* 4.7uF
+80/-20%
* 4.7uF
* 0.22uF
* 0.22uF
+80/-20%
10V, X7R, +/-10%
10V, X7R, +/-10%

L12 Y14 Y13 K20 +1.8V_SUS
VDD75 VSS240 VDD73 VSS73
Y17 VDD150 VSS241 Y16 Y15 VDD74 VSS74 K22
GND
Y19 VDD151 Y21 VDD75 VSS75 Y18
C347 C317
GND
GND * 180pF
+/-5% * 180pF
+/-5%
VTT_DDR_SUS
GND
C205 C202 C218 C222 C208 C416 C404 C401
* 4.7uF
* 4.7uF
* 0.22uF
* 0.22uF
* 1nF
* 1nF
* *
180pF 180pF
+80/-20%
+80/-20%
+/-5% +/-5%
50V, X7R, +/-10%
50V, X7R, +/-10%

10V, X7R, +/-10%
10V, X7R, +/-10%
GND
Place near processor on VLDT pour.

+1.2V_HT
A A
VTT_DDR_SUS
C184 C185
* 4.7uF
* 100nF
+80/-20%
+80%~-20% C203 C206 C217 C220 C207 C209 C400 C204

* 4.7uF
* 4.7uF
* 0.22uF
* 0.22uF
* 1nF
* 1nF
* *
180pF 180pF
+80/-20%
+80/-20%
+/-5% +/-5%
50V, X7R, +/-10%
50V, X7R, +/-10%

10V, X7R, +/-10%
10V, X7R, +/-10%
GND FOXCONN PCEG

GND Title
M2- 4 Power
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
SMB_MEM BUS ADDRESS
DIMM 0 1010 000

DIMM 1 1010 001
DIMM 2 1010 010
DIMM 3 1010 011
DIMMA0 +3.3V
First Logical DDR2 DIMM
D
+1.8V_SUS R253
DIMMB0 +3.3V
D
* 0 +1.8V_SUS
*R254
+/-5% 0
+/-5%
172
178
184
187
189
197
170
175
181
191
194
238
172
178
184
187
189
197
170
175
181
191
194
238
DIMM1 DIMM2
53
59
64
67
69
51
56
62
72
75
78
53
59
64
67
69
51
56
62
72
75
78
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDSPD
VDDQ10
VDDQ11
VDDSPD
164 236 MEM_MA_DATA63 164 236 MEM_MB_DATA63
7 MEM_MA_DM8 DQS17_H DQ63 MEM_MA_DATA[63..0] 7 8 MEM_MB_DM8 DQS17_H DQ63 MEM_MB_DATA[63..0] 8
MEM_MA_DM7
DQS17_L DQ62 MEM_MA_DATA61 MEM_MB_DM7
DQS17_L DQ62 MEM_MB_DATA61
7 MEM_MA_DM[7..0] 232 DQS16_H DQ61 230 8 MEM_MB_DM[7..0] 232 DQS16_H DQ61 230
MEM_MA_DM6
223 DQS15_H DQ59 117 223 DQS15_H DQ59 117
MEM_MA_DM5
211 DQS14_H DQ57 111 211 DQS14_H DQ57 111
MEM_MA_DM4
202 DQS13_H DQ55 227 202 DQS13_H DQ55 227
MEM_MA_DM3
155 DQS12_H DQ53 218 155 DQS12_H DQ53 218
MEM_MA_DM2
146 DQS11_H DQ51 108 146 DQS11_H DQ51 108
MEM_MA_DM1
134 DQS10_H DQ49 99 134 DQS10_H DQ49 99
MEM_MA_DM0
125 DQS9_H DQ47 215 125 DQS9_H DQ47 215
DQS9_L DQ46 MEM_MA_DATA45
7 MEM_MA_DQS_H8 46 DQS8_H DQ45 209 8 MEM_MB_DQS_H8 46 DQS8_H DQ45 209
7 MEM_MA_DQS_L8 MEM_MA_DQS_H7
8 MEM_MB_DQS_L8 MEM_MB_DQS_H7
7 MEM_MA_DQS_H[7..0] 114 DQS7_H DQ43 96 8 MEM_MB_DQS_H[7..0] 114 DQS7_H DQ43 96
MEM_MA_DQS_L7 113 95 MEM_MA_DATA42 MEM_MB_DQS_L7 113 95 MEM_MB_DATA42
7 MEM_MA_DQS_L[7..0] MEM_MA_DQS_H6
8 MEM_MB_DQS_L[7..0] MEM_MB_DQS_H6
105 DQS6_H DQ41 90 105 DQS6_H DQ41 90
MEM_MA_DQS_H5
DQS6_L DQ40 MEM_MA_DATA39 MEM_MB_DQS_H5
93 DQS5_H DQ39 206 93 DQS5_H DQ39 206
MEM_MA_DQS_H4
C 84 DQS4_H DQ37 200 84 DQS4_H DQ37 200 C
MEM_MA_DQS_H3
37 DQS3_H DQ35 87 37 DQS3_H DQ35 87
MEM_MA_DQS_H2
28 DQS2_H DQ33 81 28 DQS2_H DQ33 81
MEM_MA_DQS_H1
16 DQS1_H DQ31 159 16 DQS1_H DQ31 159
MEM_MA_DQS_H0
7 DQS0_H DQ29 153 7 DQS0_H DQ29 153
DQS0_L DQ28 MEM_MA_DATA27 +3.3V DQS0_L DQ28 MEM_MB_DATA27
DQ27 40 DQ27 40
SA2 DQ26 MEM_MA_DATA25
SA2 DQ26 MEM_MB_DATA25
240 SA1 DQ25 34 240 SA1 DQ25 34
GND SA0 DQ24 MEM_MA_DATA23
SA0 DQ24 MEM_MB_DATA23
18 SMB_MEM_SCL 120 SCL DQ23 150 18 SMB_MEM_SCL 120 SCL DQ23 150
18 SMB_MEM_SDA SDA DQ22 18 SMB_MEM_SDA SDA DQ22
54 144 MEM_MA_DATA21 GND 54 144 MEM_MB_DATA21
7,12 MEM_MA_BANK2 BA2 DQ21 MEM_MA_DATA20
8,12 MEM_MB_BANK2 BA2 DQ21 MEM_MB_DATA20
7,12 MEM_MA_BANK1 190 BA1 DQ20 143 8,12 MEM_MB_BANK1 190 BA1 DQ20 143
7,12 MEM_MA_BANK0 BA0 DQ19 MEM_MA_DATA18
8,12 MEM_MB_BANK0 BA0 DQ19 MEM_MB_DATA18
DQ18 30 DQ18 30
MEM_MA_ADD15 173 25 MEM_MA_DATA17 MEM_MB_ADD15 173 25 MEM_MB_DATA17
7,12 MEM_MA_ADD[15..0] MEM_MA_ADD14
A15 DQ17 MEM_MA_DATA16
8,12 MEM_MB_ADD[15..0] MEM_MB_ADD14
A15 DQ17 MEM_MB_DATA16
174 A14 DQ16 24 174 A14 DQ16 24
MEM_MA_ADD12
A13 DQ15 MEM_MA_DATA14 MEM_MB_ADD12
176 A12 DQ14 140 176 A12 DQ14 140
MEM_MA_ADD10
70 A10 DQ12 131 70 A10 DQ12 131
MEM_MA_ADD8
179 A8 DQ10 21 179 A8 DQ10 21
MEM_MA_ADD6
A7 DQ9 MEM_MB_DATA8
180 A6 DQ8 12 180 A6 DQ8 12
MEM_MA_ADD4
A5 DQ7 MEM_MB_DATA6
61 A4 DQ6 128 61 A4 DQ6 128
MEM_MA_ADD2
A3 DQ5 MEM_MB_DATA4
63 A2 DQ4 122 63 A2 DQ4 122
MEM_MA_ADD0
A1 DQ3 MEM_MB_DATA2
188 A0 DQ2 9 188 A0 DQ2 9
4 MEM_MA_DATA1 4 MEM_MB_DATA1
MEM_MA_CHECK7
DQ1 MEM_MA_DATA0 MEM_MB_CHECK7
DQ1 MEM_MB_DATA0
B 7 MEM_MA_CHECK[7..0] 168 CB7 DQ0 3 8 MEM_MB_CHECK[7..0] 168 CB7 DQ0 3 B
MEM_MA_CHECK6 167 MEM_MB_CHECK6 167
MEM_MA_CHECK5
CB6 MEM_MB_CHECK5
CB6
162 CB5 WE_L 73 MEM_MA_WE_L 7,12 162 CB5 WE_L 73 MEM_MB_WE_L 8,12
MEM_MA_CHECK4 161 MEM_M_VREF_SUS MEM_MB_CHECK4 161 MEM_M_VREF_SUS
MEM_MA_CHECK3
CB4 MEM_MB_CHECK3
CB4
49 CB3 VREF 1 49 CB3 VREF 1
MEM_MA_CHECK1
CB2 MEM_MB_CHECK1
CB2
43 CB1 TEST 102 43 CB1 TEST 102
CB0 CB0
ODT0 195 MEM_MA0_ODT0 7,12 ODT0 195 MEM_MB0_ODT0 8,12
7,12 MEM_MA0_CLK_H0 185 CK0_H ODT1 77 8,12 MEM_MB0_CLK_H0 185 CK0_H ODT1 77
7,12 MEM_MA0_CLK_L0 186 CK0_L 8,12 MEM_MB0_CLK_L0 186 CK0_L
7,12 MEM_MA0_CLK_H1 137 CK1_H ERR_OUT_L 55 8,12 MEM_MB0_CLK_H1 137 CK1_H ERR_OUT_L 55
138 68 138 68 GND
7,12 MEM_MA0_CLK_L1 CK1_L PAR_IN GND 8,12 MEM_MB0_CLK_L1 CK1_L PAR_IN
7,12 MEM_MA0_CLK_H2 220 CK2_H 8,12 MEM_MB0_CLK_H2 220 CK2_H
7,12 MEM_MA0_CLK_L2 221 CK2_L NC1 19 8,12 MEM_MB0_CLK_L2 221 CK2_L NC1 19
18 RESET_L 18 RESET_L
MEM_MA_CKE0 52 52
7,12 MEM_MA_CKE0 CKE0 8,12 MEM_MB_CKE0 CKE0
171 CKE1 171 CKE1
7,12 MEM_MA_RAS_L 192 RAS_L 8,12 MEM_MB_RAS_L 192 RAS_L
7,12 MEM_MA_CAS_L 74 CAS_L 8,12 MEM_MB_CAS_L 74 CAS_L
7,12 MEM_MA0_CS_L0
7,12 MEM_MA0_CS_L1
193
76
S0_L
S1_L MEM_M_VREF_SUS 8,12 MEM_MB0_CS_L0
8,12 MEM_MB0_CS_L1
193
76
S0_L
S1_L
+1.8V_SUS
*R222
59 Ohm
* C356
MEM_M_VREF_SUS
+/-1% 100nF
A A
*R220
59 Ohm
* C335
*
C337
1nF
+/-1% 100nF
GND FOXCONN PCEG

Layout: Place near DIMM sockets Title
DDR SDRAM DIMM 1 - 2
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
DDR2 Termination
VTT_DDR_SUS
VTT_DDR_SUS
MEM_MA_ADD[15..0] 47 Ohm
7,11 MEM_MA_ADD[15..0]
D
MEM_MB_ADD15 RN39D
RN38B
7
3
*
*
847 Ohm
447 Ohm
D
8,11 MEM_MB_BANK2
RN39B 3*
47 Ohm
447 Ohm MEM_MB_ADD[15..0]
RN42C
MEM_MB_ADD11 RN37D
5
7
*
*
647 Ohm
847 Ohm
8,11 MEM_MB_ADD[15..0]
MEM_MA_ADD15 RN40C
RN42D
5
7
*
*
647 Ohm
847 Ohm
MEM_MA_ADD6 RN36D
MEM_MB_ADD10 RN31C
7
5
*
*
847 Ohm
647 Ohm
MEM_MB_ADD9 RN37B
MEM_MB_ADD12 RN38C
3
5
*
*
447 Ohm
647 Ohm
MEM_MB_ADD7 RN36B
MEM_MB_ADD5 RN35C
3
5
*
*
447 Ohm
647 Ohm
MEM_MA_ADD0 RN32A
MEM_MB_ADD14 RN38A
1
1
*
*
247 Ohm
247 Ohm Place near CPU MEM_MA_ADD9 RN35B
MEM_MB_ADD3 RN34A
3
1
*
*
447 Ohm
247 Ohm
MEM_MA_ADD7 RN37C
MEM_MA_ADD11 RN37A
5
1
*
*
647 Ohm
247 Ohm
MEM_MB_ADD6 RN35A
MEM_MA_ADD5 RN34C
1
5
*
*
247 Ohm
647 Ohm
MEM_MA_ADD8 RN36A
MEM_MB_ADD8 RN36C
1
5
*
*
247 Ohm
647 Ohm
7,11 MEM_MA0_CLK_H2 C233
MEM_MB_ADD2 RN34D
MEM_MA_ADD1 RN33C
7
5
*
*
847 Ohm
647 Ohm
MEM_MB_ADD4 RN35D
MEM_MB_ADD1 RN34B
7
3
*
*
847 Ohm
447 Ohm
* 1.5pF
50V, NPO, +/-0.25pF
MEM_MA_ADD4 RN33A
MEM_MB_ADD0 RN32B
1
3
*
*
247 Ohm
4
MEM_MA_ADD2 RN33D
MEM_MA_ADD3 RN33B
7
3
*
*
847 Ohm
447 Ohm MEM_MB_ADD13 RN43A 1*
47 Ohm
247 Ohm
7,11 MEM_MA0_CLK_L2
MEM_MA_ADD10 RN32C 5* 6
47 Ohm 8,11 MEM_MB0_ODT0
RN44C
RN45D
5*
7*
647 Ohm
8
8,11 MEM_MB_WE_L
8,11 MEM_MB0_CS_L1
RN43B 3* 447 Ohm 7,11 MEM_MA0_CLK_H1
47 Ohm
7,11 MEM_MA0_CS_L0
RN44B 3* 447 Ohm C234 MEM_MA_ADD12 RN38D 7* 847 Ohm
7* 1*
7,11 MEM_MA_RAS_L
RN31D 8
47 Ohm * 1.5pF
50V, NPO, +/-0.25pF 8,11 MEM_MB_BANK1
8,11 MEM_MB_BANK0
RN31A
RN45A 1*
247 Ohm
2
7,11 MEM_MA_BANK2
RN39A 1* 247 Ohm 47 Ohm
7,11 MEM_MA_BANK1
RN32D 7* 847 Ohm 7,11 MEM_MA0_CLK_L1 8,11 MEM_MB_CKE0
RN39C 5* 647 Ohm
7,11 MEM_MA_BANK0
RN31B 3* 4 RN40A 1* 2
47 Ohm
7,11 MEM_MA_CKE0
RN40B 3* 447 Ohm 7,11 MEM_MA0_CLK_H0
47 Ohm
MEM_MA_ADD14 RN40D 7* 8 C266
7,11 MEM_MA_WE_L
RN44D 7* 847 Ohm
5*
47 Ohm * 1.5pF
50V, NPO, +/-0.25pF 7,11 MEM_MA0_ODT0
RN43C 6
8,11 MEM_MB0_CS_L0
RN45C 5* 647 Ohm 47 Ohm
7,11 MEM_MA_CAS_L
RN43D 7* 8 7,11 MEM_MA0_CLK_L0 8,11 MEM_MB_CAS_L
RN44A
*
1 247 Ohm
47 Ohm
MEM_MA_ADD13 RN42A
*
1 2
8,11 MEM_MB_RAS_L
RN45B
RN42B
*
3
*
3
447 Ohm
4
8,11 MEM_MB0_CLK_H2 C226
7,11 MEM_MA0_CS_L1
C
* 1.5pF
50V, NPO, +/-0.25pF +1.8V_SUS
C
**************** *** ***

MEM_MB_ADD15 C355 22pF
MEM_MB_ADD14 C332 22pF
+1.8V_SUS 8,11 MEM_MB0_CLK_L2 MEM_MB_ADD13 C318 22pF
**************** *** ***
MEM_MA_ADD15 C310 22pF MEM_MB_ADD12 C354 22pF

MEM_MA_ADD13 C311 22pF 8,11 MEM_MB0_CLK_H1 C228 MEM_MB_ADD10 C323 22pF
MEM_MA_ADD12
MEM_MA_ADD11
C309
C291
22pF
22pF * 1.5pF
50V, NPO, +/-0.25pF
MEM_MB_ADD9
MEM_MB_ADD8
C353
C352
22pF
22pF
MEM_MA_ADD8 C307 22pF 8,11 MEM_MB0_CLK_L1 MEM_MB_ADD5 C328 22pF
MEM_MA_ADD5 C289 22pF 8,11 MEM_MB0_CLK_H0 C275 MEM_MB_ADD2 C304 22pF
MEM_MA_ADD4
MEM_MA_ADD3
C348
C305
22pF
22pF * 1.5pF
50V, NPO, +/-0.25pF
MEM_MB_ADD1
MEM_MB_ADD0
C349
C324
22pF
22pF
MEM_MA_ADD2 C325 22pF
MEM_MA_ADD1 C326 22pF MEM_MB_CAS_L C320 22pF
MEM_MA_ADD0 C322 22pF 8,11 MEM_MB0_CLK_L0 MEM_MB_WE_L C344 22pF
MEM_MB_RAS_L C343 22pF
MEM_MA_CAS_L C312 22pF
MEM_MA_WE_L C313 22pF MEM_MB_BANK2 C331 22pF
MEM_MA_RAS_L C314 22pF MEM_MB_BANK1 C345 22pF
MEM_MB_BANK0 C316 22pF
MEM_MA_BANK2 C292 22pF
B B
Layout: Spread out on VTT pour

VTT_DDR_SUS
*C411 *C413 *C420 *C402 *C414 *C412 *C403 *C387 *C415 *C419
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
GND
GND
VTT_DDR_SUS +1.8V_SUS
*C388 *C389 *C390 *C406 *C391 *C392 *C393 *C394 *C395 *C396 *C397 *C398 *C399 *C443
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
A A
Dummy
FOXCONN PCEG
Title
DDR II terminator
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
D D
U15H
6 HT_CPU_RC_CAD_H[15..0] MCP61
SEC 1 OF 8 HT_RC_CPU_CAD_H[15..0] 6
HT_CPU_RC_CAD_H0 AG8 HTCPU_DWN0
HT_MCP_RXD0_P HT_MCP_TXD0_P AH23 HT_RC_CPU_CAD_H0
HT_CPU_RC_CAD_H2 AK9 HTCPU_DWN2
HT_MCP_RXD2_P HT_MCP_TXD2_P AJ21 HT_RC_CPU_CAD_H2
HT_CPU_RC_CAD_H3 AJ10 HTCPU_DWN3
HT_CPU_RC_CAD_H6 AK13 HTCPU_DWN6
HT_MCP_RXD6_P HT_MCP_TXD6_P AJ17 HT_RC_CPU_CAD_H6
HT_CPU_RC_CAD_H7 AJ14 HTCPU_DWN7
HT_CPU_RC_CAD_H8 AB10 HTCPU_DWN8
HT_MCP_RXD8_P HT_MCP_TXD8_P AF22 HT_RC_CPU_CAD_H8
HT_CPU_RC_CAD_H9 AD10 HTCPU_DWN9
HT_MCP_RXD9_P HT_MCP_TXD9_P AB20 HT_RC_CPU_CAD_H9
HT_CPU_RC_CAD_H10 AF10 HTCPU_DWN10
HT_MCP_RXD10_P HT_MCP_TXD10_P AC20 HT_RC_CPU_CAD_H10
HT_CPU_RC_CAD_H11 AC12 HTCPU_DWN11
HT_MCP_RXD11_P HT_MCP_TXD11_P AE20 HT_RC_CPU_CAD_H11
HT_MCP_RXD12_P HT_MCP_TXD12_P AD18 HT_RC_CPU_CAD_H12
HT_MCP_RXD13_P HT_MCP_TXD13_P AF18 HT_RC_CPU_CAD_H13
HT_CPU_RC_CAD_H14 AF14 HTCPU_DWN14
HT_MCP_RXD14_P HT_MCP_TXD14_P AB17 HT_RC_CPU_CAD_H14
HT_CPU_RC_CAD_H15 AE14 HTCPU_DWN15
HT_MCP_RXD15_P HT_MCP_TXD15_P AC16 HT_RC_CPU_CAD_H15
6 HT_CPU_RC_CAD_L[15..0] HT_RC_CPU_CAD_L[15..0] 6
HT_CPU_RC_CAD_L0 AH8 HT_MCP_RXD0_N HT_MCP_TXD0_N AJ23 HT_RC_CPU_CAD_L0
HT_CPU_RC_CAD_L2 AJ9 HT_MCP_RXD2_N HT_MCP_TXD2_N AK21 HT_RC_CPU_CAD_L2
HT_CPU_RC_CAD_L3 AH10 HT_MCP_RXD3_N HT_MCP_TXD3_N AG21 HT_RC_CPU_CAD_L3
HT_CPU_RC_CAD_L6 AJ13 HT_MCP_RXD6_N HT_MCP_TXD6_N AK17 HT_RC_CPU_CAD_L6
HT_CPU_RC_CAD_L7 AH14 HT_MCP_RXD7_N HT_MCP_TXD7_N AG17 HT_RC_CPU_CAD_L7
HT_CPU_RC_CAD_L8 AC10 HT_MCP_RXD8_N HT_MCP_TXD8_N AG22 HT_RC_CPU_CAD_L8
HT_CPU_RC_CAD_L9 AE10 HT_MCP_RXD9_N HT_MCP_TXD9_N AB19 HT_RC_CPU_CAD_L9
HT_CPU_RC_CAD_L10 AG10 HT_MCP_RXD10_N HT_MCP_TXD10_N AD20 HT_RC_CPU_CAD_L10
HT_CPU_RC_CAD_L11 AD12 HT_MCP_RXD11_N HT_MCP_TXD11_N AF20 HT_RC_CPU_CAD_L11
C HT_CPU_RC_CAD_L12 AC11 HT_MCP_RXD12_N HT_MCP_TXD12_N AE18 HT_RC_CPU_CAD_L12 C
HT_CPU_RC_CAD_L13 AB12 HT_MCP_RXD13_N HT_MCP_TXD13_N AG18 HT_RC_CPU_CAD_L13
HT_CPU_RC_CAD_L14 AG14 HT_MCP_RXD14_N HT_MCP_TXD14_N AB16 HT_RC_CPU_CAD_L14
HT_CPU_RC_CAD_L15 AD14 HT_MCP_RXD15_N HT_MCP_TXD15_N AD16 HT_RC_CPU_CAD_L15
6 HT_CPU_RC_CLK_H0 AJ11 HT_MCP_RX_CLK0_P HT_MCP_TX_CLK0_P AH20 HT_RC_CPU_CLK_H0 6

6 HT_CPU_RC_CLK_L0 AH11 HT_MCP_RX_CLK0_N HT_MCP_TX_CLK0_N AG20 HT_RC_CPU_CLK_L0 6
AE12 HT_MCP_RX_CLK1_P HT_MCP_TX_CLK1_P AC18 HT_RC_CPU_CLK_H1 6 +3.3V
6 HT_CPU_RC_CLK_H1
6 HT_CPU_RC_CLK_L1 AF12 HT_MCP_RX_CLK1_N HT_MCP_TX_CLK1_N AB18 HT_RC_CPU_CLK_L1 6
6 HT_CPU_RC_CTL_H0
6 HT_CPU_RC_CTL_L0
AJ15
AH15
HT_MCP_RXCTL0_P
HT_MCP_RXCTL0_N
HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N
AH16
AG16
HT_RC_CPU_CTL_H0
HT_RC_CPU_CTL_L0
6
6
*R200
10K
AB14 RESERVED RESERVED AE16 +/-5%
AC14 RESERVED RESERVED AF16
+1.2V_HT
AH25 HTCPU_REQ*
HT_MCP_REQ*
*
R322 HT_MCP_STOP* AH24 CPU_LDTSTOP_L 9

150 HTCPUCAL_1P2V AB9 HT_MCP_COMP_VDD HT_MCP_RST* AG23 CPU_HT_RESET_L 9
*
+/-1% R323 HT_MCP_PWRGD AG24 CPU_ALL_PWROK 9

150 HTCPUCAL_GND AB8 HT_MCP_COMP_GND
+/-1%
CLKOUT_200MHZ_P AK25 CPU_CLKIN_H 9
CLKOUT_200MHZ_N AJ25 CPU_CLKIN_L 9
+3.3V 9 CPU_PROCHOT_L_1.8 AD8 PROCHOT*/GPIO20
CPU_THERMTRIP* AE8 THERMTRIP*/GPIO58
9,21 CPU_THERMTRIP* 5MIL TRACE
+1.2V
+1.2V
R321 AF24
70mA CPU_SBVREF
*
L15 1 AC15 +1.2V_PLL_CPU_HT

1 2 +3.3_PLL_CPU +/-1%1.2V_PLLCPUHT AB15 AK26 TP_CLKOUT25MHZ
* +3.3V_PLL_CPU CLKOUT_25MHZ
40 Ohm@100MHz C521 12mA CLK200_TERM_GND AJ26 * C278
C366 * 0.1uF
C519 ?
+80/-20%
B
*
+80/-20%
*
+80/-20% C272 *R197
2.37K Ohm
4.7uF
B
4.7uF 25V, Y5V, +80%/-20% 4.7uF
* 100nF +/-1%
+80%~-20%
A A
FOXCONN PCEG
Title
MCP61_HT
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
U15A
?
MCP61
PE0_IN[15..0] SEC 2 OF 8 PE0_OUT[15..0]
19 PE0_IN[15..0] PE0_OUT[15..0] 19
0 PE0_IN0
H23 G29 0 PE0_OUT0
PE0_RX0_P PE0_TX0_P
1 PE0_IN1
H25 H27 1 PE0_OUT1
PE0_RX1_P PE0_TX1_P
2 PE0_IN2
K22 J27 2 PE0_OUT2
PE0_RX2_P PE0_TX2_P
3 PE0_IN3
K24 J30 3 PE0_OUT3
PE0_RX3_P PE0_TX3_P
4 PE0_IN4
K26 K29 4 PE0_OUT4
PE0_RX4_P PE0_TX4_P
5 PE0_IN5
M22 L29 5 PE0_OUT5
PE0_RX5_P PE0_TX5_P
6 PE0_IN6
M23 M27 6 PE0_OUT6
PE0_RX6_P PE0_TX6_P
7 PE0_IN7
M26 N27 7 PE0_OUT7
PE0_RX7_P PE0_TX7_P
8 PE0_IN8
P22 N30 8 PE0_OUT8
PE0_RX8_P PE0_TX8_P
9 PE0_IN9
P26 P29 9 PE0_OUT9
PE0_RX9_P PE0_TX9_P
10 PE0_IN10 P25 R29 10PE0_OUT10
D PE0_RX10_P PE0_TX10_P D
11 PE0_IN11 T23 T27 11PE0_OUT11
PE0_RX11_P PE0_TX11_P
12 PE0_IN12 T26 U27 12PE0_OUT12
13 PE0_IN13
U23 U30 13PE0_OUT13
14 PE0_IN14
V24 V29 14 PE0_OUT14
15 PE0_IN15 V27 W29 15PE0_OUT15
PE0_IN*[15..0] PE0_OUT*[15..0]
19 PE0_IN*[15..0] PE0_OUT*[15..0] 19
0 PE0_IN*0
H24 G28 0 PE0_OUT*0
PE0_RX0_N PE0_TX0_N
1 PE0_IN*1
H26 H28 1 PE0_OUT*1
PE0_RX1_N PE0_TX1_N
2 PE0_IN*2
K23 J28 2 PE0_OUT*2
PE0_RX2_N PE0_TX2_N
3 PE0_IN*3
K25 J29 3 PE0_OUT*3
PE0_RX3_N PE0_TX3_N
4 PE0_IN*4
K27 K28 4 PE0_OUT*4
PE0_RX4_N PE0_TX4_N
5 PE0_IN*5
L22 L28 5 PE0_OUT*5
PE0_RX5_N PE0_TX5_N
6 PE0_IN*6
M24 M28 6 PE0_OUT*6
PE0_RX6_N PE0_TX6_N
7 PE0_IN*7
M25 N28 7 PE0_OUT*7
PE0_RX7_N PE0_TX7_N
8 PE0_IN*8
P23 N29 8 PE0_OUT*8
PE0_RX8_N PE0_TX8_N
9 PE0_IN*9
P27 P28 9 PE0_OUT*9
PE0_RX9_N PE0_TX9_N
10 PE0_IN*10 P24 R28 10PE0_OUT*10
PE0_RX10_N PE0_TX10_N
11 PE0_IN*11 T24 T28 11PE0_OUT*11
PE0_RX11_N PE0_TX11_N U15B
12 PE0_IN*12 T25 U28 12PE0_OUT*12
PE0_RX12_N PE0_TX12_N ?
13 PE0_IN*13 V23 U29 13PE0_OUT*13
PE0_RX13_N PE0_TX13_N MCP61
14 PE0_IN*14 V25 V28 14PE0_OUT*14
PE0_RX14_N PE0_TX14_N
15 PE0_IN*15 V26 PE0_RX15_N PE0_TX15_N W28 15PE0_OUT*15 SEC 3 OF 8
19 PE1_IN Y28 PE1_RX_P PE1_TX_P AA28 PE1_OUT 19

B22 PE0_REFCLK_P Y24 PE0_REFCLK Y27 PE1_RX_N PE1_TX_N AA27
19 PE_WAKE* PE_WAKE*/GPIO21 PE0_REFCLK 19 19 PE1_IN* PE1_OUT* 19
AF27
UNNAMED_19_MCP61_I99_PE0PRSNTX1
PE0_REFCLK_N Y23 PE0_REFCLK* AB29 PE2_RX_P PE2_TX_P AA30
19 PE0_PRSNTX1* PE0_PRSNTX1*/SDVO_SCL PE0_REFCLK* 19
19 PE0_PRSNTX4*
UNNAMED_19_MCP61_I99_PE0PRSNTX4
AF28 PE0_PRSNTX4*/SDVO_SDA AB28 PE2_RX_N PE2_TX_N AA29
AE26 PE0_PRSNTX8*
R320
19 PE0_PRSNTX8* PECLK_TEST 100
19 PE0_PRSNTX16* AF29 PE0_PRSNTX16* PE_A_TSTCLK_N AC24
PE_A_TSTCLK_P AC25 PECLK_TEST* +/-5% AK29 PEA_CLKREQ*/GPIO51 PE1_REFCLK_P Y26 PE1_REFCLK 19
19 PE1_PRSNT*
+1.2V Dummy PE1_REFCLK_N Y25 PE1_REFCLK* 19
AG28 AB23
30mA W22 +1.2V_PLL_PE_SS PE_RESET* AH29 PE_RESET*
PE_RESET* 19 AG30
PE1_PRSNT*
PE2_PRSNT*
PE2_REFCLK_P
PE2_REFCLK_N AA23
C255 C265 Y22 +1.2V_PLL_PE_SS
*
PE_B_TSTCLK_P
* 100nF
* 4.7uF R208
Dummy
PE_B_TSTCLK_N
AC27
AC26
PE_B_TSTCLK_P
PE_B_TSTCLK_N
C PE_CLK_COMP AJ30 PE_COMP R209 2.37K Ohm AC29 C
+80%~-20% +/-1% 100 RESERVED
AD27 AC28
160mA +3.3V +/-5% AD28
RESERVED
RESERVED
RESERVED
RESERVED AE27
+80/-20% U22 R22 L20 AE30 AE28
V22
+1.2V_PLL_PE
+1.2V_PLL_PE
+3.3V_PLL_PE_SS
+3.3V_PLL_PE_SS T22 30mA 1* 2 AE29
RESERVED
RESERVED
RESERVED
RESERVED AB24
AJ29 RESERVED RESERVED AB25
C514 C51840 Ohm@100MHz AG29 RESERVED RESERVED AB27
?
+1.2V
1*
L19
2 1P2V_PLLPE * 0.1uF
* 4.7uF AH30 RESERVED RESERVED AB26
C517
40 Ohm@100MHz
* 4.7uF 25V, Y5V, +80%/-20%
26 RX_D0 D26 RGMII_RXD0/MII_RXD0 RGMII_TXD0/MII_TXD0 A28 *1
RN26
2
0 Ohm TXD0
TX_D0 26
+80/-20% 26 RX_D1 E26 RGMII_RXD1/MII_RXD1 RGMII_TXD1/MII_TXD1 B28 +/-5% TXD1
3 4 TX_D1 26
26 RX_D2 B26 RGMII_RXD2/MII_RXD2 RGMII_TXD2/MII_TXD2 D28 TXD2
5 6 TX_D2 26
26 RX_D3 B27 RGMII_RXD3/MII_RXD3 RGMII_TXD3/MII_TXD3 E27 TXD3
7 8 TX_D3 26
+80/-20% 26 RX_CLK A26 RGMII_RXC/MII_RXCLK RGMII_TXC/MII_TXCLK D27
*
R191 0 TX_CLK 26
26 RX_DV C26 RGMII_RXCTL/MII_RXDV RGMII_TXCTL/MII_TXEN E28 TX_EN 26
+/-5%
@AC131
@AC131
26 RX_ER RX_ER D24 MII_RXER/GPIO36 RGMII/MII_MDC B25 MDC MII_MDC 26
COL E24 MII_COL/GPIO13/MI2C_DATA RGMII/MII_MDIO A25 MDIO MII_MDIO 26
26 MII_COL
CRS F23 MII_CRS/GPIO14/MI2C_CLK
26 MII_CRS
RGMII/MII_PWRDWN*/GPIO37 F24 +3.3V_DUAL
R219 +3.3V
**
+3.3V_DUAL TP28 1 GMII_INTR*
G24 RGMII/MII_INTR*/GPIO35 BUF_25MHZ C24 33
LAN_X1 26
+/-5%
L16 40 Ohm@100MHz
6mA MII_RESET*/GPIO12 C25 R205 *R196
1.47K Ohm
*
C365
100nF
1 2 +3.3V_PLL_MAC_DUAL
M9 +3.3V_PLL_MAC_DUAL 4.7K +/-5% +/-1%
***
*
R240 0 +/-5%RX_ER @8100C @AC131 Dummy +80%~-20%
R332 0 +/-5%MII_COL @8100C C381 C370 MII_VREF C27
+/-5%MII_CRS
R333 0 @8100C
* 4.7uF
* 100nF
+80%~-20%
+3.3V_DUAL
R201 C296 @AC131
R190
*
**
+80/-20%
+/-1%
49.9
49.9
R204 MII_COMP_3P3V
B23
C23MII_COMP_GND
MII_COMP_3P3V
MII_COMP_GND
* 100nF 1.47K Ohm
+/-1% TX_CLK
+/-1% +80%~-20%
R392
#R1000#R1001 10K
B
DAC_RED DDC_CLK @AC131 +/-5% B
31 DAC_RED D30 DAC_RED DDC_CLK/GPIO17 B6 DDC_CLK 31
RN139 31 DAC_GREEN DAC_GREEN D29 DAC_GREEN DDC_DATA/GPIO19 A6 DDC_DATA
DDC_DATA 31
*
1
3
2
4
RX_D1
RX_D3
31 DAC_BLUE DAC_BLUE C30 DAC_BLUE
RX_D0 PLACE NEAR MCP61

5
7
6
8 RX_D2 1 1 1 31 DAC_HSYNC DAC_HSYNCB30 DAC_HSYNC R270 *R1000
10K *R1001
1.47K Ohm
@8100C
*
R202 R203 R207 DAC_VSYNCC29 MCP61_TCK
M7 10K +/-5% +/-1%
31 DAC_VSYNC DAC_VSYNC JTAG_TCK
10K @8100C 150 150 JTAG_TDI M5 +/-5% r0402h4 r0402h4
+/-5% +/-5% 150 +/-5% JTAG_TDO M6
+/-5% JTAG_TMS M8 R277 @8100C @AC131
*
2 2 2 DACRSET TP_MCP61_TRST* 10K
B29 DAC_RSET JTAG_TRST* L9
A29 DAC_VREF Dummy +/-5%
R199 C274 K7 XTALIN
XTALIN
XTALOUT
*
1
RN140
2 GMII_INTR*
124 0.1uF
*
16V, X7R, +/-10%
XTALOUT K8 X2
XTAL-25MHz
3 4 RX_CLK +/-1% 1 2
5 6 MDIO XTALIN_RTC XTALIN_RTC
K6
7 8 RX_DV L14 40 Ohm@100MHz XTALOUT_RTC
K5 C442 C440
+3.3V 1
* 2 3P3V_DAC 100mA
F28 +3.3V_DAC
XTALOUT_RTC
X3 XTAL-32.768kHz
* 27pF
* 27pF
10K @8100C C280 C284 2 1 +/-5% +/-5%
+/-5%
* *
4.7uF 100nF
*
C438
18pF
C439
* 18pF
3
+80/-20% ? +/-5% +/-5%
+80%~-20%
BYPASS CAPS
+5V_DUAL
modify 9/19
modify 9/13
C436 C430 X3_1
* 100nF
* 100nF
+80%~-20% +80%~-20%
Crystal Retainer
A A
FOXCONN PCEG
Title
MCP61_PCI-E_VGA
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
modify 8/20 MCP61 DECOUPLING

+1.2V_HT
U15F
? +1.2V
+1.2V MCP61
7.008A SEC 7 OF 8 +1.2V
1
AK27 +1.2V W15 L13
+1.2V_HT
AH27 W16
AJ27
+1.2V
+1.2V
+1.2V_HT
+1.2V_HT W17 700mA
AG26 +1.2V
FB 30Ohm 1P2V_PEA C520 C301 C303
2
AG25
U18
+1.2V
+1.2V
+1.2V_PEA
+1.2V_PEA
AK28
AJ28
MODIFY 8/21 *10uF * 100nF
* 100nF
+80%~-20%
+80%~-20%
AE22 AH28
AE23
+1.2V
+1.2V
+1.2V_PEA
+1.2V_PEA AG27 1.837A
V19 +1.2V AF26 6.3V, Y5V, +80%/-20%
+1.2V_PEA
D
V18 +1.2V +1.2V_PEA AE25 D
U19 +1.2V +1.2V_PEA AD24
W19 +1.2V +1.2V_PEA AC23
W18 +1.2V
V15 +1.2V
+1.2V
U16 +1.2V
+1.2V
T14 +1.2V
W14
AB21
+1.2V
+1.2V +1.2V_SP_D V13 97mA C263 C270 C250 C288 C277 C257 C267 C297 C282 C253
AC21
U14
+1.2V
+1.2V
+1.2V_SP_D
+1.2V_SP_D
W13
V14
*
Dummy *
10uF
Dummy *
10uF 10uF
*10uF *10uF *10uF * 100nF
* 100nF
* 10uF
+80%~-20% +80%~-20%
Dummy * 100nF
+80%~-20%
2
T18 +1.2V +1.2V_SP_D W12
U15 +1.2V
L22
R15 +1.2V 40 Ohm@100MHz 6.3V, Y5V, +80%/-20% 6.3V, Y5V,6.3V,
+80%/-20%
Y5V,6.3V,
+80%/-20%
Y5V, +80%/-20%
6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20%
1P2V_SP_A 6.3V, Y5V, +80%/-20%
*
V17 +1.2V 320mA
1
V16 +1.2V +1.2V_SP_A W9
R17 +1.2V +1.2V_SP_A W8
T16 +1.2V +1.2V_SP_A V8
U17 +1.2V +1.2V_SP_A V9
R19 +1.2V U9 1P2V_PEA
+1.2V_SP_A
C269 C262 C276 C287 C251 C300 C298 C302 C281 C254 C286
389mA +1.2V_DUAL
*10uF *10uF *10uF *10uF * 1uF
* *
100nF 100nF
* 100nF
* *10uF *10uF
10uF
AB22 +1.2V_PED
+80%~-20% +80%~-20%
AE24 F26 Dummy
Dummy Dummy
AD22
+1.2V_PED
+1.2V_PED
+1.2V_DUAL
+1.2V_DUAL F27 286mA 6.3V, Y5V, +80%/-20%
AA22 +1.2V_PED
6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20% 6.3V, Y5V,
6.3V,
+80%/-20%
Y5V,6.3V,
+80%/-20%
Y5V, +80%/-20%
AC22 +1.2V_PED
+3.3V_DUAL
+1.2V_HT
L4 1P2V_SP_A Reserved
+3.3V_DUAL
J22 C525 MODIFY 8/21 MODIFY 8/21 +1.2V_DUAL
+3.3V_DUAL 200mA * 0.1uF
+3.3V L3 * C523 25V, Y5V, +80%/-20% C373 C516
+3.3V_USB_DUAL
827mA
H15 +3.3V
+3.3V_USB_DUAL L2
350mA +80/-20%
4.7uF * 0.1uF
* 0.1uF
25V, Y5V, 25V,
+80%/-20%
Y5V, +80%/-20%
*
C264
100nF
C268
*
100nF
C258
*10uF
C J15 +3.3V
+80%~-20%
+80%~-20% C
AC6 +3.3V
PLACE CAPS CLOSE TO 3.3V_USB_DUAL
AC5 +3.3V
ISSUES IN THE PAST
6.3V, Y5V, +80%/-20%
?
+3.3V_DUAL
+3.3V
C515 C380 C379 C371
* 0.1uF
* 100nF
25V, Y5V, +80%/-20% * 100nF
*
100nF
+80%~-20% +80%~-20% +80%~-20%
C418 C339 C368 C364 C336 C372
AD26
AC13
AC19
AC17
AK14
AK30
AB30
AA25
AK10
* 100nF
* 100nF
* 100nF
* 100nF
*
100nF
* 100nF
W25
W27
W23
AG7
AG4
M15
AC8
M14
M13
AC4
AB3
AE9
AK5
AB4
N19
N12
N14
D23
H21
U25
R25
N13
R27
C28
H11
AF1
P15
P14
P12
A30
V30
P30
K30
P18
A27
E29
F30
F25
F21
F19
F29
T19
AJ7
L25
L27
J21
J25
W6
W4
U1
R9
N9
H7
N8
U8
R4
R8
D1
+80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20%

K9
K1
V3
F7
J9
U15G ?
MCP61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SEC 8 OF 8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B B
P19
H19
AE11
D7
G27
AB7
T15
U2
P13
AC9
N25
G26
F17
F15
F13
F11
F9
D25
H17
D19
J17
H13
AH26
AA9
AE21
AE19
AE17
AE15
AE13
AA8
AF30
AK22
AG19
AK18
AG15
C4
E30
D15
D11
J6
L6
N6
R6
U6
N22
R13
M19
AK1
J23
R23
M18
N18
P16
N15
R18
T13
T17
M17
L23
P17
J11
R16
A1
J13
M16
N16
N17
AG11
N23
R14
T12
R12
AC7
A A
FOXCONN PCEG
Title
MCP61_POWER
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
D D
U15C
?
MCP61
PCI_AD[31..0]
20,26 PCI_AD[31..0] SEC 4 OF 8
0 PCI_AD0
D14 G12
PCI_AD0 PCI_REQ0* PCI_REQ*0 20
1 PCI_AD1
E14 A10
PCI_AD1 PCI_REQ1* PCI_REQ*1 20
2 PCI_AD2
A13 C11
PCI_AD2 PCI_REQ2*/GPIO40/RS232_DSR* PCI_REQ*2 20
3 PCI_AD3
C14 H14
PCI_AD3 PCI_REQ3*/GPIO38/RS232_CTS* PCI_REQ*3 20
4 PCI_AD4
A14 D13
PCI_AD4 PCI_REQ4*/GPIO52/RS232_SIN* PCI_REQ*4 20,26
5 PCI_AD5
B14 PCI_AD5
6 PCI_AD6
C15 PCI_AD6
7 PCI_AD7
J16 PCI_AD7
8 PCI_AD8
G16 A9
PCI_AD8 PCI_GNT0*
9 PCI_AD9
F16 C10
PCI_AD9 PCI_GNT1*
10 PCI_AD10 E16 B10
PCI_AD10 PCI_GNT2*/GPIO41/RS232_DTR* PCI_GNT*2 20
11 PCI_AD11 B15 J14
PCI_AD11 PCI_GNT3*/GPIO39/RS232_RTS* PCI_GNT*3 20
12 PCI_AD12 D16 PCI_AD12 C12 PCI_GNT*4 26 RN51
PCI_GNT4*/GPIO53/RS232_SOUT*
13 PCI_AD13
14 PCI_AD14
C16
D17
PCI_AD13
PCI_AD14
PCI_CLK2
*1 2 PCI_CLKSLOT1
PCI_CLKSLOT1 20
15 PCI_AD15
3 4 PCI_CLKSLOT2
C17 PCI_AD15
PCI_CLK0
5 6 PCI_CLKSLOT2 20
16 PCI_AD16 J19 C22 PCI_INTW* PCI_CLK3 PCI_CLK_LAN
PCI_AD16 PCI_INTW* PCI_INTW* 20 7 8 PCI_CLK_LAN 26
17 PCI_AD17 J20 D22 PCI_INTX*
PCI_AD17 PCI_INTX* PCI_INTX* 20
18 PCI_AD18 H20 PCI_AD18 PCI_INTY* A22 PCI_INTY* 22 Ohm
PCI_INTY* 20
19 PCI_AD19 G20 PCI_AD19 PCI_INTZ* A21 PCI_INTZ* +/-5%
PCI_INTZ* 20,26
20 PCI_AD20 F20 PCI_AD20
C556C555C554
21 PCI_AD21
22 PCI_AD22
E20
B18
PCI_AD21
PCI_AD22
* *
Dummy *
22pF22pF22pF
Dummy 50V, NPO, +/-5%
Dummy
23 PCI_AD23 C19 B13 PCI_CLK0
PCI_AD23 PCI_CLK0
C 24 PCI_AD24 D20 F14 C
PCI_AD24 PCI_CLK1
25 PCI_AD25 C20 D12 PCI_CLK2
PCI_AD25 PCI_CLK2
26 PCI_AD26 D21 E12 PCI_CLK3
PCI_AD26 PCI_CLK3
27 PCI_AD27
C21 PCI_AD27 PCI_CLK4 H12 R221
*
28 PCI_AD28
B21 PCI_AD28
PCI_CLK4 22
29 PCI_AD29 H22 PCI_AD29
+/-5%
30 PCI_AD30 G22 J12 PCI_CLKIN
PCI_AD30 PCI_CLKIN
31 PCI_AD31 F22 PCI_AD31
C359
PCI_C/BE*[3..0]
20,26 PCI_C/BE*[3..0] * 22pF
50V, NPO, +/-5%
PCI_C/BE*0 H16
PCI_C/BE*1 PCI_CBE0*
B17 PCI_CBE1* Dummy
PCI_C/BE*2 A18
PCI_C/BE*3 PCI_CBE2*
B19 PCI_CBE3*
PCI_FRAME* C18
20,26 PCI_FRAME* PCI_FRAME*
20,26 PCI_IRDY* PCI_IRDY* A17 PCI_IRDY*
RN27
20,26 PCI_TRDY*
20,26 PCI_STOP*
PCI_TRDY*
PCI_STOP*
D18
F18
PCI_TRDY*
PCI_STOP*
LPC_AD0 G10
F10
*1 2 LPC_AD0
LPC_AD1
21
21
LPC_AD1 3 4
20,26 PCI_DEVSEL* PCI_DEVSEL* E18 PCI_DEVSEL* D10 LPC_AD2 21 +3.3V
LPC_AD2 5 6
PCI_PAR J18 E10
20,26 PCI_PAR PCI_PAR LPC_AD3 7 8 LPC_AD3 21
20,26 PCI_PERR* PCI_PERR* G18 PCI_PERR*/GPIO43/RS232_DCD*
R228
20,26 PCI_SERR* PCI_SERR* H18 PCI_SERR*
22 Ohm * 8.2K
Dummy
PCI_PME* E22 PCI_PME*/GPIO30
+/-5% +/-5%
20,26 PCI_PME*
C8 LPCPWRDWN* 1 R226TP35
*
LPC_PWRDWN*/GPIO54/EXT_NMI*
H10 LPCFRAME* 22 LPC_FRAME* 21
LPC_FRAME*
C9 +/-5% LPC_DRQ0*
LPC_DRQ0*/GPIO50 LPC_DRQ0* 21
B9 LPC_DRQ1* 1 TP32
LPC_DRQ1*/GPIO15/FANRPM1
C13 PCI_RESET0* LPC_SERIRQ J10 LPC_SERIRQ LPC_SERIRQ 21
33 RN28 R225
+/-5% PCI_RESET1* G14 PCI_RESET1*
8.2K
* STRAP
20 PCIRST_SLOT1*
20 PCIRST_SLOT2*
PCIRST_SLOT1*
PCIRST_SLOT2*
*1 2 PCI_RESET2* B11 PCI_RESET2*
+/-5%
3 4 R230 HDA_SDOUT
*
26 PCIRST_SLOT3* PCIRST_IDE* 5 6 PCI_RESET3* LPC_CLK0 33 PCI_CLKSIO LPC_FRAME
22 PCIRST_IDE* 7R3258 F12 PCI_RESET3* LPC_CLK0 E8 PCI_CLKSIO 21
+/-5%
*
B DEFAULT* B
LPCRST_SIO* LPC_RESET* D9 LPC_RESET*
21 LPCRST_SIO*
D8 C363
LPC_CLK1 00 = LPC BIOS
33 ? * 10pF
50V, NPO, +/-5% 01 = PCI BIOS
+/-5% Dummy 10 = SPI BIOS*
11 = RESERVED
near SB
A A
FOXCONN PCEG
Title
MCP61_PCI
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
U15_1
1 1
D D
2 2
Heatsink_NB U15D
?
SATA_1 PLACE CAPS AT CONN MCP61
1 SEC 5 OF 8 IDE_PDD[15..0]
IDE_PDD[15..0] 22
* *
CONN-SATA 2 SP_TX0P C455 SP_TX0P_C V2 IDE_DATA_P0 AJ3 0 IDE_PDD0
SATA_A0_TX_P
* *
8 3 SP_TX0M 10nF 25V, X7R, +/-10% C467 SP_TX0M_C V1 IDE_DATA_P1 AJ2 1 IDE_PDD1
SATA_A0_TX_N
4 10nF 25V, X7R, +/-10% IDE_DATA_P2 AH3 2 IDE_PDD2
9 5 SP_RX0M C477 SP_RX0M_C W3 IDE_DATA_P3 AH1 3 IDE_PDD3
SP_RX0P 10nF 25V, X7R, +/-10% C479 SP_RX0P_C SATA_A0_RX_N 4

6 W2 SATA_A0_RX_P IDE_DATA_P4 AG2 IDE_PDD4
7 10nF 25V, X7R, +/-10% IDE_DATA_P5 AF2 5 IDE_PDD5
AF4 6 IDE_PDD6
IDE_DATA_P6
AE6 7 IDE_PDD7
IDE_DATA_P7
SATA_2 PLACE CAPS AT CONN AE5 8 IDE_PDD8
IDE_DATA_P8
1 AF5 9 IDE_PDD9
IDE_DATA_P9
* *
CONN-SATA 2 SP_TX1P C472 SP_TX1P_C Y8 IDE_DATA_P10 AF3 10IDE_PDD10
SATA_A1_TX_P
* *
8 3 SP_TX1M 10nF 25V, X7R, +/-10% C474 SP_TX1M_C Y7 IDE_DATA_P11 AG1 11IDE_PDD11
SATA_A1_TX_N
4 10nF 25V, X7R, +/-10% IDE_DATA_P12 AG3 12IDE_PDD12
9 5 SP_RX1M C481 SP_RX1M_C Y5 IDE_DATA_P13 AH2 13IDE_PDD13

SP_RX1P 10nF 25V, X7R, +/-10% C483 SP_RX1P_C SATA_A1_RX_N 14IDE_PDD14
6 Y6 SATA_A1_RX_P IDE_DATA_P14 AJ1
modify 8/16 7 10nF 25V, X7R, +/-10% IDE_DATA_P15 AK2 15IDE_PDD15
PLACE CAPS AT CONN
AG6 IDE_ADDR_P0
IDE_ADDR_P0 IDE_ADDR_P1 IDE_ADDR_P0 22
SATA_3 IDE_ADDR_P1 AJ5 IDE_ADDR_P1 22
1 AH6 IDE_ADDR_P2
IDE_ADDR_P2 IDE_ADDR_P2 22
* *
CONN-SATA 2 SP_TX2P C456 SP_TX2P_C Y4 SATA_B0_TX_P
* *
8 3 SP_TX2M 10nF 25V, X7R, +/-10% C468 SP_TX2M_C Y3 AK6 IDE_CS1_P*
SATA_B0_TX_N IDE_CS1_P* IDE_CS3_P* IDE_CS1_P* 22
4 10nF 25V, X7R, +/-10% IDE_CS3_P* AJ6 IDE_CS3_P* 22
9 5 SP_RX2M C473 SP_RX2M_C AA4 AG5 IDE_DACK_P*
SATA_B0_RX_N IDE_DACK_P* IDE_IOW_P* IDE_DACK_P* 22
6 SP_RX2P 10nF 25V, X7R, +/-10% C475 SP_RX2P_C AA3
IDE_IOW_P* AH4 IDE_IOW_P* 22
10nF 25V, X7R, +/-10% SATA_B0_RX_P IDE_INTR_P
7 IDE_INTR_P AH5 IDE_INTR_P 22
C AK3 IDE_DREQ_P R235 C
IDE_DREQ_P IDE_DREQ_P 22
*
PLACE CAPS AT CONN AJ4 IDE_IOR_PR* 0 IDE_IOR_P*
IDE_IOR_P* IDE_IORDY_P IDE_IOR_P* 22
SATA_4 IDE_RDY_P AK4 +/-5%
CBLE_DET_P IDE_IORDY_P 22
1 CABLE_DET_P/GPIO63 AF6 CBLE_DET_P 22
CONN-SATA 2 SP_TX3P C478 * * SP_TX3P_C AA2 SATA_B1_TX_P
* *
8 3 SP_TX3M 10nF 25V, X7R, +/-10% C480 SP_TX3M_C AA1 SATA_B1_TX_N
4 10nF 25V, X7R, +/-10%
9 5
6
SP_RX3M
SP_RX3P
C482
10nF 25V, X7R, +/-10% C484
SP_RX3M_C AB1
SP_RX3P_C AB2 SATA_B1_RX_N
near SB
10nF 25V, X7R, +/-10% SATA_B1_RX_P
7
+3.3V
**
AD5 IDE_COMP_3P3V R271 121 Ohm
IDE_COMP_3P3
AD6 IDE_COMP_GND R258 121 Ohm
+/-1%
IDE_COMP_GND
+/-1%
AC3 RESERVED SATA_LED*/GPIO57 A5 SATA_HDLED* 27

AC2 RESERVED
AD4 RESERVED
AD3 RESERVED
+1.2V AE4 R324
RESERVED SATA_TSTCLK_P
AE3 AA6 100
RESERVED SATA_TSTCLK_P
AE1 AB6 SATA_TSTCLK_N +/-5%
RESERVED SATA_TSTCLK_N
AE2 RESERVED
L23 Dummy
1* 2 +1.2V_PLL_SP_VDD 80mA Y9 +1.2V_PLL_SP_VDD
C524 +1.2V AB5 SATA_TERMP
SATA_TERMP
40 Ohm@100MHz
* 10uF
6.3V, Y5V, +80%/-20% 7.5mA

U13 R257
+1.2V_PLL_SP_SS
U12 +3.3V_PLL_SP_SS
* 2.49K
+3.3V V12 +3.3V_PLL_LEG +/-1%
B
M12 +3.3V_PLL_DISP B
C256
L21 * 100nF
+80%~-20%
1
* 2 +3.3_PLL 73mA ?
40 Ohm@100MHz
* C522
+80/-20%
4.7uF
A A
FOXCONN PCEG
Title
MCP61_SATA_IDE
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
STRAP
HDA_SDOUT
LPC_FRAME
DEFAULT*
RN49
00 = LPC BIOS
USB_0+
USB_0-
*1 2
15K
+/-5% +3.3V
01 = PCI BIOS 3 4
* = DEFAULT USB_5+
5 6
10 = SPI BIOS* USB_5-
11 = RESERVED +3.3V 7 8
SPDIF0
(SIO CLK) C432 C426 C408 C434
1 = *24MHZ
0 = 14.318MHZ R246 U15E USB_2+
*1
RN50
15K * 100nF
* 100nF
* *
100nF 100nF
D
* 10K ?
MCP61
USB_2-
3
2
4
+/-5%
D
+/-5% USB_1+
5 6
SPDIF0 SEC 6 OF 8 USB_1-
7 8
TP33 1TP_GP_REFCLK B7 GP_REFCLK USB0_P M3 USB_0+
USB_0+ 25
* *
R71 22 B4 HDA_BCLK USB0_N M4 USB_0-
USB_0- 25 Dummy Dummy Dummy Dummy
32 AC_BITCLK RN29
AC_SDOUT
+/-5% R241
22 AC_OUT A3
USB1_P N3
N4
USB_1+
USB_1-
USB_1+ 25 USB_4+
USB_4-
*1 2
15K
+/-5%
+3.3V
32
32
AC_SDOUT
AC_SDIN_0
+/-5%
TP41 1
A2
B1
HDA_SDATA_OUT0/GPIO45
HDA_SDATA_IN0/GPIO22
USB1_N
N1 USB_2+
USB_1- 25
USB_3+
USB_3-
3
5
4
6 For EMI
HDA_SDATA_IN1/GPIO23/MGPIO0 USB2_P USB_2+ 25 7 8
AC_RST*
1 = *RGMII C66
* Dummy * R331
10K *C73
22pF C72
*
C369
10pF
B2 RESERVED USB2_N N2 USB_2-
USB_2- 25
0 = MII
* R250
10K
22pF +/-5%
Dummy * 22pF 50V, NPO, +/-5%
50V, NPO, +/-5% Dummy
USB3_P
USB3_N
P1
P2
USB_3+
USB_3-
USB_3+
USB_3-
25
25 USB_7+
*1
RN46
2
15K
+/-5% USB_7- +/-5%
3 4
Dummy USB4_P R2 USB_4+
USB_4+ 25 USB_6+
**
R236
AC_RST* 22 +/-5% USB_4- USB_6- 5 6
32 AC_RST* C3 HDA_RESET* USB4_N R3 USB_4- 25 7 8
R239
AC_SYNC 22 +/-5% B3 HDA_SYNC/GPIO44
32 AC_SYNC +3.3V_DUAL P3 USB_5+
USB5_P USB_5+ 25
R238 P4 USB_5-
* 10K
* C75 R251 10K @AC131 F2 GPIO_1
USB5_N USB_5- 25
RN30
+/-5% 22pF
* R256 GPIO2_CHIPSET F1 T3 USB_6+
USB_6+ 25 USB_8-
*1
*
GPIO_2/NMI* USB6_P 2
50V, NPO, +/-5% modify 8/20 10K F6 T4 USB_6- USB_8+
GPIO_3/SMI* USB6_N USB_6- 25 3 4
J8 USB_9+
GPIO_4/SCI_INTR* 5 6
Dummy R245 @8100C G3 GPIO_5/INIT* USB7_P U3 USB_7+
USB_7+ 25 USB_9-
*
10K @VT1708B USB_7- 7 8

G5 GPIO_6/FERR*/SYS_FERR* USB7_N U4 USB_7- 25
+/-5% G6 GPIO_7/NFERR*/SYS_PERR*
15K
+3.3V_DUAL R244 T6 USB_8+ +/-5%
10K * SPI_DI D3 GPIO_8/SPI_DI
USB8_P
USB8_N T5 USB_8- +3.3V_DUAL
+/-5% SPI_DO D4 GPIO_9/SPI_DO
SPI_CS E4 T8 USB_9+ R263
R334 GPIO PIN: Board ID Select. @ALC662 SPI_CLK
5/5. Max length: 10 inches.
E3
GPIO_10/SPI_CS
GPIO_11/SPI_CLK
USB9_P
USB9_N T7 USB_9- * 10K
10K +/-5%
+/-5% D5 RESERVED
R248 R237 E5
SPI CLK Frequency Select
* R234 *
*R249 10K * 10K RESERVED
USB_OC0*/GPIO25 P7 USB_OC0*
USB_OC0* 25
USB_OC4*
GPIO2_CHIPSET GPIO_9/SPI_DO (MSB) 10K 10K +/-5% +/-5% USB_OC1*/GPIO26 P8 USB_OC1*
USB_OC1* 25
GPIO_11/SPI_CLK (LSB) +/-5% +/-5% USB_OC2*/GPIO27 P9 USB_OC2*
USB_OC2* 25
C Dummy Dummy USB_OC3*/GPIO28/MGPIO1 P5 USB_OC3*
USB_OC3* 25 C
P6 USB_OC4*
* R335 Dummy 00
01
=
=
500 kHz
1.8 MHz
USB_OC4*/GPIO29
R262
*
10K T9 USB_RBIAS_GND 1.24K
10 = 2.5 MHz USB_RBIAS_GND
+/-5% 11 = 25 MHz +/-1% Near Memory
+3.3V_DUAL
RESERVED H9
RESERVED AE7 +3.3V_DUAL
RESERVED V5 +3.3V
RESERVED V4
V7 +3.3V_DUAL D21 D20
2
RESERVED
RESERVED V6 BAV99 BAV99
A20GATE
NV_A20GATE 21
F5 INTRUDER* R255 3 3
VBAT A20GATE/GPIO55 4.7K RN41
INTRUDER*
K2 Dummy +3.3V_DUAL
*
CLEAR CMOS CONTROL F3 EXTSMI* +/-5%
2
4
6
8
EXT_SMI*/GPIO32 EXTSMI* 21
R133 H4
*
1
CLR_CMOS(2-3) 51KOhm 1-2 CLEAR CMOS RI*/GPIO33 SPEAKER
C7
SPKR SPEAKER 27
* 13
5
7
+/-5% G4 PWRBTN#
2-3* NORMAL PWRBTN* PWRBTN# 21
F4 IO_PME*
SIO_PME*/GPIO31 IO_PME* 21
CLR_CMOS A4 SIO_KBRST* 2.7K
*DEFAULT KBRDRSTIN*/GPIO56 NV_KBRST* 21
Header_1X3 +/-5%
Jumper_2P_Blu 3 PULL BATT TO CLR TIME C2 SMB_MEM_SCL
3 SMB_CLK0 SMB_MEM_SCL 11
RTC_RST* SMB_MEM_SDA
2 2 K4 RTC_RST* SMB_DATA0
C1
SMB_SCL
SMB_MEM_SDA 11
1 1 R134 SMB_CLK1/MSMB_CLK
D2
SMB_SDA
SMB_SCL 19,20,26,28
J3 E2
*
0 28 SLP_S5* R273 All-PWROK H3
MEM_VLD
MCPVDD/HT_VLD
SMB_DATA1/MSMB_DATA
K3 VBAT R233
SMB_SDA 19,20,26,28
VBAT
*
*
+/-5% 28 All-PWROK 1K HTVDD_EN +3.3V_VBAT BUF_SIO_CLK_R 22 BUF_SIO_CLK
J4 MCPVDD/HT_EN B5 BUF_SIO_CLK 21
+/-5% R247 CPU_VLD BUF_SIO_CLK +/-5%
J1 CPU_VLD E1 1 TP42
*
0 CPU_EN SUS_CLK/GPIO34 CPU_THERM*

J2 CPUVDD_EN THERM*/GPIO59
C6 CPU_THERM* 21
+/-5% H5 C367 C422 C423 R232
RSTBTN* FP_RESET* 27
SLP_S5* H8
G8
SLP_S5*
SLP_S3*
SLP_S5*
SLP_S3*
28
21
* 10pF
50V, NPO, +/-5% * *
0.1uF 4.7uF 4.7K
+/-5%
+3.3V
*
SLP_S3*
H6 RSMRST# Dummy 6.3V, X5R, +/-10%
PWRGD_SB RSMRST# 26,28
PS_PWRGD
G2
E6 16V, X7R, +/-10%
FANRPM0/GPIO60
D6
FANCTL0/GPIO61
C5
B
PKG_TEST
R231 FANCTL1/GPIO62 B
L8 PKG_TEST AH7
*
1K THERM_SIC/GPIO48 CPU_SIC 9 R261

F8 TEST_MODE_EN THERM_SID/GPIO49
AF8 CPU_SID 9
+/-5% 0 VRM_EN
? VRM_EN 28,30
+/-5%
*
RSMRST# Dummy
R260
0
PWRGD_PS 27,28
R243 +/-5%
*
100K
*
+/-5%
NV suggest
+3.3V_DUAL +3.3V_DUAL
C279
* 100nF
*R198
4.7K
+80%~-20%
*R192
+/-5% 1K
SPI_SOCKET +/-5%
SPI_CS 1 8
SPI_DI CS VCC +3.3V_DUAL
2 DO HOLD 7
SPI_WP 3 6 SPI_CLK VBAT_SIO VBAT
21 SPI_WP WP CLK Q15
4 5 SPI_DO
GND DIO
D22 1
SPI_SOCKET_1 3 VBAT
Socket C A BATT_PWR_R 2 C161 C159 C166
BIOS_WP:programed by BIOS SPI ROM
SD103AW BAT54C
* 0.1uF
* 0.1uF
* 4.7uF
W25X80VDAIZ * R148
1K 16V, X7R, +/-10%
+/-1% 16V, X7R, +/-10% 6.3V, X5R, +/-10%
A BATT_PWR A
+
BAT
+3.3V_DUAL
VBAT Battery Holder

-
R269 R229 R227

* 1M * 4.7K * 4.7K
+/-5% +/-5% +/-5%
FOXCONN PCEG
Title
INTRUDER* SLP_S5*
SLP_S3*
MCP61_HDA_USB
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
PCI-E1_16X +3.3V
+12V +12V RN19
<PART_NAME> 10K Ohm
+/-5%
B1 +12V PRSNT1* A1
B2
B3
+12V
+12V
+12V
+12V
A2
A3 PE_TRST*
*1 2
3 4
B4 GND GND A4 5 6
SMB_SCL B5 A5 PE_TCK
18,20,26,28 SMB_SCL SMCLK TCK 7 8
SMB_SDA B6 A6 PE_TDI
18,20,26,28 SMB_SDA SMDAT TDI
B7 GND TDO A7
B8 A8 PE_TMS
+3.3V +3.3V TMS
PE_TRST* B9 TRST* +3.3V A9 +3.3V
D +3.3V_DUAL B10 +3.3V_AUX +3.3V A10 D
PE_WAKE* B11 A11 PE_RESET*
14 PE_WAKE* WAKE* PERST* PE_RESET* 14
B12 RSVD GND A12
PE0_OUT[15..0] B13 X1 CONNECTOR A13 PE0_REFCLK_V
14 PE0_OUT[15..0] GND REFCLK+ PE0_REFCLK 14
PE0_OUT*[15..0] 0 PE0_OUT0 C140 0.1uF PETP0 B14 A14 PE0_REFCLK*_V
PETP0 REFCLK- PE0_REFCLK* 14
**
14 PE0_OUT*[15..0] 0 PE0_OUT*0 16V, X7R, +/-10% PETN0 PE0_IN[15..0]
B15 PETN0 GND A15 PE0_IN[15..0] 14
0 PE0_IN*[15..0]
C144 0.1uF B16 GND PERP0 A16 PE0_IN0
PE0_IN*[15..0] 14
16V, X7R, +/-10% B17 PRSNT2* PERN0 A17 PE0_IN*0 0
14 PE0_PRSNTX1*
B18 GND GND A18
+12V
1 PE0_OUT1 C149 0.1uF PETP1 B19 A19 +3.3V_DUAL +3.3V +12V
PETP1 RSVD
**
1 PE0_OUT*1 16V, X7R, +/-10% PETN1 B20 PETN1 X4 CONNECTOR GND A20
C150 0.1uF B21 GND PERP1 A21 PE0_IN1 1
16V, X7R, +/-10% B22 GND PERN1 A22 PE0_IN*1 1 PCI-E1_1X
2 PE0_OUT2 C160 0.1uF PETP2 B23 PETP2 GND A23 B1 A1
** **
2 PE0_OUT*2 16V, X7R, +/-10% PETN2 12V PRSNT1#
B24 PETN2 GND A24 B2 12V 12V A2
C162 0.1uF B25 GND PERP2 A25 PE0_IN2 2 B3 A3
16V, X7R, +/-10% 2
RSVD 12V
B26 GND PERN2 A26 PE0_IN*2
B4 GND GND A4
3 PE0_OUT3 C169 0.1uF PETP3 B27 PETP3 GND A27 SMB_SCL B5 A5 PE_TCK_1
3 PE0_OUT*3 16V, X7R, +/-10% PETN3 SMB_SDA SMCLK JTAG2 PE_TDI_1
B28 PETN3 GND A28 B6 SMDAT JTAG3 A6
C171 0.1uF B29 GND PERP3 A29 PE0_IN3 3 B7 A7
16V, X7R, +/-10% 3
GND JTAG4 PE_TMS_1 +3.3V
B30 RSVD PERN3 A30 PE0_IN*3
B8 3.3V JTAG5 A8
B31 PRSNT2* GND A31 PE_TRST_1 B9 A9
14 PE0_PRSNTX4* JTAG1 3.3V
B32 GND RSVD A32 B10 3.3VAUX 3.3V A10
PE_WAKE* B11 A11 PE_RESET*
4 PE0_OUT4 C174 0.1uF PETP4 WAKE# PWRGD
B33 PETP4 RSVD A33
** ** ** **
4 PE0_OUT*4 16V, X7R, +/-10% PETN4 B34 PETN4 X8 CONNECTOR GND A34 KEY
16V, X7R, +/-10% B36 GND PERN4 A36 PE0_IN*4 4 B12 A12
5 PE0_OUT5 C181 0.1uF PETP5 C139 0.1uF RSVD_B12 GND
B37 PETP5 GND A37 B13 A13 PE1_REFCLK 14
**
5 PE0_OUT*5 16V, X7R, +/-10% PETN5 14 PE1_OUT 16V, X7R, +/-10% PE1_PETP0 GND REFCLK+
B38 PETN5 GND A38 B14 HSOP0 REFCLK- A14 PE1_REFCLK* 14
C183 0.1uF B39 GND PERP5 A39 PE0_IN5 5 C142 0.1uF PE1_PETN0 B15 A15
16V, X7R, +/-10% 5
14 PE1_OUT* 16V, X7R, +/-10% HSON0 GND
B40 GND PERN5 A40 PE0_IN*5
B16 GND HSIP0 A16 PE1_IN 14
6 PE0_OUT6 C187 0.1uF PETP6 B41 PETP6 GND A41 B17 A17 PE1_IN* 14
14 PE1_PRSNT* PRSNT2# HSIN0
6 PE0_OUT*6 16V, X7R, +/-10% PETN6 B42 PETN6 GND A42 B18 A18
C189 0.1uF 6
GND GND
B43 GND PERP6 A43 PE0_IN6
16V, X7R, +/-10% B44 GND PERN6 A44 PE0_IN*6 6

Slot-PCIE-1X
C 7 PE0_OUT7 C193 0.1uF PETP7 B45 PETP7 GND A45 C
7 PE0_OUT*7 16V, X7R, +/-10% PETN7 B46 PETN7 GND A46
14 PE0_PRSNTX8*
B49 GND GND A49
8 PE0_OUT8 C210 0.1uF PETP8 B50 PETP8 RSVD A50 RN18
** ** ** ** ** ** ** **
8 PE0_OUT*8 16V, X7R, +/-10% PETN8 B51 PETN8 X16 CONNECTOR GND A51 10K Ohm +3.3V
C216 0.1uF B52 GND PERP8 A52 PE0_IN8 8 +/-5%
9 PE0_OUT*9
9 PE0_OUT9 C219 0.1uF
16V, X7R, +/-10%
PETP9
PETN9
B54
B55
PETP9
PETN9
GND
GND
A54
A55
PE_TMS_1
PE_TRST_1
*1 2
C221 0.1uF 9 PE_TDI_1 3 4
B56 GND PERP9 A56 PE0_IN9
5 6
16V, X7R, +/-10% B57 GND PERN9 A57 PE0_IN*9 9 PE_TCK_1
10 PE0_OUT10 C223 0.1uF PETP10 7 8
B58 PETP10 GND A58
11 PE0_OUT11 C229 0.1uF PETP11 B62 PETP11 GND A62
16V, X7R, +/-10% B65 GND PERN11 A65 PE0_IN*1111




B 14 PE0_PRSNTX16* B
B82 RSVD GND A82
<PATH>
PLACE CAPS NEAR PEX CONNECTORS modify 8/18
+12V
C103 C106 C97

* 100nF
Dummy *
C101
+80%~-20% 100nF * 100nF
+80%~-20% 100nF
*
C126
* 100nF
+80%~-20% 100nF
*1uF
C102
*
C114
* C125
+80%~-20%
Dummy +80%~-20% +80%~-20% +80/-20%
4.7uF +3.3V_DUAL
16V, Y5V, +80%/-20%

EC29 C127 C116 C421
+3.3V
* 470uF
16V, +/-20% * 100nF
*
+80%~-20%
100nF
*
+80%~-20%
100nF
+80%~-20%
C212 C155 C195 C186 C170
A
* 100nF
*
C178
+80%~-20% 100nF *
100nF C123
*
+80%~-20% 100nF *
100nF C154
+80%~-20% 100nF
* * 4.7uF
* 1uF
16V, Y5V, +80%/-20% A
+80%~-20%
Dummy +80%~-20% +80%~-20%
Dummy
+80/-20%
modify 8/16
modify 8/18 FOXCONN PCEG

Title
PCI Express Slot x16 & X1
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
SLOT 2
SLOT 1
IDSEL23 IDSEL24
PCI2 PCI1
I135 +3.3V_DUAL I136 +3.3V_DUAL
PCI_AD[31..0] PCI124 PCI_AD[31..0] PCI124
16,26 PCI_AD[31..0]
V2.2 V2.2
0 A58
PCI_AD0
5V 32BIT A14 0 PCI_AD0
A58 5V 32BIT A14
AD0 3.3VAUX AD0 3.3VAUX
1 B58
PCI_AD1
B4 1 PCI_AD1
B58 B4
AD1 TDO AD1 TDO
2PCI_AD2
A57 B9 2 PCI_AD2
A57 B9
AD2 PRSNT1* AD2 PRSNT1*
3PCI_AD3
B56 B11 3 PCI_AD3
B56 B11
D AD3 PRSNT2* AD3 PRSNT2* D
4PCI_AD4
A55 A9 4 PCI_AD4
A55 A9
AD4 RSVD1 AD4 RSVD1
5PCI_AD5
B55 B10 5 PCI_AD5
B55 B10
AD5 RSVD2 AD5 RSVD2
6 A54
PCI_AD6
A11 6 PCI_AD6
A54 A11
AD6 RSVD3 AD6 RSVD3
7 B53
PCI_AD7
B14 7 PCI_AD7
B53 B14
AD7 RSVD5 AD7 RSVD5
8 B52
PCI_AD8
B2 8 PCI_AD8
B52 B2
AD8 TCK AD8 TCK
9 A49
PCI_AD9
A1 9 PCI_AD9
A49 A1
AD9 TRST* AD9 TRST*
10 B48
PCI_AD10
A3 10 PCI_AD10
B48 A3
AD10 TMS AD10 TMS
11 A47
PCI_AD11
A4 11 PCI_AD11
A47 A4
AD11 TDI AD11 TDI
12 B47
PCI_AD12 12 PCI_AD12
B47
AD12 AD12
13 A46
A46
AD13 AD13
14 B45
B45
AD14 AD14
15 A44
PCI_AD15
AD15
+12V 15 PCI_AD15
A44 AD15
+12V
16 A32
PCI_AD16
AD16
-12V 16 PCI_AD16
A32 AD16
-12V
17 B32
PCI_AD17
A2 17 PCI_AD17
B32 A2
AD17 +12V AD17 +12V
18 A31
PCI_AD18
B1 18 PCI_AD18
A31 B1
AD18 -12V AD18 -12V
19 B30
B30
AD19 AD19
20 A29
PCI_AD20
B5 20 PCI_AD20
A29 B5
AD20 +5V AD20 +5V
21 B29
PCI_AD21
B6 21 PCI_AD21
B29 B6
AD21 +5V AD21 +5V
22 A28
PCI_AD22
A5 22 PCI_AD22
A28 A5
AD22 +5V AD22 +5V
23 B27
PCI_AD23
A8 23 PCI_AD23
B27 A8
AD23 +5V AD23 +5V
24 A25
PCI_AD24
A10 24 PCI_AD24
A25 A10
AD24 +5V AD24 +5V
25 B24
PCI_AD25
B61 25 PCI_AD25
B24 B61
AD25 +5V AD25 +5V
26 A23
PCI_AD26
A16 26 PCI_AD26
A23 A16
AD26 +5V AD26 +5V
27 B23
PCI_AD27
B62 27 PCI_AD27
B23 B62
AD27 +5V AD27 +5V
R147 28 A22
PCI_AD28
A59 R144 28 PCI_AD28
A22 A59
*
*
AD28 +5V AD28 +5V
300 29 B21
PCI_AD29
AD29 +5V B59 +5V PCI_AD24 300 29 PCI_AD29

B21 AD29 +5V B59 +5V
16,26 PCI_AD23 +/-5% 30 +/-5% 30
A20
PCI_AD30
AD30 +5V A61 PCI_AD30

A20 AD30 +5V A61
31 B20
PCI_AD31
B19 31 PCI_AD31
B20 B19
AD31 +5V AD31 +5V
IDSEL23 A26 IDSEL +5V A62 IDSEL24 A26 IDSEL +5V A62
PCI_C/BE*[3..0] PCI_C/BE*[3..0]
16,26 PCI_C/BE*[3..0] 0 0
PCI_C/BE*0
A52 CBE0* +3.3V A21 PCI_C/BE*0
A52 CBE0* +3.3V A21
1 PCI_C/BE*1
B44 A27 1 PCI_C/BE*1
B44 A27
CBE1* +3.3V CBE1* +3.3V
2 PCI_C/BE*2
B33 A33
CBE2* +3.3V CBE2* +3.3V
3 PCI_C/BE*3
B26 A39
CBE3* +3.3V CBE3* +3.3V
+3.3V A45 +3.3V A45
PCI_INTW* A6 B43 PCI_INTX* A6 B43
16 PCI_INTW* INTA* +3.3V INTA* +3.3V
PCI_INTX* B7 B41 PCI_INTY* B7 B41
16 PCI_INTX* INTB* +3.3V INTB* +3.3V
C PCI_INTY* A7 B36 PCI_INTZ* A7 B36 C
16 PCI_INTY* INTC* +3.3V INTC* +3.3V
PCI_INTZ* B8 B31 +3.3V PCI_INTW* B8 B31 +3.3V
16,26 PCI_INTZ* INTD* +3.3V INTD* +3.3V
+3.3V B25 +3.3V B25
PCI_REQ*2 B18 B54 PCI_REQ*3 B18 B54
16 PCI_REQ*2 REQ* +3.3V 16 PCI_REQ*3 REQ* +3.3V
PCI_GNT*2 A17 GNT* +3.3V A53 PCI_GNT*3 A17 GNT* +3.3V A53
16 PCI_GNT*2 16 PCI_GNT*3
PCI_PME* A19 PCI_PME* A19
16,26 PCI_PME* PME* PME*
PCI_FRAME* A34 FRAME* GND A12 PCI_FRAME* A34 FRAME* GND A12
16,26 PCI_FRAME* PCI_TRDY* PCI_TRDY*
16,26 PCI_TRDY* A36 TRDY* GND A13 A36 TRDY* GND A13
PCI_STOP* A38 STOP* GND A18 PCI_STOP* A38 STOP* GND A18
16,26 PCI_STOP* PCI_IRDY* PCI_IRDY*
16,26 PCI_IRDY* B35 IRDY* GND A24 B35 IRDY* GND A24
PCI_DEVSEL* B37 DEVSEL* GND A30 PCI_DEVSEL* B37 DEVSEL* GND A30
16,26 PCI_DEVSEL* PCI_LOCK* PCI_LOCK*
B39 LOCK* GND A35 B39 LOCK* GND A35
PCI_PERR* B40 A37 PCI_PERR* B40 A37
16,26 PCI_PERR* PERR* GND PERR* GND
PCI_SERR* B42 A42 PCI_SERR* B42 A42
16,26 PCI_SERR* SERR* GND SERR* GND
PCI_PAR A43 PAR GND A48 PCI_PAR A43 PAR GND A48
16,26 PCI_PAR SMB_SDA SMB_SDA
18,19,26,28 SMB_SDA A41 SBO* GND A56 A41 SBO* GND A56
PCIRST_SLOT1* A15 RESET* GND B3 PCIRST_SLOT2* A15 RESET* GND B3
16 PCIRST_SLOT1* SMB_SCL 16 PCIRST_SLOT2* SMB_SCL
18,19,26,28 SMB_SCL A40 SDONE GND B12 A40 SDONE GND B12
GND B13 GND B13
PCI_REQ64A* A60 REQ64* GND B15 PCI_REQ64B* A60 REQ64* GND B15
PCI_ACK64* B60 ACK64* GND B17 PCI_ACK64* B60 ACK64* GND B17
PCI_CLKSLOT1 B16 CLOCK GND B22 PCI_CLKSLOT2 B16 CLOCK GND B22
16 PCI_CLKSLOT1 16 PCI_CLKSLOT2
GND B28 GND B28
KEY<A50> GND B34 KEY<A50> GND B34
KEY<A51> GND B38 KEY<A51> GND B38
KEY<B50> GND B46 KEY<B50> GND B46
KEY<B51> GND B49 KEY<B51> GND B49
GND B57 GND B57
PCI1 IDSEL= A23 , PCI_REQ#=2 , Routin=W/X/Y/Z PCI2 IDSEL= A24 , PCI_REQ#=3 , Routin=X/Y/Z/W
+3.3V +5V +5V

B B
EC39 C236 C165
1000uF 100nF 100nF
*
*
+/-20% +80%~-20% +80%~-20%
Dummy
*
+3.3V
C238
100nF
*
C192 +80%~-20%
****
PCI_REQ64A*R184 8.2K +/-5% 100nF

*
PCI_ACK64* R183 8.2K +/-5% +3.3V +80%~-20%

PCI_REQ64B*R182 8.2K +/-5% FOR EMI
R181 8.2K +/-5%
16,26 PCI_REQ*4
C245
RN21 100nF C383
*1
*
+80%~-20% 100nF
16 PCI_REQ*1 2
*
+80%~-20%
16 PCI_REQ*3 3 4
16 PCI_REQ*0 5 6
RN23 C213 C60
16 PCI_REQ*2 7 8
PCI_FRAME*
*1 2
100nF 100nF
*
PCI_IRDY* 8.2K +80%~-20% +80%~-20%

PCI_TRDY* 3 4 +/-5%
PCI_DEVSEL* 5 6 RN17
7 8
8.2K
16,26 PCI_INTZ*
16 PCI_INTX*
PCI_INTZ*
PCI_INTX*
*1 2 +3.3V
+/-5% PCI_INTY* 3 4
16 PCI_INTY* 5 6 EC38
PCI_INTW*
16 PCI_INTW* 7 8
*
RN25 8.2K PCI SLOT DECOUPLING

PCI_STOP*
PCI_LOCK*
*1 2
+/-5%
EC28 +5V 470uF
PCI_PERR* 3 4 1000uF 16V, +/-20%
PCI_SERR* 5 6 +12V +/-20% +5V
*
7 8 470uF C230 C360

8.2K 16V, +/-20% 100nF 100nF
*
+/-5% EC24 EC26 +80%~-20% +80%~-20%
Dummy
* 470uF
16V, +/-20%
* EC42
1000uF C104
+/-20%
Dummy C214 100nF
*
PCI_SERR*
*
A 100nF +80%~-20% A
16,26 PCI_SERR*
*
+80%~-20%
PCI_DEVSEL*
16,26 PCI_DEVSEL*
C172
PCI_IRDY* 100nF
16,26 PCI_IRDY* modify 8/16
* *
+80%~-20%
PCI_PERR* C285
16,26 PCI_PERR* place between PCIE 1X 1uF 100nF
*
Dummy +80%~-20%
+3.3V_DUAL C180 10V, Y5V, +80%/-20%
16,26 PCI_TRDY*
PCI_TRDY*
R38
FOXCONN PCEG
*
PCI_STOP* PCI_PME* 8.2K Title

16,26 PCI_STOP* 16,26 PCI_PME*
+/-5%
PCI Slot 12
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
Power On Strapping Options

Symbol value Description
1 Disabled.
JP1 Flashseg1_EN 0 Flash I/F Address Segment 1 (FFFE_0000h~FFFF_FFFFh, +5V
000F_0000h~000F_FFFFh) is enabled modify 8/16
1 FLH_SO1 is selected as the Serial Flash I/F SO pin.
JP2 SerFlh_SO_SEL C119 C91 C115
0 FLH_SO2 is selected as the Serial Flash I/F SO pin. * 100nF
+80%~-20% * 100nF
+80%~-20% * 100nF
+80%~-20%
JP3 CHIP_SEL -- Chip selection in configuration.

+3.3V
D The output buffers of PCIRST1#, PCIRST2#, PCIRST3#, PCIRST4# and D
1 PCIRST5# are open-drain.
JP4 BUF_SEL *R96
4.7K
0 The output buffers are push-pull. +5V +5V_STBY +/-5%
1 The default value of EC Index 15h / 16h / 17h is 00h

JP5 FAN_CTL_SEL CPU_THERMTRIP*
CPU_THERMTRIP* C E CPU_THERM_R
0 The default value of EC Index 15h / 16h / 17h is 40h L10 Q3
MMBT3904-7-F
1 The threshold voltage of VID is 2.0 / 0.8V
B
JP6 VID_ISEL 80 Ohm@100MHz
* R78
0 The threshold voltage of VID is 0.8 / 0.4V +5V C130
750
+/-1%
+5V *10uF
C87 C89
R102 6.3V, Y5V, +80%/-20%
* 100nF
*10uF
* 2.2K +80%~-20% +1.8V_SUS
+/-5%Dummy 6.3V, Y5V, +80%/-20%
HMGND
RN20 U12
35
99
67
4
*1 2
VCC
VCC
AVCC
VCCH
3 4
5 6 PD[0..7]
7 8 PD[0..7]
DCD1J 118 116 PD7
680 DCD1J RI1J DCD1# PD7 PD6
RI1J 119 RI1# PD6 115
+/-5% CTS1J 120 114 PD5 SPI_WP
CTS1J CTS1# PD5 SPI_WP
Note: DTR1J 121 113 PD4
DTR1J DTR1#/JP1 PD4
Parallel Port
RTS1J 122 112 PD3
RTS1J DSR1J RTS1#/JP2 PD3 PD2
If 75232 is connected, please use 680 ohm to 123 111
C
DSR1J TXD1 DSR1# PD2 PD1 R336
be the pull down resistor value. Since 124 110
Serial Port 1/2

TXD1 RXD1 SOUT1/JP3 PD1 PD0 GPIO_WP 1K B Q25
125 109
powered by 12V, 75232 has a very strong RXD1 DCD2J 126
SIN1 PD0
108 STBJ +-5% MMBT3904-7-F
DCD2J DCD2#/GP67 STB# STBJ
internal pull-up. It is hard to be pulled low. RI2J 127 107 AFDJ
AFDJ
E
RI2J CTS2J RI2#/GP66 AFD# ERRJ
(Please see specification for detail of power CTS2J 128 CTS2#/GP65 ERR# 106 ERRJ Dummy Dummy
DTR2J 1 105 INITJ
on strapping setting) DTR2J RTS2J DTR2#/JP4 INIT# SLINJ
INITJ
C
RTS2J 2 RTS2#/JP5 SLIN# 104 SLINJ C
DSR2J 3 103 ACKJ +3.3V_DUAL
DSR2J DSR2#/GP64 ACK# ACKJ
TXD2 5 102 BUSY
TXD2 SOUT2/JP6 BUSY BUSY
RXD2 6 101 PE
RXD2 SIN2/GP63 PE
SLCT 100 SLCT
PE
SLCT IR Connector
29 MIDI_IN/GP16/SO2
IT8716F-S/FX-L
+3.3V_DUAL
*R87
4.7K
25 +/-5%
JSAB1/GP22/SCK
Control
Power-on
24 78 R91
*
JSAB2/GP23/SI PWROK2/GP41 GPIO_WP 4.7K R90 Power Bottom in
77
*
SUSC#/GP53
SPI
20 76 +/-5% 10 R88
PS_ON#
*
FAN_CTL4/JSBB2/GP27 PSON#/GP42 +/-5% 10
21 FAN_CTL5/JSBB1/GP26 PANSWH#/GP43 75 PANSWHJ
R89 26 72 PWRBTN# C96 +/-5% +5V
PWRBTN#
*
0 CPU_THERM_R JSACY/GP21 PWRON#GP44 1uF

CPU_THERM*
Dummy 27 JSACX/GP20 SUSB#/GP45 71 SLP_S3*
*
+/-5% 28 10V, Y5V, +80%/-20% output to SB Near SIO (U22) IR
MIDI_OUT/GP17 C99
Dummy 1 1
CIRTX
modify 8/16 RESETCON#/CIRTX/GP15/CE_N
RSMRST#/CIRRX/GP55
30
85 CIRRX
VBAT
* 100nF
+80%~-20% IRRX 3 3
DENSELJ
DENSELJ
INDEXJ
51 DENSEL# MISC. IRTX/GP47 66 IRTX
IRRX
R79 10M
INTR 4 4
63 70 +/-5% IRTX 5
INDEXJ MOTEAJ INDEX# IRRX/GP46 COPENJ 5
MOTEAJ 52 MTRA# COPEN# 68 2
DRVBJ 55 79 1 Header_1X5_K2
DRVBJ DRVAJ ETS_CLK/DRVB# 3VSBSW#/GP40
DRVAJ 54 DRVA#
SCR I/F
MOTEBJ 53 84 EXTSMI*
MOTEBJ ETS_DAT/MTRB# PCIRST4#/SCRPSNT#/GP10 EXTSMI* Header_1X2
DIRJ 57 34
DIRJ DIR# PCIRST3#/SCRCLK/GP11
Floppy I/F
STEPJ 58 33
STEPJ WDATAJ STEP# PCIRST2#/SCRIO/GP12 GP13
WDATAJ 56 WDATA# PWROK1/SCRPFET#/GP13 32 GP13
WGATEJ 60 31
WGATEJ TK00J WGATE# PCIRST1#/SCRRST/GP14 +5V
TK00J 62 TRK0#
WPTJ 64 98 VIN0 +5V
WPTJ WPT# VIN0 VIN0
RDATAJ 61 97 VIN1
RDATAJ RDATA# VIN1 VIN1
SIDE1J VIN2
SIDE1J DSKCHGJ
59
65
HDSEL# VIN2 96
95 VIN3
VIN2
VIN3
*R103
4.7K R83
*
DSKCHGJ DSKCHG# VIN3/ATXPG VIN4 +/-5% CIRTX 10K
VIN4 94 VIN4
93 +/-5%
VIN5
Hardware Monitoring
VIN6 92
LRESETJ 37 91 Near CPU
LPCRST_SIO* LPC_DRQ0* LRESET# VIN7/PCIRSTIN# VREF
B LPC_DRQ0* 38 LDRQ# VREF 90 VREF B
SERIRQ 39 89 C108
LPC_SERIRQ SERIRQ TMPIN1 TMPIN1
LPC_FRAME* TMPIN2
LPC_FRAME*
LPC_AD0
LAD0
40
41
LFRAME#
LAD0
TMPIN2
TMPIN3/SO1
88
87
TMPIN2 * 1uF
10V, Y5V, +80%/-20% +5V +5V_STBY
LAD1 42 23
LPC_AD1 LAD2 LAD1 FAN_TAC5/JSBCX/GP24
LPC_AD2 43 LAD2 FAN_TAC4/JSBCY/GP25 22
LPC I/F
LAD3 44 12 FAN_CTL3
LPC_AD3 PCI_CLKSIO LAD3 FAN_CTL3/GP36 FAN_TAC3 FAN_CTL3
PCI_CLKSIO 47 PCICLK FAN_TAC3/GP37 11 FAN_TAC3
48 10 SIO_BEEP HMGND
Detect PCIRST5#/GP50 FAN_CTL2/GP51 SIO_BEEP
BUF_SIO_CLK IR/CIR
24MHz BUF_SIO_CLK IO_PME*
49
73
CLKIN FAN_TAC2/GP52 9
8 FAN_CTL1 1 2
IO_PME* PME#/GP54 FAN_CTL1 FAN_TAC1 FAN_CTL1 CIRRX
FAN_TAC1 7 FAN_TAC1 X 4
19 IRRX 5 6
SIO_KBRST* GP30/VID0 CIRTX
45 KRST#/GP62 GP31/VID1 18 7 8
A20GATE IRTX
KDAT
46
80
GA20 GP32/VID2 17
16
POWER ON SCHEME 9 X
KDAT KCLK KDAT/GP61 GP33/VID3 Header_2X5_K3K10
KCLK 81 KCLK/GP60 GP34/VID4 14
KB/MS
MDAT 82 13 VBAT_SIO Dummy

MDAT MCLK MDAT/GP57 GP35/VID5
MCLK 83 MCLK/GP56
69 VBAT
VBAT
36 C92
MCP61
VIDVCC +3.3V
GNDD
GNDD
GNDD
GNDD
GNDA
+5V * 1uF
10V, X7R, +/-10% SLP_S3#
Near IO PWBTN# SLP_S5#
*R74
15
50
74
117
86
4.7K
+/-5% L6
0805h11
1 2
PWRBTN#
SIO_KBRST* FB L0805 100 Ohm PWRON# PSIN
E C
Q1
NV_KBRST*
dummy
ATX
(72) (71) W83304 Power
MMBT3904-7-F
CP3
HMGND Supply
B
*R73
4.7K
1 2 PS_ON_OUT# PSON#
+5V +/-5% (7)
dummy IT8716F
A
PANSWHJ PS_ON_IN# A
*R76
4.7K +3.3V
Power button input PANSWH#
(75)
PSON#
(76) (6)
+/-5%
A20GATE E C
Q2 NV_A20GATE
MMBT3904-7-F
FOXCONN PCEG
B
R75
* 4.7K Title
+/-5%
SIO IT8716F
+3.3V C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
MH3
1 5
2 (NPTH) 6
3 7
MH
4
9
8
IDE_PDD[15..0] MH40x80_8
17 IDE_PDD[15..0]
PIDE
dummy
IDE_HDR
R317
*
10K
IDE_PDD7 7 7 IDE_PDD7
3 DD7 DD8 4 8 IDE_PDD8
+5V +/-5% 6 IDE_PDD6
5 DD6 DD9 6 9 IDE_PDD9
+3.3V +3.3V 5 IDE_PDD5
7 DD5 DD10 8 10IDE_PDD10 MH4 MH5
4 IDE_PDD4
9 10 11IDE_PDD11 1 5 1 5
D DD4 DD11 D
R318 R314 3 IDE_PDD3
11 12 12IDE_PDD12 2 6 2 6
*
*
DD3 DD12 (NPTH) (NPTH)
1K R312 8.2K 2 IDE_PDD2
13 14 13IDE_PDD13 3 7 3 7
*
DD2 DD13
+/-5% 4.7K Dummy +/-5% 1 IDE_PDD1
15 DD1 DD14 16 14IDE_PDD14
+/-5% 0 IDE_PDD0
17 DD0 DD15 18 15IDE_PDD15 MH MH
4
9
8
4
9
8
E C SLOT_IDERST# 1 RESET*
16 PCIRST_IDE* Q29 CSEL 28 MH40x80_8 MH40x80_8
MMBT3904-7-F
C485 IDE_DREQ_P 21
17 IDE_DREQ_P IDE_IOW_P* DMARQ
*33pF 23
B
17 IDE_IOW_P* DIOW*
+/-5% IDE_IOR_P* 25 34 CBLE_DET_P dummy dummy
17 IDE_IOR_P* IDE_IORDY_P DIOR* PDIAG* CBLE_DET_P 17
Dummy 27 36 MH6
17 IDE_IORDY_P IDE_DACK_P* IORDY DA2
17 IDE_DACK_P* 29 DMACK* CS1* 38 1 5
R319 IDE_INTR_P 31 R315 2 6
17 IDE_INTR_P
*
INTRQ (NPTH)
4.7K IDE_ADDR_P1 33 2 15K 3 7
+3.3V 17 IDE_ADDR_P1 IDE_ADDR_P0 DA1 GND
+/-5% 35 19 +/-5%
*
17 IDE_ADDR_P0 DA0 GND

IDE_CS1_P* 37 22 MH
4
9
8
17 IDE_CS1_P* CS0* GND
P_HDLED* 39 24
27 P_HDLED* DASP* GND
GND 26 MH40x80_8
R311 R313 30
*
GND
5.6K 10K 32 NC GND 40
+/-5% +/-5% dummy
I267 MH2 MH1
1 5 1 5
IDE_CS3_P* 2 6 2 6
17 IDE_CS3_P* (NPTH) (NPTH)
3 7 3 7
IDE_ADDR_P2
17 IDE_ADDR_P2 MH MH
4
9
8
4
9
8
MH40x80_8 A MH40x80_8 A
dummy dummy
+3.3V
R316
* 10K
C +/-5% C
P_HDLED*
27 P_HDLED*
+5V
+5V_DUAL
L1
2
4
6
8
F1
B B
KEYBRD_PWR1 KEYBRD_PWR2 RN16
* 1 2
Fuse 1.5A C28

1K
*R77
1K
FB 30Ohm
* 100nF
+/-5%
+/-5%
*
+80%~-20%
FLOPPY
1
3
5
7
RN12
PS2 KB / MS
2
4
6
8
KB/MS
* 13
5
7
FLOPPY
SIO_FDD_DRVDEN0 2 1
R57 21 DENSELJ 2 1
2.7K KEYBOARD (PURPLE) 4
*
SIO_KBDATA +/-5% SIO_KBDATA_FB 4

21 KDAT 1 DATA 6 5
6 6 5 5
2 NC
SIO_FDD_INDEX* 8 7
21 INDEXJ SIO_FDD_MTR0* 8 7
R56 0 3 GND 4 3
21 MOTEAJ 10 10 9 9
4 PWR 12 11
*
SIO_KBCLOCK +/-5% SIO_KBCLOCK_FB 21 DRVBJ SIO_FDD_DS0* 12 11

21 KCLK 5 CLK
21 DRVAJ 14 14 13 13
6 NC 2 1
MOTEBJ 16 15
21 MOTEBJ SIO_FDD_DIR* 16 15
1413
0 21 DIRJ 18 18 17 17
SIO_FDD_STEP* 20 19
+/-5% SHLD 21 STEPJ SIO_FDD_WDATA* 20 19
SHLD 21 WDATAJ 22 22 21 21
15 SIO_FDD_WGATE* 24 23
SHLD 21 WGATEJ SIO_FDD_TRK0* 24 23
SHLD 21 TK00J 26 26 25 25
SIO_FDD_WRTPRT* 28 27
R55
1716
SHLD 21 WPTJ SIO_FDD_RDATA* 28 27

MOUSE (GREEN) 30 29
*
SIO_MSDATA SIO_MSDATA_FB 21 RDATAJ SIO_FDD_HDSEL* 30 29

21 MDAT 7 DATA 21 SIDE1J 32 32 31 31
8
12 11
SIO_FDD_DSKCHG* 34 33
NC 21 DSKCHGJ 34 33
R54 0 9 GND
10 9
10 Header_2X17_K3
*
PWR
SIO_MSCLOCK +/-5% SIO_MSCLOCK_FB 11
21 MCLK CLK
12 NC 8 7
0 *
+/-5% I55
PS2
CN3
220pF
A A
50V, NPO, +/-10%
FOXCONN PCEG
Title
IDE / Floppy / PS2
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
+5V
A
RN5 D12
SIO_LPT_ALF*
SIO_LPT_STROBE*
*1 2
SIO_LPT_ALF_R*
SIO_LPT_STROBE_R*
LS4148-F
SIO_LPT_INIT* 3 4 SIO_LPT_INIT_R*
C
SIO_LPT_SLCTIN* 5 6 SIO_LPT_SLCTIN_R* PRN_VDD
7 8
22 RN13 RN7
+/-5%
8
6
4
2
8
6
4
2
RN8
7 8
7
5
3
1
7
5
3
1
*
*
5 6
* 3 4 2.2K 2.2K
D 21 PD[0..7] 1 2 +/-5% +/-5% D
0 PD3 22 SIO_LPT_PD0_R
1 PD2 +/-5% SIO_LPT_PD1_R
2 PD1 SIO_LPT_PD2_R Ver2 fix
3 PD0 SIO_LPT_PD3_R
RN6
4
5
PD4
PD5
*1 2
SIO_LPT_PD4_R
SIO_LPT_PD5_R
6 PD6 3 4 SIO_LPT_PD6_R
7 PD7 5 6 SIO_LPT_PD7_R
7 8
22
+/-5% PRN_VDD
R50
* 2.2K
+/-5% RN4
0
PARALLEL PORT
8
6
4
2
1
2
7
5
3
1
3
*
2.2K PRT
SIO_LPT_STROBE* +/-5% SIO_LPT_STROBE_R*
21 STBJ
1
SIO_LPT_ALF* SIO_LPT_ALF_R* 14
21 AFDJ R48 2
*
SIO_LPT_ERR* 22 SIO_LPT_ERR 15
21 ERRJ +/-5% 3
SIO_LPT_INIT* SIO_LPT_INIT_R* 16
21 INITJ
4
SIO_LPT_SLCTIN* SIO_LPT_SLCTIN_R* 17
21 SLINJ PRN_VDD 5
18
6
RN14 19
C 7 28 C
2
4
6
8
20 27
8 26
* 13
5
7
21
9
RN3 2.2K 22
21 ACKJ
SIO_LPT_ACK*
SIO_LPT_BUSY
*1 2
+/-5% 10
23
21 BUSY SIO_LPT_PE 3 4
21 PE 5 6 11
SIO_LPT_SLCT 24
21 SLCT 7 8
12
22 25
+/-5% 13
+12V CONN - PrinterPort

A
-12V
D7
* * * *
C
LS4148-F
C95
LS4148-F
* C34
220pF
100nF
SERIAL PORT
C
+80%~-20% D13
*
+5V
A
C36
100nF
U7 +80%~-20%
GD75232
*
COM1 CN5 220pF CN7 220pF 220pF CN6 CN4 220pF

11
+12V_COM1 VDD+ VDD- 10-12V_COM 50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
19 RY1* RA1 2 DCD1 1
21 DCD1J RY2* RA2 DSR1
21 DSR1J 18 3 6
17 RY3* RA3 4 RXD1* 2
21 RXD1 DA1 DY1* RTS1
21 RTS1J 16 5 7
15 DA2 DY2* 6 TXD1* 3
21 TXD1 RY4* RA4 CTS1
21 CTS1J 14 7 8
13 DA3 DY3* 8 DTR1 4
21 DTR1J RY5* RA5 RI1
B 21 RI1J 12 9 9 B
20 VCC GND 11 5
C67
I76
* 100nF
+80%~-20%
10
CONN-COM PORT
CN2 CN1
220pF 220pF
50V, NPO, +/-10%
* * 50V, NPO, +/-10%
C39 C94
100nF 100nF
+80%~-20% +80%~-20% SERIAL PORT
*
+5V
@COM2
U11 @COM2
GD75232
+12V_COM1 VDD+ VDD- 10-12V_COM

19 RY1* RA1 2 DCD2 COM2
21 DCD2J RY2* RA2 DSR2 DCD2 RXD2*
21 DSR2J 18 3 1 2
17 RY3* RA3 4 RXD2* TXD2* 3 4 DTR2
21 RXD2 DA1 DY1* RTS2 DSR2
21 RTS2J 16 5 5 6
15 DA2 DY2* 6 TXD2* RTS2 7 8 CTS2
21 TXD2 RY4* RA4 CTS2 RI2
21 CTS2J 14 7 9
13 DA3 DY3* 8 DTR2
21 DTR2J RY5* RA5 RI2 Header_2X5_K10
21 RI2J 12 9
20 VCC GND 11
C68 @COM2
I76
* 100nF
+80%~-20%
A A
CN9 CN8
220pF 220pF
@COM2 50V, NPO, +/-10%
@COM2 * * 50V, NPO, +/-10%
@COM2 @COM2
modify 8/20 FOXCONN PCEG

Title
Parallel / Gamr Port
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
+V_CPU +1.8V_SUS +3.3V +5V +12V
R117
*10K
*R108 *R106 *R104 *R101
Voltage Monitor +/-1% 49.9
+/-1%
10K
+/-1%
6.8K
+/-1%
30K
+/-1%
21 VIN0
21 VIN1
D 21 VIN2 D
21 VIN3
21 VIN4
New FAN Header Definition
CPU FAN pin1. GND
pin2. +12V
R111
* 10K *R107
10K *R105
10K
pin3. Sense
pin4. Control
+/-1% +/-1% +/-1%
Dummy
HMGND HMGND HMGND +5V
C128 C124 C120 C118 C117

* 100nF
*
100nF 100nF
* 100nF
* * 100nF *R206
4.7K
+80%~-20% Dummy
Dummy +80%~-20% Dummy
+80%~-20% Dummy
+80%~-20% +80%~-20% +/-5% +12V
+12V
R214 C341
21 FAN_CTL1
100
+/-5% R218 * 100nF
+80%~-20%
C
4.7K
* +/-5%
HMGND Header_1X4 FAN4P LS4148-F
D17
4 R216
A
CMD
TACH 3CPUFAN-P3 27KOhm
FAN_TAC1 21
*
2CPUFAN-P2 +/-5% 1
Thermal Controller +12V
GND 1
C358 C340 C299
R213
22K
CPU_FAN * 4.7uF
* 100nF
16V, Y5V, +80%~-20%
Dummy +80%/-20% * 470pF
2
+/-5%
21 VREF
C C
C107
0.1uF
* *R100
30K
50V, X7R, +/-10%
16V, X7R, +/-10% +/-1%
Dummy Dummy
HMGND CP5 dummy
C113 2 1
21 TMPIN1
* 3.3nF
+/-10%
CPU_THERMDA 9
SYSTEM
CP6 dummy
2 1 CPU_THERMDC 9 +5V
FAN
HMGND
*R122
4.7K
+/-5% +12V
+12V
R125 C98
21 FAN_CTL3
100
+/-5% R115 * 100nF
+80%~-20%
C
21 VREF 4.7K
*
*R95
10K Header_1X4 FAN4P LS4148-F
D15
+/-5%
+/-1%
4 R118
A
CMD
TACH 3SYSFAN-P3 27KOhm
FAN_TAC3 21
*
21 TMPIN2 +12V 2SYSFAN-P2 +/-5% 1
1 R120
GND
C109
* C131 C141 22K
0.1uF
16V, X7R, +/-10% * T RT1
10KOhm
SYS_FAN * 4.7uF
* 470pF
16V, Y5V, +80%/-20%
2
+/-5%
+/-1%
Dummy
50V, X7R, +/-10%
B B
HMGND
A A
FOXCONN PCEG
Title
Need to check GPIO default Hardware Monitor / Over Volt

value at power-on . Size Document Number Rev
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
BACK PANEL LAN/USB -> Near Connector

Connect to rear LAN/USB port
+/-5%
0
D 18
18
USB_6+
USB_6-
USB_6+
USB_6-
2
4
* 13 USB_6_FB+
USB_6_FB-
USB_6_FB+
USB_6_FB-
26
26
D
USB_1+ 6 5 USB_1_FB+ USB_1_FB+ 26
18 USB_1+
USB_1- 8 7 USB_1_FB- USB_1_FB- 26
18 USB_1-
RN15
REAR_PWR 26
PWR SHOULD BE 75MIL MIN
5V_DUAL_USB_1PLACE NEAR CONN REAR_PWR
F3
PLACE NEAR CONN R39 C29 C25
REAR_PWR USB_OC0*
* 5.1KOhm
+/-1%
USB_OC0* 18 * 1uF
* 100nF
10V, Y5V, +80%/-20% +80%~-20%
Fuse 2.6A EC18 R40 Dummy
1000uF C32 C21 * 10K USB_OC3*
USB_OC3* 18
* * 100nF
* 100nF +/-5%
Dummy
EMI CAPS U2
USB_0_FB+ 1 6 USB_0_FB-
Header_1X3 I/O1 I/O4
C C
USB_PWR2(1-2) 2 5 REAR_PWR
REF1 REF2
3 3 +5V_STBY
2 5V_DUAL_USB_1 USB_7_FB+ 3 4 USB_7_FB-
2 I/O2 I/O3
10
11
1 1 +5V
USB
USB_PWR2 Jumper_2P_Blu IP4220CZ6 Dummy
8
USB_0_FB+ 7
USB_0_FB- 6
TOP
REAR_PWR 5
+/-5%
0
18
18
USB_0+
USB_0-
USBP0P-1394
USBP0N-1394
2
4
* 13 4
BOTTOM
USBP1P-1394 6 5 USB_7_FB+ 3
18 USB_7+
USBP1N-1394 8 7
18 USB_7-
USB_7_FB- 2
RN1
1
CONN-USBx2
12
5V_DUAL_USB
B FRONT PANEL USB Header_1X3 USBPWR_FNTPNL B

*
USB_PWR1(1-2)
F4 USB_OC1* 3 +5V_STBY C407 C417
USB_OC1* 18 3
Fuse 2.6A 2
1
2
1
5V_DUAL_USB
+5V
f_usb2 * 10uF
* 100nF
+80%~-20%
R274 Dummy
USBPWR_FNTPNL 5.1KOhm USB_OC2* USB_PWR1 Jumper_2P_Blu Dummy
USB_OC2* 18
+/-1%
C378 C386 EC48
f_usb1 * 10uF
* 100nF * 1000uF *R275
10K
6.3V, Y5V, +80%/-20%
+80%~-20% +/-20% +/-5%
Dummy
F_USB2
6.3V, Y5V, +80%/-20% 1 2
USB_FP_5- 3 4 USB_FP_3-
USB_FP_5+ 5 6 USB_FP_3+
F_USB1 7 8
1 2 X 10
USB_FP_4- 3 4 USB_FP_2-
USB_FP_4+ 5 6 USB_FP_2+ Header_2X5_K9
7 8
10 modify 9/13
X
U18
Header_2X5_K9 U19
USB_FP_4- 1 6 USB_FP_4+ Dummy
I/O1 I/O4 USB_FP_5- USB_FP_5+
1 I/O1 I/O4 6
modify 9/13 2 5 USBPWR_FNTPNL
REF1 REF2 USBPWR_FNTPNL
2 REF1 REF2 5
USB_FP_2- 3 4 USB_FP_2+
I/O2 I/O3 USB_FP_3- USB_FP_3+
3 I/O2 I/O3 4
Dummy
IP4220CZ6
IP4220CZ6
A modify 9/13 A
+/-5%
modify 9/14 0
+/-5%
18 USB_2+
USB_2+
USB_2-
2
4
* 13 USB_FP_2+
USB_FP_2-
0
18 USB_2-
18 USB_4+
USB_4+
USB_4-
6
8
5
7
USB_FP_4+
USB_FP_4- 18 USB_3-
USB_3-
USB_3+
2
4
* 13 USB_FP_3-
USB_FP_3+
18 USB_4-
modify 9/13
18
18
USB_3+
USB_5-
USB_5-
USB_5+
6 5 USB_FP_5-
USB_FP_5+
FOXCONN PCEG
RN47 18 USB_5+ 8 7
Title
RN48 USB Connector
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
R27
0 @AC131 VDD33
18,28 RSMRST# VDD33 +3.3V_DUAL
*
+/-5%
R28
LAN EEPROM
*
100K PHY_RST R288 stuff 10K
R350for 93C56 VDD33
+3.3V_DUAL
+/-5% +5V Dummy 10K
Dummy C18 C15 +/-5% U25
*
*
10uF 100nF
+80%~-20% * L_X1 LAN_EECS
LAN_EESK
1 CS VCC 8
*
C553
Dummy
*R355 2 SK NC 7 100nF
10V, Y5V, +80%/-20%

1K LAN_X2 LAN_EEDI 3 6 +80%~-20%
Dummy +/-5% LAN_EEDO DI ORG
4 DO GND 5
PWR_LAN C19
LAN_LINK_UP
100nF R352 @8100C
LINK_100_C
*
+80%~-20% LAN_ISO 5.6K LAN_RSET AT93C46DN-SH-T
*
@8100C +/-1% R349 VDD33 @8100C
R177 use 3.6k for 3.3v Voltage. 5.6k for 5v voltage
*
+3.3V_DUAL
AD0
AD1
R348 3.6K
* 15K @8100C +/-1% DVDD
@AC131 +/-5%
D TX_EN 14 D
TX_CLK
RX_ER
14
14
*R35
1.5K
@8100C
+3.3V_DUAL PWR_LAN +/-5%
TX_EN
@8100C
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
U24
EC59 MDIO
*R46
RXCLK_U
* 100uF 0 @AC131 AVDDL
EESK
AUX/EEDI
EECS
LWAKE
RSET
NC26
NC27
XTAL2
XTAL1
NC25
NC24
LED0
NC23
LED1
LED2
NC22
NC21
NC20
EEDO
VDD33
AD0
AD1
GND
GND
GND
GND
+/-20% +/-5%
RXDV_U
RN2
RX_ER
*1
RX0
RX1
RX0 +/-5% RX_D0 14 MX0+ 1 102 AD2
2 TX+ AD2
TXC
RX1 0 Ohm RX_D1 14 MX0- 2 101
@AC131 RX2 3 4 TX- GND
5 6 RX_D2 14 3 AVDD33 GND 100
RX3 RX_D3 14 4 99
7 8 MX1+ GND VDD25 AD3
24
23
22
21
20
19
18
17
5 98
**
U1 RXDV_U R44 0
R45 +/-5% MX1- RX+ AD3 AD4
RX_DV 14 6 RX- AD4 97
RXCLK_U @AC1310 7 96 AD5
RXDV
RXD0/PHY0
TXEN
TXC
OVDD2
RXER
RXC
RXD1/ANEN
RX_CLK 14 AVDD33 AD5
+/-5%
@AC131 CTRL25 8 95 AD6
C41 CTRL25 AD6
9 NC1 VDD33 94
AD7
GND 33
* 10pF
@AC131
50V, NPO, +/-5%
10
11
NC2
NC3
AD7
CBEB0
93
92 CBEJ0
Dummy V_12P 12 91
TXD0 RX2 AVDD25 GND AD8
14 TX_D0 25 TXD0 RXD2/F100 16 13 NC4 AD8 90
14 89 AD9
RTL8100C-LF
TXD1 RX3 NC5 AD9
14 TX_D1 26 TXD1 RXD3/ISOLATE 15 15 NC6 NC19 88
TXC 16 87 AD10
TXD2 MDC NC7 AD10 AD11
14 TX_D2 27 TXD2 MDC 14 MII_MDC 14 17 GND AD11 86
C551 18 85 AD12
TXD3 MDIO NC8 AD12
14 TX_D3 28 TXD3 MDIO 13 MII_MDIO 14 * 10pF
50V, NPO, +/-5%
19
20
NC9
AVDD33(REG)
VDD33
AD13
84
83 AD13
COL LINK_100_C Dummy AD14
14 MII_COL 29 COL/ENGYDET AC131KMLG LED1 12 21
22
GND AD14 82
81
CRS LAN_LINK_UP LAN_ISO NC10 GND
14 MII_CRS 30 CRS/STANDBY LED2 11 23 ISOLATEB GND 80
24 79 AD15
PHY_RST NC11 AD15
PWR_LAN 31 REGIN RESET 10 16,20 PCI_INTZ* 25 INTAB VDD25 78
26 77 CBEJ1
VDD33 CBEB1
AVDD_FE 32 REGOUT OVDD1 9 PWR_LAN 16 PCIRST_SLOT3* 27 PCIRSTB PAR 76 PCI_PAR 16,20
C14 C31 28 75 R351
PCI_SERR* 16,20
**
2.2uF C40 2.2uF 16 PCI_CLK_LAN PCICLK SERRB 0
C
16 PCI_GNT*4 29 GNTB NC18 74 Dummy SMB_SDA 18,19,20,28 C
C17 C13
* 100nF
* 30 73 R353
+/-5%
XTALO
16,20 PCI_REQ*4 REQB NC17

RDAC
XTALI
AVDD
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

* * 100nF
* 100nF +80%~-20% 31 72 0
Dummy
RD+
SMB_SCL 18,19,20,28
TD+
16,20 PCI_PME* PMEB NC16

RD-
TD-
+80%~-20% +80%~-20% 32 71 +/-5%

AD31 VDD25 VDD33
33 AD31 PERRB 70 PCI_PERR* 16,20
AD30 34 69 PCI_STOP* 16,20
1
AD30 STOPB
@AC131 35 GND DEVSELB 68 PCI_DEVSEL* 16,20
@AC131 AD29 36 67
@AC131 @AC131 AD29 TRDYB PCI_TRDY* 16,20
AD28 37 66
R23 AD28 GND
38 65
FRAMEB
1.24K GND CLKRUNB
CBEB3
CBEB2
VDD33
VDD25
VDD33
IRDYB
IDSEL
NC12
NC13
NC14
NC15
+/-1%
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
GND
GND
@AC131
LXO
MX0+
MX1+
MX0-
MX1-
place near XTAL FB2 AVDD_FE

LXI
@AC131
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
@AC131
R24 *
*
L_X1 C5 AD[31..0]
14 LAN_X1 PCI_AD[31..0] 16,20
LAN_X2 2.2uF C6 FB 600 Ohm
MX0+ CBEJ[3..0]
0 * * 100nF Dummy PCI_C/BE*[3..0] 16,20
16V, Y5V, +80%/-20%
MX0- +80%~-20%
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
1 2
+/-5%
CBEJ3
CBEJ2
MX1- @8100C
MX1+ SHORT1
short pad
PCI_IRDY* 16,20
PCI_FRAME* 16,20
Dummy R354
@AC131 PCI_AD25 100 LAN_IDSEL
L_X1 +/-5%
*
R25 LINK_1000
*
LAN_X2 470KOhm
Dummy LAN_LINK_UP @8100C
+/-1% LINK_100_C
X1
1 2 Dummy VDD33
C62 C63 C56
@AC131
*
C7XTAL-25MHz C8
33pF 33pF
* *
Dummy*
Dummy*
100nF 100nF 100nF
C549
DVDD
V_12P
+/-5%
Dummy +/-5%
Dummy Dummy 10nF
E
@AC131 25V, X7R, +/-10% C531
* CTRL25 B Q30
* 100nF
****
B BCP69T1G B
C548 R328 49.9 +/-1% @AC131 MX0+ +80%~-20%
10nF R326 49.9 +/-1% @AC131 MX0-
R329
25V, X7R, +/-10% 49.9 +/-1% MX1+
4
C
*
+3.3V_DUAL R327 49.9 +/-1% MX1- Place at pin 24,32,45,54,64,78,99,110,116
@8100C +/-20% C532 @8100C
* * *
NIC_USB C530 100nF C454 C529 C168 C105 C528 C33 C445 C100
100uF10uF
+3.3V_DUAL * R62
330 * R59
330 EC63
+80%~-20%
* 100nF
* 100nF
*
100nF
*
100nF 100nF
* 100nF
*100nF
*100nF
+80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20% +80%~-20% *
+/-5% +/-5%
27 1- MDIO+ & MDIO- pairs should be
R390 LINK_1000 22 28 @8100C @8100C @8100C
* 100-ohm differential impedance.
GRN_LED
YLW_LED
0 LINK_100_C 21 29 Route equal length and

+/-5% @8100C @8100C @8100C @8100C @8100C @8100C @8100C @8100C
USB-2
USB-1
30 symmetrically. Separate every

pairs. AVDDL VDD33
9 1 REALUSB_PWR REAR_PWR 25 Place at pin 3,7,16,20
@AC131 MX0+ 10 5
C42 C65 MX0- 11 U20
RJ45-MJ2
* 470pF
* *
C64
1uF MX1+
MX1-
10V, Y5V, +80%/-20%
12
13
2
6
USB_6_FB-
USB_1_FB-
USB_6_FB-
USB_1_FB-
25
25
MX0- 1 1 8 8 MX0-
*C541*
C539
100nF
*
C546
100nF
C536
*
100nF
C543
*
100nF
C534
*
100nF
*
C540
100nF
100nF 14 MX0+ 2 7 MX0+ +80%~-20%
+80%~-20%
+80%~-20%
+80%~-20%
+80%~-20% +80%~-20%
USB_6_FB+ 2 7 10uF
15 3 USB_6_FB+ 25
16 7 USB_1_FB+ USB_1_FB+ 25 MX1- 3 6 MX1- 10V, Y5V, +80%/-20%
3 6
@AC131 17
@AC131 @AC131 18 4 MX1+ 4 5 MX1+
4 5 @8100C@8100C @8100C @8100C @8100C @8100C @8100C
8
SLVU2.8-4.TBT VDD33
GRN_LED
Place at pin 26,41,56,71,84,94,107

*
R67 330 +/-5% 20 23 dummy

+3.3V_DUAL
LAN_LINK_UP 19 24 C537 C545 C547 C535 C538 C533 C542 C544
C527C526 R68
25
26
* 100nF
* 100nF
+80%~-20%
+80%~-20% *
100nF
+80%~-20% *
100nF 100nF
+80%~-20% * 100nF
+80%~-20% * 100nF
+80%~-20% *
1uF
+80%~-20% *
16V, Y5V, +80/-20%
**
100nF
100nF 0
*
+/-5%
Dummy
Dummy CONN-USBx2_RJ45
C550 @8100C @8100C @8100C @8100C @8100C @8100C @8100C @8100C
A A
#NIC_USB1#NIC_USB2
*
**
U10 R389 49.9 +/-1% @8100C MX0+

NIC_USB1 10nF R330 49.9 +/-1% @8100C MX0-
USB_6_FB- 1 6 USB_6_FB+ 25V, X7R, +/-10%
I/O1 I/O4 NIC_USB2 @8100C
2 5 REAR_PWR
REF1 REF2
USB_1_FB- 3 4 USB_1_FB+ Place near Lan connector
I/O2 I/O3
@AC131
@8100C FOXCONN PCEG
Dummy
IP4220CZ6 Title
LAN
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
+5V -12V +3.3V +3.3V +5V +12V +5V_STBY

+5V_STBY
1 +5V +3.3V
R300 PWR1
22K Header_2x12
+/-5% 13 1
+3.3V3 +3.3V1
R302 2
14
15
-12V +3.3V2 2
3 *R296
10K *R284
10K
* *
0 GND4 GND1 +/-5% +/-5%
D 28 PS_OUT# 16 PSON +5V1 4 D
+/-5% 17 5
R301 C453 GND5 GND2
18 GND6 +5V2 6
21,28 PS_ON#
0
+/-5% * 100nF
+80%~-20%
19
20
GND7 GND3
RSVD PWR0K
7
8 E C PWRGD_PS PWRGD_PS 18,28
21 9 Q24
+5V3 +5V_AUX MMBT3904-7-F
Dummy 22 +5V4 +12V_1 10
23 11 C448
B
+5V5 +12V_2
24 GND8 +3.3V4 12
C461 C460 * 1uF
10V, Y5V, +80%/-20%
* 100nF
*
+80%~-20%
100nF
+80%~-20% *R279
10K
+/-5%
R289
GP13 0
Dummy PWRGD_PS
21 GP13
*
+/-5%
+3.3V
+5V
+5V_STBY
*R186
10K
+/-5%
SATA_HDLED* *R210
10K
+/-5%
Q19
SATA_HDLED* 2 SWITCH_ON*
17 SATA_HDLED* PANSWHJ 21
C 3 BAT54A P1 C294 C
P_HDLED*
22 P_HDLED* 1
* 100nF
+80%~-20%
* C249
Dummy 470pF
50V, X7R, +/-10%
+5V_STBY
+3.3V_DUAL
*R266
300
R189
330 *R212
390 Ohm
+/-5% +-5% +/-5% Dummy
R211 +5V +3.3V Dummy
* 10K
+/-5% R187
Dummy 330
R217 +-5%
*
33 FP_RESET*_FP R188 330
18 FP_RESET* +/-5% FP1
+-5% FP_1 1 2 SLED SLED 28
C295 P1 3 4 PLED PLED 28
* 100nF
+80%~-20% FP_RESET*_FP
5
7
6
8
SWITCH_ON*
+5V +3.3V +12V 9 X

C376 Header_2X5_K10
100nF EC56
EC25
*
+80%~-20% 1000uF
*
+/-20%
*
C458
100nF 470uF
B 16V, +/-20% B
*
+80%~-20% C224 C462

100nF Dummy 100nF
*
C463 +80%~-20% +80%~-20%

*
100nF
*
+80%~-20%
C459 -12V
100nF
C
*
+80%~-20% C457 R130 +5V

*
100nF 2.2K B Q14 BUZ

21 SIO_BEEP MMBT3904-7-F
*
+80%~-20% +/-5% + Dummy BAT1_1

Dummy
E
Dummy BUZZER
-
LITHIUM BATT
+5V Buzzer
CR2032
Battery
R139 +5V
* 100 SPEAKER
+/-5% 1
**
10K R132 1
Dummy +3.3V
+/-5% Dummy RN22 3 3
18 SPEAKER
SPEAKER 10K
+/-5%
R127
*1 2
SPEAK 4 4
3 4 C152 Header_1X4_K2
5 6
* 1nF
C
R123 7 8 50V, X7R, +/-10%

*
2.2K B Q13 100 Ohm Dummy

+/-5% MMBT3904-7-F +/-5%
E
A A
FOXCONN PCEG
Title
PWR Connector / Front Panel / VBAT
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
+5V_STBY
+5V_DUAL
R242 +12V +5V_STBY +5V +3.3V +3.3V
+3.3V C374 2.2
* 4.7uF
A
+80/-20% +/-5%
C384 D18 C375
*R252
4.7K * 100nF
+80%~-20%
D19
LS4148-F +9V_SB C466 C465 EC55 * 100nF
+80%~-20%
*
C450
100nF
*
C444
100nF *
EC36
470uF
*
C227
100nF
+/-5% SD103AW
VCC_PWM * 10nF
*
25V, X7R,
100nF
+/-10%
Dummy
*
+80%~-20%
1000uF
+/-20%
+80%~-20%
+80%~-20%
Dummy
Dummy
16V, +/-20% +80%~-20%
Dummy
C
C382
Dummy
LR1_SEN
1uF
* C424 Dummy modify 8/16
VDDA_DRV
VDDA_SEN
* 1uF
VLDT_DRV
VLDT_SEN
LR2_DRV
LR1_SEN
D D
+3.3V_DUAL
36
35
34
33
32
31
30
29
28
27
26
25
U17
C43 C24 C23 C121 C12 C122
LR2_DRV
LR1_DRV
VSB5V
CP
VDDA_DRV
VLDT_DRV
C1
C2
LR1_SEN
GND
VDDA_SEN
VLDT_SEN
Dummy R278 * 100nF
+80%~-20%
Dummy * 100nF
+80%~-20%
Dummy * 100nF
+80%~-20%
Dummy * 100nF
+80%~-20%
Dummy * 100nF
+80%~-20% * 100nF
+80%~-20%
Dummy
0 DUALGATE
+/-5% C409
DUAL5V_GATE R276 0 USBGATE +3.3V_DUAL 100nF
+/-5% LR2_SEN 37 24 +80%~-20%
*
VDUAL3V_SEN LR2_SEN SS
38 VDUAL3V_SEN VTT_OPS 23 VTT_OPS 29
VDUAL3V_DRV
*R283
4.7K VCCGATE
39
40
VDUAL3V_DRV
VCCGATE
GND
VRAM_UGATE
22
21 VRAM_UGATE 29
+/-5% USBGATE 41 20
DUALGATE USBGATE VRAM_LGATE VCC_PWM VRAM_LGATE 29 C428
42 DUALGATE TIGER ONE VCC_PWM 19
R288 43 18
* 100nF
*
0 GND VRAM_OPS VRAM_OPS 29 +80%~-20% FD1 FD3 FD4 FD5 FD6 FD8
18,26 RSMRST# 44 RSMRST# VRAM_FB 17 VRAM_FB 29
+/-5%All-PWROK 45 16
18 All-PWROK R280 PWOK COMP COMP 29
46 15
*
4.7K VCC3V VTT_FB VTT_FB 29

+3.3V 47 TURBO1# VTT_PWM 14 VTT_PWM 29
R291 +/-5% 48 13 +5V_STBY Optics Optics Optics Optics Optics Optics
*
10K FAULT#/TURBO2# VSB5V R305

+12V
PS_ONOUT#
+/-5% R298 2.2
VCORE_GD
VCORE_EN
* *
dummy dummy dummy dummy dummy dummy
PS_ONIN#
+3.3V 4.7K C470 +/-5%
PWOKIN
+/-5%
* 100nF
SDATA
VREF
SCLK
PLED
SLED
C451 R299 +80%~-20%
GND
S5#
* * R286 +3.3V
3.9KOhm
4.7K
+/-5%
+80%~-20% +/-5%
1
2
3
4
5
6
7
8
9
10
11
12
100nF +3.3V_DUAL R306
*
+3.3V PWRGD_PS
4.7K
+/-5% C471
R307
* 1uF
*
R308 R309 4.7K 10V, Y5V, +80%/-20%

C * *
4.7K 4.7K
+5V_STBY
21,27 PS_ON#
+/-5% C
+/-5% +/-5%
27 PS_OUT#
18 SLP_S5* R310 PWM_GD 30
*
18,19,20,26 SMB_SCL 0
18,19,20,26 SMB_SDA PLED +/-5% VRM_EN 18,30
27 PLED SLED
27 SLED
PWRGD_PS
18,27 PWRGD_PS
+5V_STBY +3.3V
+5V
+3.3V +5V_STBY
C447 C240 VDDA_DRV
* 4.7uF
+80/-20% *
Q18
100nF
+80%~-20% EC58
Q27
C283 C476 * 1000uF
S
S
2
P3055LDG P3055LDG
* 4.7uF
* 4.7uF +/-20%
2
Q31 G VCCGATE R195 +80/-20% G VCCGATE
D
2.2 Q21 Dummy
VDUAL3V_DRV 1 +/-5% Q28
APM2054N 1 Reserved
P3055LDG
APM2054N DUAL5V_GATE G
3
D
VDUAL3V_SEN +2.5V
+3.3V_DUAL
3
S
EC40 C215 R194 +5V_DUAL
*
B * 470uF
16V, +/-20% * 100nF
+80%~-20%
VDDA_SEN 215 Ohm
+/-1% EC57 B
*R193 C271 * 1000uF
+3.3V_DUAL
Dummy 100 Ohm
+/-1% C248 C252 * 22uF
C261
6.3V, Y5V, +80%/-20% +5V_DUAL +/-20%
10uF
* 10uF * * 100nF
+80%~-20%
Dummy
VDDA Dummy
6.3V, Y5V, +80%/-20% 6.3V, Y5V, +80%/-20%
+3.3V_DUAL
LR2_DRV
+3.3V
VLDT_DRV
C246
* 100nF
2
C338 R185 +80%~-20%
* C247
* 4.7uF 2.2 Q20 +80/-20%
D
R215 +80/-20% +/-5% 4.7uF Dummy

2.2 Q22 1
+/-5% P3055LDG APM2054N
G
3
R264
S
A LR2_SEN 121 Ohm +1.2V_DUAL A

R265 +/-1%C259
*
VLDT_SEN 121 Ohm

+/-1%
+1.2V_HT
*R268
240 Ohm 10uF
*
* R267 +/-1% * C273
240 Ohm
+/-1% *
EC46
1000uF
*
C260
4.7uF
Dummy EC45
100uF
* 100nF
+80%~-20%
+/-20% +80/-20% 6.3V, Y5V, +80%/-20% +/-20%
Dummy
Dummy
VLDT +1.2V_DUAL FOXCONN PCEG
Title
ACPI
Modify 23/8
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
+5V_DUAL
C441 modify 8/18

L17
* * 4.7uF
+80/-20%
1uH@1KHz
modify 8/16
EC49 C446 C435
D
* 470uF
*+/-20%
4.7uF
* 100nF D
D
6.3V, +80/-20% +80%~-20%
Q23
R259 P3055LDG +1.8V_SUS
2.2 G
28 VRAM_UGATE +/-5%
S
R282
*
*
20K L18 2.5uH@100KHz
28 VRAM_OPS +/-5%
D
*
R272 10K
Q26 *R303
2.2 C333 EC52 EC50 EC53 EC47
P3055LDG +/-5%
* 100nF * 1000uF * 1000uF * 1000uF * 1000uF
*
R294 0 G +80%~-20% +/-20% +/-20% +/-20% +/-20%
28 VRAM_LGATE +/-5% C469 Dummy
* 4.7nF
S
50V, X7R, +/-10%
28 VRAM_FB
R287
*
33KOhm
+/-1%
R281
* 24K
+/-1% R292
*
C437 1nF 220 Ohm
*
50V, X7R, +/-10% +/-1%
Dummy Dummy
C C
+5V +12V
R151
* L11
2.2 1uH@1KHz modify 8/16
+/-5%
C175
1uF
16V, Y5V, +80%/-20% * C153
modify 8/18
* 1uF
16V, Y5V, +80%/-20% EC37 +1.2V
D
Q17
Dummy
* 330uF
16V, +/-20% * C151
R153 2.2 C182 0.1uF R156 P3055LDG +80/-20%
*
2.2 G 4.7uF
+/-5% +/-5%
U14
*
S
1 8 L12 2.5uH@100KHz
UGATE PHASE
2 7
D
*
BOOT PVCC R155 10K Q16

28 VTT_PWM 3
4
PWM
GND
VCC
LGATE
6
5 +/-5% *R169
2.2 EC43 EC41 EC44
ISL6612ACBZA-T R163
R152
0 G
P3055LDG +/-5%
C198
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
*
28 VTT_OPS
20K
+/-5% C176
+/-5%
* 4.7nF
50V, X7R, +/-10% Dummy
S
*
1uF
modify 8/16
R304
*
1.5KOhm
28 VTT_FB
*R295
3KOhm
+/-1%
C449 1.5nF +/-1%

COMP R297
*
*
B 28 COMP C464 1nF 220 Ohm B

*
50V, X7R, +/-10% 50V, X7R, +/-10% +/-1%
Dummy Dummy
R293
C452 47nF
*
11K
+1.22V
*
+/-1%
+/-10%
+3.3V_DUAL
+1.8V_SUS
U16
1 VIN NC3 8
C137 2 7
GND NC2
* 1uF
10V, Y5V, +80%/-20%
PADDLE
3 REFEN VCNTL 6
*R290
1K
4 VOUT NC1 5
C431 C429
+/-1%
* 22uF
* 1uF
9
RT9173CPSP 10V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%
A Dummy VTT_DDR_SUS A
*R285 C427 C425
+/-1% * * *
1K C433 100nF 1uF
1nF +80%~-20% 10V, Y5V, +80%/-20%
50V, X7R, +/-10%
C405
*
EC54
1000uF *
EC51
1000uF
*
Dummy +80/-20%
C385
* C410 * 1uF
10V, Y5V, +80%/-20%
+/-20% +/-20% 4.7uF Dummy +80/-20%
4.7uF
FOXCONN PCEG
Dummy
Title
MCP CORE +1.2V
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
L5
12V_VIN 12V_VRM 12V_VIN
emi
*
C80 C79 C83
1.2uH@100KHz
EC23 EC21 EC20 EC22
* 100nF
* 100nF
* 100nF
2
* 1000uF * 1000uF* 1000uF * 1000uF C93 PWR2
* C129
+80/-20%
+/-20% +/-20% +/-20% +/-20%* C82
+80/-20%
+80%~-20%
Dummy +80%~-20% Dummy
Dummy * 10nF
25V, X7R, +/-10%
4.7uF 4.7uF
Dummy
1
+5V
Header_2X2
+80%~-20%
D D
A
C570 D16
* 10uF
+/-10%
B120-13-F
Dummy 12V_VIN
C
+3.3V +3.3V C148 12V_VRM
* 4.7uF
6.3V, X5R, +/-10%
R145
2.2
32PIN 5x5QFN +/-5%
7
R141 R146 U13
HIGH(>1.24V) 1K * 10K 38 33
* C85
VCC
* 9 VREG_VID4 VID4 PVCC1
* *
+/-5% +/-5% R140 2.2 C164
ENABLE VRM 39 30
*R84 1uF
D
9 VREG_VID3 VID3 BOOT1
40 1uF 10K
9 VREG_VID2 VID2
1 C158 +/-5% Q12
9 VREG_VID1 VID1
2 0.1uF
9 VREG_VID0 VID0
3 31 UGATE1 R92 1 +/-5% G
VID12.5 UGATE1 AOD452 +V_CPU
28 PWM_GD 35 PGOOD L7
37 Orig 2.2R 0603
*
18,28 VRM_EN
S
C167 C163 ENLL PHASE1
PHASE1 29
VRM_EN > 0.6V ENABLE
* 100nF
* 100nF
D
+80%~-20% +80%~-20% R142 R98
*
ISEN1 1.8KOhm Q5 Q4 2.2 600nH@100KHz EC34 EC30
ISEN1 32
R126 34 LGATE1
+/-1%
G G
+/-5% * 1800uF
6.3V, +/-20%
* 1800uF6.3V, +/-20%
*
10K C146 5.6nF LGATE1 AOD472 AOD472

8
*
+/-5% COMP 12V_VIN C112 Dummy
S
modify 8/16 C143 220pF * 1nF
*
R138 modify 8/16

9 2.2 12V_VRM
FB +/-5%
+V_CPU R124
*
1K
+/-1%
10 VDIFF PVCC2 24
* C145 * C84
1uF
Orig 2K
*R116 26 R135 2.2 1uF
*R86
D
BOOT2
C156*
C 49.9 10K C
+/-1% +/-5% Q11
0.1uF
27 UGATE2 R93 1 +/-5% G
C136 UGATE2 AOD452
9 CPU_VDD_RUN_FB_H 12 VSEN L8
Orig 2.2R 0603
* 1nF
*
S
28 PHASE2
PHASE2
9 CPU_VDD_RUN_FB_L 11
D
RGND R129 R97
Dummy
*
ISEN2 600nH@100KHz
*R119 C132 R131 25 1.8KOhm Q7 Q6 2.2 EC27 EC32
*
ISEN2
49.9
+/-1% * 1nF
+5V
150K
+/-5%
6 OFS LGATE2
+/-1% +/-5% * 1800uF * 1800uF
Dummy
*R136
51KOhm LGATE2 23 G
AOD472
G
AOD472
6.3V, +/-20% 6.3V, +/-20%
+10mV +/-5% 12V_VIN C110 Dummy
S
OFFSET R128
* 1nF
Dummy
2.2
modify 8/16
36 FS +/-5%
*R143
120KOhm
5 REF
PVCC3 18 12V_VRM
+/-5%
*
C157
10nF R121 2.2 * C147
1uF
21
*R85
D
BOOT3
25V, X7R, +/-10%
4 VRM10
C138 * 10K
+/-5% Q10 * C81
1uF
modify 8/16 0.1uF
*
R113 820 13 20 UGATE3 R94 1 +/-5% G

+/-1% OCSET UGATE3 AOD452
Orig 2.2R 0603 L9
*
S
ICOMP 14 22 PHASE3
ICOMP PHASE3
D
R137 R99 EC35 EC33 EC31
*
600nH@100KHz
C134
100nF
ISUM 15 ISUM ISEN3 19 ISEN3 1.8KOhm
+/-1%
Q8 Q9 2.2
+/-5%
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
GND
*
+80%~-20% 16 17 LGATE3 G G
IREF LGATE3 AOD472 AOD472
ISL6566CRZA-TR5184 C111
S
41
B * 1nF
B
modify 8/16
BOTTOM PAD CONNECT TO
GND THROUGH 10vias
Orig 33K
R112 R114
***
13.3KOhm 24K
+/-1% R110
+/-1%
C135 24K
47nF R109
+/-1%
+/-10% 24K
*
+/-1%
Orig 47nF Y5V Orig 33K
A A
FOXCONN PCEG
Title
VRM
C MCP61M05 A

5 4 3 2 1
1 2 3 4 5 6 7 8
A A
+5V +3.3V
+5V +5V +5V +5V
2
D9 D10 D2 D1 D4
C26 BAV99 BAV99 C179 BAV99 BAV99 BAV99
2
* 10uF
6.3V, Y5V, +80%/-20%
3 3
* 100nF
+80%~-20%
3 3 3 D5
BAV99
D11
BAV99
3 3 *R42*R43
2.2K 2.2K
+/-5%+/-5%
1
***
B FB1 68nH@100MHz LRED B
14 DAC_RED FB3 68nH@100MHz LGREEN
14 DAC_GREEN FB4 68nH@100MHz LBLUE
14 DAC_BLUE R51
**
DDC_DATA 33 5VSDA
14 DDC_DATA R52
+/-5%
DDC_CLK 33 5VCLK
14 DDC_CLK +/-5%
**
L2 1 2 27nH@100MHz HSYNC
1
+5V 5 U6 R63 L3 1 2 27nH@100MHz VSYNC
*
DAC_HSYNC 2 V
4 22 1 1 1
14 DAC_HSYNC +/-5% R9 R10 R11
3 G
NC7SZ125M5X
C58
10pF
**
C55
10pF
150
+/-5%
150
+/-5%
150
+/-5%
*
C9
*
5.6pF
C10
*
5.6pF
C11
5.6pF
*
C3
10pF
*
C2
10pF
*
C1
10pF C37 ** C38
+/-0.25pF +/-0.25pF +/-0.25pF 50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5% 470pF 470pF
2 2 2 Dummy
1
5 U8 R65 Dummy
*
DAC_VSYNC 2 V
4 22
14 DAC_VSYNC +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5% 50V, X7R, +/-10%
3 G
NC7SZ125M5X
50V, X7R, +/-10%
C57
* 100nF
+80%~-20% Place near VGA-Connector <0.5"
+5V
*
F2
FUSE_1.1A
C35
* 100nF
+80%~-20%
C VGA C
VGA
5VCLK 15 SCL GND 5
10 GND
VSYNC 14 VSYNC ID0 4
9 NC
HSYNC 13 HSYNC B 3 LBLUE
8 GND
5VSDA 12 SDA G 2 LGREEN
7 GND
11 ID1 R 1 LRED
6 GND
CONN-VGA
16
17
D D
FOXCONN PCEG
Title
VGA
C MCP61M05 A

1 2 3 4 5 6 7 8
Standby Mode: +12V *R1016
75 *R1017
75 *R1018
75 *R1019
75 *R1020
0 *R1021
0 *R1022
33 *R1023
33 FRONT AUDIO HEADER +3.3V
+/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5%
For Power ON/OFF POP Noise
A
r0402h4 r0402h4 r0402h4 r0402h4 r0402h4 r0402h4 r0402h4 r0402h4
+5V_STBY D8 @ALC662 @ALC662 @ALC662 @ALC662 @VT1708B @VT1708B @VT1708B @VT1708B R66
LS4148-F Place near AUDIO header * 100K
+/-5%
A
D3 R1013 R1012 MIC2-L C52 10uF +/-10%
* *
****
*R60 2.2K 2.2K F_AUDIO
* ***
10 +/-5% +/-5% MIC2-R C53 10uF +/-10% R4 0 +/-5% #R1016#R1020 1 2
SD103AW U4 H78L05AA +/-5% R5 0 +/-5% #R1017#R1021 3 4 Detect
+5VA 1 3 @ALC662 @ALC662 LINE2-R EC17 100uF +/-20% R6 33 +/-5% #R1018#R1022 5 6 MIC2-JD
C
OUT IN Digital
7 X
C59 LINE2-L EC14 100uF +/-20% R7 33 +/-5% #R1019#R1023 9 10 LINE2-JD
GND
EC16 C30 * * 100nF
EC19 *R1014
3.3K *R1015
3.3K Header_2X5_8
*
*
100uF
* 100nF 100uF +/-5% +/-5% D14
** **
+/-20% +80%~-20% +80%~-20%
Dummy 2 R18 3.3K #R1013#R1014 RN11
7
5
3
1
16V, +/-20% @VT1708B @VT1708B MIC2-VREFO 3 +/-5% 22K
Dummy 1 R8 3.3K #R1012#R1015 +/-5%
8
6
4
2
+/-5%
D6 BAT54A @ALC662
2 R14 2.2K +/-5% @ALC662
Detect 21
LINE2-VREFO 3
1 R12 2.2K +/-5% @ALC662
BAT54A
@ALC662
close to Codec VCas possible EC4

R520 4.99K MIC1-VREFO-R 100uF R3
*
R33 FRONT-R +/-20% 75 FB15 FB 600 Ohm LINE_OUT_R5
*
* *
*
MIC2-JD 20K Sense_B C45 10uF @VT1708B +/-5%
**
+/-1% 6.3V, Y5V, +80%/-20% EC10
R26 C44 100nF +80%~-20% 100uF R21
*
LINE2-JD 39.2K @VT1708B LINE2-VREFO FRONT-L +/-20% 75 FB11 FB 600 Ohm LINE_OUT_L2
*
*
+/-1% MIC2-VREFO +/-5% 1 1
R15 R19 C557 C558
LINE1-VREFO-L
MIC1-VREFO-L1
Close to Chip 22K
+/-5%
22K
+/-5%
C46
1nF * * C50
1nF * 100pF 100pF
*
C16 10uF 50V, X7R, +/-10% 50V, X7R, +/-10% c0402h6
c0402h6
**
FRONT-L 6.3V, Y5V, +80%/-20% +5VA 2
@ALC662 2
@ALC662 #C557#C559 #C558#C560 @ALC662 @ALC662
C22 100nF +80%~-20%
FRONT-R
C27 C559 C560
* * 100nF R58
* 1nF
* 1nF
*
C569 +80%~-20% MIC1-VREFO-L1 0 MIC1-VREFO-L
+5VA 10uF +/-5%@ALC662 c0402h6 c0402h6
@VT1708B 6.3V, Y5V, +80%/-20% U50 @VT1708B @VT1708B
U5
*R1025
2.2K *R1024
2.2K
D23 +/-5% +/-5%
36
35
34
33
32
31
30
29
28
27
26
25
C20 VT1708B G @ALC662 2 MIC1-VREFO-L

* 100nF ALC662-GR MIC1-VREFO-L1 3
SENSE B
FRONT_L
NC4
LINE2_VREFO
AVSS1
AVDD1
FRONT_R
MIC1_VREFO_R
MIC_VREFO
NC3
MIC1_VREFO_L
VREF
@ALC662 @ALC662
+80%~-20% #U50#U51 U51 1 MIC1-VREFO-R
BAT54A
Close to the Codec
LINE1_R 24 LINE1-R
*R29 *R30 *R1026
3.3K *R1027
3.3K
37 23 LINE1-L @VT1708B 3.3K 3.3K +/-5% +/-5%
NC5 LINE1_L MIC1-R +/-5% +/-5%
38 AVDD2 MIC1_R 22
39 21 MIC1-L @VT1708B @VT1708B @VT1708B
SURR_L MIC1_L CD_R VT1708B G #R1025#R1026 #R1024#R1027
40 JDREF/NC CD_R 20
41 19 CD_GND R17
* *
SURR_R CD_GND_REF CD_L MIC1-R C70 10uF +/-10% 75 FB14 FB 600 Ohm MIC1_R5
42 18
*
* *
AVSS2 CD_L MIC2-R +/-5%
43 CEN MIC2_R 17
R41 MIC2-L
5.1KOhm *R1004
20K
R1005
5.1KOhm
44
45
LFE
SIDESURR_L
MIC2_L
LINE2_R
16
15 LINE2-R MIC1-L C54 10uF +/-10%
R47
75 FB13
* FB 600 Ohm MIC1_L2
+/-1% +/-1% +/-1% 46 14 LINE2-L R64 +/-5%
SIDESURR_R LINE2_L Sense_A 5.1KOhm FRONT-JD
47 NC6 SENSE A 13 1 1
SPDIF_OUT
@ALC662@VT1708B 48 SPDIF_OUT
+/-1% Close to Chip R20 R49 C48
* * C49 C562 C563
SDATA_OUT
R53 22K 22K 1nF 1nF

* 100pF 100pF
*
* *
SDATA_IN
#R1004#R1005 10K LINE1-JD +/-5% +/-5% 50V, X7R, +/-10% 50V, X7R, +/-10%
BIT_CLK
PCBEEP
RESET#
+/-1% #C562#C564 #C563#C561 c0402h6

c0402h6
DVDD1
DVDD2
DVSS1
DVSS2
2 2
SYNC
R61 @ALC662 @ALC662

NC1
NC2
20K MIC1-JD @ALC662 @ALC662

+/-1%
C564 C561
1
2
3
4
5
6
7
8
9
10
11
12
* 1nF
* 1nF
c0402h6 c0402h6
C76 Arrangement of Jack Detection Pin: @VT1708B @VT1708B
* 100nF
+80%~-20%
Sense A for jacks at back panel
Sense B for jacks at front panel
D24
2
+3.3V LINE1-VREFO-L 3
L4 1
1
* 2
BAT54A
C69 C77 R31
40 Ohm@100MHz
* 100nF
* 100nF @VT1708B
*
3.3K *R32
3.3K
* C74 +80%~-20%
Dummy +/-5% +/-5%
+80/-20% +80%~-20% @VT1708B
4.7uF Dummy @VT1708B
AC_RST* 18
For EMI AC_SYNC 18
R72 R13
*
* *
CP1 2 COPPER 22 LINE1-R C377 10uF +/-10% 75 FB16 FB 600 Ohm LINE1_R5
1 AC_SDIN_0 18 *
* *
dummy +/-5% +/-5%
CP2
R16
LINE1-L C71 10uF +/-10% 75 FB12 FB 600 Ohm LINE1_L2
1 2 AC_BITCLK 18
+/-5% 1 1
*
R22 R34
dummy COPPER AC_SDOUT 18
CP4 1 2
dummy modify 9/13 Close to Chip
22K
+/-5%
22K
+/-5%
C47
1nF * * C51
1nF
*
C566
100pF
C567
100pF
*
50V, X7R, +/-10% 50V, X7R, +/-10%
C552 2 2 c0402h6
c0402h6
* 10pF
50V, NPO, +/-5%
@ALC662 @ALC662 #C566#C568 #C567#C565 @ALC662 @ALC662
Dummy
C4 100nF +80%~-20%
Dummy C568 C565
* *
* 1nF
* 1nF
C78 100nF +80%~-20%

Dummy c0402h6 c0402h6
@VT1708B @VT1708B
AUDIO
Light Blue
Audio Jack
CD-IN
PLACE near to connector
LINE1_L2
LINE1-JD
32
33
INSULATOR
LINE IN
C86
1uF R80
SPDIF Header LINE1_R5
34
35
C (UAJ)
* * *
CD_L 10V, Y5V, +80%/-20% 330 #R1006#R1009 SPDIF_OUT

* * *
C88 +/-5% CD_IN LINE OUT

1uF R81 1 1 +5V
1 36 B (UAJ)
CD_GND 10V, Y5V, +80%/-20% 0 #R1007#R1011 SPDIF_OUT
C90 +/-5%
2
3
3 3
4 LINE_OUT_L2 22
Lime
1uF R82 4 FRONT-JD
4 23 37 MIC IN
CD_R 10V, Y5V, +80%/-20% 330 #R1008#R1010 Header_1X4_K2 24 A
+/-5% Header_1X4 LINE_OUT_R5 25
(UAJ)
38
Close to Chip
C361 R223 SPDIF_OUT
* *C362
*
R224
* MIC1_L2 2 39
3.3nF 100K 3.3nF 100K * C61

470pF
MIC1-JD 3
4 Pink
R1006 R1007 R1008 +/-10% +/-5% +/-10% +/-5% +/-5% MIC1_R5 5
*
1K *1K *1K @VT1708B @VT1708B @VT1708B
@VT1708B Dummy 1
+/-5% +/-5% +/-5%
@ALC662 @ALC662 @ALC662 CONN-JACK
FOXCONN PCEG
R1009 R1011 R1010 Title
* 330 * 0 * 330 ALC888/ALC662
+/-5% +/-5% +/-5%
@VT1708B @VT1708B @VT1708B C MCP61M05 A

5 4 3 2 1
ATX PowerSupply MCP61

PROCESSOR
+1.2V (Core Power)
D D
Vccp (CPU Vcore) MCP61
Voltage=0.8375-1.6V +1.2V_PEA Super I/O
3-Phase Icc(Max)=89A +1.2V_PED VCC5
Switcher +1.2V_SP_A
+12V 3-Phase Swithing +1.2V_SP_D +3.3V 5V Icc(Max)=50mA
CPU PLL +1.2V_PLL_SP_SS
+2.5V_VDDA +1.2V_PLL_SP_VDD
Imax=105mA(S0/S1)
Tiger One +1.2V_PLL_PE
+1.2V_PLL_PE_SS +5VSB
+3.3V_DAC 5VSB Icc(Max)=50mA(S0)
+1.2V_PLL_CPU_HT 5VSB Icc(Max)=38mA(S3)
+12V +1.2V_CORE
SWITCHER
Total I=10A
+3.3V PCI Express

+12V X16 Slot(1)
+12V=5.5 A
+3.3VSB 3.3VSB
Icc(Max)=0.375A(Wake)
+5V SLP_S3# +5V_SB Q30 Icc(Max)=0.02A(NoWake)
Controller +5V_STBY to 3.3SB +3.3V
Icc(Max)=1.5A +3.3V=3A
USB 8 Pprts
SLP_S5# Tiger One
+5v_DUAL=500mA(S0/S1)
+5v_DUAL=500mA(S3)
C PS/2 +12V PCI Express C

MOS FET X1 Slot(1)
+5v_DUAL +5v DUAL=300mA(S0/S1)
+5v_DUAL=300mA(S3) +12V=0.5 A
+3.3VSB 3.3VSB
+5V_SB Icc(Max)=0.375A(Wake)
Icc(Max)=0.02A(NoWake)
+3.3V
MOS FET MCP61 +3.3V=3A
DDR2 1.2V_DUAL +5V

+1.8V_SUS Q32 +1.2V_DUAL
Switch Imax=14A(S0/S1) Total 250mA
Imax=300mA(S3) VBAT
+5V PCI Per Slot (2)
I DDR_Vtt=1.2A +5V Icc(Max)=5A
+0.9V_SUS (S0/S1) +3.3V -12V Icc(Max)=0.1A

Integrated (S3)
Switcher I DDR_Vtt=50mA +3.3V Icc(Max)=6A
+12V
+12V Icc(Max)=0.5A
+3.3VSB +3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(NoWake)
+3.3V
+3.3V
RTC Battery
-12V
+1.5V
B RTL8100C/8110SC B
1.8V
MCP61
+1.2VHT HT Link
Linear
1.2VHT=1A(S0,S1)
J4
1
2 J2
1 J1
A Header_1X2 2 J3 1 A
T1 1 2
dummy Header_1X2 2
T1 Header_1X2
dummy Header_1X2 T1
T1 dummy
dummy
FOXCONN PCEG
Title
Power Map
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
6/18 ： 1,USB: 0 ohm R change to 0 ohm RN, 4pin Bead change to 8pin
Bead; 2, BIOS,LPC change to SPI . 3, LAN change to AC131 + PCI
LAN :RTL8100C/8110SC,
6/20 : 1,LAN_CLK 走南橋，Dummy 外部晶振, Remove AC131 PHY LAN；

2，R623，R624 16.9 ohm 改為15 ohm ； 3，USB Fuse 2.6A 替代2個1.5A
；4，F_Audio 75 ohm /22k ohm 電阻閤並成排阻
6/21 : 1，LAN 49.9 ohm 電阻閤並成排阻49.9 ohm；

2，R388 去掉，SIO部分有串接10ohm 電阻；
D D
3，Dummy C332,C301,C310,C300,C320,C290,C347.
6/22 : 1,去掉R355，R829，R830，R832； 2， dummy C572 ；

3， ADD C2136 0.1uF to GMII_RXCLK, R57 change to 330K;
6/29: 1, Add 75 ohm damping resistance for Audio ; 2,F_Audio

detect pin connect to sense_B pin of CODEC; 3, ADD prtection Diode
to COM port .
7/2 : 1,remove L99,L100,L102; Change heatsink with foxconn log; 2, Remove RN122 .
7/3: 1, ADD C 956( 4.7uF/805) to 3.3v_Dual ; 2, dummy EC83 (5V_SB);

3, Remove C412, C352,C354;
7/5: 1, change C374,C378 to 0.1uF/0603; 2, dummy
C157,C244,C267,C193,C286,C645,C199,C247,C312,C315,C325,C327,C328; 3,
Remove C385,C386,C407,C865,C387,C866;
7/7: 1, Change D6,D7,D8,D17,D20,D23,D47 footprint to so80h16; 2, change

RN45,RN46 from 8p4r0603 to 8p4r0402 ; 3, add EC106 100uF to
+1.2V_dual, dummy EC105 ; 4, Q129,Q131 change to AP15N03GH;
7/9: 1, GPIO PIN: Board ID Select. add R363,R364,R365; Default add R363;
C 2, Remove C808,C809,C810,C811,C821,C89,C806,C807,C156,C268,C970, C
C52,C74,C49,C976,C61,C83,C73,C76,C72,EC66 ; 3, add EC50, dummy EC14;
7/11 : 1, add EC107 to aduio 12 V power, C733 change to 10uF, add L28 to audio power DVDD ;
2, ADD EC60 to 3.3V_DUAL for LAN Power ,default dumy ; 3, add R368, R371 to modify the SPI
clock; 4, Remove C7,C8,C11,R517,R530,R536 ( Audio ).
8/16 : 1 .L12/L20 change to 1uH/1kHz
2 .EC39/38 change to 680uF
3 . add R501/502 for CD-IN
4 .PCI SLOT IDSEL
5 .add EC103 (1.2V OUTPUT)
6 .EC35/37 change to 470uF
7 . add EC104/105
8 .C392/396 change to 22p
B B
9 .Retention Module for CPU change HH P/N
10 .PEA POWER del copper,FB

11 .R83 dummy,and add thermal trip to SIO through level shift
12 .C238 change to 220pF
13 .R163 change to 680R
14 .SATA2,SATA3 change each other
15 .Del R77/72/133
16 .R262 change to 1.1k

17 .C495 change to 10uF and reserved
18 .C496 reserved
9/12 : 1 .USB_OC add R550/R51/R552/R553 for 3.3V
2 .Exchange usb3/4;
2 .change C385/C391/C392/C396 from 0603 to 0402

A A
9/19 : 1 .change c392/c396 22pf to 24pf
FOXCONN PCEG
Title
Modify list
C MCP61M05 A

5 4 3 2 1
5 4 3 2 1
D D
C C
U9_1
HEATSINK_SOCKET_940_M2
modify 8/16
B B
A A
FOXCONN PCEG
Title
CHANGE LIST
C MCP61M05 A

5 4 3 2 1

Foxcom M61PMV

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5 4 3 2 1

nVIDIA MCP61 Chipset for AMD M2 CPU

PAGE CONTENT PAGE CONTENT

5 05. PCI DEVICE / VID TABLE 29 29. MCP61 CORE POWER

24 24. FAN / HARDWARE MONITOR /VID

Date: Friday, June 27, 2008 Sheet 1 of 35

MCP61M05 Block Diagram

PWRBTN# S I/O PANSWHJ SW

VRM_EN ATX POWER

PCI V2.3 / 33MHZ

X8 USB ( V2.0 EHCI / V1.1 OHCI ) USB2 PORTS 7,8

USB2 PORTS 1,6

USB2 PORTS 4,5

SERIAL CONN (COM1)

SERIAL Header (COM2)

Date: Friday, June 27, 2008 Sheet 2 of 35

PWR CONN PWRBTN*

PCI RST3* PCIRST_IDE*

SIO FLASH PRI IDE VT6307 PCI SLOT 2 PCI SLOT 1

Date: Friday, June 27, 2008 Sheet 3 of 35

HT_CPU_RXCLK1 MEMCLK_L[1,4,6] DIMM 1

LPC_CLK1 PCI SLOT 3

32.768 KHZ RTC_XTAL FLASH LPC

Date: Friday, June 27, 2008 Sheet 4 of 35

PCI INTERRUPT/IDSEL MAP

0X00000 1.550V 0X10000 1.150V

0X00100 1.450V 0X10100 1.050V

0X00101 1.425V 0X10101 1.025V

0X00110 1.400V 0X10110 1.000V

0X00111 1.375V 0X10111 0.975V

0X01000 1.350V 0X11000 0.950V

0X01001 1.325V 0X11001 0.925V

0X01010 1.300V 0X11010 0.900V

0X01011 1.275V 0X11011 0.875V

0X01100 1.250V 0X11100 0.850V PCI DEVICE MAP

0X01110 1.200V 0X11110 0.800V

SMBUS ADDRESS MAP SATA0 0 X8 0 0X0054

DEVICE SMBUS # ADDRESS MODEM CODEC 0 X4 1 0X0058

Date: Friday, June 27, 2008 Sheet 5 of 35

R150 49.9 +/-1% HT_CPU_CTLIN_H1 V4 Y6 HT_CPU_CTLOUT_H1 1 TP14

13 HT_RC_CPU_CTL_H0 U1 L0_CTLIN_H(0) L0_CTLOUT_H(0) W2 HT_CPU_RC_CTL_H0 13

Layout: Add stitching caps if crossing plane split

Date: Friday, June 27, 2008 Sheet 6 of 35

Date: Friday, June 27, 2008 Sheet 7 of 35

MB_DATA(31) E31 MEM_MB_DATA31

Date: Friday, June 27, 2008 Sheet 8 of 35

Level translation buffers

C199 C211 C200 C201

10V, X7R, +/-10%

13 CPU_ALL_PWROK CPU_ALL_PWROK C9 D2 CPU_VID5 1 TP7

DUMMY CPU_ALL_PWROK 1 TP11

CPU_M_VREF_SUS AMD NPT 0Fh Processors

Date: Friday, June 27, 2008 Sheet 9 of 35

Processor Power & Ground

VLDT_RUN_B is connected to the VLDT_RUN power

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

25V, X7R, +/-10%

10V, X7R, +/-10%

10V, X7R, +/-10%

************** * ***

AC3 RESERVED SATA_LED/GPIO57 A5 SATA_HDLED 27