library ieee;

use ieee.std_logic_1164.all;

entity decade_counter is
port (
clk : in std_logic; -- señal de reloj
rst : in std_logic; -- señal de reset
count : out integer -- salida del contador
);
end entity;

architecture behavior of decade_counter is

signal count_int : integer range 0 to 10;
begin
-- incrementar el contador en cada flanco positivo de la señal de reloj
process (clk, rst)
begin
if rst = '1' then
count_int <= 0;
elsif rising_edge(clk) then
count_int <= count_int + 1;
if count_int = 10 then
count_int <= 0;
end if;
end if;
end process;

-- convertir la salida del contador interno a un formato de salida de 4 bits

count <= count_int;
end architecture;