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Chapter 1*
Computer Abstractions
and Technology
Some text, pictures and slides were added to update the original
edition
Implications:
More transistors,
→ more innovations
Smaller transistors,
→ higher frequency
Server computers
Network based
High capacity, performance, reliability
Range from small servers to building sized
Embedded computers
Hidden as components of
systems
Stringent power/performance/cost constraints
Chapter 1 — Computer Abstractions and Technology — 5
The PostPC Era
Algorithm
Determines number of operations executed
Programming language, compiler, architecture
Determine number of machine instructions executed
per operation
Processor and memory system
Determine how fast instructions are executed
I/O system (including OS)
Determines how fast I/O operations are executed
Hierarchy of memories
A12 processor
DRAM capacity
Silicon: semiconductor
Add materials to transform properties:
Conductors
Insulators
Switch
300mm wafer, 280 chips, 32nm 300mm wafer, 506 chips, 10nm
Each chip is 20.7 x 10.5 mm Each chip is 11.4 x 10.7 mm
Clock (cycles)
Data transfer
and computation
Update state
Performance improved by
Reducing number of clock cycles
Increasing clock rate
Hardware designer must often trade off clock
rate against cycle count
B = I × 600ps = 1.2
CPU Time
…by this much
CPU Time I × 500ps
A
Chapter 1 — Computer Abstractions and Technology — 29
CPI in More Detail
If different instruction classes take different
numbers of cycles
n
Clock Cycles = (CPIi × Instruction Count i )
i=1
Relative frequency
Class A B C
CPI for class 1 2 3
IC in sequence 1 2 1 2
IC in sequence 2 4 1 1
Sequence 1: IC = 5 Sequence 2: IC = 6
Clock Cycles Clock Cycles
= 2×1 + 1×2 + 2×3 = 4×1 + 1×2 + 1×3
= 10 =9
Avg. CPI = 10/5 = 2.0 Avg. CPI = 9/6 = 1.5
Chapter 1 — Computer Abstractions and Technology — 31
Performance Summary
The BIG Picture
Performance depends on
Algorithm: affects IC, possibly CPI
Programming language: affects IC, CPI
Compiler: affects IC, CPI
Instruction set architecture: affects IC, CPI, Tc
n
n
∏ Execution time ratio
i=1
i
1
Speedup = =2
(1 − 0,4) + (0,4 / Genh )
Instruction count
MIPS =
Execution time × 10 6
Instruction count Clock rate
= =
Instruction count × CPI CPI × 10 6
× 10 6
Clock rate
CPI varies between programs on a given CPU
Chapter 1 — Computer Abstractions and Technology — 43
MIPS vs CPU time example
For a given machine (fck = 100 MHz), the
number of instructions for the same
program but with different compilers was
measured.
Class CPI Number of inst. per class (106)
Compiler
A 1 A B C
B 2 1 5 1 1
C 3 2 10 1 1
10 × 1 + 1× 2 + 1× 3
CPI 2 = = 1,25
10 + 1 + 1
Freq 100 ×10 6
MIPS 2 = 6 = 6 = 80
10 × CPI1 10 × 1,25
N inst 2 (10 + 1 + 1) × 106
texec 2 = = = 0,15s
MIPS 2 × 10 6
80 × 10 6