VHDL Processes General form of Process process(sensitity-ist) begin sequential-statements ‘end process: Process example process (8, C, D) begin ‘A<= 6; ~ statement 1 B<=C; ~ statement 2 C <=; statement 3 fend process, Simulation results time delta ABCD Oo 401230 10 +01 2 3 4 (statements 1,2,3 execute; then update A,5,0) 10 41-2 3 4 4 (statements 1/2,3 execute: then update A,B,C) 10 423-4 4 4 (statements 1,2,3 execute: then update A,B,C) 410 +3 4 4 4 4 (no further execution occurs) Concurrent Statements ‘Simulation Results stetement 1 time a ABCD - statement 2 040 1230 Statement 3 10.40 1.2.34 (statement 3 executes fist) 10 41 12-4 4 (then statement 2 executes) 10 42 14.44 (then statement 1 executes} 10 +3. 44 4.4 (po further execution occurs) ° e. ° ee ee ee ee entity OFF ort (D, CLK: im bits s (Q: out bit; QN! out bit := "1; initialize QN to T’ since bit signals are initialized to 0" by defauit , ee fend OFF; architecture SIMPLE of OFF is = process (C1X) process is executed when CLK changes rising edge of clock feng SIMPLE; Ae eeJK Flip-flop entity KF is Ort (SK, RN, J, Ky CLK: im bit inputs imout bit; Ns out bit == see Note 1 fend FF; architecture IKFFI Of IEF Is ‘process (SN, FN, CLK) see Note 2 wil clea the FF ull ot the FF = see Note 3 G <= (land not Q) oF (not Kand Q) after 10s; ~ see Note 4 fend it; fend process; ON <= not C, ~ see Note 5 fend oF Mote 1: Qe decared a inst (rathr than out because it appears on bth the eft and ight sides of an Note 2: The ofp cs chane sate response to changes SX, RN, and CLK, So these 3 signals are te ota 3: he cron (COX = and C.Kerent) fs TRUE only CLK has st changed fram to Note a: Choroctersicsquaton when describes benawor of 1-6 pf, Note 3: ery tame @ changes, QN wil be upaates. Uti statement weve placed within the process he od vasodof@ wuss be ued tend Modelo VHDL Sequencial eocceee Wbrary declarations entity model_name is port ** lista de entradas e saidas ** architecture behavior of model_name is * declaragées de sinais imtermos ** begin —o state process define o médulo meméria state: proces senstvly Ist — clock, reset, nex sate inputs) gin comandos VHDI. para definigdo de estados ** ‘end process states — 0 comb process define a logica combinacional comb: process ( sensitivity list — geralmente inclul todas as entradas) begin * comandas VHDI. pare end process comb; finicdo da lég. combinacional ** ‘end behavior; ©8-bit Loadable Register with Asynchronous clear library ieee use iecestd_ logic 1164, entity regSbit is port ( Signal elk, reset, load: in std_logie: std_logie_vector(7 downto 0): » end regBbits architecture behavior of eeSbit is state state st hogic_vector(? downto Os begin ‘dout <= p_state; __ estado presente atribuido & saida rocess(p_stateoad.din) ‘state <=p_state; ifload="1") then n_ state <= di end process comb; process(ctk, reset) if (reset =°0°) then p_state <= (others =>"0'); clsif(clk'event and clk ="1") then p_state <= n_state; end if fend process sate: end behavior Comando WAIT Método alternativo para caracterizar os elementos de memoria ° state: process begin wait until ((clk’event and clk 1’) or (reset 0"); if (reset = °0°) then p_state <= (others => °0°); else p_state <= n_state; end if; end process state; 0 comando WAIT é sequencial ¢ suspende 0 processo (ou subrotina) até que a condicao seja satisfeita. Observe que 0 processo ni tem sensitivity list.Exercicio : analisar 0 conversor de cédigo abaixo a, afer et aj @ grergr | oz 19203] x-0 xa1 [xno x= 700 100 Lor m1 on 10 oo 01, S3 = 121, $4 = 110, $5 s6=019 eeegeus |3 (a) Mealy state graph.. VHDL do conversor de c6digo (projeto) ‘entity its 2 pore, Clk im lt: 2: eut bit) end SH 2 architecture Tole of M12 is Signal Ste, Nextstate neger = beain rocess(Stae%) Combntional Network Nedtstate<=t; end i Nemetates=2: end BRS Gi LL GRE whan 5 => Atel then Z<—'T Nextstate==0; end W wen 6 == "Pio then 2<~''; Nesstate<=0; end if when others "> nal ‘howd ne occur end ease rocess(CLt) te Regier esi cue then sng eae of clock BS sa ai45 ee Saati quince st nt ere tt scey tlealies Relient |