A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Yonah uFCPGA with Intel
3
Calistoga_GM/PM+ICH7-M core logic 3

2005-12-15
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 1 of 60
A B C D E
 A B C D E

Compal confidential
File Name : LA-2841
ZZZ

1
PCB Thermal Sensor Mobile Yonah 1

VRAM ADM1032 uFCBGA-479/uFCPGA-478 CPU

128/256MB page 4
page 4, 5, 6
page 22,23,24,25
Clock Generator
Fan Control H_A#(3..31)
FSB ICS 954306
page 4
H_D#(0..63) 533/667MHz

Nvidia page 15
NV71/72M DDR2-SO-DIMM X2
PCI-E x 16 Intel Calistoga GMCH DDR2 -400/533/667 BANK 0, 1, 2, 3 page 13,14
page 18,19,20,21,26

PCBGA 1466 Dual Channel

LVDS Panel
Interface page 16
page 7, 8, 9, 10,11,12
2 Mini-PCIE Card 2

page 37
CRT & TV OUT DMI
page 17 New Card
PCIE x3
Connector x2
page 34
USB2.0
LAN I/F
Intel ICH7-M AC-LINK

PCI BUS mBGA-652

3.3V 33 MHz

page 27, 28, 29, 30

USB conn X3
page 41
CardBus Controller
10/100 LAN TI PCI7412 BT Conn
LPC BUS
page 35 page 32 page 41
3 3
MO DEM
RTC CKT. Audio CKT AMOM page 39

page 29 RJ45 CONN Slot 0 13 94 Card reader AMOM page 38

page 35 page 33 page 32 page 32
ENE KB910/L AMP & Audio Jack
page 44 page 40
SATA HDD
Connector x2
page 31 SPR CONN.
Touch Pad Int.KBD *RJ45 CONN
page 42 page 42
PATA CDROM *MIC IN JACK
*LINE OUT JACK
Power On/Off CKT. BIOS Connector *1394 CONN
page 42 page 45 page 31 *SPDIF CONN
*DC JACK
*TVOUT CONN
DC/DC Interface CKT. *USB CONN x1
4 *CIR x1 4

page 47
page 46

Power Circuit DC/DC Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
page 48~56 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 2 of 60
A B C D E
 A

Voltage Rails
+5VS
+3VS
power
plane +2.5VS
+1.8VS
+B
+1.5VS
LDO3 +5VALW +1.8V
+1.2VS
LDO5 +3VALW +5V
+VGA_CORE
+0.9VS
State
+CPU_CORE
+VCCP

S0 O O O O

S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

O MEANS ON
X MEANS OFF

1 1

PCI Devices
EXTERNAL IDSEL# REQ/GNT# PIRQ

CARD BUS & 1394 AD22 2 C,D,E,G

Load BOM check item

1.U31 GM/PM/GML part number
2.U6 ICH7 part number
3.VRAM part number and Page26 RAM_CFG[0:3]/PCI_DEVID[0:3] modify check
4.For NV73 R510/R75/R533/R168 change to 499ohm
5.U33 NV7x part number

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 3 of 60
A
 5 4 3 2 1

+VCCP

This shall place near CPU

ITP_TDI R6 1 2 56_0402_5%
<7> H_A#[3..31] H_D#[0..63] <7>
JP16A ITP_TMS R3 1 2 56_0402_5%

H_A#3 J4 E22 H_D#0 ITP_TDO R2 1 2 56_0402_5%

H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 ITP_BPM#5 R1 56_0402_5%
M3 A5# D2# E26 1 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 ITP_TRST# R4 56_0402_5%
M1 A7# D4# F23 1 2
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 ITP_TCK R5 56_0402_5%
J1 A9# D6# E25 1 2
D H_A#10 H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12 ITP_DBRESET# R181 1 2 @ 200_0402_5% PAD T27
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26
H_A#17 Y2 K22 H_D#14 ITP_BPM#0 PAD T5
H_A#18 A17# D14# H_D#15 ITP_BPM#1 T4
U5 A18# D15# H25 PAD
H_A#19 R3 N22 H_D#16 ITP_BPM#2 PAD T3
H_A#20 A19# D16# H_D#17 ITP_BPM#3 T1
W6 A20# D17# K25 PAD
H_A#21 U4 P26 H_D#18 ITP_BPM#4 PAD T2
H_A#22 A21# D18# H_D#19
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26
H_A#27
T3
W3
A25#
A26#
D22#
D23# M23
P25
H_D#23
H_D#24
Thermal Sensor ADM1032AR
H_A#28 A27# D24# H_D#25 +3VS
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26
H_A#30 A29# D26# H_D#27
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28 2
<7> H_REQ#[0..4] A31# D28#
L26 H_D#29 C598
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31 0.1U_0402_16V4Z
H_REQ#2 REQ1# D31# H_D#32 1
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 U30
H_REQ#4 REQ3# D33# H_D#34 EC_SMC_2
L5 REQ4# D34# V24 1 VDD SCLK 8
V26 H_D#35
H_ADSTB#0 D35# H_D#36 H_THERMDA EC_SMD_2
<7> H_ADSTB#0 L2 ADSTB0# D36# W25 2 D+ SDATA 7
H_ADSTB#1 V4 U23 H_D#37 C592
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38 1 2 H_THERMDC 3 6
C D38# H_D#39 D- ALERT# C
D39# U22
AB25 H_D#40 2200P_0402_50V7K THERM# 4 5
D40# H_D#41 THERM# GND
D41# W22
Y23 H_D#42 R458
CLK_CPU_BCLK A22 D42# H_D#43 ADM1032AR_SOP8
<15> CLK_CPU_BCLK BCLK0 D43# AA26 +3VS 1 2
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45 10K_0402_5%
D45# Y22 Address:100_1100
AC26 H_D#46
D46# H_D#47 EC_SMC_2
D47# AA24 <44> EC_SMC_2
H_ADS# H1 AC22 H_D#48 EC_SMD_2
<7> H_ADS# ADS# D48# <44> EC_SMD_2
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
<7> H_DRDY# DRDY# D53#
R17 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+VCCP
<7> H_LOCK#
H_LOCK#
H_RESET#
H4
B1
IERR#
LOCK#
D56#
D57# AD24
AE21
H_D#57
H_D#58
FAN control +5VS
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60 C765 1
<7> H_RS#[0..2] D60# AE25 2 10U_1206_16V4Z
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62 U40
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63 1 8
H_TRDY# RS2# D63# VEN GND
<7> H_TRDY# G2 TRDY# 2 VIN GND 7
FAN1 3 6
H_DINV#0 VO GND
DINV0# J26 H_DINV#0 <7> <44> EN_FAN1 4 VSET GND 5
M26 H_DINV#1
DINV1# H_DINV#1 <7>
ITP_BPM#0 AD4 V23 H_DINV#2 G993P1UF_SOP8
BPM0# DINV2# H_DINV#2 <7>
ITP_BPM#1 AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 <7>
ITP_BPM#2 AD1
B ITP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] <7>
H23 H_DSTBN#0
ITP_DBRESET# C20 DSTBN0# H_DSTBN#1
<29> ITP_DBRESET# DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2# +5VS +3VS
H_DPSLP# B5 AD23 H_DSTBN#3
<28> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<28,53> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
ITP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<53> H_PROCHOT# PRDY# DSTBP2#

2
ITP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
+VCCP 1 R18 2 H_PROCHOT# D21
PROCHOT# 1SS355_SOD323
R551
75_0402_5% 10K_0402_5%
H_PW RGOOD D6 D28
<28> H_PWRGOOD H_CPUSLP# PWRGOOD JP30
D7

1
<7> H_CPUSLP# ITP_TCK SLP# FAN1
AC5 TCK 1
ITP_TDI AA6 A6 H_A20M#
TDI A20M# H_A20M# <28> 2

1000P_0402_50V7K

C763 10U_0805_10V4Z
ITP_TDO AB3 A5 H_FERR#
TDO FERR# H_FERR# <28> 3

1
R456 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# 1 1
TEST1 IGNNE# H_IGNNE# <28>
R455 1 2 51_0402_5% TEST2 D25 B3 H_INIT# ACES_85205-0300
TEST2 INIT# H_INIT# <28>
ITP_TMS AB5 C6 H_INTR
TMS LINT0 H_INTR <28>
ITP_TRST# AB6 B4 H_NMI D22
TRST# LINT1 H_NMI <28> 2 2
LEGACY CPU BAS16_SOT23
THERMAL

C761
H_THERMDA A24 D5 H_STPCLK#
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <28>
A25 A3 H_SMI# <28>

2
H_THERMTRIP# C7 THERMDC SMI#
<7,28> H_THERMTRIP# THERMTRIP#
H_THERMDA, H_THERMDC routing together.
FOX_PZ47903-2741-42_YONAH
Trace width / Spacing = 10 / 10 mil <44> FAN_SPEED1
1
C762
1000P_0402_50V7K
A +VCCP 2 A

+VCCP
1

R437
R457 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R436 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2005/03/10 2006/03/10 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <29>
C

Q35 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCP +CPU_CORE
Length match within 25 mils JP16B JP16C
D D
The trace width 18 mils space

1
<53> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
VCCSENSE VSS VCC VSS
+CPU_CORE 7 mils <53> VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R454 R442 AD25 AB15 M2
V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R441 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C586

C587
N6 AD22 AA13 D26
R451
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22

POWER, GROUNG, RESERVED SIGNALS AND NC

W21 VCCP VSS AA16 AE12 VCC VSS E21
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<53> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
<53> CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
<53> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<53> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<53> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C <53> CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
<53> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<53> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
1 <15> CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R453

R452

R439

R438

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

D +CPU_CORE D

1 1 1 1 1 1 1 1
Place these capacitors on L8 C13 C14 C28 C23 C34 C18 C19 C30
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C33 C39 C42 C35 C38 C41 C2 C48
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C40 C32 C27 C22 C16 C11 C36 C31
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C26 C21 C15 C10 C1 C6 C24 C12
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+CPU_CORE
820U_E9_2_5V_M_R7
330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

@330U_V_2.5VK_R9

820U_E9_2_5V_M_R7
1 1 1 1 1 1 1 1 ESR <= 1.5m ohm
Capacitor > 1980uF
@ C8
C37

C47

@ C583

C576

C584

C585

@ C578
+ + + + + + + + North Side Secondary
South Side Secondary
2 2 2 2 2 2 2 2
B B

+VCCP

1
1 1 1 1 1 1
C591 + Place these inside
C43 C44 C45 C3 C4 C5 socket cavity on L8
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4> Description at page15.

U31A U31B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <29> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <29> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <29> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T6
HD4# HA7# <29> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T9
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T7
HD7# HA10# <29> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <29> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T12
HD9# HA12# <29> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <29> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T10
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <29> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <29> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T8
HD15# HA18# <29> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T16
HD16# HA19# <29> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T14
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <29> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <29> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <29> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <29> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 CLK_MCH_DREFCLK#

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# <15>
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 CLK_MCH_DREFCLK
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK <15>
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 MCH_SSCDREFCLK# MCH_SSCDREFCLK# <15>
H_D#31 T5 M_CLK_DDR#1 AT1 D41 MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 CLKREQB#
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ# CLKREQB# <15>
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 T17 PAD M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 T11 PAD AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 <13> M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R40 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R41 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

HD59# RESERVED2
R461

R462

H_D#60 AB5 <29> PM_BMBUSY# PM_BMBUSY# G28 F3

H_D#61 HD60# H_RESET# PM_EXTTS#0 PM_BMBUSY# RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> <13,14> PM_EXTTS#0 F25 PM_EXTTS0# RESERVED4 F7

RESERVED
PM
H_D#62 AD4 E8 H_ADS# <29,53> DPRSLPVR DPRSLPVR H26 AG11
HD62# HADS# H_ADS# <4> PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,28> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# ICH_POK PM_THERMTRIP# RESERVED6

HDPWR# J9 H_DPWR# <4> <29,44> ICH_POK AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 J19
HDRDY# H_DRDY# <4> <27,31,32,34,37> PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R98 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
H_VREF K13 D4 H_HITM# <27> MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# <4> ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# <4>
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4>
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4>
24.9_0402_1%

24.9_0402_1%

V_DDR_MCH_REF
1

trace width and

R466

R464

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 spacing is 20/20.
D6 H_RS#2
HRS2#
H_RS#[0..2] <4>
2

CALISTOGA_FCBGA1466~D +1.8V

1
R483

Layout Note: 100_0402_1% +3VS

2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / V_DDR_MCH_REF
<13,14> V_DDR_MCH_REF
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 10/20.

1 1 R481 R71
+VCCP +VCCP 10K_0402_5%
C663

100_0402_1% PM_EXTTS#0 2 1
+VCCP
2

2
221_0603_1%

221_0603_1%

R79
1

1
100_0402_1%

@ 10K_0402_5%
1

R38

R463

DPRSLPVR 1 2
R45

A A
2

H_SWNG0 H_SWNG1
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0402_1%

R37

R465

1
R42

C87

C82

C601

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

D D

U31D U31E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T18 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T13 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T19 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T15 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

D D

R89 +1.5VS_PCIE
U31C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38 PEG_RXP[0..15] <18>
F34 PEG_RXN0
LVDSA0+ EXP_RXN0 PEG_RXN1
<16> LVDSA0+ B37 LA_DATA0 EXP_RXN1 G38
<16> LVDSA1+ LVDSA1+ B34 H34 PEG_RXN2
LVDSA2+ LA_DATA1 EXP_RXN2 PEG_RXN3
<16> LVDSA2+ A36 LA_DATA2 EXP_RXN3 J38
L34 PEG_RXN4
LVDSA0- EXP_RXN4 PEG_RXN5
C37 LA_DATA#0 EXP_RXN5 M38
<16> LVDSA0- LVDSA1- PEG_RXN6
<16> LVDSA1- B35 LA_DATA#1 EXP_RXN6 N34
LVDSA2- A37 P38 PEG_RXN7
<16> LVDSA2- LA_DATA#2 EXP_RXN7
R34 PEG_RXN8
LVDSB0+ EXP_RXN8 PEG_RXN9
<16> LVDSB0+ F30 LB_DATA0 EXP_RXN9 T38
LVDSB1+ PEG_RXN10

LVDS
<16> LVDSB1+ D29 LB_DATA1 EXP_RXN10 V34
LVDSB2+ F28 W38 PEG_RXN11
<16> LVDSB2+ LB_DATA2 EXP_RXN11 PEG_RXN12
EXP_RXN12 Y34
LVDSB0- G30 AA38 PEG_RXN13
<16> LVDSB0- LB_DATA#0 EXP_RXN13
LVDSB1- D30 AB34 PEG_RXN14
<16> LVDSB1- LB_DATA#1 EXP_RXN14
LVDSB2- F29 AC38 PEG_RXN15
<16> LVDSB2- LB_DATA#2 EXP_RXN15 PEG_RXN[0..15] <18>
LVDSAC+ A32 D34 PEG_RXP0
<16> LVDSAC+ LA_CLK EXP_RXP0
LVDSAC- A33 F38 PEG_RXP1
<16> LVDSAC- LVDSBC+ LA_CLK# EXP_RXP1 PEG_RXP2
<16> LVDSBC+ E26 LB_CLK EXP_RXP2 G34
LVDSBC- E27 H38 PEG_RXP3
<16> LVDSBC- LB_CLK# EXP_RXP3
J34 PEG_RXP4

PCI-EXPRESS GRAPHICS
EXP_RXP4 PEG_RXP5
D32 LBKLT_CTL EXP_RXP5 L38
C GMCH_ENBKL PEG_RXP6 C
<16> GMCH_ENBKL J30 LBKLT_EN EXP_RXP6 M34
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 LCTLB_DATA EXP_RXP8 P34
EDID_CLK_LCD G26 R38 PEG_RXP9
<16> EDID_CLK_LCD LDDC_CLK EXP_RXP9
EDID_DAT_LCD G25 T34 PEG_RXP10
<16> EDID_DAT_LCD LDDC_DATA EXP_RXP10
<16> GMCH_LVDDEN GMCH_LVDDEN F32 V38 PEG_RXP11
LVDD_EN EXP_RXP11 PEG_RXP12
2 1 B38 LIBG EXP_RXP12 W34
R482 1.5K_0402_1% C35 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 LVREFH EXP_RXP14 AA34
C32 AB38 PEG_RXP15 PEG_M_TXP[0..15] <18>
LVREFL EXP_RXP15
F36 PEG_TXN0 C231 G71@ 0.1U_0402_16V4Z PEG_M_TXN0
TV_COMPS EXP_TXN0 PEG_TXN1 C661 G71@ 0.1U_0402_16V4Z PEG_M_TXN1
<17> TV_COMPS A16 TVDAC_A EXP_TXN1 G40
<17> TV_LUMA TV_LUMA C18 H36 PEG_TXN2 C230 G71@ 0.1U_0402_16V4Z PEG_M_TXN2
TV_CRMA TVDAC_B EXP_TXN2 PEG_TXN3 C659 G71@ 0.1U_0402_16V4Z PEG_M_TXN3
<17> TV_CRMA A19 TVDAC_C EXP_TXN3 J40

TV
L36 PEG_TXN4 C228 G71@ 0.1U_0402_16V4Z PEG_M_TXN4
EXP_TXN4
2 R58 1 J20 TV_IREF EXP_TXN5 M40 PEG_TXN5 C657 G71@ 0.1U_0402_16V4Z PEG_M_TXN5
4.99K_0402_1% N36 PEG_TXN6 C237 G71@ 0.1U_0402_16V4Z PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C655 G71@ 0.1U_0402_16V4Z PEG_M_TXN7
B16 TV_IRTNA EXP_TXN7 P40
B18 R36 PEG_TXN8 C238 G71@ 0.1U_0402_16V4Z PEG_M_TXN8
TV_IRTNB EXP_TXN8 PEG_TXN9 C653 G71@ 0.1U_0402_16V4Z PEG_M_TXN9
B19 TV_IRTNC EXP_TXN9 T40
V36 PEG_TXN10 C239 G71@ 0.1U_0402_16V4Z PEG_M_TXN10
EXP_TXN10 PEG_TXN11 C651 G71@ 0.1U_0402_16V4Z PEG_M_TXN11
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 Y36 PEG_TXN12 C250 G71@ 0.1U_0402_16V4Z PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C649 G71@ 0.1U_0402_16V4Z PEG_M_TXN13
EXP_TXN13 AA40
AB36 PEG_TXN14 C677 G71@ 0.1U_0402_16V4Z PEG_M_TXN14
EXP_TXN14 PEG_TXN15 C648 G71@ 0.1U_0402_16V4Z PEG_M_TXN15
EXP_TXN15 AC40 PEG_M_TXN[0..15] <18>
3VDDCCL C26
<17> 3VDDCCL DDCCLK
CRT

3VDDCDA C25 D36 PEG_TXP0 C229 G71@ 0.1U_0402_16V4Z PEG_M_TXP0

<17> 3VDDCDA DDCDATA EXP_TXP0
F40 PEG_TXP1 C662 G71@ 0.1U_0402_16V4Z PEG_M_TXP1
CRT_VSYNC EXP_TXP1 PEG_TXP2 C232 G71@ 0.1U_0402_16V4Z PEG_M_TXP2
<17> CRT_VSYNC H23 VSYNC EXP_TXP2 G36
<17> CRT_HSYNC CRT_HSYNC G23 H40 PEG_TXP3 C660 G71@ 0.1U_0402_16V4Z PEG_M_TXP3
B CRT_B HSYNC EXP_TXP3 PEG_TXP4 C233 G71@ 0.1U_0402_16V4Z PEG_M_TXP4 B
<17> CRT_B E23 BLUE EXP_TXP4 J36
D23 L40 PEG_TXP5 C658 G71@ 0.1U_0402_16V4Z PEG_M_TXP5
CRT_G BLUE# EXP_TXP5 PEG_TXP6 C234 G71@ 0.1U_0402_16V4Z PEG_M_TXP6
<17> CRT_G C22 GREEN EXP_TXP6 M36
B22 N40 PEG_TXP7 C656 G71@ 0.1U_0402_16V4Z PEG_M_TXP7
CRT_R GREEN# EXP_TXP7 PEG_TXP8 C235 G71@ 0.1U_0402_16V4Z PEG_M_TXP8
<17> CRT_R A21 RED EXP_TXP8 P36
B21 R40 PEG_TXP9 C654 G71@ 0.1U_0402_16V4Z PEG_M_TXP9
RED# EXP_TXP9 PEG_TXP10 C236 G71@ 0.1U_0402_16V4Z PEG_M_TXP10
EXP_TXP10 T36
V40 PEG_TXP11 C652 G71@ 0.1U_0402_16V4Z PEG_M_TXP11
EXP_TXP11 PEG_TXP12 PEG_M_TXP12
2 R65 1 J22 CRT_IREF EXP_TXP12 W36 C249 G71@ 0.1U_0402_16V4Z
255_0402_1% Y40 PEG_TXP13 C650 G71@ 0.1U_0402_16V4Z PEG_M_TXP13
EXP_TXP13 PEG_TXP14 C678 G71@ 0.1U_0402_16V4Z PEG_M_TXP14
EXP_TXP14 AA36
AB40 PEG_TXP15 C664 G71@ 0.1U_0402_16V4Z PEG_M_TXP15
EXP_TXP15

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCP
2

D5 +2.5VS
D D
@ CH751H-40_SC76 U31H
1 1

+VCCP H22 1 2
VCC_SYNC C162
R80 +2.5VS AC14 0.1U_0402_16V4Z
VTT0
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
@ 10_0402_5% W14 C30
VTT2 VCCTX_LVDS1 +1.5VS_PCIE R490
V14 A30
2

VTT3 VCCTX_LVDS2 0_0805_5%

T14
R14
VTT4
VTT5 VCC3G0 AB41 W=40 mils 2 1 +1.5VS

10U_1206_6.3V6M

10U_1206_6.3V6M
P14 VTT6 VCC3G1 AJ41
+1.5VS

220U_D2_4VM
N14 VTT7 VCC3G2 L41 1
M14 VTT8 VCC3G3 N41 1 1

C682
L14 R41 +
VTT9 VCC3G4
2

+2.5VS

C666

C665

0.1U_0402_16V4Z
AD13 VTT10 VCC3G5 V41
220U_D2_4VM

D19 AC13 Y41

VTT11 VCC3G6 2 2 2
AB13 VTT12 1
@ CH751H-40_SC76 1 AA13 AC33 +1.5VS_3GPLL
VTT13 VCCA_3GPLL

C225
Y13 G41 +2.5VS
1 1

VTT14 VCCA_3GBG
C610

+ W13 H41
VTT15 VSSA_3GBG 2 +1.5VS_DPLLA L28 +1.5VS_DPLLB L29
V13 VTT16
R520 +3VS U13 L7 BLM11A601S_0603 MBK160808_0603 MBK160808_0603
2 VTT17 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5VS 2 1 +1.5VS 2 1 +1.5VS

2200P_0402_50V7K
@ 10_0402_5% R13 F21
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z

330U_V_2.5VK_R9

UMA@ C616

0.1U_0402_16V4Z

330U_V_2.5VK_R9

UMA@ C645
0.1U_0402_16V4Z
N13 G21 close pin G41
2

VTT20 VSSA_CRTDAC2
M13 VTT21 1 1 1 1
L13 VTT22 1 1

C115

C116

C138

C226
+ +
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA CRTDAC: Route caps within
AA12 VTT24 VCCA_DPLLB C39 +1.5VS_DPLLB
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
2 2 250mil of Alviso. Route FB
W12 2 2 2 2
VTT26 within 3" of Calistoga
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
P12 +2.5VS
VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
+3VS_TVDACC +3VS +3VS_TVDACB +3VS +3VS_TVDACA +3VS

0.01U_0402_16V7K
4.7U_0805_10V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z
L12 VTT34 VCCA_TVBG H20 +3VS_TVBG
R11 G20 R52 R55 R44
VTT35 VSSA_TVBG
1 1 P11 VTT36 2 1 2 1 2 1
C612

C613

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
N11 1 1 0_0805_5% 0_0805_5% 0_0805_5%
VTT37

C160

C215

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19 1 1 1 1 1 1
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB 2 2

C110

C111

C114

C109

C107

C106
N10 VTT41 VCCA_TVDACB1 D20
M10 VTT42 VCCA_TVDACC0 E20 +3VS_TVDACC 2 2 2 2 2 2
P9 VTT43 VCCA_TVDACC1 F20
N9 VTT44
M9 VTT45 close pin A38
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48
M8 +3VS_TVBG +3VS
VTT49 R39
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28 2 1
M7 C28 0_0805_5%
VTT52 VCCD_LVDS2

2200P_0402_50V7K

0.1U_0402_16V4Z
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS_TVDAC 1 1
M6 VTT55 VCCDQ_TVDAC H19

C117
MCH_A6 A6 VTT56
0.47U_0603_10V7K

C112
R5 VTT57 VCCHV0 A23 +3VS 2 2
P5 VTT58 VCCHV1 B23
0.1U_0402_16V4Z

10U_1206_6.3V6M

1 N5 VTT59 VCCHV2 B25

C607

M5 VTT60 1 1
P4 VTT61 VCCAUX0 AK31
N4 VTT62 VCCAUX1 AF31
2
C124

C615

M4 VTT63 VCCAUX2 AE31

2 2
R3 VTT64 VCCAUX3 AC31
B P3 AL30 B
N3
VTT65
VTT66
VCCAUX4
VCCAUX5 AK30 PCI-E/MEM/PSB PLL decoupling
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30

R2 AH30 +1.5VS
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
+1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z

1 M2 AF30 R99 R46

VTT70 VCCAUX9
C81

MCH_D2 D2 AE30 0_0603_5% 0_0603_5%

VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1 2 1 2 1
0.22U_0603_10V7K

2200P_0402_50V7K
0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C163

1 P1 VTT74 VCCAUX13 AG29

C597

N1 VTT75 VCCAUX14 AF29 1 1 1 1 1 1

2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

C174

C248

C280

C113

C614

C105
VCCAUX16 AD29
2
1 VCCAUX17 AC29
2 2 2 2 2 2
C596

VCCAUX18 AG28
VCCAUX19 AF28
AE28 @ @
2 VCCAUX20
VCCAUX21 AH22
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
+1.5VS_MPLL R459 +1.5VS_HPLL R460
AF13 VCCAUX36 VCCAUX27 P19
AE13 P16 0_0603_5% 0_0603_5%
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
AE12 VCCAUX39 VCCAUX30 P15

0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

10U_1206_6.3V6M
AD12 VCCAUX40 VCCAUX31 AH14

1 1 1 1
CALISTOGA_FCBGA1466~D

C604

C593

C605

C594
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U31F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U31G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C669
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C668
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30
C86

C85
C164

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG6 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 10 = 1.05V*(Default)
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG10 CFG18 01 = 1.5V
1U_0603_10V4Z
10U_1206_6.3V6M

10U_1206_6.3V6M

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C83

C84
C222

C128
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C173

C600

C139

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
@ 220U_D2_4VM

AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22

C125
+ R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
C595

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22

2 R48
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R54 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R51 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 <7> CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R47 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11

330U_V_2.5VK_R9
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19

10U_1206_6.3V6M

10U_1206_6.3V6M
R20 N26 AW19 R49 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
V19 AE26 N25 AU19 1 1 R50 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 <7> CFG13

C599
U19 AE25 M25 AT19 +
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62

C609

C641
@ 220U_D2_4VM

T19 AE24 L25 AR19 R53 1 2 @ 2.2K_0402_5%

VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 <7> CFG16
1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19
2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
C606

AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18

Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R74 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R82 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R87 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C104
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C603

C602

AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

U31I U31J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 16, 2005 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14>

<8> DDR_A_D[0..63] JP21

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C368

C369
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C130

C129

C131

C204

C206

C180

C143

C193

C187
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C643

C642

C640

C639

C192

C175

C166

C630

C629

C158

C145

C136

C628

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9VS NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP25 RP27 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP41,all 171 172
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D54 173 DQ50 DQ54 174 DDR_A_D51
DDR_A_D50 175 176 DDR_A_D55
RP24 56_0404_4P2R_5% RP15 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D61 179 180 DDR_A_D57
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D60 181 DQ57 DQ61 182 DDR_A_D56
183 VSS VSS 184
RP6 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 DDR_A_D59 189 190
DDR_A_D58 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP23 56_0404_4P2R_5% RP12 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 <14,15> CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 CLK_SMBCLK 197 198
<14,15> CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP22 56_0404_4P2R_5% RP9 56_0404_4P2R_5%

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C80 FOX_ASOA426-M4R-TR

R33

R35
A A
CONN@
RP21 56_0404_4P2R_5% RP3
DDR_CS1_DIMMA# 2
56_0404_4P2R_5% 0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 M_ODT0
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP18 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA Top side
3 2 DDR_A_MA11 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13>
<8> DDR_B_DM[0..7] JP24

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C366

C367
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C132

C214

C205

C159

C157

C169

C142

C141

C140
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C156

C146

C137

C202

C179

C170

C165

C147

C144

C133

C191

C176

C168

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP42,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP10 RP16 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP7 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_B_MA11 177 178
DDR_B_MA10 DDR_CKE3_DIMMB DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP8 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_BS#1 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP5 56_0404_4P2R_5% RP14 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_CS2_DIMMB# 1 4 4 1 DDR_B_MA6 193 194 DDR_B_D63
DDR_B_RAS# DDR_B_MA7 CLK_SMBDATA VSS DQ63
2 3 3 2 <13,15> CLK_SMBDATA 195 SDA VSS 196
CLK_SMBCLK 197 198 R32
<13,15> CLK_SMBCLK SCL SAO
RP4 56_0404_4P2R_5% RP11 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA2

1
10K_0402_5%
DDR_B_WE# 2 3 3 2 DDR_B_MA4 1 10K_0402_5%

R34
A RP1 C79 FOX_ASOA426-M4R-TR A
56_0404_4P2R_5% RP2 56_0404_4P2R_5% CONN@
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 DDR_B_MA13
M_ODT2
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2
STANDARD

2
56_0404_4P2R_5% RP19
4 1 DDR_B_BS#2 Bottom side
3 2 DDR_CKE2_DIMMB

56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS +CK_VDD_MAIN1

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
+3VS 1 2
R299 R323 R324 0_0805_5% 1 1 1 1 1 1 1
0 0 1 133 100 33.3 C456 C422 C431 C440 C450 C441 C430
2.2K_0402_5% 2.2K_0402_5%
Q12 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
CLK_SMBDATA

S
<29,34,37> ICH_SMBDATA 1 3
Table : ICS954306 +CK_VDD_MAIN2

G
2
D D
FSB Frequency Selet: +3VS 1 2 1 2 +CK_VDD_REF
+3VS R174 0_0805_5% 1 1 1 R188
C416 C418 C417 1_0805_1%
Stuff CLK_Ra CLK_Rb CLK_Rc 1 2 +CK_VDD_48

2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R187

G
CPU Driven 2 2 2 2.2_0805_1%
CLK_SMBCLK
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf
<29,34,37> ICH_SMBCLK 1 3

S
2N7002_SOT23
Stuff CLK_Rd CLK_Re CLK_Rf Q15
533MHz C419 2 1 22P_0402_50V8J
+CK_VDD_MAIN1

1
No Stuff CLK_Ra CLK_Rb CLK_Rc U13 Place crystal within
Y2
CLK_XTAL_IN 14.31818MHZ_20P_1BX14318BE1A
500 mils of CK410
16 VDD X1 57
Stuff CLK_Rd CLK_Rf
Place near U54

2
+CK_VDD_48 10 56 CLK_XTAL_OUT 2 1
VDD48 X2 C421 22P_0402_50V8J
667MHz 1
Place these components
No Stuff CLK_Ra CLK_Rb CLK_Rc C424 5 VDDPCI
28 1 2
CLK_Re 0.1U_0402_16V4Z
2
24 VDDSRC
SATACLKT R305 9LP@ 0_0402_5% near each pin within 40
29 1 2
+VCCP
33 VDDSATA
SATACLKC R311 9LP@ 0_0402_5% mils.
1
C425 41 52 CPU_BCLK 1 2 CLK_CPU_BCLK
VDDSRC CPUCLKT0 CLK_CPU_BCLK <4>
R239 10_0402_5%
2

0.1U_0402_16V4Z 50 51 CPU_BCLK# 1 2 CLK_CPU_BCLK# CLK_CPU_BCLK 2 1

2 VDDCPU CPUCLKC0 CLK_CPU_BCLK# <4>
@ R232 R247 10_0402_5% R240 @ 49.9_0402_1%
56_0402_5% +CK_VDD_REF 55 CLK_CPU_BCLK# 2 1
R237 R236 12_0402_5% VDDREF MCH_BCLK CLK_MCH_BCLK R248 @ 49.9_0402_1%
CLK_Rd CPUCLKT1 49 1 2 CLK_MCH_BCLK <7>
8.2K_0402_5% <29> CLK_48M_ICH CLK_48M_ICH 2 1 R254 10_0402_5%
1

FSA 2 1 1 2 CLK_48M_CB 2 1 FSA 11 48 MCH_BCLK# 1 2 CLK_MCH_BCLK# CLK_MCH_BCLK 2 1

C MCH_CLKSEL0 <7> <32> CLK_48M_CB FSLA/USB_48MHz CPUCLKC1 CLK_MCH_BCLK# <7> C
R243 12_0402_5% R258 10_0402_5% R255 @ 49.9_0402_1%
1 2 R227 FSB 15 CLK_MCH_BCLK# 2 1
<5> CPU_BSEL0 FSLB/TEST_MODE
R231 1K_0402_5% 2 1 +3VS R259 @ 49.9_0402_1%
0_0402_5% <29> CLK_14M_ICH CLK_14M_ICH 2 1 CLKREF1 59 R218 @ 10K_0402_5%
FSLC/TEST_SEL/REF1
1

CLK_Ra R230 33_0402_5% 64 CLKREQA#

*CLKREQA# CLKREQA# <37>
R228
18 SSCDREFCLK 1 2 MCH_SSCDREFCLK MCH_SSCDREFCLK 1 2
LCDCLK_SST/SRCCLKT0 MCH_SSCDREFCLK <7>
@ 1K_0402_5% 2.4K_0402_1%1 2 R266 CLKIREF 46 R257 UMA@ 10_0402_5% R256 @ 49.9_0402_1%
IREF SSCDREFCLK#1 MCH_SSCDREFCLK# MCH_SSCDREFCLK# 1
19 2 MCH_SSCDREFCLK# <7> 2
2

LCDCLK_SSC/SRCCLKC0 R270 UMA@ 10_0402_5% R269 @ 49.9_0402_1%

61 CPU_STOP#
H_STP_CPU# CLK_PCIE_MCARD 1 2
<29> H_STP_CPU#
H_STP_PCI# 8 22 PCIE_MCARD 1 2 CLK_PCIE_MCARD R281 @ 49.9_0402_1%
+VCCP <29> H_STP_PCI# PCI/SRC_STOP# SRCCLKT2 CLK_PCIE_MCARD <37>
CLK_ENABLE# R282 10_0402_5% CLK_PCIE_MCARD#1 2
<53> CLK_ENABLE#
9 23 PCIE_MCARD#1 2 CLK_PCIE_MCARD# R283 @ 49.9_0402_1%
Vtt_PwrGd#/PD SRCCLKC2 CLK_PCIE_MCARD# <37>
R284 10_0402_5% CLK_MCH_3GPLL 1 2
2

CLK_PCI_ICH 2 R229 1 PCI_ICH 7 R287 @ 49.9_0402_1%

<27> CLK_PCI_ICH **SEL_LCDCLK#/PCICLK_F1
R201 33_0402_5% 30 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_MCH_3GPLL# 1 2
SATA1/SRCCLKT4 CLK_PCIE_SATA <28>
R297 10_0402_5% R291 @ 49.9_0402_1%
@ 1K_0402_5% 60 31 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_VGA 1 2
REF0/PCICLK1 SATA1/SRCCLKC4 CLK_PCIE_SATA# <28>
R304 10_0402_5% R267 @ 49.9_0402_1%
1

FSB 1 2 33_0402_5% 2 1 R206 PCI_MINI 62 2 1 +3VS CLK_PCIE_VGA# 1 2

MCH_CLKSEL1 <7> <36> CLK_PCI_MINI *REQ_SEL/PCICLK2 R226 @ 10K_0402_5% R275 @ 49.9_0402_1%
1 2 R200 10K_0402_5%2 1 R216 1 63 CLKREQB# CLK_PCIE_ICH 1 2
<5> CPU_BSEL1 *SEL_PCI1/PCICLK3 *CLKREQB# CLKREQB# <7>
R191 1K_0402_5% R295 @ 49.9_0402_1%
0_0402_5% +3VS 33_0402_5% 2 1 R215 PCI_EC 2 20 PCIE_VGA 1 2 CLK_PCIE_VGA CLK_PCIE_ICH# 1 2
<44> CLK_PCI_EC **SEL_SATA1/PCICLK4 SRCCLKT1 CLK_PCIE_VGA <18>
1

CLK_Rb R268 G71@ 10_0402_5% R302 @ 49.9_0402_1%

@ R199 @ 33_0402_5% 2 1 R225 PCI_SIO 3 21 PCIE_VGA# 1 2 CLK_PCIE_VGA# CLK_MCH_DREFCLK 1 2
<42> CLK_PCI_SIO **SEL_SATA2/PCICLK5 SRCCLKC1 CLK_PCIE_VGA# <18>
1

R276 G71@ 10_0402_5% R245 @ 49.9_0402_1%

0_0402_5% R589 <32> CLK_PCI_PCM 33_0402_5% 2 1 R224 PCI_PCM 6 CLK_MCH_DREFCLK#1 2
PCICLK6 MCH_3GPLL CLK_MCH_3GPLL R252 @ 49.9_0402_1%
CLK_Re 26 1 2 CLK_MCH_3GPLL <7>
2

100K_0402_5% SRCCLKT3 R288 10_0402_5% CLK_PCIE_SATA 1 2

27 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# R296 @ 49.9_0402_1%
CLK_MCH_3GPLL# <7>
2

B PCI_PCM CLK_SMBDATA SRCCLKC3 R292 10_0402_5% CLK_PCIE_SATA# 1 B

<13,14> CLK_SMBDATA 54 SDATA 2
R303 @ 49.9_0402_1%
<13,14> CLK_SMBCLK CLK_SMBCLK 53 35 PCIE_ICH 1 2 CLK_PCIE_ICH CLK_CPU_XDP 2 1
SCLK SATA2/SRCCLKT5 CLK_PCIE_ICH <29>
R294 10_0402_5% R279 @49.9_0402_1%
34 PCIE_ICH# 1 2 CLK_PCIE_ICH# CLK_CPU_XDP# 2 1
+VCCP SATA2/SRCCLKC5 CLK_PCIE_ICH# <29>
R301 10_0402_5% R272 @ 49.9_0402_1%
CLK_PCIE_NC1 2 1
<7> CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 13 2 1 CLKREQC# R286 @ 49.9_0402_1%
DOTT_96MHz CLKREQC# <34>
2

R246 UMA@ 10_0402_5% R273 10K_0402_5% CLK_PCIE_NC1# 2 1

R202 <7> CLK_MCH_DREFCLK# CLK_MCH_DREFCLK#1 2 MCH_DREFCLK# 14 45 CPU_XDP 1 2 CLK_CPU_XDP R290 @ 49.9_0402_1%
R253 UMA@ 10_0402_5% DOTC_96MHz *CPUCLKT2_ITP/CLKREQC# R278 @ 10_0402_5% CLK_PCIE_NC2 1 2
R205 @ 1K_0402_5% 37 PCIE_NC1 1 2 CLK_PCIE_NC1 R318 @ 49.9_0402_1%
SRCCLKT6 CLK_PCIE_NC1 <34>
8.2K_0402_5% R285 17@ 10_0402_5% CLK_PCIE_NC2# 1 2
1

CLKREF1 2 1 1 2 36 PCIE_NC1# 1 2 CLK_PCIE_NC1# R319 @ 49.9_0402_1%

MCH_CLKSEL2 <7> SRCCLKC6 CLK_PCIE_NC1# <34>
4 R289 17@ 10_0402_5%
R184 GND
<5> CPU_BSEL2 1 2
R177 1K_0402_5% 12 43
0_0402_5% GND SRCCLKT8
1

CLK_Rc 17 GND SRCCLKC8 42

@ R183
58 2 1 CLKREQD#
GND CLKREQD# <34>
0_0402_5% R277 10K_0402_5%
CLK_Rf 47 44 CPU_XDP# 1 2 CLK_CPU_XDP#
2

GNDCPU *CPUCLKC2_ITP/CLKREQD# R271 @ 10_0402_5%

LCD clock select Pin44/45 function select 25 39 PCIE_NC2 1 2 CLK_PCIE_NC2 CLKREQA# C802 1 2 1000P_0402_50V7K
GNDSRC SRCCLKT7 CLK_PCIE_NC2 <34>
R309 15.4@ 10_0402_5%
+3VS +3VS +3VS 40 38 PCIE_NC2# 1 2 CLK_PCIE_NC2# CLKREQB# C803 1 2 1000P_0402_50V7K
GNDSRC SRCCLKC7 CLK_PCIE_NC2# <34>
R310 15.4@ 10_0402_5%
32 CLKREQC# C804 1 2 1000P_0402_50V7K
GNDSATA
1

R235 R233 R312 CLKREQD# C805 1 2 1000P_0402_50V7K

ICS954306_TSSOP64
A 10K_0402_5% @ 10K_0402_5% 10K_0402_5% A
* Internal Pull-Up Resistor
2

CLK_ENABLE# PCI_ICH PCI_MINI ** Internal Pull-Down Resistor

1

R238 R308

10K_0402_5% @ 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
High:Pin18/19 = 100MHz High:Pin44/45 = CLKREQ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
*Low:Pin18/19 = 96MHz *Low:Pin44/45 = CPUCLK2_ITP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2841
Date: Thursday, December 15, 2005 Sheet 15 of 60
5 4 3 2 1
 A B C D E F G H

LCD Panel & inverter Connector

1 JP2 UMA 1
WL_LED# LVDSAC+ +3VS
+3VS <37,42> WL_LED# 39 40 LVDSAC+ <9>
DISPOFF# LVDSAC-
INVT_PWM 37 38 LVDSAC- <9>
<44> INVT_PWM 35 36

2
R434 DAC_BRIG LVDSA1-
<44> DAC_BRIG 33 34 LVDSA1- <9>
1 2 EDID_CLK_LCD 31 32
LVDSA1+ LVDSA1+ <9> R430
10K_0402_5% EDID_CLK_LCD
<9> EDID_CLK_LCD 29 30
R435 EDID_DAT_LCD LVDSBC+ 4.7K_0402_5%
<9> EDID_DAT_LCD 27 28 LVDSBC+ <9>
1 2 EDID_DAT_LCD LVDSBC-
LVDSBC- <9>
D17

1
10K_0402_5% 25 26 CH751H-40_SC76
+5VS 23 24 LVDSB1- 1 2 DISPOFF#
21 22 LVDSB1- <9> <44> BKOFF#
+3VS LVDSB1+
19 20 LVDSB1+ <9>
LVDSB0+
17 18 LVDSB0+ <9>
LVDSB0- D16
+LCDVDD 15 16 LVDSB0- <9>
LVDSB2+ UMA@ CH751H-40_SC76
13 14 LVDSB2- LVDSB2+ <9>
11 12 <9> GMCH_ENBKL 1 2
LVDSB2- <9>
9 10

2
LVDSA0-
INVPWR_B+ 7 8 LVDSA0- <9>
LVDSA0+ R431
5 6 LVDSA2- LVDSA0+ <9> UMA@ 100K_0402_5%
3 4 LVDSA2- <9>
LVDSA2+
1 2 LVDSA2+ <9>

1
ACES_88107-4000G

2 B+ INVPWR_B+ 2

L25 1 2 FBMA-L10-201209-301LMT
JP1 Discrete
WL_LED# LVDS_AC-
DISPOFF# 39 40 LVDS_AC+ LVDS_AC- <18> @ L24
37 38 LVDS_AC+ <18> 1 2 FBMA-L10-201209-301LMT
INVT_PWM 1 1
DAC_BRIG 35 36 LVDS_A2+ C806 C807
33 34 LVDS_A2+ <18>
LVDS_A2-
31 32 LVDS_A2- <18>
LCD_I2C_CLK_C LVDS_A1+ LVDS_A1+ <18>
<18> LCD_I2C_CLK_C 29 30 2 2
LCD_I2C_DAT_C LVDS_A1-
<18> LCD_I2C_DAT_C 27 28 LVDS_A1- <18>
LVDS_A0+
25 26 LVDS_A0- LVDS_A0+ <18>
+5VS 23 24 LVDS_A0- <18> 0.1U_0402_16V4Z 68P_0402_50V8K
21 22
+3VS 19 20 LVDS_B1-
17 18 LVDS_B1- <18>
LVDS_B1+
+LCDVDD 15 16 LVDS_B1+ <18>
LVDS_B2+
13 14 LVDS_B2- LVDS_B2+ <18>
11 12 LVDS_B0+ LVDS_B2- <18>
9 10 LVDS_B0+ <18>
LVDS_B0-
INVPWR_B+ 7 8 LVDS_B0- <18>
5 6 LVDS_BC+
3 4 LVDS_BC+ <18>
LVDS_BC-
1 2 LVDS_BC- <18>

ACES_88107-4000G

3 3

+LCDVDD +5VALW

+LCDVDD +3VS
1

Q33
2

R429 SI2301BDS_SOT23
R428
100_0402_1% 100K_0402_5%

S
1 3

D
1 2

G
2
2N7002_SOT23 0.047U_0402_16V4Z
2
Q32 G
S 1 1 1 1
3

C572 C574 C575

C573
1

4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2
<9> GMCH_LVDDEN 2 R433 1 Q31
UMA@ 0_0402_5% DTC124EK_SC59

ENVDD 2 0.1U_0402_16V4Z
<18> ENVDD
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 16 of 60
A B C D E F G H
 A B C D E

+R_CRT_VCC , +CRTVDD (40mils) NZQA5V6AXV5T1_SOT533-5

+5VS +CRTVDD
+R_CRT_VCC
D1 F1 3 4
2 1 1 2

R15 RB411D_SOT23 1.1A_6VDC_FUSE 1

1 2 2
<18> M_RED
G71@ 0_0402_5% CRT CONNECTOR C582
R11 0.1U_0402_16V4Z
2
<18> M_GRN 1 2
G71@ 0_0402_5% 1 5
1
R8 EMI 1
1 2 JP3
<18> M_BLU
G71@ 0_0402_5% ALLTO_C10510-115A5-L_15P-s
L3 6 D46
R13 MBK2012800YZF M_SEN# 11
1 2 CRTR 1 2 CRTL_R 1
<9> CRT_R
UMA@ 0_0402_5% L2 7
R12 MBK2012800YZF EMI 12 16
CLOSE TO JP3
1 2 CRTG 1 2 CRTL_G 2 17
<9> CRT_G
UMA@ 0_0402_5% L1 8
R9 MBK2012800YZF 13
1 2 CRTB 1 2 CRTL_B 3 R20
<9> CRT_B

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

33P_0402_25V8K

33P_0402_25V8K

33P_0402_25V8K
UMA@ 0_0402_5% +CRTVDD 9 1 2 M_DDCDATA <18>

2
75_0402_5%

75_0402_5%

75_0402_5%
1 1 1 1 1 1 14 G71@ 0_0402_5%
4
+5VS EMI

R16 4.7K_0402_5%

R443 4.7K_0402_5%
10 R446

R7
R14

R10
C580 15 1 2
2 2 2 2 2 2 M_DDCCLK <18>

C29

C20

C25

C17
C9

C7
1 2 5 G71@ 0_0402_5%

1
Q1
5

1
0.1U_0402_16V4Z U29 2N7002_SOT23
R449 @ @ @ R21
P

OE#

CR THSYNC CRT_HSYNC_R CRT_HSYNCRFL 3V_DDCDA

S
<9> CRT_HSYNC 1 2 2 A Y 4 1 2 1 3 1 2 3VDDCDA <9>
UMA@ 0_0402_5% L27 UMA@ 0_0402_5%
G

R450 74AHCT1G125GW_SOT353-5 FBM-L11-160808-800LMT_0603 Q34

1 2 2N7002_SOT23

G
<18> M_HSYNC
3

2
G71@ 0_0402_5% 1 2 CRT_VSYNCRFL R445

220P_0402_25V8K

220P_0402_25V8K
L26 3V_DDCCL

S
1 3 1 2 3VDDCCL <9>

10P_0402_50V8K

C579 10P_0402_50V8K
FBM-L11-160808-800LMT_0603 1 1 1 1 UMA@ 0_0402_5%

R19 R444

G
2
5

U28 2 2 2 2

C581
R447 2.2K_0402_5%
P

OE#

2 CRTVSYNC CRT_VSYNC_R 2
<9> CRT_VSYNC 1 2 2 A Y 4
UMA@ 0_0402_5%
+3VS
G

C46

C577
R448 74AHCT1G125GW_SOT353-5
1 2 2.2K_0402_5%
<18> M_VSYNC
3

G71@ 0_0402_5%

R25
1 2 TVLUMA
<18> M_LUMA TVLUMA <46>
G71@ 0_0402_5%
R30 TVCRMA
<18> M_CRMA 1 2
TVCRMA <46> TV-Out Connector
G71@ 0_0402_5% TVCOMPS
R27
TVCOMPS <46> S-Video
<18> M_COMP 1 2
G71@ 0_0402_5%
EMI L4
R24 MBC1608121YZF_0603
1 2 TVLUMA 1 2 LUMA_CL
<9> TV_LUMA
UMA@ 0_0402_5%
L6 JP17
R31 MBC1608121YZF_0603 1
TVCRMA CRMA_CL 1
<9> TV_CRMA 1 2 1 2 2 2
3 UMA@ 0_0402_5% 3
3 3
4 4
L5 5
R26 MBC1608121YZF_0603 5
6 6 GND 8
1 2 TVCOMPS 1 2 COMPS_CL 7 9
<9> TV_COMPS UMA@ 0_0402_5% 7 GND
270P_0402_50V7K

270P_0402_50V7K

270P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
SUYIN_030107FR007G317ZR
1

1
75_0402_5%

75_0402_5%

75_0402_5%

1 1 1 1 1 1
R28

R29

R23

C75

C77

C49

C74

C76

C50
2 2 2 2 2 2
R22
2

1 2 TVGND

0_0805_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 17 of 60
A B C D E
 5 4 3 2 1

U33A
PEG_RXP[0:15]
PEG_RXP[0:15] <9>
PEG_M_TXP0 AK13 Part 1 of 6 K3
PEG_M_TXN0 PEX_RX0 GPIO0 PEG_RXN[0:15]
AK14 PEX_RX0_N GPIO1 H1 PEG_RXN[0:15] <9>
PEG_M_TXP1 AM14 K5
PEG_M_TXN1 PEX_RX1 GPIO2 ENVDD PEG_M_TXP[0..15]
AM15 PEX_RX1_N GPIO3 G5 ENVDD <16> PEG_M_TXP[0..15] <9>
PEG_M_TXP2 AL15 E2 NV_ENBKL
PEX_RX2 GPIO4 NV_ENBKL <44> PEG_M_TXN[0..15]
PEG_M_TXN2 AL16 J5
PEX_RX2_N GPIO5 PEG_M_TXN[0..15] <9>
PEG_M_TXP3 AK16 G6
PEG_M_TXN3 PEX_RX3 GPIO6 For VDD_CORE voltage select
AK17 PEX_RX3_N GPIO7 K6
PEG_M_TXP4 AL17 E1 THER_ALERT# U33D
PEG_M_TXN4 PEX_RX4 GPIO8
AL18 PEX_RX4_N GPIO9 D2 <16> LVDS_AC+ AK9 IFPA_TXC NC_0 B32
PEG_M_TXP5 AM18 H5 AJ9 Part 4 of 6 C20
PEG_M_TXN5 PEX_RX5 GPIO10 GPIO11 <16> LVDS_AC- IFPA_TXC_N NC_1
AM19 PEX_RX5_N GPIO11 F4 <16> LVDS_A0+ AH6 IFPA_TXD0 NC_2 D1
PEG_M_TXP6 AK19 E3 AJ6 J6
D PEG_M_TXN6 PEX_RX6 GPIO12 <16> LVDS_A0- IFPA_TXD0_N NC_3 D
AK20 PEX_RX6_N <16> LVDS_A1+ AH8 IFPA_TXD1 NC_4 U3
PEG_M_TXP7 AL20 P2 PEX_PLL_TERM AH7 U4
PEX_RX7 MIOAD0 PEX_PLL_TERM <26> <16> LVDS_A1- IFPA_TXD1_N NC_5
PEG_M_TXN7 AL21 N2 SUB_VENDOR AJ8 U5
PEX_RX7_N MIOAD1 SUB_VENDOR <26> <16> LVDS_A2+ IFPA_TXD2 NC_6
PEG_M_TXP8 AM21 N1 AK8 U6
PEG_M_TXN8 PEX_RX8 MIOAD2 <16> LVDS_A2- IFPA_TXD2_N NC_7
AM22 PEX_RX8_N MIOAD3 N3 AJ5 IFPA_TXD3 NC_8 V1
PEG_M_TXP9 AK22 M1 AH5 V3
PEG_M_TXN9 PEX_RX9 MIOAD4 IFPA_TXD3_N NC_9
AK23 PEX_RX9_N MIOAD5 M3 <16> LVDS_BC+ AK4 IFPB_TXC NC_10 V4
PEG_M_TXP10 AL23 P5 PEX_CFG0 AL4 V5
PEX_RX10 MIOAD6 PEX_CFG0 <26> <16> LVDS_BC- IFPB_TXC_N NC_11

DVO / GPIO
PEG_M_TXN10 AL24 N6 AM6 V6

NC
PEG_M_TXP11 PEX_RX10_N MIOAD7 PEX_CFG1 <16> LVDS_B0+ IFPB_TXD4 NC_12
AM24 PEX_RX11 MIOAD8 N5 PEX_CFG1 <26> <16> LVDS_B0- AM5 IFPB_TXD4_N NC_13 W1
PEG_M_TXN11 AM25 M4 PEX_CFG2 AM7 W3
PEX_RX11_N MIOAD9 PEX_CFG2 <26> <16> LVDS_B1+ IFPB_TXD5 NC_14
PEG_M_TXP12 AK25 L4 AL7 W4
PEG_M_TXN12 PEX_RX12 MIOAD10 <16> LVDS_B1- IFPB_TXD5_N NC_15
AK26 PEX_RX12_N MIOAD11 L5 <16> LVDS_B2+ AK6 IFPB_TXD6 NC_16 W5
PEG_M_TXP13 AL26 AK5 Y5

LVDS/TMDS
PEG_M_TXN13 PEX_RX13 <16> LVDS_B2- IFPB_TXD6_N NC_17
AL27 PEX_RX13_N MIOA_HSYNC R3 1 2 MIOA_VDDQ AK7 IFPB_TXD7 NC_18 Y6
PEG_M_TXP14 AM27 R1 R101 @ 2K_0402_5% AL8 Y30
PEG_M_TXN14 PEX_RX14 MIOA_VSYNC R467 IFPB_TXD7_N NC_19
AM28 PEX_RX14_N MIOA_DE P1 1 2 NC_20 AC26
PEG_M_TXP15 AL28 P3 R100 @ 2K_0402_5% 1 2 AL5 AG12
PEG_M_TXN15 PEX_RX15 MIOA_CTL3 R115 @ 1K_0402_5% IFPAB_RSET NC_21
AL29 PEX_RX15_N NC_22 AH13
MIOA_CLKIN M5 2 1 AM2 IFPC_TXC NC_23 AM8
PEG_RXP0 128@ 0.1U_0402_16V4Z 1 2 C122 PEG_DTXP0 AJ15 R4 128@ 10K_0402_5% AM3 AM9
PEG_RXN0 128@ 0.1U_0402_16V4Z 1 C123 PEG_DTXN0 AK15 PEX_TX0 MIOA_CLKOUT IFPC_TXC_N NC_24
2 PEX_TX0_N MIOA_CLKOUT_N P4 AE2 IFPC_TXD0 NC_25 AM10
PEG_RXP1 128@ 0.1U_0402_16V4Z 1 2 C626 PEG_DTXP1 AH16 AE1
PEG_RXN1 128@ 0.1U_0402_16V4Z 1 C625 PEG_DTXN1 AG16 PEX_TX1 IFPC_TXD0_N
2 PEX_TX1_N MIOA_VREF L2 AF1 IFPC_TXD1 BUFRST_N F3
PEG_RXP2 128@ 0.1U_0402_16V4Z 1 2 C88 PEG_DTXP2 AG17 AF2 AE26
PEG_RXN2 128@ 0.1U_0402_16V4Z 1 C89 PEG_DTXN2 AH17 PEX_TX2 RAM_CFG0 IFPC_TXD1_N MEMSTRAPSEL0 FAE recommand 6/29
2 PEX_TX2_N MIOBD0 AC3 RAM_CFG0 <26> AG1 IFPC_TXD2 MEMSTRAPSEL1 AD26
PEG_RXP3 128@ 0.1U_0402_16V4Z 1 2 C90 PEG_DTXP3 AG18 AC1 RAM_CFG1 AH1 AH31

GENERAL
PEX_TX3 MIOBD1 RAM_CFG1 <26> IFPC_TXD2_N MEMSTRAPSEL2

PCI EXPRESS
PEG_RXN3 128@ 0.1U_0402_16V4Z 1 2 C91 PEG_DTXN3 AH18 AC2 CRYSTAL_0 AG3 AH32
PEX_TX3_N MIOBD2 CRYSTAL_0 <26> IFPD_TXC MEMSTRAPSEL3 +3VS
PEG_RXP4 128@ 0.1U_0402_16V4Z 1 2 C92 PEG_DTXP4 AK18 AB2 PCI_DEVID2 AH2 T3
PEX_TX4 MIOBD3 PCI_DEVID2 <26> IFPD_TXC_N STEREO
PEG_RXN4 128@ 0.1U_0402_16V4Z 1 2 C93 PEG_DTXN4 AJ18 AB1 PCI_DEVID0 AK1 F1 R105
PEX_TX4_N MIOBD4 PCI_DEVID0 <26> IFPD_TXD4 STRAP
PEG_RXP5 128@ 0.1U_0402_16V4Z 1 2 C624 PEG_DTXP5 AJ19 AA1 PCI_DEVID1 AJ1 M6 1 2
PEX_TX5 MIOBD5 PCI_DEVID1 <26> IFPD_TXD4_N SWAPRDY_A
PEG_RXN5 128@ 0.1U_0402_16V4Z 1 2 C623 PEG_DTXN5 AH19 AB3 CRYSTAL_1 AL2 J1 D- 10K_0402_5%
C PEX_TX5_N MIOBD6 CRYSTAL_1 <26> IFPD_TXD5 THERMDN C
PEG_RXP6 128@ 0.1U_0402_16V4Z 1 2 C94 PEG_DTXP6 AG20 AA3 MOBILE_MODE AL1 K1 D+ 128@
PEX_TX6 MIOBD7 MOBILE_MODE <26> IFPD_TXD5_N THERMDP
PEG_RXN6 128@ 0.1U_0402_16V4Z 1 2 C95 PEG_DTXN6 AH20 AC5 RAM_CFG2 AJ2
PEX_TX6_N MIOBD8 RAM_CFG2 <26> IFPD_TXD6
PEG_RXP7 128@ 0.1U_0402_16V4Z 1 2 C96 PEG_DTXP7 AG21 AB5 RAM_CFG3 AJ3 AA7
PEX_TX7 MIOBD9 RAM_CFG3 <26> IFPD_TXD6_N ROM_SCLK
PEG_RXN7 128@ 0.1U_0402_16V4Z 1 2 C97 PEG_DTXN7 AH21 AB4 W2
PEG_RXP8 128@ 0.1U_0402_16V4Z 1 C622 PEG_DTXP8 AK21 PEX_TX7_N MIOBD10 PCI_DEVID3 ROM_SI
PEG_RXN8 128@ 0.1U_0402_16V4Z 1
2
2 C621 PEG_DTXN8 AJ21 PEX_TX8 MIOBD11 AA5 PCI_DEVID3 <26> 1 2 AH3
R88 @ 1K_0402_5% IFPCD_RSET SERIAL ROM_SO AA6
AA4
PEG_RXP9 128@ 0.1U_0402_16V4Z 1 C98 PEG_DTXP9 AJ22 PEX_TX8_N ROMCS_N
2 PEX_TX9 MIOB_HSYNC AF3
PEG_RXN9 128@ 0.1U_0402_16V4Z 1 2 C99 PEG_DTXN9 AH22 AE3
PEG_RXP10 128@ 0.1U_0402_16V4Z 1 C100 PEG_DTXP10 AG23 PEX_TX9_N MIOB_VSYNC G71@ NV72/73M_BGA820
2 PEX_TX10 MIOB_DE AD1
PEG_RXN10 128@ 0.1U_0402_16V4Z 1 2 C101 PEG_DTXN10 AH23 AD3
PEG_RXP11 128@ 0.1U_0402_16V4Z 1 C620 PEG_DTXP11 AK24 PEX_TX10_N MIOB_CTL3
2 PEX_TX11
PEG_RXN11 128@ 0.1U_0402_16V4Z 1 2 C619 PEG_DTXN11 AJ24 AE4 2 1
PEG_RXP12 128@ 0.1U_0402_16V4Z 1 C102 PEG_DTXP12 AJ25 PEX_TX11_N MIOB_CLKIN R90 128@ 10K_0402_5% +3VS
PEG_RXN12 128@ 0.1U_0402_16V4Z 1
2
2 C103 PEG_DTXN12 AH25 PEX_TX12 MIOB_CLKOUT AD4
AD5 1
Thermal sensor
PEG_RXP13 128@ 0.1U_0402_16V4Z 1 C126 PEG_DTXP13 AH26 PEX_TX12_N MIOB_CLKOUT_N
2 PEX_TX13

1
PEG_RXN13 128@ 0.1U_0402_16V4Z 1 2 C127 PEG_DTXN13AG26 Y2 C686
PEX_TX13_N MIOB_VREF

1
PEG_RXP14 128@ 0.1U_0402_16V4Z 1 2 C618 PEG_DTXP14 AK27 0.1U_0402_16V4Z +3VS
PEG_RXN14 128@ 0.1U_0402_16V4Z 1 C617 PEG_DTXN14 AJ27 PEX_TX14 M_HSYNC 128@ R503 R504 2
2 AF10 M_HSYNC <17> 128@
PEG_RXP15 128@ 0.1U_0402_16V4Z 1 C134 PEG_DTXP15 AJ28 PEX_TX14_N DACA_HSYNC M_VSYNC 2.2K_0402_5% 200_0402_5%
2 PEX_TX15 DACA_VSYNC AK10 M_VSYNC <17>

1
PEG_RXN15 128@ 0.1U_0402_16V4Z 1 2 C135 PEG_DTXN15 AH27 AH11 M_RED 128@ U34
M_RED <17>

2
PEX_TX15_N DACA_RED M_BLU LCD_I2C_CLK_C R499
AH12 M_BLU <17> 1 VDD 8

2
CLK_PCIE_VGA DACA_BLUE M_GRN SCLK 2.2K_0402_5% DVI pull-high close to GPU +3VS
<15> CLK_PCIE_VGA AH14 PEX_REFCLK DACA_GREEN AJ12 M_GRN <17>
CLK_PCIE_VGA# AJ14 AG9 D+ 1 2 7 LCD_I2C_DAT_C 128@
<15> CLK_PCIE_VGA# PEX_REFCLK_N DACA_IDUMP R85 D+ SDATA LCD_I2C_DAT_C
AH9 1 2128@ R502 1 128@ 2 2.2K_0402_5%

2
VGA_RST# DACA_RSET 124_0402_5% THER_ALERT# LCD_I2C_CLK_C
R500 128@ 2.2K_0402_5%
<27> VGA_RST# AH15 PEX_RST_N 3 D- ALERT# 6 1 2 1 2
AH10 DACAVREF 1 2 D- R501 128@ 0_0402_5% DVI_SCLK R110 1 128@ 2 2.2K_0402_5%
DACA_VREF 128@ C171 0.01U_0402_16V7K 2
128@ C683 DVI_SDATA R106 128@ 2.2K_0402_5%
4 OVERT# GND 5 1 2
AM12 AG7 2200P_0402_25V7K I2CH_SCL R130 1 128@ 2 2.2K_0402_5%
PEX_TSTCLK_OUT DACC_HSYNC
DACs

AM11 AG5 I2CH_SDA R128 1 128@ 2 2.2K_0402_5%

PEX_TSTCLK_OUT_N DACC_VSYNC Close to Sensor 128@ MAX6649MUA_8UMAX
DACC_RED AF6
AE5 I2C address
R5121 128@ DACC_BLUE 1001 100x
2 10K_0402_5% A26 TESTMEMCLK DACC_GREEN AG6
B R1131 128@ B
2 10K_0402_5% H2 TESTMODE DACC_IDUMP AG4
+3VS AF5
R81 1 DACC_RSET
2 10K_0402_5% AJ11 JTAG_TCK
TEST

R57 1 2@ 10K_0402_5% AK12 AH4

JTAG_TDI DACC_VREF
AL12 JTAG_TDO
R56 1 2@ 10K_0402_5% AK11 R6 M_CRMA
JTAG_TMS DACB_RED M_CRMA <17>
R77 1 2 10K_0402_5% AL13 T6 M_COMP
JTAG_N DACB_BLUE M_COMP <17>
T5 M_LUMA
DACB_GREEN M_LUMA <17>
C152 1 2 AM4 V7
128@ 0.1U_0402_16V4Z AK3 IFPAB_VPROBE DACB_IDUMP DACB_RSET
IFPCD_VPROBE DACB_RSET R7
C161 1 2
@ 0.1U_0402_16V4Z R5 DACBVREF C270 1 2
XTALIN DACB_VREF 128@ 0.01U_0402_16V7K
U1 XTALIN
XTALOUT U2 K2 M_DDCCLK
XTALOUT I2CA_SCL M_DDCCLK <17>
J3 M_DDCDATA
I2CA_SDA M_DDCDATA <17>
T2 H4 DVI_SCLK
XTALOUTBUFF I2CB_SCL
CLK

J4 DVI_SDATA
I2C

I2CB_SDA LCD_I2C_CLK_C
I2CC_SCL G2 LCD_I2C_CLK_C <16>
T1 G1 LCD_I2C_DAT_C
XTALSSIN I2CC_SDA LCD_I2C_DAT_C <16>
G3 I2CH_SCL
Y5 I2CH_SCL I2CH_SDA
I2CH_SDA H3
4 3 R139
GND OUT @ 316_0402_1%
1 2 1 G71@ NV72/73M_BGA820 1 2
IN GND C646
1 OSC_SPREAD <26>
128@ 27MHz_16PF_6P27000126 128@ 1 2 R140
OSC_OUT <26>
22P_0402_50V8J R496 @ 316_0402_1%
2

C680 2 128@ DACB_RSET

1 2
1

2 128@ 22_0402_5% R489 D

22P_0402_50V8J @10K_0402_5% GPIO11 2 Q6
1

R492 G @ 2N7002_SOT23
@ 10K_0402_5% If Spread spectrum not stuff than stuff resistor S R145 R146
1

A 128@ 124_0402_5% 88.7_0402_1% R1178 、 R1180 are optional A

@ trim resistor to provide finer
control of the RSET value
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

FBAD[63..0]
FBAD[63..0] <22,23> FBCD[63..0]
FBCD[63..0] <24,25>
FBAA[12..0]
FBAA[12..0] <22,23> FBCA[12..0]
FBCA[12..0] <24,25>
FBBA[2..5]
FBBA[2..5] <23> FBDA[2..5] +1.8VS
+1.8VS FBDA[2..5] <25>
DQSA#[7..0]
DQSA#[7..0] <22,23>

1
DQSC#[7..0]
DQSC#[7..0] <24,25>

1
R161
DQSA[7..0] R487 @ 10K_0402_5%
DQSA[7..0] <22,23> DQSC[7..0]
@ 10K_0402_5%
D DQSC[7..0] <24,25> D
ODTC0

12
DQMA#[7..0] ODTA0
DQMA#[7..0] <22,23>

12
DQMC#[7..0] R160
DQMC#[7..0] <24,25>
R484 256@ 10K_0402_5%
128@ 10K_0402_5%

2
2
U33B U33C
FBAD0 N27 P32 FBAA3 FBCD0 B7 C13 FBCA3
FBAD1 FBAD0 Part 2 of 6 FBA_CMD0 FBAA0 FBCD1 FBCD0 Part 3 of 6 FBC_CMD0 FBCA0
M27 FBAD1 FBA_CMD1 U27 A7 FBCD1 FBC_CMD1 A16
FBAD2 N28 P31 FBAA2 FBCD2 C7 A13 FBCA2
FBAD3 FBAD2 FBA_CMD2 FBAA1 FBCD3 FBCD2 FBC_CMD2 FBCA1
L29 FBAD3 FBA_CMD3 U30 A2 FBCD3 FBC_CMD3 B17
FBAD4 K27 Y31 FBBA3 FBCD4 B2 B20 FBDA3
FBAD5 FBAD4 FBA_CMD4 FBBA4 FBCD5 FBCD4 FBC_CMD4 FBDA4
K28 FBAD5 FBA_CMD5 W32 C4 FBCD5 FBC_CMD5 A19
FBAD6 J29 W31 FBBA5 FBCD6 A5 B19 FBDA5
FBAD7 FBAD6 FBA_CMD6 FBACS1# FBCD6 FBC_CMD6
J28 FBAD7 FBA_CMD7 T32 PAD T21 FBCD7 B5 FBCD7 FBC_CMD7 B14 FBCCS1# PAD T24
FBAD8 P30 V27 FBACS0# FBCD8 F9 E16 FBCCS0#
FBAD8 FBA_CMD8 FBACS0# <22,23> FBCD8 FBC_CMD8 FBCCS0# <24,25>
FBAD9 N31 T28 FBAWE# FBCD9 F10 A14 FBCWE#
FBAD9 FBA_CMD9 FBAWE# <22,23> FBCD9 FBC_CMD9 FBCWE# <24,25>
FBAD10 N30 T31 FBA_BA0 FBCD10 D12 C15 FBC_BA0
FBAD10 FBA_CMD10 FBA_BA0 <22,23> FBCD10 FBC_CMD10 FBC_BA0 <24,25>
FBAD11 N32 U32 FBA_CKE FBCD11 D9 B16 FBC_CKE
FBAD11 FBA_CMD11 FBA_CKE <22,23> FBCD11 FBC_CMD11 FBC_CKE <24,25>
FBAD12 L31 W29 1 R96 2 ODTA0 FBCD12 E12 F17 1 R142 2 ODTC0
FBAD12 FBA_CMD12 FBCD12 FBC_CMD12

1
FBAD13 L30 W30 FBBA2 128@ 0_0402_5% FBCD13 D11 C19 FBDA2 256@ 0_0402_5%
FBAD13 FBA_CMD13 FBCD13 FBC_CMD13

1
FBAD14 J30 T27 FBAA12 R97 FBCD14 E8 D15 FBCA12
FBAD15 FBAD14 FBA_CMD14 FBARAS# 10K_0402_5% FBCD15 FBCD14 FBC_CMD14 FBCRAS# R135
L32 FBAD15 FBA_CMD15 V28 FBARAS# <22,23> D8 FBCD15 FBC_CMD15 C17 FBCRAS# <24,25>
FBAD16 H30 V30 FBAA11 128@ FBCD16 E7 A17 FBCA11 10K_0402_5%
FBAD17 FBAD16 FBA_CMD16 FBAA10 FBCD17 FBCD16 FBC_CMD16 FBCA10
K30 U31 F7 C16 256@

2
C FBAD18 FBAD17 FBA_CMD17 FBA_BA1 FBCD18 FBCD17 FBC_CMD17 FBC_BA1 C
H31 R27 FBA_BA1 <22,23> D6 D14 FBC_BA1 <24,25>

2
FBAD19 FBAD18 FBA_CMD18 FBAA8 FBCD19 FBCD18 FBC_CMD18 FBCA8
F30 FBAD19 FBA_CMD19 V29 D5 FBCD19 FBC_CMD19 F16
FBAD20 H32 T30 FBAA9 FBCD20 D3 C14 FBCA9
FBAD21 FBAD20 FBA_CMD20 FBAA6 FBCD21 FBCD20 FBC_CMD20 FBCA6
E31 FBAD21 FBA_CMD21 W28 E4 FBCD21 FBC_CMD21 C18
FBAD22 D30 R29 FBAA5 FBCD22 C3 E14 FBCA5
FBAD23 FBAD22 FBA_CMD22 FBAA7 FBCD23 FBCD22 FBC_CMD22 FBCA7
E30 FBAD23 FBA_CMD23 R30 B4 FBCD23 FBC_CMD23 B13
FBAD24 H28 P29 FBAA4 FBCD24 C10 E15 FBCA4
FBAD25 FBAD24 FBA_CMD24 FBACAS# FBCD25 FBCD24 FBC_CMD24 FBCCAS#
H29 FBAD25 FBA_CMD25 U28 FBACAS# <22,23> B10 FBCD25 FBC_CMD25 F15 FBCCAS# <24,25>
FBAD26 E29 Y32 FBCD26 C8 A20
FBAD27 FBAD26 FBA_CMD26 FBCD27 FBCD26 FBC_CMD26
J27 FBAD27 A10 FBCD27
MEMORY INTERFACE A

MEMORY INTERFACE B
FBAD28 F27 M29 DQMA#0 FBCD28 C11 A4 DQMC#0
FBAD29 FBAD28 FBADQM0 DQMA#1 FBCD29 FBCD28 FBCDQM0 DQMC#1
E27 FBAD29 FBADQM1 M30 C12 FBCD29 FBCDQM1 E11
FBAD30 E28 G30 DQMA#2 FBCD30 A11 F5 DQMC#2
FBAD31 FBAD30 FBADQM2 DQMA#3 FBCD31 FBCD30 FBCDQM2 DQMC#3
F28 FBAD31 FBADQM3 F29 B11 FBCD31 FBCDQM3 C9
FBAD32 AD29 AA29 DQMA#4 FBCD32 B28 C28 DQMC#4
FBAD33 FBAD32 FBADQM4 DQMA#5 FBCD33 FBCD32 FBCDQM4 DQMC#5
AE29 FBAD33 FBADQM5 AK30 C27 FBCD33 FBCDQM5 F24
FBAD34 AD28 AC30 DQMA#6 FBCD34 C26 C24 DQMC#6
FBAD35 FBAD34 FBADQM6 DQMA#7 FBCD35 FBCD34 FBCDQM6 DQMC#7
AC28 FBAD35 FBADQM7 AG30 B26 FBCD35 FBCDQM7 E20
FBAD36 AB29 FBCD36 C30
FBAD37 FBAD36 DQSA#0 FBCD37 FBCD36 DQSC#0
AA30 FBAD37 FBADQS_RN0 M28 B31 FBCD37 FBCDQS_RN0 C6
FBAD38 Y28 K32 DQSA#1 FBCD38 C29 E9 DQSC#1
FBAD39 FBAD38 FBADQS_RN1 DQSA#2 FBCD39 FBCD38 FBCDQS_RN1 DQSC#2
AB30 FBAD39 FBADQS_RN2 G31 A31 FBCD39 FBCDQS_RN2 E6
FBAD40 AM30 G27 DQSA#3 FBCD40 D28 A8 DQSC#3
FBAD41 FBAD40 FBADQS_RN3 DQSA#4 FBCD41 FBCD40 FBCDQS_RN3 DQSC#4
AF30 FBAD41 FBADQS_RN4 AA28 D27 FBCD41 FBCDQS_RN4 B29
FBAD42 AJ31 AL31 DQSA#5 FBCD42 F26 E25 DQSC#5
FBAD43 FBAD42 FBADQS_RN5 DQSA#6 FBCD43 FBCD42 FBCDQS_RN5 DQSC#6
AJ30 FBAD43 FBADQS_RN6 AF31 D24 FBCD43 FBCDQS_RN6 A25
FBAD44 AJ32 AH29 DQSA#7 FBCD44 E23 F21 DQSC#7
FBAD45 FBAD44 FBADQS_RN7 FBCD45 FBCD44 FBCDQS_RN7
AK29 FBAD45 E26 FBCD45
FBAD46 AM31 L28 DQSA0 FBCD46 E24 C5 DQSC0 +1.8VS
FBAD47 FBAD46 FBADQS_WP0 DQSA1 +1.8VS FBCD47 FBCD46 FBCDQS_WP0 DQSC1
AL30 FBAD47 FBADQS_WP1 K31 F23 FBCD47 FBCDQS_WP1 E10
FBAD48 AE32 G32 DQSA2 FBCD48 B23 E5 DQSC2
FBAD48 FBADQS_WP2 FBCD48 FBCDQS_WP2

1
FBAD49 AE30 G28 DQSA3 FBCD49 A23 B8 DQSC3
FBAD49 FBADQS_WP3 FBCD49 FBCDQS_WP3
1

B FBAD50 DQSA4 FBCD50 DQSC4 R138 B

AE31 FBAD50 FBADQS_WP4 AB28 C25 FBCD50 FBCDQS_WP4 A29
FBAD51 AD30 AL32 DQSA5 R506 FBCD51 C23 D25 DQSC5 1K_0402_1%
FBAD52 FBAD51 FBADQS_WP5 DQSA6 1K_0402_1% FBCD52 FBCD51 FBCDQS_WP5 DQSC6
AC31 FBAD52 FBADQS_WP6 AF32 A22 FBCD52 FBCDQS_WP6 B25 @
FBAD53 AC32 AH30 DQSA7 FBCD53 C22 F20 DQSC7

2
FBAD54 FBAD53 FBADQS_WP7 FBCD54 FBCD53 FBCDQS_WP7
AB32 C21
2

FBAD55 FBAD54 FBA_VREF1 10mil 10mil FBCD55 FBCD54 FBA_VREF2 10mil

AB31 FBAD55 FB_VREF1 E32 B22 FBCD55 FB_VREF2 A28
FBAD56 AG27 FBCD56 E22
FBAD56 FBCD56
1

FBAD57 AF28 P28 CLKA0 1 FBCD57 D22 E13 CLKC0

FBAD57 FBA_CLK0 CLKA0 <22> FBCD57 FBC_CLK0 CLKC0 <24>

1
FBAD58 AH28 R28 CLKA0# C687 R505 FBCD58 D21 F13 CLKC0# 1
FBAD58 FBA_CLK0_N CLKA0# <22> FBCD58 FBC_CLK0_N CLKC0# <24>
FBAD59 AG28 Y27 CLKA1 1K_0402_1% FBCD59 E21 F18 CLKC1 C355 R143
FBAD59 FBA_CLK1 CLKA1 <23> FBCD59 FBC_CLK1 CLKC1 <25>
FBAD60 AG29 AA27 CLKA1# 0.1U_0402_16V4Z FBCD60 E18 E17 CLKC1# @ 1K_0402_1%
FBAD60 FBA_CLK1_N CLKA1# <23> 2 FBCD60 FBC_CLK1_N CLKC1# <25>
FBAD61 AD27 D32 FBCD61 D19 B1 0.1U_0402_16V4Z @
2

FBAD62 FBAD61 FBA_REFCLK FBCD62 FBCD61 FBC_REFCLK 2

AF27 D31 D18 C1

2
FBAD63 FBAD62 FBA_REFCLK_N ODTA0 FBCD63 FBCD62 FBC_REFCLK_N ODTC0
AE28 FBAD63 FBA_DEBUG AC27 1 2 ODTA0 <22,23> E19 FBCD63 FBC_DEBUG F12 1 2 ODTC0 <24,25>
R94 @ 0_0402_5% R141 @ 0_0402_5%

G71@ NV72/73M_BGA820 G71@ NV72/73M_BGA820

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

+1.2VS
(+1.1VS) 1808mA
VID_PLLVDD、PLLVDD、 0.022U_0402_16V7K 0.022U_0402_16V7K
+VGA_CORE
IFPAB_PLLVDD at G71/72 U33E C197 C195
is +2.5VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 330U_V_2.5VK_R9 K16 AD23 1 128@ 1 1 128@ 1 1 1
VDD_0 Part 5 of 6 PEX_IOVDD_0
1 K17 VDD_1 PEX_IOVDD_1 AF23
C265 1 1 C289 1 1 C287 1 C706
1 N13 AF24 C190
128@ 128@ 128@ 128@ + VDD_2 PEX_IOVDD_2 C178 C172 C220 128@
N14 VDD_3 PEX_IOVDD_3 AF25
N16 AG24 128@ 2 2 128@ 2 2 128@ 2 2 2.2U_0603_6.3V6K
C286 C269 C266 VDD_4 PEX_IOVDD_4
N17 VDD_5 PEX_IOVDD_5 AG25
2 128@ 2 2 128@ 2 2 128@ 2 2 0.022U_0402_16V7K 0.022U_0402_16V7K 0.022U_0402_16V7K
N19 VDD_6
+2.5VS N20 AC16
L17 VDD_7 PEX_IOVDDQ_0
P13 VDD_8 PEX_IOVDDQ_1 AC17
1 2 VID_PLLVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z P14 AC21 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 10U_0805_10V4Z
D BLM11A121SPT_0603 40mA VDD_9 PEX_IOVDDQ_2 C184 1 C177 1 C183 1 C260 1 D
P16 VDD_10 PEX_IOVDDQ_3 AC22 1 1 1 1 1
128@ 1 1 1 P17 AE18 128@ 128@ 128@ 128@ C277
C278 C267 C279 128@ VDD_11 PEX_IOVDDQ_4 128@
P19 VDD_12 PEX_IOVDDQ_5 AE21
128@ 470P_0402_50V7K R16 AE22 10U_0805_10V4Z
4700P_0402_25V7K 220P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J VDD_13 PEX_IOVDDQ_6 C198 2 2 C212 2 2 C182 2 2 C242 2 2 2
R17 VDD_14 PEX_IOVDDQ_7 AF12
2 2 2 R104 NV 128@ 128@ 128@ 128@
1 2 T13 VDD_15 PEX_IOVDDQ_8 AF18
C243 1 1 C281 1 1 C257 1 1 @ 0_0402_5% T14 AF21
128@ 128@ 128@ 128@ VDD_16 PEX_IOVDDQ_9 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 10U_0805_10V4Z +1.2VS
T15 VDD_17 PEX_IOVDDQ_10 AF22
2.2U_0603_6.3V6K T18 PEX_PLLAVDD L14
C264 C263 C241 VDD_18 PEX_PLLAVDD 180mA 470P_0402_50V7K
T19 VDD_19 PEX_PLLAVDD AF15 1 2
2 128@ 2 2 128@ 2 2 128@ 2 PEX_PLLDVDD 20mA BLM11A121SPT_0603
U13 VDD_20 PEX_PLLDVDD AE15
+2.5VS U14 VDD_21 1 C189 1 1 128@
L16 100P_0402_50V8J U15 M7 MIOA_VDDQ +1.8VS 128@
PLLVDD 220P_0402_50V7K 100P_0402_50V8J VDD_22 MIOA_VDDQ_0 128@ L10 C221
1 2 U19 VDD_23 MIOA_VDDQ_1 M8
BLM11A121SPT_0603 40mA V16 R8 2.2U_0603_6.3V6K 1 2 C188 128@
128@ VDD_24 MIOA_VDDQ_2 2 2 128@ 2 2.2U_0603_6.3V6K
1 1 1 V17 VDD_25 MIOA_VDDQ_3 T8 1 C121 1 1 BLM11A121SPT_0603
C247 C227 C255 128@ 220P_0402_50V7K 220P_0402_50V7K W13 U9 128@ 4700P_0402_25V7K
128@ 470P_0402_50V7K VDD_26 MIOA_VDDQ_4 MIOB_VDDQ L15
W14 VDD_27 MIOB_VDDQ_0 AA8
4700P_0402_25V7K W16 AB7 C185 C186 4700P_0402_25V7K 1 2
2 2 2 C320 1 C284 1 VDD_28 MIOB_VDDQ_1 128@ 2 2 128@ 2 BLM11A121SPT_0603
1 1 W17 VDD_29 MIOB_VDDQ_2 AB8
C321 128@ 128@ W19 AC6 470P_0402_50V7K 4700P_0402_25V7K 1 C203 1 1 128@ 1
128@ 128@ VDD_30 MIOB_VDDQ_3 T22 128@ C218
Y13 VDD_31 MIOB_VDDQ_4 AC7
2.2U_0603_6.3V6K 220P_0402_50V7K C245 Y14 L1 MIOACAL_PD_VDDQ PAD C196 128@
2 2 128@ 2 2 VDD_32 MIOACAL_PD_VDDQ MIOBCAL_PD_VDDQ T20 128@ 2.2U_0603_6.3V6K
Y16 VDD_33 MIOBCAL_PD_VDDQ Y1
+1.2VS Y17 PAD C210 2 2 2 2.2U_0603_6.3V6K 2
VDD_34
L19 Y19 VDD_35 IFPA_IOVDD AF9 120mA IFPA_IOVDD 128@
1 2 FBA_PLLAVDD 220P_0402_50V7K Y20 AF8 IFPB_IOVDD
BLM11A121SPT_0603 VDD_36 IFPB_IOVDD
U18 VDD_37 IFPC_IOVDD AD6 128@ 1 R61 2 10K_0402_5% 470P_0402_50V7K
128@ AE7 128@ 1 R62 2 10K_0402_5% +2.5VS
1 1 1 IFPD_IOVDD
C306 C336 C335 128@ 100P_0402_50V8J P20 L13
VDD_LP_0
128@ 4700P_0402_25V7K 1 1 C258 1 1 T20 VDD_LP_1 IFPAB_PLLVDD AC9 40mA IFPAB_PLLVDD 2.2U_0603_6.3V6K 1 2
2.2U_0603_6.3V6K C254 128@ T23 AA10 40mA1 R93 2 C201 1 BLM11A121SPT_0603 +3VS
2 2 2 VDD_LP_2 IFPCD_PLLVDD 1 1
C 128@ 128@ 10K_0402_5% 128@ C
U20 VDD_LP_3 128@
10U_0805_10V4Z C244 C251 U23 AD10 DACA_VDD 70mA MIOA_VDDQ L18
128@ 2 128@ 2 2 128@ 2 VDD_LP_4 DACA_VDD DACB_VDD 140mA C213 C208 MIOA_VDDQ
W20 VDD_LP_5 DACB_VDD V8 1 2
4700P_0402_25V7K +3VS 0.1U_0402_16V4Z 220P_0402_50V7K AD7 2 R91 1 128@ 2 2 128@ 2 BLM11A121SPT_0603
+3VS DACC_VDD 128@ 10K_0402_5% 470P_0402_50V7K 4700P_0402_25V7K 128@
1
L21 4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K H7 A3
FBA_PLLVDD C209 1 C296 1 C291 1 VDD33_0 FBVDD_0 128@ C268
1 2 1 1 1 J7 VDD33_1 FBVDD_1 A6
@ BLM11A121SPT_0603 128@ 128@ 128@ K7 A9 0.1U_0402_16V4Z
VDD33_2 FBVDD_2 2
1 1 1 L7 VDD33_3 FBVDD_3 A12
C294 C339 C346 C181 C219 C288 L8 A15
128@ 2 2 128@ 2 2 128@ 2 2 VDD33_4 FBVDD_4 MIOB_VDDQ L11
@ 4700P_0402_25V7K L10 VDD33_5 FBVDD_5 A18 IFPA_IOVDD、IFPB_IOVDD
@ 2.2U_0603_6.3V6K M10 A21 MIOB_VDDQ 1 2
2 2 2 4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K VDD33_6 FBVDD_6 at G71/72 is +1.8VS BLM11A121SPT_0603
AC11 VDD33_7 FBVDD_7 A24
AC12 A27 at NV43/44 is +LCDVDD 1 128@
@ 4700P_0402_25V7K 0.1U_0402_16V4Z VDD33_8 FBVDD_8
AC24 VDD33_9 FBVDD_9 A30
1 1 C322 1 AD24 C32 128@ C211
+1.2VS C290 128@ VDD33_10 FBVDD_10 0.1U_0402_16V4Z
AE11 F32

POWER
L22 128@ VDD33_11 FBVDD_11 2
AE12 VDD33_12 FBVDD_12 J32
1 2 FBC_PLLAVDD 1U_0603_10V4Z C340 M32
BLM11A121SPT_0603 2 128@ 2 2 VID_PLLVDD T10 FBVDD_13
VID_PLLVDD FBVDD_14 R32
128@ 1 1 1 0.1U_0402_16V4Z PLLVDD T9 V32
C332 C334 PLLVDD FBVDD_15
FBVDD_16 AA32
128@ C788 AD32
2.2U_0603_6.3V6K 4700P_0402_25V7K FBA_PLLAVDD FBVDD_17
G25 FBA_PLLAVDD FBVDD_18 AG32
2 2 2 128@ FBC_PLLAVDD G10 FBC_PLLAVDD FBVDD_19 AK32
+1.8VS FBA_PLLVDD G23
128@ FBC_PLLVDD FBA_PLLVDD
G8 FBC_PLLVDD FBVDDQ_0 G11
4700P_0402_25V7K R102 1 2 K26 G12
128@ 40.2_0603_1% FBCAL_PD_VDDQ FBVDDQ_1
FBVDDQ_2 G15
H16 G18 +1.8VS
+3VS +1.8VS FBVTT_0 FBVDDQ_3
H17 FBVTT_1 FBVDDQ_4 G21
L20 J9 G22 4700P_0402_25V7K 4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0805_10V4Z 1
B R95 FBVTT_2 FBVDDQ_5 B
1 2 FBC_PLLVDD J10 H11 1 C276 1 1 C217 1 1 C282 1 1 C338 1 1 C667 1
@ BLM11A121SPT_0603 0.022U_0402_16V7K +VGA_FBVTT FBVTT_3 FBVDDQ_6 128@ 128@ 128@ 128@ 128@ +
1 2 J23 FBVTT_4 FBVDDQ_7 H12
1 1 1 1 C223 1 1 J24 FBVTT_5 FBVDDQ_8 H15
C317 C344 C337 @ 4700P_0402_25V7K 0_0603_5% 128@ K9 H18 C293 C253 C319 C271 C285 C627
FBVTT_6 FBVDDQ_9 128@ 2 2 128@ 2 2 128@ 2 2 128@ 2 2 128@ 2 2 128@ 2
128@ K11 FBVTT_7 FBVDDQ_10 H21
@ 2.2U_0603_6.3V6K C262 C256 4700P_0402_25V7K K12 L25
2 2 2 128@ 2 2 128@ 2 FBVTT_8 FBVDDQ_11 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K 0.022U_0402_16V7K 4.7U_0805_10V4Z 330U_V_2.5VK_R9
K21 FBVTT_9 FBVDDQ_12 L26
K22 FBVTT_10 FBVDDQ_13 M25
@ 4700P_0402_25V7K 0.1U_0402_16V4Z K24 M26
FBVTT_11 FBVDDQ_14 0.022U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L23 FBVTT_12 FBVDDQ_15 R25
M23 R26 1 C326 1 1 C342 1 1 C240 1 1 C292 1 1
FBVTT_13 FBVDDQ_16 128@ 128@ 128@ 128@
T25 FBVTT_14 FBVDDQ_17 V25
L9 U25 V26
DACA_VDD 2.2U_0603_6.3V6K FBVTT_15 FBVDDQ_18 C324 C325 C343 C216 C345
1 2 +3VS AA23 FBVTT_16 FBVDDQ_19 AA25
BLM11A121SPT_0603 AB23 AA26 128@ 2 2 128@ 2 2 128@ 2 2 128@ 2 2 128@ 2
128@ 1 FBVTT_17 FBVDDQ_20 0.022U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 128@ FBVDDQ_21 AB25
C200 C120 T33 AB26
128@ 128@ C199 PAD FBVDDQ_22
F6 CLAMP FBVDDQ_23 H22
470P_0402_50V7K 4700P_0402_25V7K
2 2 2
G71@ NV72/73M_BGA820

L8
DACB_VDD 2.2U_0603_6.3V6K 1 2
BLM11A121SPT_0603
L12
1 128@ 1 1 128@
C252 C119 +1.2VS 1 2 NV
128@ 128@ C261
470P_0402_50V7K 4700P_0402_25V7K 128@ BLM11A121SPT_0603 2 1
2 2 2 C207 C283

128@ 4.7U_0603_6.3V6M 0.022U_0402_16V7K

A 1 2 128@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

U33F
B3 GND_0 GND_85 W18
B6 Part 6 of 6 Y4
GND_1 GND_86
B9 GND_2 GND_87 Y15
B12 GND_3 GND_88 Y18
B15 GND_4 GND_89 Y29
B18 GND_5 GND_90 AA2
D D
B21 GND_6 GND_91 AA12
B24 GND_7 GND_92 AA21
B27 GND_8 GND_93 AA31
B30 GND_9 GND_94 AB6
C2 GND_10 GND_95 AB27
C31 GND_11 GND_96 AC4
D4 GND_12 GND_97 AC10
D7 GND_13 GND_98 AC23
D10 GND_14 GND_99 AC29
D13 GND_15 GND_100 AD2
D17 GND_16 GND_101 AD16
D20 GND_17 GND_102 AD17
D23 GND_18 GND_103 AD31
D26 GND_19 GND_104 AE6
D29 GND_20 GND_105 AE17
F2 GND_21 GND_106 AE27
F8 GND_22 GND_107 AF4
F11 GND_23 GND_108 AF7
F14 GND_24 GND_109 AF11
F19 GND_25 GND_110 AF26
F22 GND_26 GND_111 AF29
F25 GND_27 GND_112 AG2
F31 GND_28 GND_113 AG8
G4 GND_29 GND_114 AG10
G7 GND_30 GND_115 AG11
G26 AG13
GND
GND_31 GND_116
G29 GND_32 GND_117 AG14
H27 GND_33 GND_118 AG15
H6 GND_34 GND_119 AG19
J2 GND_35 GND_120 AG22
J16 GND_36 GND_121 AG31
J17 GND_37 GND_122 AH24
C C
J31 GND_38 GND_123 AJ4
K10 GND_39 GND_124 AJ7
K23 GND_40 GND_125 AJ10
K29 GND_41 GND_126 AJ13
K4 GND_42 GND_127 AJ16
L6 GND_43 GND_128 AJ17
L27 GND_44 GND_129 AJ20
M2 GND_45 GND_130 AJ23
M12 GND_46 GND_131 AJ26
M21 GND_47 GND_132 AJ29
M31 GND_48 GND_133 AK2
N4 GND_49 GND_134 AL3
N15 GND_50 GND_135 AL6
N18 GND_51 GND_136 AL9
N29 GND_52 GND_137 AL10
P6 GND_53 GND_138 AK28
P15 GND_54 GND_139 AK31
P18 GND_55 GND_140 AL11
P27 GND_56 GND_141 AL14
R2 GND_57 GND_142 AL19
R13 GND_58 GND_143 AL22
R14 GND_59 GND_144 AL25
R15 GND_60 GND_145 AM13
R18 GND_61 GND_146 AM16
R19 GND_62 GND_147 AM17
R20 GND_63 GND_148 AM20
R31 GND_64 GND_149 AM23
T4 GND_65 GND_150 AM26
T16 GND_66 GND_151 AM29
T17 GND_67 GND_152 D16
T24 GND_68 GND_153 W27
T29 GND_69 GND_154 W15
B B
U8 GND_70
U16 GND_71 IFPAB_PLLGND AD9
U17 GND_72 IFPCD_PLLGND AB10
U24 GND_73
U29 GND_74 MIOACAL_PU_GND L3
V2 GND_75 MIOBCAL_PU_GND Y3
V13 GND_76
V14 GND_77 PEX_PLLGND AE16
V15 GND_78
V18 GND_79 PLLGND U10
V19
V20
GND_80
G24
For NV73 R116 change to 40.2_0603_1%(SD014402A80)
GND_81 FBA_PLLGND
V31 GND_82 FBC_PLLGND G9
W6 GND_83
H26 128@ 1 R116 2 30_0603_1%
FBCAL_PU_GND 128@ 1 R103 2 40.2_0402_1%
FBCAL_TERM_GND J26

G71@ NV72/73M_BGA820

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

U35 U2
FBA_BA0 L2 B9 FBAD5 FBA_BA0 L2 B9 FBAD25
FBA_BA1 BA0 DQ15 FBAD1 FBA_BA1 BA0 DQ15 FBAD27
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD7 D9 FBAD26
D FBAA12 DQ13 FBAD0 FBAA12 DQ13 FBAD30 D
R2 A12 DQ12 D1 R2 A12 DQ12 D1
FBAA11 P7 D3 FBAD3 FBAA11 P7 D3 FBAD29
FBAA10 A11 DQ11 FBAD6 FBAA10 A11 DQ11 FBAD24
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBAA9 P3 C2 FBAD2 FBAA9 P3 C2 FBAD28 FBAD[63..0]
A9 DQ9 A9 DQ9 <19,23> FBAD[63..0]
FBAA8 P8 C8 FBAD4 FBAA8 P8 C8 FBAD31
FBAA7 A8 DQ8 FBAD21 FBAA7 A8 DQ8 FBAD11
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBAA6 N7 F1 FBAD19 FBAA6 N7 F1 FBAD14 FBAA[12..0]
A6 DQ6 A6 DQ6 <19,23> FBAA[12..0]
FBAA5 N3 H9 FBAD18 FBAA5 N3 H9 FBAD8
FBAA4 A5 DQ5 FBAD17 FBAA4 A5 DQ5 FBAD12
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBAA3 N2 H3 FBAD16 FBAA3 N2 H3 FBAD13 DQSA#[7..0]
A3 DQ3 A3 DQ3 <19,23> DQSA#[7..0]
FBAA2 M7 H7 FBAD22 FBAA2 M7 H7 FBAD10
FBAA1 A2 DQ2 FBAD23 FBAA1 A2 DQ2 FBAD15
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBAA0 M8 G8 FBAD20 FBAA0 M8 G8 FBAD9 DQSA[7..0]
A0 DQ0 A0 DQ0 <19,23> DQSA[7..0]

CLKA0# K8 A9 CLKA0# K8 A9 DQMA#[7..0]

CK VDDQ1 CK VDDQ1 <19,23> DQMA#[7..0]
CLKA0 J8 C1 CLKA0 J8 C1
CK VDDQ2 CK VDDQ2
VDDQ3 C3 VDDQ3 C3
FBA_CKE K2 C7 FBA_CKE K2 C7 FBA_BA[1..0]
CKE VDDQ4 CKE VDDQ4 <19,23> FBA_BA[1..0]
VDDQ5 C9 VDDQ5 C9
E9 +1.8VS E9
VDDQ6 VDDQ6 +1.8VS
VDDQ7 G1 VDDQ7 G1
FBACS0# L8 G3 FBACS0# L8 G3 ODTA0
CS VDDQ8 CS VDDQ8 <19,23> ODTA0
VDDQ9 G7 VDDQ9 G7
FBAWE# K3 G9 FBAWE# K3 G9 FBA_CKE
WE VDDQ10 WE VDDQ10 <19,23> FBA_CKE
FBARAS# K7 A1 FBARAS# K7 A1 FBARAS#
RAS VDD1 RAS VDD1 <19,23> FBARAS#
VDD2 E1 VDD2 E1
FBACAS# L7 J9 FBACAS# L7 J9 FBACAS#
CAS VDD3 CAS VDD3 <19,23> FBACAS#
VDD4 M9 VDD4 M9
DQMA#2 F3 R1 DQMA#1 F3 R1 FBAWE#
LDM VDD5 LDM VDD5 <19,23> FBAWE#
DQMA#0 B3 DQMA#3 B3
C UDM UDM FBACS0# C
VDDL J1 VDDL J1 <19,23> FBACS0#
VSSDL J7 1 1 VSSDL J7 1 1
ODTA0 K9 ODTA0 K9
ODT C675 C676 ODT C359 C358
0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
+1.8VS DQSA2 2 128@ 2 128@ DQSA1 2 128@ 2 128@
F7 LDQS F7 LDQS
DQSA#2 E8 A7 DQSA#1 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2 Close to U10
R485 DQSA0 B7 D8 DQSA3 B7 D8 CLKA0
UDQS VSSQ5 UDQS VSSQ5 <19> CLKA0

1
VRAM_VREFA 1K_0402_1% DQSA#0 A8 E7 VRAM_VREFA DQSA#3 A8 E7
UDQS VSSQ6 UDQS VSSQ6 R513
128@ VSSQ7 F2 VSSQ7 F2
F8 F8 @ 120_0402_5%
VSSQ8 VSSQ8 +1.8VS
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2

2
(SSTL-1.8) VREF = .5*VDDQ H8 (SSTL-1.8) VREF = .5*VDDQ H8

2
VSSQ10 VSSQ10 R510
A2 NC#A2 A2 NC#A2 1
R486 E2 A3 E2 A3 120_0402_5%
NC#E2 VSS1 NC#E2 VSS1

1
1K_0402_1% C672 L1 E3 C362 L1 E3 128@ C365
128@ 0.047U_0402_16V4Z NC#L1 VSS2 0.047U_0402_16V4Z NC#L1 VSS2 R515 0.1U_0402_16V4Z
R3 J3 R3 J3

1
NC#R3 VSS3 128@ NC#R3 VSS3 120_0402_5% 2
128@ R7 N1 R7 N1 @
NC#R7 VSS4 NC#R7 VSS4 @
Close to U76 R8 NC#R8 VSS5 P9 Close to U77 R8 NC#R8 VSS5 P9
CLKA0#
<19> CLKA0#

2
128@ HY5PS561621F-25 128@ HY5PS561621F-25

For NV73 R510 change to 481_0402_1%(SD00000CA80)

DDR2 BGA MEMORY DDR2 BGA MEMORY
B B

+1.8VS +1.8VS
128@ C692 128@ C705 128@ C703 128@ C363 128@ C274 128@ C323
0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.01U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
128@ 128@
C674 C702 C360 C354
1000P_0402_50V7K 0.01U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_16V7K
2 2 2 2 2 2 2 2 128@ 2 2 2 2 2 2 2 2 128@
128@ C684 128@ C671 128@ C704 128@ C361 128@ C364 128@ C673
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

D D

U32 U1
FBA_BA0 L2 B9 FBAD39 FBA_BA0 L2 B9 FBAD57
FBA_BA1 BA0 DQ15 FBAD35 FBA_BA1 BA0 DQ15 FBAD56
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD38 D9 FBAD58
FBAA12 DQ13 FBAD34 FBAA12 DQ13 FBAD63 FBAD[63..0]
R2 A12 DQ12 D1 R2 A12 DQ12 D1 <19,22> FBAD[63..0]
FBAA11 P7 D3 FBAD32 FBAA11 P7 D3 FBAD61
FBAA10 A11 DQ11 FBAD37 FBAA10 A11 DQ11 FBAD59
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBAA9 P3 C2 FBAD33 FBAA9 P3 C2 FBAD60 FBAA[12..0]
A9 DQ9 A9 DQ9 <19,22> FBAA[12..0]
FBAA8 P8 C8 FBAD36 FBAA8 P8 C8 FBAD62
FBAA7 A8 DQ8 FBAD45 FBAA7 A8 DQ8 FBAD51
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBAA6 N7 F1 FBAD46 FBAA6 N7 F1 FBAD55 FBBA[2..5]
A6 DQ6 A6 DQ6 <19> FBBA[2..5]
FBBA5 N3 H9 FBAD41 FBBA5 N3 H9 FBAD50
FBBA4 A5 DQ5 FBAD40 FBBA4 A5 DQ5 FBAD54
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBBA3 N2 H3 FBAD47 FBBA3 N2 H3 FBAD52 DQSA#[7..0]
A3 DQ3 A3 DQ3 <19,22> DQSA#[7..0]
FBBA2 M7 H7 FBAD42 FBBA2 M7 H7 FBAD48
FBAA1 A2 DQ2 FBAD44 FBAA1 A2 DQ2 FBAD53
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBAA0 M8 G8 FBAD43 FBAA0 M8 G8 FBAD49 DQSA[7..0]
A0 DQ0 A0 DQ0 <19,22> DQSA[7..0]

CLKA1# K8 A9 CLKA1# K8 A9 DQMA#[7..0]

CK VDDQ1 CK VDDQ1 <19,22> DQMA#[7..0]
CLKA1 J8 C1 CLKA1 J8 C1
CK VDDQ2 CK VDDQ2
VDDQ3 C3 VDDQ3 C3
FBA_CKE K2 C7 FBA_CKE K2 C7 FBA_BA[1..0]
CKE VDDQ4 CKE VDDQ4 <19,22> FBA_BA[1..0]
VDDQ5 C9 VDDQ5 C9
VDDQ6 E9 VDDQ6 E9
G1 +1.8VS G1 +1.8VS ODTA0
VDDQ7 VDDQ7 <19,22> ODTA0
FBACS0# L8 G3 FBACS0# L8 G3
CS VDDQ8 CS VDDQ8 FBA_CKE
VDDQ9 G7 VDDQ9 G7 <19,22> FBA_CKE
FBAWE# K3 G9 FBAWE# K3 G9
C WE VDDQ10 WE VDDQ10 FBARAS# C
<19,22> FBARAS#
FBARAS# K7 A1 FBARAS# K7 A1
RAS VDD1 RAS VDD1 FBACAS#
VDD2 E1 VDD2 E1 <19,22> FBACAS#
FBACAS# L7 J9 FBACAS# L7 J9
CAS VDD3 CAS VDD3 FBAWE#
VDD4 M9 VDD4 M9 <19,22> FBAWE#
DQMA#5 F3 R1 DQMA#6 F3 R1
DQMA#4 LDM VDD5 DQMA#7 LDM VDD5 FBACS0#
B3 UDM B3 UDM <19,22> FBACS0#
VDDL J1 VDDL J1
J7 1 1 C632 J7 1 1
ODTA0 VSSDL 1U_0402_6.3V4Z ODTA0 VSSDL
K9 ODT K9 ODT
C633 128@ C272 C273
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
DQSA5 2 128@ 2 DQSA6 2 128@ 2 128@
F7 LDQS F7 LDQS
+1.8VS DQSA#5 E8 A7 DQSA#6 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2
DQSA4 B7 D8 DQSA7 B7 D8
VRAM_VREFB R574 DQSA#4 UDQS VSSQ5 VRAM_VREFB DQSA#7 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
1K_0402_1% F2 F2
VSSQ7 VSSQ7
128@ VSSQ8 F8 VSSQ8 F8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
VSSQ10 H8 VSSQ10 H8
(SSTL-1.8) VREF = .5*VDDQ A2 (SSTL-1.8) VREF = .5*VDDQ A2 CLKA1
NC#A2 NC#A2 <19> CLKA1

1
R575 E2 A3 E2 A3
1K_0402_1% C636 NC#E2 VSS1 C670 NC#E2 VSS1 R70
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
128@ 0.047U_0402_16V4Z R3 J3 0.047U_0402_16V4Z R3 J3 120_0402_5%
NC#R3 VSS3 128@ NC#R3 VSS3 @ +1.8VS
128@ R7 N1 R7 N1
NC#R7 VSS4 NC#R7 VSS4

2
Close to U78 R8 P9 Close to U79 R8 P9

2
NC#R8 VSS5 NC#R8 VSS5 R75 1
120_0402_5%

1
128@ HY5PS561621F-25 128@ HY5PS561621F-25 128@ C154
B R69 0.1U_0402_16V4Z B

1
120_0402_5% 2 @
@
CLKA1#
<19> CLKA1#

2
Close to U11

For NV73 R75 change to 481_0402_1%(SD00000CA80)

+1.8VS DDR2 BGA MEMORY +1.8VS DDR BGA MEMORY
128@ C634 128@ C259 128@ C246 128@ C637 128@ C153 128@ C150
0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.01U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
128@ C631 128@ C224 128@ C155 128@ C148
1000P_0402_50V7K 0.01U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
128@ C635 128@ C638 128@ C194 128@ C275 128@ C151 128@ C149
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G72/73VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

U7 U37
FBC_BA0 L2 B9 FBCD13 FBC_BA0 L2 B9 FBCD19
FBC_BA1 BA0 DQ15 FBCD10 FBC_BA1 BA0 DQ15 FBCD18
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D FBCD11 FBCD17 D
DQ13 D9 DQ13 D9
FBCA12 R2 D1 FBCD14 FBCA12 R2 D1 FBCD22
FBCA11 A12 DQ12 FBCD15 FBCA11 A12 DQ12 FBCD20
P7 A11 DQ11 D3 P7 A11 DQ11 D3
FBCA10 M2 D7 FBCD12 FBCA10 M2 D7 FBCD23
FBCA9 A10/AP DQ10 FBCD9 FBCA9 A10/AP DQ10 FBCD21 FBC_BA[1..0]
P3 A9 DQ9 C2 P3 A9 DQ9 C2 <19,25> FBC_BA[1..0]
FBCA8 P8 C8 FBCD8 FBCA8 P8 C8 FBCD16
FBCA7 A8 DQ8 FBCD4 FBCA7 A8 DQ8 FBCD27
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBCA6 N7 F1 FBCD1 FBCA6 N7 F1 FBCD31 FBCD[63..0]
A6 DQ6 A6 DQ6 <19,25> FBCD[63..0]
FBCA5 N3 H9 FBCD7 FBCA5 N3 H9 FBCD25
FBCA4 A5 DQ5 FBCD0 FBCA4 A5 DQ5 FBCD30
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBCA3 N2 H3 FBCD3 FBCA3 N2 H3 FBCD29 FBCA[12..0]
A3 DQ3 A3 DQ3 <19,25> FBCA[12..0]
FBCA2 M7 H7 FBCD6 FBCA2 M7 H7 FBCD26
FBCA1 A2 DQ2 FBCD2 FBCA1 A2 DQ2 FBCD28
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBCA0 M8 G8 FBCD5 FBCA0 M8 G8 FBCD24 DQSC#[7..0]
A0 DQ0 A0 DQ0 <19,25> DQSC#[7..0]

CLKC0# K8 A9 CLKC0# K8 A9 DQSC[7..0]

CK VDDQ1 CK VDDQ1 <19,25> DQSC[7..0]
CLKC0 J8 C1 CLKC0 J8 C1
CK VDDQ2 CK VDDQ2
VDDQ3 C3 VDDQ3 C3
FBC_CKE K2 C7 FBC_CKE K2 C7 DQMC#[7..0]
CKE VDDQ4 CKE VDDQ4 <19,25> DQMC#[7..0]
VDDQ5 C9 VDDQ5 C9
VDDQ6 E9 VDDQ6 E9
G1 G1 +1.8VS
FBCCS0# VDDQ7 +1.8VS FBCCS0# VDDQ7 ODTC0
L8 CS VDDQ8 G3 L8 CS VDDQ8 G3 <19,25> ODTC0
VDDQ9 G7 VDDQ9 G7
FBCWE# K3 G9 FBCWE# K3 G9 FBC_CKE
WE VDDQ10 WE VDDQ10 <19,25> FBC_CKE
FBCRAS# K7 A1 FBCRAS# K7 A1 FBCRAS#
RAS VDD1 RAS VDD1 <19,25> FBCRAS#
VDD2 E1 VDD2 E1
FBCCAS# L7 J9 FBCCAS# L7 J9 FBCCAS#
CAS VDD3 CAS VDD3 <19,25> FBCCAS#
VDD4 M9 VDD4 M9
DQMC#0 F3 R1 DQMC#3 F3 R1 FBCWE#
C LDM VDD5 LDM VDD5 <19,25> FBCWE# C
DQMC#1 B3 DQMC#2 B3
UDM UDM FBCCS0#
VDDL J1 VDDL J1 <19,25> FBCCS0#
VSSDL J7 1 1 C384 VSSDL J7 1
ODTC0 K9 1U_0402_6.3V4Z ODTC0 K9 1 C726
ODT C385 256@ ODT C725 1U_0402_6.3V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 256@
+1.8VS DQSC0 2 256@ 2 DQSC3 2 256@
F7 LDQS F7 LDQS
DQSC#0 DQSC#3 2
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
R163 D2 D2 Close to U14
1K_0402_1% DQSC1 VSSQ4 DQSC2 VSSQ4 CLKC0
B7 UDQS VSSQ5 D8 B7 UDQS VSSQ5 D8 <19> CLKC0

1
VRAM_VREFC 256@ DQSC#1 A8 E7 VRAM_VREFC DQSC#2 A8 E7
UDQS VSSQ6 UDQS VSSQ6 R531
VSSQ7 F2 VSSQ7 F2
F8 F8 120_0402_5%
VSSQ8 VSSQ8 @ +1.8VS
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2

2
H8 H8

2
(SSTL-1.8) VREF = .5*VDDQ VSSQ10 (SSTL-1.8) VREF = .5*VDDQ VSSQ10 R533
A2 NC#A2 A2 NC#A2 1
E2 A3 E2 A3 481_0402_1%
NC#E2 VSS1 NC#E2 VSS1

1
R162 L1 E3 C728 L1 E3 256@ C733
1K_0402_1% C388 NC#L1 VSS2 0.047U_0402_16V4Z NC#L1 VSS2 R534 0.1U_0402_16V4Z
R3 J3 R3 J3

1
0.047U_0402_16V4Z NC#R3 VSS3 NC#R3 VSS3 120_0402_5% 2 @
256@ R7 N1 256@ R7 N1
NC#R7 VSS4 NC#R7 VSS4 @
256@ R8 NC#R8 VSS5 P9 Close to U81 R8 NC#R8 VSS5 P9
Close to U80 CLKC0#
<19> CLKC0#

2
256@ HY5PS561621F-25 256@ HY5PS561621F-25
For NV73 R533 change to 481_0402_1%(SD00000CA80)

B B

DDR2 BGA MEMORY

+1.8VS
256@ C412 256@ C413 256@ C382 +1.8VS DDR BGA MEMORY
0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 256@ C716 256@ C751 256@ C753
1 1 1 1 1 1 1 1 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.01U_0402_16V7K
1 1 1 1 1 1 1 1
256@ C398 256@ C410
1000P_0402_50V7K 0.01U_0402_16V7K 256@ C735 256@ C717
2 2 2 2 2 2 2 2 1000P_0402_50V7K 0.01U_0402_16V7K
256@ C383 256@ C411 256@ C395 2 2 2 2 2 2 2 2
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 256@ C718 256@ C750 256@ C752
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G71/72VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

FBDA[2..5]
<19> FBDA[2..5]
U8 U36
FBC_BA0 L2 B9 FBCD36 FBC_BA0 L2 B9 FBCD54 FBCD[63..0]
BA0 DQ15 BA0 DQ15 <19,24> FBCD[63..0]
FBC_BA1 L3 B1 FBCD33 FBC_BA1 L3 B1 FBCD49
D BA1 DQ14 FBCD39 BA1 DQ14 FBCD52 D
DQ13 D9 DQ13 D9
FBCA12 R2 D1 FBCD34 FBCA12 R2 D1 FBCD48 FBCA[12..0]
A12 DQ12 A12 DQ12 <19,24> FBCA[12..0]
FBCA11 P7 D3 FBCD35 FBCA11 P7 D3 FBCD51
FBCA10 A11 DQ11 FBCD37 FBCA10 A11 DQ11 FBCD53
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
FBCA9 P3 C2 FBCD32 FBCA9 P3 C2 FBCD50 DQSC#[7..0]
A9 DQ9 A9 DQ9 <19,24> DQSC#[7..0]
FBCA8 P8 C8 FBCD38 FBCA8 P8 C8 FBCD55
FBCA7 A8 DQ8 FBCD45 FBCA7 A8 DQ8 FBCD62
P2 A7 DQ7 F9 P2 A7 DQ7 F9
FBCA6 N7 F1 FBCD43 FBCA6 N7 F1 FBCD56 DQSC[7..0]
A6 DQ6 A6 DQ6 <19,24> DQSC[7..0]
FBDA5 N3 H9 FBCD42 FBDA5 N3 H9 FBCD61
FBDA4 A5 DQ5 FBCD46 FBDA4 A5 DQ5 FBCD57
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBDA3 N2 H3 FBCD47 FBDA3 N2 H3 FBCD58 DQMC#[7..0]
A3 DQ3 A3 DQ3 <19,24> DQMC#[7..0]
FBDA2 M7 H7 FBCD40 FBDA2 M7 H7 FBCD63
FBCA1 A2 DQ2 FBCD44 FBCA1 A2 DQ2 FBCD59
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBCA0 M8 G8 FBCD41 FBCA0 M8 G8 FBCD60 FBC_BA[1..0]
A0 DQ0 A0 DQ0 <19,24> FBC_BA[1..0]

CLKC1# K8 A9 CLKC1# K8 A9
CLKC1 CK VDDQ1 CLKC1 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
VDDQ3 C3 VDDQ3 C3
FBC_CKE K2 C7 FBC_CKE K2 C7
CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9
E9 E9 ODTC0
VDDQ6 +1.8VS VDDQ6 +1.8VS <19,24> ODTC0
VDDQ7 G1 VDDQ7 G1
FBCCS0# L8 G3 FBCCS0# L8 G3 FBC_CKE
CS VDDQ8 CS VDDQ8 <19,24> FBC_CKE
VDDQ9 G7 VDDQ9 G7
FBCWE# K3 G9 FBCWE# K3 G9 FBCRAS#
WE VDDQ10 WE VDDQ10 <19,24> FBCRAS#
FBCRAS# K7 A1 FBCRAS# K7 A1 FBCCAS#
RAS VDD1 RAS VDD1 <19,24> FBCCAS#
VDD2 E1 VDD2 E1
FBCCAS# L7 J9 FBCCAS# L7 J9 FBCWE#
CAS VDD3 CAS VDD3 <19,24> FBCWE#
VDD4 M9 VDD4 M9
DQMC#5 F3 R1 DQMC#7 F3 R1 FBCCS0#
C LDM VDD5 LDM VDD5 <19,24> FBCCS0# C
DQMC#4 B3 DQMC#6 B3
UDM UDM
VDDL J1 VDDL J1
VSSDL J7 1 1 C390 VSSDL J7 1 1
ODTC0 K9 1U_0402_6.3V4Z ODTC0 K9
ODT C386 256@ ODT C722 C719
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
DQSC5 2 256@ 2 DQSC7 2 256@ 2 256@
F7 LDQS F7 LDQS
+1.8VS DQSC#5 E8 A7 DQSC#7 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2
DQSC4 B7 D8 DQSC6 B7 D8
VRAM_VREFD R576 DQSC#4 UDQS VSSQ5 VRAM_VREFD DQSC#6 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
1K_0402_1% F2 F2
VSSQ7 VSSQ7
256@ VSSQ8 F8 VSSQ8 F8
J2 H2 J2 H2 CLKC1
VREF VSSQ9 VREF VSSQ9 <19> CLKC1

1
VSSQ10 H8 VSSQ10 H8
(SSTL-1.8) VREF = .5*VDDQ A2 (SSTL-1.8) VREF = .5*VDDQ A2 R167
R577 NC#A2 NC#A2 120_0402_5%
E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3
1K_0402_1% C392 L1 E3 C724 L1 E3 @ +1.8VS
NC#L1 VSS2 NC#L1 VSS2

2
256@ 0.047U_0402_16V4Z R3 J3 0.047U_0402_16V4Z R3 J3

2
NC#R3 VSS3 NC#R3 VSS3 R168
256@ R7 N1 256@ R7 N1 1
NC#R7 VSS4 NC#R7 VSS4 481_0402_1%
Close to U82 R8 NC#R8 VSS5 P9 Close to U83 R8 NC#R8 VSS5 P9

1
256@ C710
R169 0.1U_0402_16V4Z

1
256@ HY5PS561621F-25 256@ HY5PS561621F-25 120_0402_5% 2 @
@
CLKC1#
<19> CLKC1#

2
Close to U15

B For NV73 R168 change to 481_0402_1%(SD00000CA80) B

DDR2 BGA MEMORY DDR2 BGA MEMORY

+1.8VS +1.8VS
256@ C409 256@ C378 256@ C403 256@ C748 256@ C749 256@ C713
0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.01U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
256@ C406 256@ C405 256@ C745 256@ C404
1000P_0402_50V7K 0.01U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
256@ C407 256@ C402 256@ C374 256@ C744 256@ C747 256@ C746
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G71/72VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

STRAPS PIN DESCRIPTION Value

CRYSTAL[1:0] MIOBD[6,2] 27MHz=10, 14.318MHz=01, 13.5MHz=00 10

+3VS
MIOBD Parallel=00, SERIAL M25P10=01,
ROM_TYPE[1:0] [11:10] Serial SST45VF=10 01
VBIOS on card (pull high)
SUB_VENDOR MIOAD1 VBIOS with system BIOS (pull down) 0
CRYSTAL_1 1 2
D <18> CRYSTAL_1 D
R78 @ 2K_0402_5%
PEX_PLL_TERM MIOAD0 0
CRYSTAL_0 1 2
<18> CRYSTAL_0
R468 @ 2K_0402_5% MIOAD
PEX_CFG[2:0] [9,8,6] Overridden 001
16Mx16 (1.8V or 2.5V)Hynix X 4pcs 0011
RAM_CFG[3:0]
16Mx16 (1.8V or 2.5V)Infineon X 4pcs 0010
16Mx16 (1.8V or 2.5V)Samsung X 4pcs 0001
16Mx16 (1.8V or 2.5V)Hynix X 8pcs 1011
16Mx16 (1.8V or 2.5V)Infineon X 8pcs 1010
16Mx16 (1.8V or 2.5V)Samsung X 8pcs 1001
A01 NV72M 1000
PCI_DEVID[3:0] VIPD[5:3]
MIOA_HSYNC NV73M 1000

+3VS
1

1
C R73 R472 R64 R476 R67 R112 R493 R497 C
128@ 128@ @ 2K_0402_5% @ 2K_0402_5% 128@ @ @ 2K_0402_5% @ 2K_0402_5%
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
2

2
RAM_CFG0 R60 R474 R469 R108 R118 R84
<18> RAM_CFG0 RAM_CFG1 @ 2K_0402_5% @ 2K_0402_5% @ 2K_0402_5% 128@ @ 2K_0402_5% @ 2K_0402_5%
<18> RAM_CFG1 RAM_CFG2 2K_0402_5%
<18> RAM_CFG2 RAM_CFG3
<18> RAM_CFG3 PCI_DEVID0
<18> PCI_DEVID0 PCI_DEVID1
<18> PCI_DEVID1 PCI_DEVID2
<18> PCI_DEVID2 PCI_DEVID3
<18> PCI_DEVID3 PEX_CFG0
<18> PEX_CFG0 PEX_CFG1
<18> PEX_CFG1 PEX_CFG2
<18> PEX_CFG2 PEX_PLL_TERM
<18> PEX_PLL_TERM MOBILE_MODE
<18> MOBILE_MODE SUB_VENDOR
<18> SUB_VENDOR
R72 R59 R475 R470 R107 R117 R83
1

1
128@ @ @ @ @ @
@ 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%

R473 R63 R477 R66 R111 R494 R498

2

2
@ 2K_0402_5% 128@ @ 2K_0402_5% @ 2K_0402_5% 128@ 128@
2K_0402_5% @ 2K_0402_5% 2K_0402_5% 2K_0402_5%

B B

+3VS
Spread spectrum
1
128@ C376
0.1U_0402_16V4Z
2 U3
7 VDD REF 5

<18> OSC_OUT 1 XIN MODOUT 4 R133 1 128@ 2 22_0402_5% OSC_SPREAD <18>

8 XOUT NC 3 R134 2 1@ 10K_0402_5%

2 VSS PD# 6 R148 2 1@ 10K_0402_5%

ASM3P1819N-SR_SO8
128@

EMI request 6/7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
G71/72 VGA Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

R179 1 2 8.2K_0402_5% PCI_DEVSEL#

R529 1 2 8.2K_0402_5% PCI_STOP#

R528 1 2 8.2K_0402_5% PCI_TRDY#

R530 1 2 8.2K_0402_5% PCI_FRAME# <32,36> PCI_AD[0..31] U6B

PCI_AD0 E18 D7 PCI_REQ0#
R526 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 AD1 GNT0# E7
PCI_AD2 A16 C16 PCI_REQ1#
R540 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16
PCI_AD4 AD3 GNT1# PCI_REQ2#
E16 AD4 REQ2# C17 PCI_REQ2# <32>
R538 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2# <32>
PCI_AD6 E17 E13 PCI_REQ3#
R213 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4#
R178 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14
PCI_AD10 E14 C8 PCI_REQ5#
R527 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8

5
PCI_AD12 B12 U10
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 1

P
AD13 C/BE0# PCI_CBE#0 <32,36> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <32,36> Y PCI_RST# <32,33,36,42,44>
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 <32,36> A

G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 <32,36>
PCI_AD17 C11 @ TC7SH08FU_SSOP5

3
PCI_AD18 AD17 PCI _IRDY# R186
D11 AD18 IRDY# A7 PCI_IRDY# <32>
C PCI_AD19 PCI_PAR 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR <32>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <32>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <32> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR# R203
D9 AD24 SERR# B10 PCI_SERR# <32>
R195 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP# 2 1
AD25 STOP# PCI_STOP# <32> VGA_RST# <18>

5
PCI_AD26 A8 F14 PCI_TRDY# U11 0_0402_5%
AD26 TRDY# PCI_TRDY# <32,36>
R196 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1

P
AD27 FRAME# PCI_FRAME# <32,36> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# <7,31,32,34,37>
R194 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R193 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# @ TC7SH08FU_SSOP5
PCI_PME# <32,44>

3
AD31 PME#
R197 1 2 8.2K_0402_5% PCI_PIRQE# R185
0_0402_5%
R524 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3
Interrupt I/F G8 PCI_PIRQE# 2 1
PIRQA# GPIO2 / PIRQE# PCI_PIRQE# <32>
PCI_PIRQB# B4 F7 PCI_PIRQF#
R525 1 PCI_PIRQG# PCI_PIRQC# PIRQB# GPIO3 / PIRQF# PCI_PIRQG#
2 8.2K_0402_5% <32> PCI_PIRQC# C5 PIRQC# GPIO4 / PIRQG# F8 PCI_PIRQG# <32>
PCI_PIRQD# B5 G7 PCI_PIRQH#
<32> PCI_PIRQD# PIRQD# GPIO5 / PIRQH#
R198 1 2 8.2K_0402_5% PCI_PIRQH#

R192 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R211 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R210 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R212 1 2 8.2K_0402_5% PCI_REQ5# Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R176

@ 10_0402_5%

1
1
C415

@ 8.2P_0402_50V
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

C370
18P_0402_50V8J
2 1 ICH_RTCX1

10M_0402_5%
1
Y1

R144
2 NC IN 1
32.768KHZ_12.5P_1TJS125BJ4A421P
3 NC OUT 4
U6A
LPC_AD[0..3] <42,44>

2
C356

RTC
18P_0402_50V8J AB1 AA6 LPC_AD0
ICH_RTCX2 RTXC1 LAD0 LPC_AD1
2 1 AB2 RTCX2 LAD1 AB5
D LPC_AD2 D
LAD2 AC4
+RTCVCC R517 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3

LPC
20K_0402_5%
ICH_INTVRMEN W4 AC3 LPC_DRQ0#
+3VALW INTVRMEN LDRQ0# LPC_DRQ#0 <42>
CLRP1 SM_INTRUDER# Y5 AA5
INTRUDER# LDRQ1# / GPIO23
1 2
U4 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# <42,44>
SHORT PADS 8 1 EEP_CS W1
VCC CS EEP_SK EE_CS
7 NC SK 2 Y1 EE_SHCLK 2 1 R122 10K_0402_5% +3VS
C707 1 6 3 EEP_DOUT Y2 AE22 GATEA20
NC DI EE_DOUT A20GATE GATEA20 <44>

LAN
1U_0603_10V4Z C372 5 4 EEP_DIN W3 AH28 H_A20M#
GND DO EE_DIN A20M# H_A20M# <4>

CPU
1 2
0.1U_0402_16V4Z AT93C46-10SI-2.7_SO8 LAN_JCLK V3 AG27 H_CPUSLP_R# PAD T23
2 <35> LAN_JCLK LAN_CLK CPUSLP#
LAN_RSTSYNC U3 AF24 DPRSLP# 2 1 R121 0_0402_5%
<35> LAN_RSTSYNC LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# <4,53>
AH25 H_DPSLP#
TP2 / DPSLP# H_DPSLP# <4>
<35> LAN_RXD0 LAN_RXD0 U5 2 1 56_0402_5% +VCCP
LAN_RXD1 LAN_RXD0 H_FERR# R114
Q52 <35> LAN_RXD1 V4 LAN_RXD1 FERR# AG26 H_FERR# <4>
<35> LAN_RXD2 LAN_RXD2 T5
@ 2N7002_SOT23 LAN_RXD2 H_PW RGOOD
GPIO49 / CPUPWRGD AG24 H_PWRGOOD <4>
LAN_TXD0 U7
<35> LAN_TXD0 LAN_TXD0
S

D
3 1 LAN_TXD1 V6 AG22 H_IGNNE#
<35> LAN_TXD1 LAN_TXD1 IGNNE# H_IGNNE# <4>
LAN_TXD2 V7 AG21
<35> LAN_TXD2 LAN_TXD2 INIT3_3V#
C381 @ 10P_0402_25V8K AF22 H_INIT#
INIT# H_INIT# <4>
C828 1 R150 H_INTR
G

2 1 2 AF25 H_INTR <4>

2

@ 10_0402_5% INTR
+VCCP

AC-97/AZALIA
@ 0.1U_0402_16V4Z 2 1 <38> ACZ_BITCLK ACZ_BITCLK U1 2 1 R508 10K_0402_5%
ACZ_BCLK +3VS
ACZ _SYNC R6 AG23 KB_RST#
<38> ACZ_SYNC ACZ_SYNC RCIN# KB_RST# <44>
R155

1
R608 33_0402_5% 1 2 ACZRST# R5 AF23 H_SMI#
<38,44> ACZ_RST# ACZ_RST# SMI# H_SMI# <4>
1 2 AH24 H_NMI R119
NMI H_NMI <4>
@ 47K_0402_5% ACZ_SDIN0 T2
C <38> ACZ_SDIN0 ACZ_SDIN0 C
T3 AH22 H_STPCLK# 56_0402_5%
ACZ_SDIN1 STPCLK# H_STPCLK# <4>
T1

2
ACZ_SDIN2 THRMTRIP_ICH#
THERMTRIP# AF26 1 R120 2 H_THERMTRIP# <4,7>
ACZ_SDOUT T4 24.9_0402_1%
<38> ACZ_SDOUT ACZ_SDOUT
EC_RTCRESET AH17 PD_A0
<44> EC_RTCRESET DA0 PD_A0 <31>
IDE_LED# AF18 AE17 PD_A1
<43> IDE_LED# SATALED# DA1 PD_A1 <31>
AF17 PD_A2
DA2 PD_A2 <31>
PSATA_IRX_DTX_N0_C AF3 AE16 PD_CS#1
+RTCVCC <31> PSATA_IRX_DTX_N0_C SATA0RXN DCS1# PD_CS#1 <31>
PSATA_IRX_DTX_P0_C AE3 AD16 PD_CS#3
<31> PSATA_IRX_DTX_P0_C SATA0RXP DCS3# PD_CS#3 <31>
PSATA_ITX_DRX_N0_C AG2 SATA0TXN

SATA
PSATA_ITX_DRX_P0_C AH2 SATA0TXP PD_D0
DD0 AB15
1

SSATA_IRX_DTX_N0_C AF7 AE14 PD_D1

<31> SSATA_IRX_DTX_N0_C SATA2RXN DD1
R516 SSATA_IRX_DTX_P0_C AE7 AG13 PD_D2
<31> SSATA_IRX_DTX_P0_C SATA2RXP DD2
SSATA_ITX_DRX_N0_C AG6 AF13 PD_D3
1M_0402_5% SSATA_ITX_DRX_P0_C SATA2TXN DD3 PD_D4
AH6 SATA2TXP DD4 AD14
AC13 PD_D5
2

SM_INTRUDER# CLK_PCIE_SATA# DD5 PD_D6

<15> CLK_PCIE_SATA# AF1 SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 PD_D7
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 PD_D8
R127 DD8 PD_D9
AH10 SATARBIASN DD9 AF12
+RTCVCC 1 2 AG10 AB13 PD_D10
+3VS SATARBIASP DD10 PD_D11
DD11 AC14
24.9_0402_1% AF14 PD_D12
DD12 PD_D13
DD13 AH13
1

PD_D14
R519 4.7K_0402_5% 2 1 R126 PD _IORDY PD _IORDY AG16
IDE DD14 AH14
AC15 PD_D15
<31> PD_IORDY IORDY DD15
8.2K_0402_5% 2 1 R125 PD_IRQ PD_IRQ AH16
<31> PD_IRQ IDEIRQ
332K_0402_1% PD_DACK# AF16
<31> PD_DACK# DDACK#
PD_IOW# AH15 AE15 PD_DREQ
<31> PD_IOW# PD_DREQ <31>
2

B PD_IOR# DIOW# DDREQ B

<31> PD_IOR# AF15 DIOR#
ICH_INTVRMEN

ICH7_BGA652~D

PD_D[0..15]
PD_D[0..15] <31>
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C
<31> PSATA_ITX_DRX_N0
C353 3900P_0402_50V7K

PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C
<31> PSATA_ITX_DRX_P0
C351 3900P_0402_50V7K

LDO3
+RTCVCC
SSATA_ITX_DRX_N0 1 2 SSATA_ITX_DRX_N0_C JP23
<31> SSATA_ITX_DRX_N0
C348 3900P_0402_50V7K
D26
<31> SSATA_ITX_DRX_P0
SSATA_ITX_DRX_P0 1
C341
2 SSATA_ITX_DRX_P0_C
3900P_0402_50V7K 1
2
R488
BATT1.1
+ - BATT1

3 1 2 1 + - 2
W=20mils
2 DAN202U_SC70 1K_0402_5%
close ICH7
C679 CR2032 RTC BATTERY
1U_0603_10V4Z
1 SUYIN_060003FA002TX00NL~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS Place closely pin B2 Place closely pin AC1

CLK_48M_ICH CLK_14M_ICH
+3VALW +3VALW

1
10K_0402_5%
R123 1 2 SIRQ R539 R136

1
2

2
8.2K_0402_5% R222 R220 @ 10_0402_5% @ 10_0402_5%
R124 1 2 PCI_CLKRUN# R208 R207

2
2.2K_0402_5% 2.2K_0402_5% U6C
10K_0402_5% 10K_0402_5% 1 1

2
<15,34,37> ICH_SMBCLK ICH_SMBCLK C22 AF19 C740 C350

1
D ICH_SMBDATA SMBCLK GPIO21 / SATA0GP D
<15,34,37> ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R507 2
ICH_SMLINK1 A25 100_0402_5%
SMLINK1
+3VALW +3VALW
R172 AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH <15>

Clocks
10K_0402_5% 1 2 I CH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
R173 1 2 LINKALERT# 8.2K_0402_5%
SB_SPKR A19
<38>SB_SPKR SPKR
150_0402_5% PAD T25 SUS_STAT# A27 C20 ICH_SUSCLK T28 PAD
R221 1 SUS_STAT# SUSCLK
2 ITP_DBRESET# <4> ITP_DBRESET#
ITP_DBRESET# A22 SYS_RST#

SYS
B24 SLP_S3#
SLP_S3# SLP_S3# <44>
10K_0402_5% PM_BMBUSY# AB18 D23 SLP_S4#
<7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S4# <44>
R219 1 2 OCP# F22 SLP_S5#
SLP_S5# SLP_S5# <44>
OCP# B23
<4> OCP# GPIO11 / SMBALERT#
10K_0402_5% AA4 ICH_POK R511
PWROK ICH_POK <7,44>

POWER MGT
R156 1 2 SPI_MISO <15> H_STP_PCI#
H_STP_PCI# AC20 GPIO18 / STPPCI# 1 2 10K_0402_5%

GPIO
H_STP_CPU# AF21 AC22 DPRSLPVR
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR <7,53>
10K_0402_5%
R159 1 2 SPI_CS# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT#

10K_0402_5% B21 C23 PWRBTN_OUT#

GPIO27 PWRBTN# PWRBTN_OUT# <44>
R223 1 2 BT_DET# EC_FLASH# E23
<45> EC_FLASH# GPIO28
C19 LAN_RST#
LAN_RST# LAN_RST# <44>
1K_0402_5% PCI_CLKRUN# AG18
<32> PCI_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
R182 1 2 ICH_PCIE_WAKE# Y4
RSMRST# EC_RSMRST# <44>
AC19 R514 10K_0402_5%
8.2K_0402_5% GPIO33 / AZ_DOCK_EN#
U2 GPIO34 / AZ_DOCK_RST# 1 2
R209 2 1 ICH_LOW_BAT#
10K_0402_5% ICH_PCIE_WAKE# F20 E20 EC_SCI#
<34,37> ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# <44>
R153 1 2 WL_ON SIRQ AH21 A20 BT_DET#
C <32,42,44> SIRQ SERIRQ GPIO10 BT_DET# <41> C
EC_THERM# AF20 F19 PCBEEP DPRSLPVR 2 1
<44> EC_THERM# THRM# GPIO12 PCBEEP <40>
10K_0402_5% E19 LID_OUT# R509
GPIO13 LID_OUT# <44>
R578 1 2 SPI_MOSI VGATE AD22 R4 @ 100K_0402_5%
<44,53> VGATE VRMPWRGD GPIO14
E22 CPUSB#
GPIO15 CPUSB# <34,44>
10K_0402_5% R3 WL_ON
GPIO24 WL_ON <37>
R590 1 2 PCBEEP AC21 D20 BT_ON#
AC18
GPIO6 GPIO GPIO25
AD21
BT_ON# <41>
EC_SMI# GPIO7 GPIO35 / SATAREQ#
<44> EC_SMI# E21 GPIO8 GPIO38 AD20
GPIO39 AE20

ICH7_BGA652~D Need update symbol

U6D
PCIE_RXN1 F26 V26 DMI_RXN0
<34> PCIE_RXN1 PERn1 DMI0RXN DMI_RXN0 <7>
PCIE_RXP1 F25 V25 DMI_RXP0
<34> PCIE_RXP1 PERp1 DMI0RXP DMI_RXP0 <7>

DIRECT MEDIA INTERFACE

<34> PCIE_TXN1 0.1U_0402_16V4Z 2 1 C399 PCIE_C_TXN1 E28 U28 DMI_TXN0
PETn1 DMI0TXN DMI_TXN0 <7>
<34> PCIE_TXP1 0.1U_0402_16V4Z 2 1 C396 PCIE_C_TXP1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 <7>
PCIE_RXN2 H26 Y26 DMI_RXN1
<34> PCIE_RXN2 PERn2 DMI1RXN DMI_RXN1 <7>
PCIE_RXP2 H25 Y25 DMI_RXP1
<34> PCIE_RXP2 PERp2 DMI1RXP DMI_RXP1 <7>
<34> PCIE_TXN2 0.1U_0402_16V4Z 2 1 C391 PCIE_C_TXN2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
<34> PCIE_TXP2 0.1U_0402_16V4Z 2 1 C393 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 <7>

PCI-EXPRESS
PCIE_RXN3 K26 AB26 DMI_RXN2
<37> PCIE_RXN3 PERn3 DMI2RXN DMI_RXN2 <7>
PCIE_RXP3 K25 AB25 DMI_RXP2
<37> PCIE_RXP3 PERp3 DMI2RXP DMI_RXP2 <7>
<37> PCIE_TXN3 0.1U_0402_16V4Z 2 1 C389 PCIE_C_TXN3 J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
<37> PCIE_TXP3 0.1U_0402_16V4Z 2 1 C387 PCIE_C_TXP3 J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 <7>
M26 AD25 DMI_RXN3
B PERn4 DMI3RXN DMI_RXN3 <7> B
M25 AD24 DMI_RXP3
PERp4 DMI3RXP DMI_RXP3 <7>
L28 AC28 DMI_TXN3
PETn4 DMI3TXN DMI_TXN3 <7>
L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R166 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 RP20
PERn6 USB20_N0 USB_OC#7
T24 PERp6 USBP0N F1 USB20_N0 <41> 4 5 +3VALW
R28 F2 USB20_P0 USB_OC#1 3 6
PETn6 USBP0P USB20_P0 <41>
R27 G4 USB20_N1 USB_OC#2 2 7
PETp6 USBP1N USB20_N1 <46>
G3 USB20_P1 USB_OC#4 1 8
USBP1P USB20_P1 <46>
R2 SPI_CLK USBP2N H1
SPI_CS# P6 H2 10K_1206_8P4R_5%
SPI_CS# SPI USBP2P USB20_N3
P1 SPI_ARB USBP3N J4 USB20_N3 <41>
J3 USB20_P3 R175
USBP3P USB20_P3 <41>
SPI_MOSI P5 K1 USB20_N4 10K_0402_5%
SPI_MOSI USBP4N USB20_N4 <42>
SPI_MISO P2 K2 USB20_P4 USB_OC#6 1 2
SPI_MISO USBP4P USB20_P4 <42>
L4 USB20_N5
USBP5N USB20_N5 <42>
L5 USB20_P5
USBP5P USB20_P5 <42>
USB_OC#0 D3 M1 USB20_N6
<41> USB_OC#0 OC0# USBP6N USB20_N6 <41>
USB_OC#1 C4 M2 USB20_P6
USB_OC#2 D5
OC1# USB USBP6P
N4 USB20_N7
USB20_P6 <41>
OC2# USBP7N USB20_N7 <34>
USB_OC#3 D4 N3 USB20_P7
<41> USB_OC#3 OC3# USBP7P USB20_P7 <34>
USB_OC#4 E5
<42> USB_OC#4 OC4#
USB_OC#5 C3 R165 22.6_0402_1%
<42> USB_OC#5 OC5# / GPIO29
USB_OC#6 A2 D2 USBRBIAS 1 2
USB_OC#7 OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1
Within 500 mils
A ICH7_BGA652~D A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCP
U6F U6E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C721 C711 + C708 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 220U_D2_4VM D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS

220U_D2_4VM
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
+ C714 C715 C739 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] VSS[10] VSS[108]

C693
AC23 T11 1U_0603_10V4Z C6 T12
Vcc1_5_B[5] Vcc1_05[11] VSS[11] VSS[109]
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R518 D18 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% CH751H-40_SC76 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
C697 C729 D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C701 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VALW VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C695 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C694 G6 V28

R164 D8 Vcc1_5_B[26] Vcc3_3[5] C700 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% CH751H-40_SC76 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C690 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C732 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C731

C737

C730
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C743 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C712

C709
V23 A24 C741 C738 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R109 R129 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C723 C720 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C349

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C352

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C691 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C698

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C688

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C696 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C699 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T32 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T26 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T29 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C734 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C727 P15 AH3
0.1U_0402_16V4Z C742 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T30 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T31 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3VALW W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C375
A A
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS
+5VS +3VS

22U_1206_6.3V6M

22U_1206_6.3V6M
0.1U_0402_16V4Z 0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

22U_1206_6.3V6M

22U_1206_6.3V6M
0.1U_0402_16V4Z 0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1
C439

C453

C457

C434

C468

C460
1 1 1 1 1 1 1 1 1 1

C500

C514

C524

C465

C482

C486
C449 C445 C464 C447
C518 C513 C485 C473
2 2 2 2 2 2 2 2 2 2
D 1U_0603_10V4Z 1U_0603_10V4Z 2 2 2 2 2 2 2 2 2 2 D
1U_0603_10V4Z 1U_0603_10V4Z
Pleace near HD CONN
Pleace near HD CONN
Pleace near HD CONN Pleace near HD CONN
JP33
JP31
1 GND
PSATA_ITX_DRX_P0 2 1
<28> PSATA_ITX_DRX_P0 A+ GND
C505 PSATA_ITX_DRX_N0 3 SSATA_ITX_DRX_P0 2
<28> PSATA_ITX_DRX_N0 A- <28> SSATA_ITX_DRX_P0 A+
3900P_0402_50V7K 4 C480 SSATA_ITX_DRX_N0 3
GND <28> SSATA_ITX_DRX_N0 A-
2 1 PSATA_IRX_DTX_N0 5 3900P_0402_50V7K 4
<28> PSATA_IRX_DTX_N0_C B- GND
6 2 1 SSATA_IRX_DTX_N0 5
B+ <28> SSATA_IRX_DTX_N0_C B-
7 GND 6 B+
2 1 PSATA_IRX_DTX_P0 7
<28> PSATA_IRX_DTX_P0_C GND
2 1 SSATA_IRX_DTX_P0
<28> SSATA_IRX_DTX_P0_C
C503 +3VS 8
3900P_0402_50V7K V33 C484
9 V33 +3VS 8 V33
10 3900P_0402_50V7K 9
V33 V33
11 GND 10 V33
12 GND 11 GND
close SATA connector 13 GND 12 GND
+5VS 14 V5 close SATA connector 13 GND
15 V5 +5VS 14 V5
16 V5 15 V5
17 GND 16 V5
18 Reserved 17 GND
19 GND 18 Reserved
20 V12 19 GND
21 V12 20 V12
22 V12 21 V12
C C
22 V12
SUYIN_127059FR022S305ZL
SUYIN_127059FR022S305ZL
Main HDD
2nd HDD
Need update symbol
Need update symbol
Main SATA +5V Default
Main SATA +5V Default

PD_D[0..15]
PD_D[0..15] <28>

B B

CD_AGND <38>
JP25
<38> CDROM_L 1 1 2 2 CDROM_R <38>
3 3 4 4
PLT_RST# 2 R217 1 33_0402_5% 5 6 PD_D8
<7,27,32,34,37> PLT_RST# 5 6
PD_D7 7 8 PD_D9
PD_D6 7 8 PD_D10
9 9 10 10
PD_D5 11 12 PD_D11
PD_D4 11 12 PD_D12
13 13 14 14
PD_D3 15 16 PD_D13
PD_D2 15 16 PD_D14
17 17 18 18
PD_D1 19 20 PD_D15
PD_D0 19 20 PD_DREQ
21 21 22 22 PD_DREQ <28>
23 24 PD_IOR#
23 24 PD_IOR# <28>
PD_IOW# 25 26 +5VS
<28> PD_IOW# 25 26
PD _IORDY 27 28 PD_DACK# R157
<28> PD_IORDY 27 28 PD_DACK# <28>
PD_IRQ 29 30 100K_0402_5%
<28> PD_IRQ 29 30
PD_A1 31 32 PDIAG# 1 2
<28> PD_A1 31 32 +5VS
PD_A0 33 34 PD_A2 1 1
<28> PD_A0 33 34 PD_A2 <28>
PD_CS#1 35 36 PD_CS#3
<28> PD_CS#1 35 36 PD_CS#3 <28>
ACT_LED# 37 38 C371 C357
<43> ACT_LED# 37 38
39 40 1U_0603_10V4Z 10U_0805_10V4Z
39 40 2 2
+5VS 41 41 42 42 +5VS
43 43 44 44 2 1
45 45 46 46
PRI_CSEL 47 48 C380
47 48 0.1U_0402_16V4Z
49 49 50 50
2

51 GND GND 52
53 GND GND 54
A R147 A
470_0402_5% SUYIN_800059MR050S119ZL
1

CD-ROM Connector
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
L23
+3VS +3VS_CBPLL +VCC_MS +VCC_MS +VCC_SD +VCC_MS +VCC_SM_XD
1 2
7412@ MBK160808_0603

CR@ 100K_0402_5%

CR@ 100K_0402_5%

CR@ 100K_0402_5%

22K_0402_5%
+VDD_PLL2 1 +VDDPLL

S
R234 C458 7412@ 0.1U_0402_16V4Z

D
3 1 3 1
+3VS_CBVCCP +3VS

0.01U_0402_16V7K
7412@ 0_0805_5% Q43 Q44

2
10U_0805_10V4Z

1U_0603_10V4Z

K1 C452 1U_0603_10V4Z
CR@ CR@

G
1 1 1

2
1U_0603_10V4ZC467
SI2301BDS_SOT23 C779 R565 SI2301BDS_SOT23C782 R566
PCI_AD[0..31] 1 1 1 7412@ R293
<27,36> PCI_AD[0..31]

CR@
C429

C432

C433

R554

R557

R556

R559
0.1U_0402_16V4Z @47K_0402_5% @47K_0402_5%
2 2 2

7412@
PCI_CBE#[0..3] 1 1 7412@ 0_0805_5%
<27,36> PCI_CBE#[0..3]

1
1 C435 C448
2 2 2 MSBS_SDCMD_SMWE# CR@ 10U_0805_10V4Z CR@ 10U_0805_10V4Z
+3VS

7412@

7412@

7412@

7412@
D 7412@ D
2 2 0.1U_0402_16V4Z
2 SDCLK_SMRE#

2
U15

U19
P13
P14

P15

K19

W8
+3VS R564 +3VS

P1
U18B SDWP#_SMCE#
CR@ 10K_0402_5%

VCCP
VCCP
AVDD_33
AVDD_33
AVDD_33

VDDPLL_33
VDDPLL_15

VR_PORT
VR_PORT

2
M1 PCI_AD31

1
AD31 PCI_AD30 SM_RB# R374 MS_CD# SD_CD# R358
AD30 M2
M3 PCI_AD29
AD29

2
G

G
M6 PCI_AD28 CR@ 10K_0402_5% CR@ 10K_0402_5%
MC_PWRON# AD28 PCI_AD27
C8 M5

1
PWR_CTRL_1/SM_R/B# MC_PWR_CTRL_0 AD27 PCI_AD26 MC_PWRON#
F8 MC_PWR_CTRL_1/SM_R/B# AD26 N1 3 1 3 1
PCI_AD25 +VCC_SD +VCC_SM_XD

D
AD25 N2

1
PCI_AD24 D Q22 Q19
AD24 N3
P3 PCI_AD23 CARD_LED 2 CR@ 2N7002_SOT23 CR@ 2N7002_SOT23
SD_CD# AD23 PCI_AD22
E9 SD_CD# AD22 R1 2 C823 2 C824 G Q23
MS_CD# A8 R2 PCI_AD21 +3VS 1000P_0402_50V7K 1000P_0402_50V7K S @ 2N7002_SOT23

3
SM_CD# MS_CD# AD21 PCI_AD20 SD_CD#
B8 SM_CD# AD20 P5 2 1
R3 PCI_AD19 near JP32 pin1 D9 @ CH751H-40_SC76
AD19 PCI_AD18 1 SM_CD#
AD18 T1 2 1

1
R360 T2 PCI_AD17 D10 @ CH751H-40_SC76
MSCLK_SDCLK_SMELWP# 1 AD17 PCI_AD16 R241
2 A7 MS_CLK/SD_CLK/SM_EL_WP# AD16 W4
CR@ 22_0402_5% MSBS_SDCMD_SMWE# E8 W7 PCI_AD15 D29 CH751H-40_SC76
MS_BS/SD_CMD/SM_WE# AD15

2
G
1 MSD3_SDD3_SMD3 B6 R8 PCI_AD14 @ 10K_0402_5% +VCC_MS 1 2 D33 CH751H-40_SC76 1 2
C825 MSD2_SDD2_SMD2 MS_DATA3/SD_DAT3/SM_D3 AD14 PCI_AD13 D30 CH751H-40_SC76
A6 U8

2
MSD1_SDD1_SMD1 MS_DATA2/SD_DAT2/SM_D2 AD13 PCI_AD12 CB_PME#
C7 MS_DATA1/SD_DAT1/SM_D1 AD12 V8 3 1 PCI_PME# <27,44> 1 2 D34 CH751H-40_SC76 1 2
15P_0402_50V8J MSD0_SDD0_SMD0 PCI_AD11 D31 CH751H-40_SC76

D
B7 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD11 W9
2 PCI_AD10 Q8
AD10 V9 1 2 D35 CH751H-40_SC76 1 2
U9 PCI_AD9 @ 2N7002_SOT23 D32 CH751H-40_SC76
AD9 PCI_AD8
AD8 R9 1 2 D36 CH751H-40_SC76 1 2
V10 PCI_AD7
C SDCLK_SMRE# AD7 PCI_AD6 C
A4 SD_CLK/SM_RE# AD6 U10
SDCMD_SMALE C5 R10 PCI_AD5 JP32
SDD0_SMD4 SD_CMD/SM_ALE AD5 PCI_AD4 MSD0_SDD0_SMD0 R595 CR@
C6 SD_DAT0/SM_D4 AD4 W11 34 SM-D0 SD-DAT3 11 1 33_0402_5%
2MSD3_SDD3_SMD3
SDD1_SMD5 A5 V11 PCI_AD3 MSD1_SDD1_SMD1 33 12 R596 CR@ 2MSD2_SDD2_SMD2
1 33_0402_5%
SDD2_SMD6 SD_DAT1/SM_D5 AD3 PCI_AD2 MSD2_SDD2_SMD2 SM-D1 / XD-D1 SD-DAT2 R597 CR@
B5 SD_DAT2/SM_D6 AD2 U11 32 SM-D2 / XD-D2 SD-DAT1 6 1 33_0402_5%
2MSD1_SDD1_SMD1
SDD3_SMD7 E6 P11 PCI_AD1 MSD3_SDD3_SMD3 31 5 IN 1 CONN SD-DAT0 7 R598 CR@ 2MSD0_SDD0_SMD0
1 33_0402_5%
SDWP#_SMCE# SD_DAT3/SM_D7 AD1 PCI_AD0 SDD0_SMD4 SM-D3 / XD-D3 SDWP#_SMCE#
E7 SD_WP/SM_CE# AD0 R11 21 SM-D4 / XD-D4 SD-WP-SW 5
SDD1_SMD5 22 10 R599 CR@1 33_0402_5%
2MSBS_SDCMD_SMWE#
SDD2_SMD6 SM-D5 / XD-D5 SD-CMD MSCLK_SDCLK_SMELWP#
G5 SC_PWR_CTRL 23 SM-D6 / XD-D6 SD_CLK 8
P2 PCI_CBE#3 SDD3_SMD7 24 9 +VCC_SD
SMCLE C/BE3# PCI_CBE#2 SM-D7 / XD-D7 SD-VCC C826 1
B4 SM_CLE C/BE2# U5 NC 4 21000P_0402_50V7K
XD_CD#/SM_PHYS_WP#1 2 A3 V7 PCI_CBE#1 MSCLK_SDCLK_SMELWP# 35 42 SD_CD#
R607 10_0402_5%
1 2
XD_CD#/SM_PHYS_WP#
PCI7412 C/BE1#
C/BE0# W10 PCI_CBE#0 SM_PHYS_WP#
MSBS_SDCMD_SMWE#
43
36
SM_WP-IN / XD_WP-IN
SM-WP-SW
SD-CD-SW
SD-CD-COM 41

@ C827 10P_0402_50V8J SDCMD_SMALE #SM_-WE / XD_-WE MSD0_SDD0_SMD0

PAR U7 PCI_PAR <27> 37 #SM-ALE / XD-ALE MS-DATA0 15
P12 R6 PCI_FRAME# <27,36> +VCC_SM_XD 14 MSD1_SDD1_SMD1
CLK_48M_CB TEST0 FRAME# MS-DATA1 MSD2_SDD2_SMD2
<15> CLK_48M_CB F1 CLK_48 TRDY# W5 PCI_TRDY# <27,36> 25 SM-LVD MS-DATA2 16
+3VS 1 2 R316 P17 PHY_TEST_MA IRDY# V5 PCI_IRDY# <27> SM_CD# 3 SM-CD-SW MS-DATA3 18 MSD3_SDD3_SMD3
7412@ 4.7K_0402_5% V6 29 19 MSCLK_SDCLK_SMELWP#
STOP# PCI_STOP# <27> SM_-VCC / XD_-VCC MS-SCLK +VCC_MS
1U_0603_10V4Z

2 U6 SM_RB# 26 17 MS_CD#
DEVSEL# PCI_DEVSEL# <27> #SM_R/-B / XD_R/-B MS-INS
1

1
1394@ C426

1394@ R263

1394@ R262
56.2_0603_1%

56.2_0603_1%

IDSEL N5 2 R249 1 PCI_AD22 1 SDCLK_SMRE# 27 #SM_-RE / XD_-RE MS-BS 13 MSBS_SDCMD_SMWE#

R280 7412@ 6.34K_0402_1% R7 7412@ 100_0402_5% C771 SDWP#_SMCE# 28 20 +VCC_SM_XD
PERR# PCI_PERR# <27> #SM_-CE / XD_-CE MS-VCC
1 2 T18 W6 CR@ 30
1 R0 SERR# PCI_SERR# <27> #SM_-CD
T19 L3 0.1U_0402_16V4Z 2 40
R1 REQ# PCI_REQ2# <27> SM-CD-COM XD-VCC
8
7
6
5

XTPBIAS0 2 SMCLE XD_CD#

R13 L2 PCI_GNT2# <27> 38 39
2

XTPA0+ TPBIAS0 GNT# SM-CLE / XD-CLE XD-CD

4 V14 45 1
GND4
GND3
GND2
GND1

4 XTPA0- TPA0P CLK_PCI_PCM GND GND

3 3 W14 TPA0N PCLK L1 CLK_PCI_PCM <15> 46 GND GND 44
2 XTPB0+ V13 K3 PCI_RST# PCI_RST# <27,33,36,42,44>
2 XTPB0- TPB0P PRST# GRST# R321 1 TAITN_R007-N3P-15-S
1 1 W13 TPB0N GRST# K5 2 PLT_RST# <7,27,31,34,37>
270P_0603_50V8J 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

XTPBIAS1 W17 L5 CB_PME# @ 0_0402_5%

TPBIAS1 RI_OUT#/PME#
1

1
1394@ R264

1394@ R265

JP28 XTPA1+ V16

SUYIN_020204FR004S506ZL XTPA1- TPA1P R329 R315
W16 TPA1N SUSPEND# J5 +3VS
B XTPB1+ 7412@ 43K_0402_5% PCI_RST# 1 B
V15 TPB1P 2 GRST#
XTPB1- W15 H3 7412@ 0_0402_5%
TPB1N SPKROUT PCM_SPK <38> +VCC_MS
CPS R12
2

CPS R314 7412@

MFUNC0 G1 2 1 0_0402_5% PCI_PIRQC# <27>
X_OUT R18 H5 R190 2 7412@1 0_0402_5% CARD_LED
XO MFUNC1 PCI_PIRQD# <27>
1

2
1 X_IN R19 H2 R204 2 7412@1 0_0402_5%
XI MFUNC2 PCI_PIRQG# <27>

2
1394@ C427

1394@ R242

H1 R313 2 7412@1 0_0402_5% R389

+3VS MFUNC3 SIRQ <29,42,44>
J1 R189 2 7412@1 0_0402_5% R602
MFUNC4 PCI_PIRQE# <27>
J2 CARD_LED @ 470_0402_5%
2 MFUNC5 CARD_LED <43>
J3 7412@ 10K_0402_5%
2

1 1
R342 1 MFUNC6 PCI_CLKRUN# <29>
2 CPS

1
7412@ 4.7K_0402_5% R328 D
SCL G2 2 1 7412@ 220_0402_5%
G3 R344 2 1 7412@ 220_0402_5% PCM_SPK MC_PWRON# 2
SDA
VSSPLL

G Q24
CLOSE TO CHIP
AGND
AGND
AGND

C451 1 2 X_OUT K2 R320 2 1 7412@ 220_0402_5% S @ 2N7002_SOT23

3
VR_EN#

2
7412@
1

10P_0402_50V8J R588
CLOSE TO CHIP R298 Y3 PCI7412ZHK_PBGA257 7412@ 43K_0402_5%
R14
U13
U14

R17

@ 1M_0402_5% 7412@ 7412@

24.576MHZ_16P_1BG24576CK1A +3VS +3VS
2

1
1

+VCC_MS
7412@ C423

7412@ R251

7412@ R250
1U_0603_10V4Z

56.2_0603_1%

56.2_0603_1%

C444 1 2 X_IN +VDDPLL

2 7412@

2
10P_0402_50V8J CLK_48M_CB CLK_PCI_PCM U42
R567
1

1 8
2

1 R334 R214 GND OUT CR@ 10K_0402_5%

2 IN OUT 7
XTPBIAS1 3 6

1
XTPA1+ @ 10_0402_5% @ 10_0402_5% MC_PWRON# IN OUT
<46> XTPA1+ 4 EN# OC# 5
XTPA1-
<46> XTPA1-
2

XTPB1+ 2 1
<46> XTPB1+
XTPB1- C470 C420 CR@ TPS2041BDR_SO8
<46> XTPB1-
270P_0603_50V8J 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

SM_RB#/SC_RFU R3491 2 SM_RB# R352 1 2 PWR_CTRL_1/SM_R/B#

<33> SM_RB#/SC_RFU
1

1
7412@ C428 7412@ R261

7412@ R244 7412@ R260

A @ 0_0402_5% CR@ 0_0402_5% @ 10P_0402_50V8J @ 15P_0402_50V8J C781 2 A

1 CR@ 10U_0805_10V4Z
1 2
SM_PHYS_WP#R363 1 2 C778 2 1 CR@ 0.01U_0402_16V7K
CR@ 0_0402_5%
R362 1 2 XD_CD#/SM_PHYS_WP#
2

CR@ 0_0402_5%
XD_CD# R361 1 2 SM_CD#
1

1 @ 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
2 PCI7412
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

CardBus Power Switch

7412@10U_0805_10V4Z

0.1U_0402_16V4Z
+S1_VCC +3VS U20

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 CB_DAT 3 20
CB_CLK DATA 12V
4 CLOCK 12V 7
+3VS

C780

C489

C490

C483

C481

C436

C478

C469
C487 C461 CB_LATCH 5
D PCI_RST# LATCH D
<27,32,36,42,44> PCI_RST# 12 RESET#
7412@ 2 2 7412@ 2 2 2 2 2 2 2 2
15 OC# NC3 14

7412@ 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

7412@

7412@

7412@

7412@

7412@

7412@

7412@
21 SHDN# 3.3V 13
1

A15

P10
F12
F14

L14
J19

J14
+5VS

P6
P8
F6
F9

L6
J6

C523
U18A +S1_VPP 8 24
AVPP NC4

7412@ 0.1U_0402_16V4Z
19 2

VCCB
VCCB

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
S1_D10 NC0 5V 2
C10 CAD31/D10 5V 1 1
S1_D9 A10 CAD30/D9

C495
S1_D1 F11 B9 CB_DAT +S1_VCC 9 11
S1_D8 CAD29/D1 DATA/VD2/VPPD1 CB_CLK AVCC GND
E11 CAD28/D8 CLOCK/VD1/VCCD0# A9 10 AVCC
S1_D0 CB_LATCH 2
C11 CAD27/D0 LATCH/VD3/VPPD0 C9
S1_A0 B13 17 23
S1_A1 CAD26/A0 NC1 NC5
C13 CAD25/A1 18 NC2 NC6 22
S1_A2 A14 16
S1_A3 CAD24/A2 NC7
B14 CAD23/A3 NC8 6
S1_A4 B15
S1_A5 CAD22/A4
E14 CAD21/A5
S1_A6 A16 7412@TPS2220ADBRG4_SSOP24
S1_A25 CAD20/A6 +3VS
D19 CAD19/A25
S1_A7 E17 B10 S1_D2 43K_0402_5%
S1_A24 CAD18/A7 RSVD/D2 R350 1
F15 CAD17/A24 RSVD/VD0/VCCD1# C4 2
S1_A17 H19 D1 SM_RB#/SC_RFU @ 43K_0402_5% JP10
S1_IOWR# CAD16/A17 RSVD SM_RB#/SC_RFU <32> R351 1
J17 CAD15/IOWR# RSVD E1 2 GND 1
S1_A9 J15 E2 7412@ 35
S1_IORD# CAD14/A9 RSVD GND S1_D3
J18 E3 2
S1_A11 K15
CAD13/IORD# RSVD
F2
Near to PCMCIA slot. DATA3
36 S1_CD1#
S1_OE# CAD12/A11 RSVD CD1# S1_D4
K17 CAD11/OE# RSVD F3 DATA4 3
S1_CE2# K18 F5 37 S1_D11
S1_A10 CAD10/CE2# RSVD +S1_VCC DATA11 S1_D5
L15 CAD9/A10 RSVD G6 +3VS DATA5 4
S1_D15 L18 H17 S1_A18 38 S1_D12
S1_D7 CAD8/D15 RSVD S1_D14 DATA12 S1_D6
L19 CAD7/D7 RSVD M19 DATA6 5
C S1_D13 S1_D13 C
M17 CAD6/D13 1 1 DATA13 39
S1_D6 M18 C491 C492 6 S1_D7
S1_D12 CAD5/D6 7412@ 7412@ DATA7 S1_D14
N19 CAD4/D12 NC A2 DATA14 40
S1_D5 M15 A17 10U_0805_10V4Z 0.1U_0402_16V4Z 7 S1_CE1#
S1_D11 CAD3/D5 NC 2 2 CE1# S1_D15
N17 CAD2/D11 NC A18 DATA15 41
S1_D4 N18 B1 8 S1_A10
S1_D3 CAD1/D4 NC ADD10 S1_CE2#
P19 CAD0/D3 NC B2 CE2# 42
B3 9 S1_OE#
NC OE# S1_VS1
B17 43
S1_REG#
S1_A12
E13
E18
CC/BE3#/REG# PCI 7412 NC
NC B18
B19
VS1#
ADD11 10
44
S1_A11
S1_IORD#
S1_A8 CC/BE2#/A12 NC +S1_VPP IORD# S1_A9
H18 CC/BE1#/A8 NC C1 ADD9 11
S1_CE1# L17 C2 45 S1_IOWR#
CC/BE0#/CE1# NC IOWR# S1_A8
NC C3 ADD8 12
S1_A13 H14 C16 1 1 46 S1_A17
S1_A23 CPAR/A13 NC C494 C493 ADD17 S1_A13
E19 CFRAME#/A23 NC C17 ADD13 13
S1_A22 G15 C18 7412@ 7412@ 47 S1_A18
S1_A15 CTRDY#/A22 NC 10U_0805_10V4Z 0.1U_0402_16V4Z ADD18 S1_A14
F17 CIRDY#/A15 NC C19 ADD14 14
S1_A20 2 2 S1_A19
G18 CSTOP#/A20 NC D2 ADD19 48
S1_A21 F19 D3 15 S1_WE#
S1_A19 CDEVSEL#/A21 NC WE# S1_A20
H15 CBLOCK#/A19 NC D17 ADD20 49
S1_A14 G19 D18 16 S1_RDY#
S1_WAIT# CPERR#/A14 NC READY S1_A21
C12 CSERR#/WAIT# NC E5 ADD21 50
S1_INPACK# C14 N14 17 S1_VCC
CREQ#/INPACK# NC VCC +S1_VCC
S1_WE# G17 P18 51
S1_BVD1 CGNT#/WE# NC VCC
A12 CSTSCHG/BVD1(STSCHG#/RI#) NC T3 VPP 18
R343 S1_WP A11 T17 52 S1_VPP
S1_A16_C 1 S1_A16 CCLKRUN#/WP(IOIS16#) NC VPP S1_A16_C +S1_VPP
2 F18 CCLK/A16 NC U1 ADD16 19
7412@ 33_0402_5% S1_RDY# E12 U2 53 S1_A22
CINT#/READY(IREQ#) NC ADD22 S1_A15
NC U3 ADD15 20
S1_RST C15 U4 54 S1_A23
CRST#/RESET NC ADD23 S1_A12
NC U12 ADD12 21
B S1_BVD2 S1_A24 B
B12 CAUDIO/BVD2(SPKR#) NC U16 ADD24 55
U17 22 S1_A7
S1_CD1# NC ADD7 S1_A25
N15 CCD1#/CD1# NC U18 ADD25 56
S1_CD2# B11 V1 23 S1_A6
S1_VS1 CCD2#/CD2# NC ADD6 S1_VS2
A13 CVS1/VS1# NC V2 VS2# 57
S1_VS2 B16 V3 24 S1_A5
CVS2/VS2# NC ADD5 S1_RST
NC V4 RESET 58
V12 25 S1_A4
C443 NC ADD4 S1_WAIT#
E10 A_USB_EN# NC V17 WAIT# 59
2 1 S1_CD1# V18 26 S1_A3
NC ADD3 S1_INPACK#
NC V19 INPACK# 60
7412@ 100P_0402_50V8J W2 27 S1_A2
NC ADD2 S1_REG#
NC W3 REG# 61
C488 W12 28 S1_A1
S1_CD2# NC ADD1 S1_BVD2
2 1 W18 62
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC BVD2 S1_A0
ADD0 29
7412@ 100P_0402_50V8J 63 S1_BVD1
7412@ PCI7412ZHK_PBGA257 BVD1 S1_D0
30
F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

DATA0 S1_D8
DATA8 64
31 S1_D1
DATA1 S1_D9
69 GND DATA9 65
70 32 S1_D2
GND DATA2 S1_D10
71 GND DATA10 66
72 33 S1_WP
GND WP S1_CD2#
CD2# 67
GND 34
GND 68

SANTA_130609-1_LT

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 33 of 60
5 4 3 2 1
 A B C D E

Express Card Power Switch

EXP@ C471 U16 +3VS_PEC

+3VS
0.1U_0402_16V4Z
2 1 5 3.3Vin1 3.3Vout1 7
6 3.3Vin2 3.3Vout2 8
1 EXP@ C454 +3V_PEC 1
+3VALW
0.1U_0402_16V4Z
2 1 21 3.3Vaux_in Aux_out 20
+1.5VS +1.5VS_PEC
EXP@ C466
2 1 18 1.5Vin1 1.5Vout1 16
19 1.5Vin2 1.5Vout2 17
+3VS 0.1U_0402_16V4Z
+3VALW 2 R180 1EXP@ 100K_0402_5%
<29,44> CPUSB# 14 CPUSB#
15 CPPE# OC# 23

2
G
SUSP# 4 STBY# R307 @ 0_0402_5%
<44,45,47,51,52,54> SUSP#
SYSON 3 SHDN# 22 2 1 EXPCRD_RST#
<44,47,51> SYSON RCLKEN EXPCRD_RST# <44>
3 1 PLTRST# 2 SYSRST# 9 PERST#
<7,27,31,32,37> PLT_RST# PERST#

GND

NC1
NC2
NC3
NC4
NC5
EXP@ 2N7002_SOT23
Q51
EXP@

11

1
10
12
13
24
TPS2231PWPR_PWP24

close to JP36 JP14

17_EXP@ 0_0402_5% 1
<29> USB20_N7
USB20_N7 R413 1 2 USB7- 2
GND Near to Express Card slot. 17
USB20_P7 R412 USB7+ USB_D-
<29> USB20_P7 1 2 3 USB_D+
CPUSB# 4
2 17_EXP@ 0_0402_5% CPUSB# +3VS_PEC +3V_PEC 2
5 RSV
6 4.7U_0805_10V4Z
ICH_SMBCLK RSV
<15,29,37> ICH_SMBCLK 7 SMB_CLK
ICH_SMBDATA 8
<15,29,37> ICH_SMBDATA SMB_DATA
+1.5VS_PEC 9 +1.5V 1 1 1 1
+1.5VS_PEC 10 +1.5V
<29,37> ICH_PCIE_WAKE# R391 1 2 PCIE_PME#_R 11 17_EXP@ C530 C532 17_EXP@ 17_EXP@ C542 C543 17_EXP@
WAKE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+3V_PEC 12 +3.3VAUX
17_EXP@ PERST# 2 2 2 2
13 PERST#
0_0402_5% 14
+3VS_PEC +3.3V
15 +3.3V
CLKREQC# 16
<15> CLKREQC# CLKREQ#
CPUSB# 17
CLK_PCIE_NC1# CPPE# +1.5VS_PEC
<15> CLK_PCIE_NC1# 18 REFCLK-
CLK_PCIE_NC1 19 4.7U_0805_10V4Z
<15> CLK_PCIE_NC1 REFCLK+
20 GND
PCIE_RXN1 21 1 1
<29> PCIE_RXN1 PERn0
PCIE_RXP1 22
<29> PCIE_RXP1 PERp0
23 17_EXP@ C558 C555 17_EXP@
PCIE_TXN1 GND 0.1U_0402_16V4Z
<29> PCIE_TXN1 24 PETn0
PCIE_TXP1 2 2
<29> PCIE_TXP1 25 PETp0
26 GND
27 GND
28 GND
FOX_1CH4110C

3 3
JP13

1
USB20_N7 2
GND
USB_D-
Near to Express Card slot. 15.4
USB20_P7 3
CPUSB# USB_D+
4 CPUSB#
5 +3VS_PEC +3V_PEC
RSV 4.7U_0805_10V4Z
6 RSV
ICH_SMBCLK 7
ICH_SMBDATA SMB_CLK
8 SMB_DATA
+1.5VS_PEC 9 +1.5V 1 1 1 1
+1.5VS_PEC 10 +1.5V
PCIE_PME#_R 11 15_EXP@ C528 C529 15_EXP@ 15_EXP@ C537 C545 15_EXP@
WAKE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+3V_PEC 12 +3.3VAUX
PERST# 2 2 2 2
13 PERST#
+3VS_PEC 14 +3.3V
15 +3.3V
CLKREQD# 16
<15> CLKREQD# CLKREQ#
CPUSB# 17
CLK_PCIE_NC2# CPPE# +1.5VS_PEC
<15> CLK_PCIE_NC2# 18 REFCLK-
CLK_PCIE_NC2 19 4.7U_0805_10V4Z
<15> CLK_PCIE_NC2 REFCLK+
20 GND
PCIE_RXN2 21 1 1
<29> PCIE_RXN2 PERn0
PCIE_RXP2 22
<29> PCIE_RXP2 PERp0
23 15_EXP@ C554 C553 15_EXP@
PCIE_TXN2 GND 0.1U_0402_16V4Z
<29> PCIE_TXN2 24 PETn0
PCIE_TXP2 2 2
<29> PCIE_TXP2 25 PETp0
26 GND
27 GND
28 GND
4 4
FOX_1CH4110C

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Express Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 34 of 60
A B C D E
 5 4 3 2 1

R36
300_0603_5% JP19
D ACTLED# D
1 2 12 Amber LED-
R583 11
+3VALW Amber LED+
75_0402_5% 16
SHLD4
1 2 8 PR4-
SHLD3 15
7 PR4+
close to U41chip(Intel rule) MDO1- 6 PR2-
TDP R584 5
75_0402_5% PR3-

2
RJ45_GND 1 2 4
R561 PR3+
110_0402_1% MDO1+ 3
+3VALW +3VLAN PR2+
MDO0- 2

1
TDN PR1-
SHLD2 14
2 1 15 mil R43 MDO0+ 1
L31 300_0603_5% PR1+
SHLD1 13
BLM11A121SPT_0603 LINK_LED100# 1 2 10 Green LED-

+3VALW 9 Green LED+

+3VLAN CONN@ SUYIN_100073FR012S100ZL
close to U41chip(Intel rule)

2
+3VLAN RDP
R582

2
@ 0_0402_5%
U41 R606 U12
@ 110_0402_1%

1
C TDN MDO0- R171 C414 C
8 TD- TX- 9 MDO0- <46>
1 10 TDP TDP 7 10 MDO0+ 75_0402_5%
MDO0+ <46>

1
VCC TDP TDN RDN TD+ TX+ MCT0 RJ45_GND 2
25 VCC TDN 11 6 CT CT 11 2 1 1
10U_0805_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 1 36 15 RDP
VCCP RDP RDN
40 VCCP RDN 16
C767

C774

C772

C773

C775

C770

2 3 14 MCT1 2 1 1000P_1206_2KV7K
+3VLAN VCCA RDN CT CT MDO1- R170
7 VCCA2 SPDLED# 31 2 RD- RX- 15 MDO1- <46>
2 2 2 2 2 2

C756

C757
9 32 ACTLED# RDP 1 16 MDO1+ 75_0402_5%
VCCT ACTLED# RD+ RX+ MDO1+ <46>
12 27 LINK_LED100#
VCCT LILED#
1

14 VCCT
17 @ @ NS0013_16P
VCCT

0.01U_0402_16V7K

0.01U_0402_16V7K
R555 37 LAN_RXD2
JRXD2 LAN_RXD2 <28>
0_0603_5% 35 LAN_RXD1 1 1
JRXD1 LAN_RXD1 <28>
19 34 LAN_RXD0
LAN_RXD0 <28>
2

+3V_LAN VCCR JRXD0 LAN_RSTSYNC

23 42
VCCR JRSTSYNC LAN_RSTSYNC <28> close to U12
LAN_TXD2 2 2
8 VSS JTXD2 45 LAN_TXD2 <28>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V4Z

1 1 1 13 44 LAN_TXD1 LAN_TXD1 <28> RDP

VSS JTXD1 LAN_TXD0
18 VSS JTXD0 43 LAN_TXD0 <28>

2
C768

C769

C766

24 39 LAN_JCLK LAN_JCLK <28>

VSS JCLK R560
48 VSS
2 2 2
33 VSSP TOUT 26 110_0402_1%
38 VSSP
3 5 R562 1 2 619_0402_1%

1
VSSA RBIAS100 RDN
6 VSSA2
20 4 R563 1 2 619_0402_1%
VSSR RBIAS10
22 VSSR

C777
28 46 LAN1_XO 1 2
B ISOL_TI X1 B
30 ISOL_TCK

2
29 22P_0402_50V8J
ISOL_EXEC
1 2 21 TESTEN
R558 200_0402_5% Y6
25MHZ_20P_1BG25000CK1A
41 ADV10 X2 47
C776
1
LAN1_XI 1 2
82562GT_SSOP48
22P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
82562EZ LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

Port 80 Debug Card Connector

JP27
D D
<27,32> PCI_CBE#0 20
<27,32> PCI_AD6 19
<27,32> PCI_AD4 18
<27,32> PCI_AD2 17
<27,32> PCI_AD0 16
<27,32> PCI_AD1 15
<27,32> PCI_AD3 14
<27,32> PCI_AD5 13
<27,32> PCI_AD7 12
<27,32> PCI_AD8 11
<27,32> PCI_CBE#1 10
<27,32> PCI_CBE#2 9
<27,32> PCI_CBE#3 8
7
<15> CLK_PCI_MINI 6
+5VS 5
<27,32,33,42,44> PCI_RST# 4
<27,32> PCI_FRAME# 3
<27,32> PCI_TRDY# 2
<27,32> PCI_AD9 1
@ HEADER 20

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Debug port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 36 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(Slot 1-WLAN)

2 1 C608
0.1U_0402_16V4Z
1 JP18 1

<29,34> ICH_PCIE_WAKE# 1 1 2 2 +3VS

<41> WL_PRIORITY 3 3 4 4
<41> BT_PRIORITY 1 R600 2 100_0402_5% 5 5 6 6 +1.5VS

0.1U_0402_16V4Z
<15> CLKREQA# 7 7 8 8

0.1U_0402_16V4Z
9 9 10 10 1

C78
CLK_PCIE_MCARD# 11 12 1
<15> CLK_PCIE_MCARD# 11 12

C167
CLK_PCIE_MCARD 13 14
<15> CLK_PCIE_MCARD 13 14
15 16 C797 1 2
15 16 2
@ 0.1U_0402_16V4Z 2
17 17 18 18
19 19 20 20 WL_ON <29>
21 22 PLT_RST#
21 22 PLT_RST# <7,27,31,32,34>
<29> PCIE_RXN3 23 23 24 24 +3VALW
25 26 +3VS
<29> PCIE_RXP3 25 26
27 27 28 28
29 30 ICH_SMBCLK ICH_SMBCLK <15,29,34>
29 30 ICH_SMBDATA
<29> PCIE_TXN3 31 31 32 32 ICH_SMBDATA <15,29,34> 47K

3
<29> PCIE_TXP3 33 33 34 34
35 36 D2
35 36
37 37 38 38
39 40 2 LED_WLANOUT# 2 10K
39 40 R592
41 41 42 42
43 44 LED_WLAN_OUT# 1 470_0402_5%
43 44 WLED#
45 45 46 46 2 1 WL_LED# <16,42>
47 48 3 Q48
47 48
49 50

1
49 50

1
DTA114YKA_SC59 D
51 51 52 52
53 54 BAS16_SOT23 2
53 54 G
55 55 56 56

1
Q49 S

3
2 MOLEX_67910-0002 R593 2N7002_SOT23 2
100K_0402_5%

1
D

<41> WIRELESS_LED_BT 2
G

1
Q50 S

3
R594 2N7002_SOT23
100K_0402_5%

2
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 37 of 60
A B C D E
 A B C D E

+3VAMP_CODEC
+VDDA_CODEC
W=40Mil U26 (3.33V)
+5VS 4 5
250mA
VIN VOUT

1
10U_0805_10V4Z

0.1U_0402_16V4Z
R408 1 1 2 6 1 2 1 1
10K_0402_1% DELAY SENSE or ADJ R392 C533 @ C538

1
C504

C526
R385 7 1 47K_0603_1% 1U_0603_10V4Z 0.1U_0402_16V4Z
ERROR CNOISE
1

2
R411 C563 2 2 R403 2 2
8 3

2
0_0402_5% 1U_0603_10V4Z SD GND C565 27K_0603_1%
MONO_IN 1 2 MONO_IN1 1 2 MONO_INR 10K_0402_5% SI9182DH-AD_MSOP8
MONO_INR <40>

2
2
1 R409 1
5.1K_0402_5% 0.01U_0402_16V7K
1 2

R416 R422
1

1
560_0402_5% Q29 Q28 560_0402_5%
<32> PCM_SPK 1 2 2 MMBT3904_SOT23 2 1 2 SB_SPKR <29>
MMBT3904_SOT23 @ C502
For Layout: 0.1U_0402_16V4Z
3

3
1 2
Place decoupling caps near the
power pins of SmartAMC @ C519
0_0402_5%
device. 1 2

R401 +3VDD_CODEC +3VAMP_CODEC R404 @C516

0_0805_5% 0_0805_5% 0.1U_0402_16V4Z
+3VALW 1 2 1 2 +VDDA_CODEC 1 2

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z
R423
1 1 1 1 1 1 1 1 0_1206_5%
1 2

@ R300
2 2 2 2 2 2 2 2
C560

C566

C569

C568

C567

C564

C546

C559
+CODEC_REFF 0_1206_5%
1 2 GNDA <40,42,46>
U27

12

14

25
35
1
9

1
R386 R387 GND GNDA

VDDCK
DVDD1
DVDD2
DVDD3

AVDD1
AVDD2
2.2K_0402_5% 2.2K_0402_5%
2 2

2
ACZ_RST# 11 26 MIC_INR C539 1 2 10U_0805_10V4Z
<28,44> ACZ_RST# RST# MIC_R MIC_R <42>
C571 27 MIC_INL C540 1 2 10U_0805_10V4Z
MIC_L MIC_L <42>
150P_0402_50V8J R418 1 2 0_0402_5% 47 20 +CODEC_REFF
1 <39> DIB_DATAN DIBN MICBIAS_F
R417 1 2 0_0402_5% 48 21 +CODEC_REFC
<39> DIB_DATAP DIBP MICBIAS_C
R420 1 2 0_0402_5% 3 22
<39> PWRCLKP PWRCLKP MICBIAS_B
R419 1 2 0_0402_5% 4
<39> PWRCLKN PWRCLKN
28 CDROM_RC_L C536 2 1 2.2U_0603_6.3V4Z CDROM_R_L R377 1 2 @ 6.8K_0402_5%
CD_L CDROM_L <31>
2 R407 1 2 33_0402_5% 13 29 C DGNDA C535 2 1 2.2U_0603_6.3V4Z CD_GNA R376 1 2 0_0402_5%
<28> ACZ_BITCLK BCLK CD_GND CD_AGND <31>
R158 1 2 33_0402_5% 10 30 CDROM_RC_R C534 2 1 2.2U_0603_6.3V4Z CDROM_R_R R375 1 2 @ 6.8K_0402_5%
<28> ACZ_SYNC SYNC CD_R CDROM_R <31>
C570 R421 1 2 33_0402_5% 8
<28> ACZ_SDIN0 SDI

1
0_0402_5%
6.8K_0402_5%

6.8K_0402_5%
150P_0402_50V8J R151 1 2 33_0402_5% 7 40 LINE_OUTL
1 <28> ACZ_SDOUT SDO PORT-A_L LINE_OUTL <40>
39 LINE_OUTR
PORT-A_R LINE_OUTR <40>
MONO_INR 43 PCBEEP
1

38 DOCK_LOUTL
PORT-B_L

R378

R381

R379
R149 R152 37 DOCK_LOUTR

2
PORT-B_R C541 R380
10K_0402_5% 10K_0402_5% 15 XTALIN
16 34 DOCKMIC 1 2DOCK_MICR2 1 DOCK_MIC <46>
XTALOUT PORT-C_L
33
2

PORT-C_R 10U_0805_10V4Z 18K_0402_5%

PORT-D_L 32
PORT-D_R 31 2 R384 1 DOCK_MICR 1 R388 2 +CODEC_REFC
2K_0402_5% 2.2K_0402_5%
REF_FILT 23 45 EAPD
VREF VREF_FILT EAPD SPDIFO
19 VREF SPDIF_OUT 44 SPDIFO <42,46>
VC 18 VC
0.1U_0402_16V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

41 SENSEA
SENSEA SENSEB DOCK_LOUTR C521 1 DOCK_LOUT_R
1 R356

+
1 1 1 1 SENSEB 42 2 2 DOCK_LOUT_R <46>
C548

C547

C549

C562

150U_D2_6.3VM 33_0805_5%
VSSCK
DVSS1
DVSS2
DVSS3

AVSS1
AVSS2
VSUB

R414 DOCK_LOUTL C520 1 1 R355 2 DOCK_LOUT_L

+
2 DOCK_LOUT_L <46>
3 2 2 2 2 SENSEA 3
1 2 HP_DET# <40>
20K_0402_5% 150U_D2_6.3VM 33_0805_5%

1
R354 R357
2
5
46
6

17

24
36

CX20551-22_TQFP48 R415
1 2 JACK_DET# <46>
10K_0402_5%
1

2
1K_0402_5% 1K_0402_5%

2
R410
R393 1.5K_0402_5%
0_0402_5%
R405
2

1
SENSEB 1 2 MIC_DET <42>
5.1K_0402_5%
+3VS

2
HP_DET# JACK_DET# PORT-A PORT-B EQ R591
100_0402_5%
0 0 ON OFF Disable

1
0 NC ON OFF Disable MUTE_LED <42,46>

1
D
NC 0 OFF ON Disable
EAPD 2
NC NC ON OFF Enable G
S Q47

3
2N7002_SOT23

MIC_DET PORT-C PORT-F

4 4

0 ON OFF
NC OFF ON

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMOM_codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 38 of 60
A B C D E
 MTP28

1
MTP52

1
VDD MTP59
MTP26 BR908_CC
0.1U_0402_10V6K
1

1
MBR908A 1 1

6
BAV99DW-7_SOT363 MTP29 MC928
MC930 VDD MC978 C906 and C908 must be Y3 type
MTP22 2.2U_0805_10V6K 0.1U_0402_10V6K Capacitors for Nordic
2 2 1 1

1
1 2 MTP36 MTP37 Countries only
1
1 MTP35 1 MTP38
1

MR932 MC926 AGND_LSD MTP58 MFB902

1
15K_0402_5% 10P_0402_50V8J DGND_LSD RING_2 MOD_RING

24
1 MTP39 1 2 1

2
MT902 1 2CLK2 1 2 CLK MU902 MR902 MMZ1608D301BT_0603 MTP41

4
1 4BR908_AC1 1M_0805_5% MC902

DVdd
AVdd
<38> PWRCLKN
1 MFB906 21 RAC1 1 2 RAC1/RING 1 2 0.033U_1206_100V7K 1 MC906
RAC1

1
MTP23 1 2 MC904 470P_1808_3KV
MC962 1 MMZ1608D301BT_0603 26 20 TAC1 2 1 TAC1/TIP 1 2 0.033U_1206_100V7K MBR904
CLK TAC1

TB3100M-13-01_SMB
1

47P_0603_50V8J 1M_0805_5% MMBD3004S_SOT23

2 MBR908B MC970 MTP30 MTP34 MR904 TIP_2 2 MJ2
3
1 MTP40 1

1
1

MRV902
2 3 PCLK BAV99DW-7_SOT363 0.1U_0402_10V6K 19
<38> PWRCLKP PRI SEC 2 RAC2 2
MTP24 TRDC MR906 1 2 6.8M_0805_5%

1
3

2
30U_82154R_1%_1:1.67 PWR+ 1
MTP27
Check 0.047u or 10p cap 7 PWR+ TAC2 18 1

2
MTP60 MTP33 E&T_3800-02
1

2
1

MTP72 AGND_LSD MR922 MC958 MC918 AGND_LSD 1 GND

2
1 1 0_0402_5% 1 EIC 1 MTP32
TRDC 12 1 2 0.1U_0603_16V7K
MC922 1 2 10P_1808_3KV DIB_P1 1 2 DIB_P2 27 0.015U_0603_25V7K 2 MBR906 MC908
<38> DIB_DATAP DIB_P
11 MR910 MMBD3004S_SOT23 470P_1808_3KV
EIC 237K_0805_1% 2
AGND_LSD
MC924 1 2 10P_1808_3KV DIB_N1 1 2 DIB_N2 28 9 RXI 1 2 RXI-1
<38> DIB_DATAN

1
0_0402_5% DIB_N RXI 1 MTP71 MFB904
MTP25 MTP73 MTP62
MR924 1 TIP_2 1 2 MOD_TIP
MT922 GPIO1 1 MTP70 1
AGND_LSD MMZ1608D301BT_0603 MTP42
1 1 1

1
MJ1 1 4 MTP61 5 RBias 1 MR9542
RBias 59K_0402_1%
1 1 1 2 MC966
2 Vc_LSD 3 MTP69 MC910 0.01U_0805_100V7M
2 Vc VZ 1 1 MR908 2 BRIDGE_CC
3 3 VZ 10 1 2
4 Vref_LSD 4 348K_0805_1% 0.047U_1206_100V7K AGND_LSD
4 VRef

1
5 MC940 MTP68 MTP67 C
5 1U_0603_6.3V6M MTP63 EIO 1 1 MQ902
6 6 2 3 EIO 17 2
PRI SEC B PMBTA42_SOT23
7 1 1 1 1 8 Use 59K_0402_1% for MR954
1
7 NC1

2
4
8 @ 30U_82154R_1%_1:1.67 22 16 EIF E

3
8 MC974 MC944 MC976 NC2 EIF MQ904
25 NC3

1
@ HEADER8 @ 0.001U_0402_50V7M 14 C 1
2 22 2 TXO TXO MQ906
MJ1B 2
0.001U_0402_50V7M B PMBTA42_SOT23 FZT458TA_SOT223
1 1 0.1U_0402_10V6K
29 PADDLE TXF 13
E MTP66
2 2

DC_GND

1 3
TXF 1
3 3 AGND_LSD 1 MTP64

DGnd
AGnd
4 4
5 5

1
CX20493-58_QFN28 MR928
6 6

1
1 MTP65 MR938 27_0805_5%
7 7
6

15

23
110_0603_5%
8 8

2
MTP31
@ HEADER8 1 MTP49

2
GND AGND_LSD

DGND_LSD AGND_LSD AGND_LSD

AGND_LSD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMOM_modem
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 39 of 60
 A B C D E

+5VAMP R322 +5VS

0.1U_0402_16V4Z 0_1206_5%
1 2 HEADPHONE OUT/LINE OUT
1 1 1
C462 C479 C501 Gain Settings
10U_0805_10V4Z
2 2 2
GAIN0 GAIN1 SE/BTL# Av(inv)
0.1U_0402_16V4Z

1 0 0 0 6 dB 1

* 10 dB

19

18
0 1 0

7
U21

VDD

PVDD2
PVDD1
<38> LINE_OUTR
C475 1 2 0.047U_0603_16V7K LINE_C_OUTR 23 RLINEIN 1 0 0 15.6 dB
9 SPKL-
C476 1 HP_C_OUTR LOUT- SPKL+
2 0.47U_0603_16V7K 20 RHPIN LOUT+ 4 SPKL+ <42>
16 SPKR- 21.6 dB
C509 1 2 0.47U_0603_16V7K 8
ROUT-
21 SPKR+ 10 dB
1 1 0
RIN ROUT+ SPKR+ <42>
+5VS
X X 1 4.1 dB

1
C510 1 2 0.47U_0603_16V7K 10 15 HP_DET
LIN SE/BTL# R371 @ R368
C508 1 2 0.47U_0603_16V7K HP_C_OUTL 6 17 100K_0402_5% 100K_0402_5%
LHPIN HP/LINE#
C507 1 2 0.047U_0603_16V7K LINE_C_OUTL 5

2
<38> LINE_OUTL LLINEIN
U45 GAIN1 3
GAIN0 2
1 6 C477 1 2 0.47U_0603_16V7K 14
<29> PCBEEP IN NO PC-BEEP JP11
+5VS 2 V+ COM 5 BYPASS 11
3 4 22 SPKL+ 1
GND NC <44> EC_MUTE# SHUTDOWN# 1

1
2 SPKL- 2 2

GND1
GND2
GND3
GND4
PI5A4599ACEX @ R373 R364 SPKR+ 3
C511 100K_0402_5% 100K_0402_5% SPKR- 3
<38> MONO_INR 4 4
0.1U_0402_16V4Z
1 ACES_85205-0400

1
12
13
24

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J
TPA0312PWPRG4_TSSOP24
1 1 1 1

C496

C497

C498

C499
2 2 2 2 2 2
@ @ @ @

+5VS +5V
1

R353
1

10K_0402_5%
R345
10K_0402_5%
2

HP_DET
2
1

D
Q13 2 HPDET#
G HPDET# <42>
2N7002_SOT23 S
3

+5V
C785
1 2

0.1U_0402_16V4Z
1

5P
OE#

3 3
<38> HP_DET# 4 Y A 2
G

U44
74AHCT1G125GW_SOT353-5
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 40 of 60
A B C D E
 +5V
U38 +USB_VCCB
C754
2 1 3 VIN VOUT 1
4 VIN/CE VOUT 5

1
0.1U_0402_16V4Z
2 R542
GND
RT9701PBL_SOT25 10K_0402_5%

2
USB_OC#0
USB_OC#0 <29>
1 R543 2 USB_OC#3
USB_OC#3 <29>

1
0_0402_5%
R544
20K_0402_5%

2
USB CONNECTOR (Left side)

JP26
1 1 5 5
USB20_P0 R535 1 2 0_0603_5% USBP0+ 2 6 USBP3+ R523 1 2 0_0603_5% USB20_P3
<29> USB20_P0 2 6 USB20_P3 <29>
USB20_N0 R537 1 2 0_0603_5% USBP0- 3 7 USBP3- R532 1 2 0_0603_5% USB20_N3
<29> USB20_N0 3 7 USB20_N3 <29>
+USB_VCCB 4 4 8 8 +USB_VCCB

1000P_0402_50V7K
1 1 W=40mils W=40mils

1000P_0402_50V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

100U_D2_10VM
1 1 9 GND 1

150U_D_6.3VM

100U_6.3V_M
+ + 10 GND 1 1
C789

C736

C401

C400

C397

C394

C408
11 +
GND
12 GND
2 2 2 2
SUYIN_020122MR008S573ZR 2 2 2

@
@

USBP0+ 1
U9
4 USBP3-
BT CONNECTOR
D1+ D2+ <29> BT_ON#

1
2 GND VCC 5 +USB_VCCB
R541
USBP3+ 3 6 USBP0- 100K_0402_5%
D2- D1-

2
G
@ IP4220CZ6_SO6 C108

2
1U_0603_10V4Z
+3VALW 3 1 +3V_BT 1 2

D
1
C118
1U_0603_10V4Z AO3419_SOT23
Q2
2
JP6
1 1
2 2
USB20_P6 3
<29> USB20_P6 3
USB20_N6 4
<29> USB20_N6 4
WIRELESS_LED_BT 5
<37> WIRELESS_LED_BT 5
<37> WL_PRIORITY 1 R601 2 100_0402_5% 6 6
<37> BT_PRIORITY 7 7
BT_DET# 8
<29> BT_DET# 8
ACES_87213-0800
1 1
C808 C611
@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bluetooth & USB CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 41 of 60
 5 4 3 2 1

D38 D39
Power BTN
KSO2 1 5 KSO7 KSI1 1 5 KSO9 D11 R396 100K_0402_5%
DAN202U_SC70 1 2 LDO3
INT_KBD CONN.( TYPE "D" KB) 3 ON/OFF# ON/OFF# <44>
2 2
ON/OFFBTN# 1
1
2 EC_PWR_ON# <48>
KSI[0..7] KSO4 3 4 KSO8 KSI7 3 4 KSI6 C809
KSI[0..7] <44>
15.4 ( TYPE "C" KB) ESD 0.1U_0402_16V4Z

1
2
D KSO[0..16] JP8 LDO3 D

O
KSO[0..16] <44>
KSI1 Q26
24

1
NZQA5V6AXV5T1_SOT533-5 NZQA5V6AXV5T1_SOT533-5 KSI7 DTC124EK_SC59 1
23

1
D40 D41 KSI6 C544 D12
KSO9 22 R383
21

G
JP4 KSI4 4.7K_0402_5% RLZ20A_LL34

I
KSI7 KSO6 1 20 2
26 5 KSO12 KSI4 1 5 KSO0 KSI5

2
KSI0 26 KSO0 19 R603
25

2
KSI5 25 KSI2 18 EC_ON
24 24 17 <44,50> EC_ON 2 1
KSI1 23 KSI3 0_0402_5%
23 16

1
KSI4 22 2 2 KSO5 1000P_0402_50V7K
KSI6 22 KSO1 15 R604
21 21 14
KSI3 20 KSI0 @ 0_0402_5%
KSI2 20 KSO2 13
19 19 12 WHEN R=0,Vbe=1.35V
KSO1 18 KSO3 3 4 KSO13 KSI5 3 4 KSI2 KSO4 WHEN R=33K,Vbe=0.8V

2
KSO2 18 KSO7 11
17 17 10

1
KSO4 KSO8 D
16 16 9
KSO0 15 KSO6 2
KSO16 15 KSO3 8 Q25 G
14 14 7
KSO5 13 NZQA5V6AXV5T1_SOT533-5 NZQA5V6AXV5T1_SOT533-5 KSO12 @ 2N7002_SOT23 S

3
KSO6 13 D42 D43 KSO13 6
12 12 5
KSO3 11 KSO14
KSO7 11 KSO11 4
10 10 3
KSO8 9 KSO141 5 KSO15 KSI3 1 5 KSO1 KSO10
KSO9 9 KSO15 2
8 8 1
KSO10 7
KSO11 7
6 6
KSO12 5 2 2 ACES_85201-2405
KSO13 5 LDO5
4 4
KSO14 3
KSO15 3
2 2 Consumer IR

1
KSO_D_17 1 KSO113 4 KSO10 KSO5 3 4 KSI0
C <44> KSO_D_17 1 C
CIR@ R569
ACES_85201-2605 100_0402_5%
CONN@ TP to MB CONN(15.4)

2
NZQA5V6AXV5T1_SOT533-5 NZQA5V6AXV5T1_SOT533-5
D44
+5V 1 1 1
1 CIR@ C784
2

0.1U_0402_10V6K
KSO161 5 TP_DATA 10U_0805_10V4Z CIR@ C783
<44> TP_DATA 3 0.1U_0402_10V6K
TP_CLK
<44> TP_CLK 4 2 2 U43 CIR@
@ 2 5
6 3 Vs GND 1
2 CIR_ IN 4 2
7 <44,46> CIR_IN OUT GND

C442
JP7 8 TSOP36236TR_4P
ACES_87152-0807
KSO_D_173 4
R612
LDO3 10K_0402_5%
1 2

NZQA5V6AXV5T1_SOT533-5

D45
Switch board conn
JP5
<29> USB_OC#5
USB_OC#5 Audio board conn
B ON/OFFBTN# KSI0 1 KSI3 B
1 1 6

1
KSI0 2 +5V
<44> KSI0 2
KSI1 3 R274 JP9
<44> KSI1 3
KSI3 4 0_0402_5% +5V 1
<44> KSI3 4 1
KSI4 5 2 5 KSI4 2
<44> KSI4 5 2

2
KSO_D_17 Q10 USB20_P4

G
6 <29> USB20_P4 3

2
WL_LED# 6 USB20_N4 3
<16,37> WL_LED# 7 7 <29> USB20_N4 4 4
VOL_UP# 8 USB_OC#4 1 3 OVCUR#4 5
<44> VOL_UP# 8 <29> USB_OC#4 5
VOL_DWN# 9 KSI1 3 4KSO_D_17 6

S
<44> VOL_DWN# 9 6
LID_SW# 10 USB20_P5 7
<44> LID_SW# 10 <29> USB20_P5 7
NUMLED# 11 2N7002_SOT23 USB20_N5 8
<44> NUMLED# 11 <29> USB20_N5 8
MUTE_LED 12 L32 9
<38,46> MUTE_LED 12 9
13 NUP5120X6T1_SOT563-6 1 2 SPDIFO_R 10
13 <38,46> SPDIFO 10
14 FBMA-L10-201209-301LMT 11
PWR_ACTIVE# 14 NUMLED# C795 11
<44> PWR_ACTIVE# 15 15 1 2 100P_0402_50V8J 1
<38> MIC_L
MIC_L 12 12
+5VALW 16 16 13 13
PA_LED_ALW 17 +5VALW C796 1 2 100P_0402_50V8J C822 +5VS 14
<43,44> PA_LED_ALW 17 14
PR_LED_ALW 18 220P_0402_25V8K MIC_R 15
<43> PR_LED_ALW 18 <38>
2 MIC_R 15
+5V 19 WL_LED# C810 1 2 0.1U_0402_16V4Z 16
PA_LED 19 MIC_DET 16
<43> PA_LED 20 20 <38> MIC_DET 17 17
PR_LED 21 HPDET# 18
<43> PR_LED 21 <40> HPDET# 18
+5VS 22 LID_SW# C813 1 2 0.1U_0402_16V4Z SPKR+ 19
22 <40> SPKR+ 19
JP15 PA_LED_VS 23 MUTE_LED C814 1 2 0.1U_0402_16V4Z SPKL+ 20
<43> PA_LED_VS 23 <40> SPKL+ 20
1 PR_LED_VS 24 PWR_ACTIVE# C815 1 2 0.1U_0402_16V4Z
1
2 2
+5VS FOR LPC SIO DEBUG PORT <43> PR_LED_VS
+3VALW 25
24
25
PA_LED_ALW C816 1 2 0.1U_0402_16V4Z
3 +3VS PR_LED_ALW C817 1 2 0.1U_0402_16V4Z ACES_87213-2000
3 ACES_85201-2505 PA_LED C818 0.1U_0402_16V4Z
4 4 D47 1 2
5 PR_LED C819 1 2 0.1U_0402_16V4Z
5 VOL_UP# PA_LED_VS C820 0.1U_0402_16V4Z
6 6 LPC_AD[0..3] <28,44> 2 1 2
7 LPC_AD0 1 PR_LED_VS C821 1 2 0.1U_0402_16V4Z
7 LPC_AD1 VOL_DWN#
8 8 3
9 LPC_AD2
A 9 LPC_AD3 A
10
10
11 11 LPC_FRAME# LPC_FRAME# <28,44>
ESD SM05_SOT23
12 LPC_DRQ#0 LPC_DRQ#0 <28> @ R424
12 PCI_RST# 10K_0402_5%
13 13 PCI_RST# <27,32,33,36,44>
14 14 2 1
15 15 CLK_PCI_SIO <15>
16 SIRQ
16 SIRQ <29,32,44>
17
17
18 18
Security Classification Compal Secret Data Compal Electronics, Inc.
19 19 Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
20
20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD,ON/OFF,T/P,LED/B,DEBUG
ACES_85201-2005 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 42 of 60
5 4 3 2 1
 5 4 3 2 1

For PA For PR
FOR POWER BUTTON BACKLIGHT SYSTEM POWER FOR POWER BUTTON BACKLIGHT SYSTEM POWER
"Vertical" "Right Angle"
R573
D D23 D
PALED@ 220_0402_5% R425 D13
<44> PMLED_1# PMLED_1# 1 2 1 2 PRLED@ 560_0402_5% 2
PA_LED <42> PR_LED <42>
+5VS PMLED_1# 1 2 1
3
HT-170NBQA_0805
15.4@ 12-21UYOC/S530-A2/TR8_YEL

2
R570 +3VS
20K_0402_5% +5VS
R572 R426 D14
D25
PALED@ 220_0402_5% PRLED@ 560_0402_5% 2 PR_LED_ALW <42>

1
<44> BATLED_0# BATLED_0# 2 1 1 2 BATLED_0# 2 1 1
PA_LED_ALW <42,44>

2
3
R568
HT-170NBQA_0805 10K_0402_5% 15.4@ 12-21UYOC/S530-A2/TR8_YEL

5
U48 R427 D15
R571 IDE_LED# 1 PRLED@ 560_0402_5% 2

P
D24 <28> IDE_LED# A PR_LED_VS <42>
PALED@ 220_0402_5% 4 IDE_ACT_LED# 1 2 1
IDE_ACT_LED# ACT_LED# O
1 2 1 2 PA_LED_VS <42> <31> ACT_LED# 2 B 3

G
SN74AHCT1G08DCKR_SC70 15.4@ 12-21UYOC/S530-A2/TR8_YEL

3
HT-170NBQA_0805
C830 1

0.1U_0402_16V4Z

R86 D6 2 R92 D7
D@ 470_0402_5% PRLED@ 560_0402_5%
CAPSLED# 1 2 1 2 PA_LED_VS CAPSLED# 1 2 1 2 PR_LED_VS
C <44> CAPSLED# C
15.4@ 17-21UYOC/S530-A2/TR8_ORG
D@ HT-170NBQA_0805

R76 D4
PALED@ 470_0402_5%
CAPSLED# 1 2 1 2 PA_LED_VS

15.4@ HT-170NBQA_0805

PR_LED_VS

PA_LED_VS
2

D21
D20 HT-110NBQA_0805
B 17-21UYOC/S530-A2/TR8_ORG B
15.4@
1

1
2

15.4@ R547 R548

560_0402_5% 330_0402_5%
1

R550
1

1K_0402_5% Q39
CARD_LED 2 1 2
<32> CARD_LED
MMBT3904_SOT23
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

0.1U_0402_16V4Z 0.01U_0402_16V7K 1 R579 2 PA_PR#DET

<42,43> PA_LED_ALW
1K_0402_5%
LDO3
1 1 1 1 1
BID definition,

1
C472 C527 C512 C551 C550 R580 High (3.3V): Before SI2 type D KB(17")
4.7U_0805_6.3V6K 2K_0402_5%
2 2 2 2 2 Low (0V): Before SI2 type C KB(15")

2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2.2V(R325=1K,R333=2K): After PV type D KB(17")
1
LDO3 +EC_AVCC 1.65V(R605=2K,R333=2K): After PV type C KB(15")
C51
4U47

5
D @ 2200P_0603_50V7K~D +3VALW D

CD
N.C.

105
127
141
11
26
37

75
RESET

1
@ G696L263T1UF_SOT23-5 U24
GND

VCC

GATEA20 1 71 BATT_TEMP C@ R605 D@ R325

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

EC_AVCC / AVCC
<28> GATEA20 GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_TEMP <56>
KB_RST# 2 72 BATT_OVP 2K_0402_5% 1K_0402_5%
<28> KB_RST# KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 BATT_OVP <49>
SIRQ 3 73 ADP_IR 1 2
<29,32,42> SIRQ ADP_I <49>
3

LPC_FRAME# SERIRQ ADP_I/AD2/GPIO3A BID R332 BID

<28,42> LPC_FRAME# 5 74

2
LPC_AD3 LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B 10K_0402_5%
<28,42> LPC_AD3 6 LPC AD3/LAD3 1
LPC_AD2 9 AD INtput or GPI
<28,42> LPC_AD2 LPC AD2/LAD2

1
LPC_AD1 10 Host C463
<28,42> LPC_AD1 LPC AD1/LAD1 INTERFACE
LPC_AD0 12 0.22U_0603_10V7K R333
<28,42> LPC_AD0 LPC AD0/LAD0 2
CLK_PCI_EC 14 76 DAC_BRIG 2K_0402_5%
<15> CLK_PCI_EC CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D DAC_BRIG <16>
R382 PCI_RST# 15 PWR 78 EN_FAN1
<27,32,33,36,42> PCI_RST# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 <4>
1 2 EC_RST# 42 79 IR EF
LDO3 IREF <49>

2
47K_0402_5% EC_SCI# EC RST#/ ECRST# IREF2/DA2
1 <29> EC_SCI# 24 EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F 80 EC_RTCRESET <28>
1

J1 C525 PA_PR#DET 44
0.1U_0402_16V4Z PM_CLKRUN#/ CLKRUN# DA output or GPO
R611 JOPEN FAN/PWM
2

2 KSI[0..7] INVT_PWM
<42> KSI[0..7] INVT_PWM/GPIO0F/PWM1 25 INVT_PWM <16>
1

KSI0 63 27 CONA# CONA# <46>

@ 100K_0402_5% KSI1 KSI0/GPIO30 BEEP#/GPIO10/PWM2 PGD_IN
64 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 30 PGD_IN <53>
KSI2 65 31 ACOFF
KSI2/GPI032 ACOFF/GPIO18/PWM4 ACOFF <49>
KSI3 66 32 FAN_SPEED1
KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 FAN_SPEED1 <4>
KSI4 67 33 VOL_DWN#
VOL_DWN# <42>
2

KSI5 KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2

68 KSI5/GPI035
KSI6 69
KSI7 KSI6/GPIO36
70 KSI7/GPIO37 PSCLK1 91 ACZ_RST# <28,38>
KSO[0..16] key Matrix 92 EXPCRD_RST#
<42> KSO[0..16] scan PSDAT1 EXPCRD_RST# <34>
KSO0 47 93 PWR_ACTIVE#
C KSO0/GPIO20 PSCLK2 PWR_ACTIVE# <42> C
KSO1 48 PS2 interface 94 DOCK_VOL_UP# DOCK_VOL_UP# <46>
KSO2 KSO1/GPIO21 PSDAT2 TP_CLK
49 KSO2/GPIO22 PSCLK3 95 TP_CLK <42>
KSO3 50 96 TP_DATA
KSO3/GPIO23 PSDAT3 TP_DATA <42>
KSO4 51
CLK_PCI_EC R586 2 GM_PM#DET KSO5 KSO4/GPIO24 ADB0 ADB[0..7]
+3VALW 1 52 KSO5/GPIO25 ADB0/D0 125 ADB[0..7] <45>
UMA@ 10K_0402_5% KSO6 53 126 ADB1
KSO6/GPIO26 ADB1/D1
1

KSO7 54 128 ADB2

KSO7/GPIO27 ADB2/D2
1

KSO8 55 Data 130 ADB3

@ R399 R587 KSO9 KSO8/GPIO28 BUS ADB3/ D3 ADB4
56 KSO9/GPIO29 ADB4/D4 131
10_0402_5% G71@ 100K_0402_5% KSO10 57 132 ADB5
KSO11 KSO10/GPIO2A ADB5/D5 ADB6
58 133
2

KSO12 KSO11/GPIO2B ADB6/D6 ADB7

1 59 134
2

KSO13 KSO12/GPIO2C ADB7/D7 KBA0 KBA[0..19]

60 KSO13/GPIO2D KBA0/A0 111 KBA[0..19] <45>
@ C556 KSO14 61 112 KBA1
15P_0402_50V8J KSO15 KSO14/GPIO2E KBA1/A1 KBA2
62 KSO15/GPIO2F KBA2/A2 113
2 KSO16 KBA3
89 EC URXD/KSO16/GPIO48 KBA3/A3 114
KSO_D_17 90 115 KBA4
<42> KSO_D_17 EC UTXD/KSO17/GPIO49 KBA4/A4
116 KBA5
+3VALW KBA5/A5 KBA6
KBA6/A6 117
EC_SMD_2 88 Address 118 KBA7
<4> EC_SMD_2 EC SMD2/ GPIO47/SDA2 KBA7/A7
EC_SMC_2 87 BUS 119 KBA8
<4> EC_SMC_2 EC SMC2/GPIO46/SCL2 SM BUS KBA8/A8
2 R337 1 EC_SMD_2 <45,56> EC_SMD_1
EC_SMD_1 86 EC SMD1/GPIO44/SDA1 KBA9/A9 120 KBA9
10K_0402_5% EC_SMC_1 85 121 KBA10
<45,56> EC_SMC_1 EC SMC1/GPIO44/SCL1 KBA10/A10
2 R338 1 EC_SMC_2 KBA11/A11 122 KBA11
10K_0402_5% 123 KBA12
KBA12/A12
2 R400 1 EC_SMI# UTXD 34 PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13 124 KBA13
@ 10K_0402_5% SLP_S4# 35 110 KBA14
<29> SLP_S4# SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14
2 R397 1 EC_SCI# <43> PMLED_1#
PMLED_1# 38 PWRLED#/ GPIO19 KBA15/A15 109 KBA15
@ 10K_0402_5% NUMLED# 40 108 KBA16
<42> NUMLED# NUMLED#/ GPIO1A KBA16/A16
BATLED_0# 99 107 KBA17
<43> BATLED_0# BATT CHGI LED#/ E51CS# KBA17/A17
+5VALW GM_PM#DET 101 106 KBA18
CAPSLED# BATT LOW LED#/ E51MR0 KBA18/A18 KBA19
<43> CAPSLED# 100 CAPS LED#/ E51TMR1 KBA19/A19 98
B CPUSB# B
<29,34> CPUSB# 102 ARROW LED#/ E51 INT0
2 R339 1 EC_SMD_1 <34,47,51> SYSON
SYSON 104 SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 84 NV_ENBKL
NV_ENBKL <18>
10K_0402_5% 97 DOCK_VOL_DWN# DOCK_VOL_DWN# <46>
SELIO#/ GPIO50
2 R340 1 EC_SMC_1 <29> EC_RSMRST#
EC_RSMRST# 4 EC_RSMRST#/ GPIO02 FRD#/RD# 135 FR D#
FRD# <45>
10K_0402_5% BKOFF# 7 136 FWR#
<16> BKOFF# BKOFF#/GPIO03 FWR#/WR# FWR# <45>
SLP_S3# 8 144 FSEL#
LDO3 <29> SLP_S3# PM SLP S3#/GPIO04 FSEL#/SELMEM# FSEL# <45>
LID_OUT# 16
<29> LID_OUT# EC LID OUT#/GPIO06
SLP_S5# 17 41 EC_ON
<29> SLP_S5# PM SLP S05#/ GPIO07 EC ON/ GPIO1B EC_ON <42,50>
2 R394 1 FSEL# <29> EC_SMI# EC_SMI# 18 EC SMI#/GPIO08 AC IN/ GPIO1C 43 ACIN
ACIN <48,50>
NV_ENBKL
10K_0402_5% <29> LAN_RST# LAN_RST# 19 29 EC_THERM#
EC SWI#/GPIO09 ECTHERM#/GPIO11 EC_THERM# <29>
2 R390 1 FR D# <42> LID_SW#
LID_SW# 20 LID SW#/ GPIO0A ONOFF/GPIO18 36 ON/OFF#
ON/OFF# <42>

2
10K_0402_5% SUSP# 21 45 VOL_UP#
<34,45,47,51,52,54> SUSP# SUSP#/GPIO0B PCMRST#/GPIO1E VOL_UP# <42>
2 R585 1 LID_SW# <29> PWRBTN_OUT#
PWRBTN_OUT# 22 PBTN_OUT#/GPIO0C WL OFF#/GPIO1F 46 ICH_POK
ICH_POK <7,29>
R581
@ 10K_0402_5% PCI_PME# 23 100K_0402_5%
<27,32> PCI_PME# EC PME#/GPIO0D
81 AIR_ACIN AIR_ACIN <49>
ALI/MH#/GPIO40 FSTCHG
82 FSTCHG <49>

1
FSTCHG/GPIO41 VR_ON
VR ON/ GPIO42 83 VR_ON <53>
GPIO57/GPIO57 137 R365 2 1 0_0402_5% VGATE <29,53>
+5V C RY2 140 142 CIR_ IN
XCLKO GPIO58/GPIO58 CIR_IN <42,46>
AGND

R335 C RY1 138 143 EC_MUTE#

GND
GND
GND
GND
GND
GND

Y7 XCLKI GPIO59/GPIO59 EC_MUTE# <40>

10K_0402_5% 2 1 TP_DATA
R336 3 2
10K_0402_5% 2 1 TP_CLK KB910LQF_LQFP144
139
129
103
13
28
39

77

4 1 LDO3

R372
32.768KHZ_12.5P_MC-146
1

10K_0402_5%
1 2 VOL_UP# +EC_AVCC
+3VS 0_0603_5%
R402 C RY1 R327
10K_0402_5% C RY2
R326
2

1 2 VOL_DWN# C474
A ECAGND A
EC DEBUG port 2 1 1 2
R331 1 1 0_0603_5%
10K_0402_5% 0.1U_0402_16V4Z
1 2 DOCK_VOL_UP# C517 C522 JP20
10P_0402_50V8K 10P_0402_50V8K 1
2 2 1 LDO5
R330 2
10K_0402_5% 2 UTXD
3 3
1 2 DOCK_VOL_DWN# 4
4
ACES_85205-0400
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB910L(LPC)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 44 of 60
5 4 3 2 1
 ADB[0..7]
<44> ADB[0..7]
KBA[0..19]
<44> KBA[0..19]

JP12
KBA16 KBA17
KBA15 1 2
KBA14 3 4
KBA13 5 6 KBA19
KBA12 7 8 KBA10
KBA11 9 10 ADB7
KBA9 11 12 ADB6
KBA8 13 14 ADB5
FWR# 15 16 ADB4
RESET# 17 18
19 20 LDO3
21 22
KBA18 23 24 ADB3
KBA7 25 26 ADB2
KBA6 27 28 ADB1
KBA5 29 30 ADB0
KBA4 31 32 FR D#
KBA3 33 34
KBA2 35 36 FSEL#
KBA1 37 38 KBA0
39 40
SUYIN-80065A-040G2T

U14 LDO3

KBA0 21 31
A0 VCC0 LDO3 +3VALW +3VALW
KBA1 20 30
KBA2 A1 VCC1
19 A2 2
KBA3 18 C437
A3

1
KBA4 17 25 ADB0 1
KBA5 A4 D0 ADB1 0.1U_0402_16V4Z C531
16 A5 D1 26
KBA6 ADB2 1 0.1U_0402_16V4Z R366
15 A6 D2 27
KBA7 14 28 ADB3 100K_0402_5%
KBA8 A7 D3 ADB4 2 U22
8 32

2
KBA9 A8 D4 ADB5
7 A9 D5 33 8 VCC A0 1
KBA10 36 34 ADB6 LDO3 7 2
KBA11 A10 D6 ADB7 WP A1
6 A11 D7 35 <44,56> EC_SMC_1 6 SCL A2 3
KBA12 5 <44,56> EC_SMD_1 5 4
KBA13 A12 SDA GND
4 A13
KBA14 3 10 RESET# 1 2 LDO3 1 AT24C16AN-10SI-2.7_SO8
A14 RP#

2
KBA15 2 11 C829
KBA16 A15 NC R370 @ 0.1U_0402_16V4Z R609 SUSP#
1 A16 READY/BUSY# 12 SUSP# <34,44,47,51,52,54>

1
KBA17 40 29 100K_0402_5% @ 10K_0402_5%
KBA18 A17 NC0 2 R367
13 A18 NC1 38
KBA19 37 100K_0402_5%

1
A19

2
FSEL# Q53 @ 2N7002_SOT23

G
<44> FSEL# 22

2
CE#

5
<44> FRD# FR D# 24 23 U46
FWE# OE# GND0 EC_FLASH#
9 39 1 1 3

P
WE# GND1 A EC_FLASH# <29>
FWE# 4

S
Y
B 2

G
SST39VF080-70_TSOP40
@ SN74AHC1G32DCKR_SC70-5

3
FWR#
FWR# <44>

1 2
0_0402_5%
R610

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 45 of 60
 A B C D E

L30 DOCK@
KC FBM-L18-453215-900LMA90T_1812
DOCK_VIN 1 2 DOCKVIN

1 1
1 1
DOCK@ C689 C685 DOCK@
1000P_0402_50V7K 1000P_0402_50V7K
2 2

Tampa 2
JP22
1 2 DOCK_PRES_GND
1 2
3 3 4 4
MDO1+ 5 6
<35> MDO1+ 5 6
R478 DOCK@ MDO1- 7 8 MDO0+
<35> MDO1- 7 8 MDO0+ <35>
22_0402_5% JACK_DET# 9 10 MDO0-
<38> JACK_DET# 9 10 MDO0- <35>
<38,42> SPDIFO 1 2 SPDIFO_L 11 12
DOCK@ R479 1 11 12
+5VS 2 100_0402_5% 13 13 14 14 DOCK_MIC
DOCK_MIC <38>
1 <38,42> MUTE_LED MUTE_LED 15 16
XTPA1+ 15 16 DOCK_LOUT_R R480 DOCK@
<32> XTPA1+ 17 17 18 18 DOCK_LOUT_R <38>
@ C644 XTPA1- 19 20 DOCK_LOUT_L DOCK_LOUT_L <38> 200_0402_5%
<32> XTPA1- 19 20
1000P_0402_50V7K XTPB1+ 21 22 1 2 DOCK_VOL_UP# <44>
2 <32> XTPB1+ 21 22
XTPB1- 23 24 USB20_N1
<32> XTPB1- 23 24 USB20_N1 <29>
25 26 USB20_P1 1
25 26 USB20_P1 <29>
27 28 C647 DOCK@
27 28 1000P_0402_50V7K
29 29 30 30
31 32
EMI 33
31 32
34
2
33 34
35 35 36 36
37 37 38 38
2 TVCOMPS 2
39 39 40 40 TVCOMPS <17>
41 42 TVLUMA R491 DOCK@
41 42 TVLUMA <17>
43 44 TVCRMA 200_0402_5%
43 44 TVCRMA <17>
45 45 46 46 2 1 DOCK_VOL_DWN# <44>
47 48 CIR_ IN
47 48 CIR_IN <42,44>
+5V 49 50 +5V DOCK@ 1
49 50 1K_0402_5% 2
51 51 52 52 1 R495
DOCK_PRESENT 53 54 V_Bat V_Bat <48,49> C681 DOCK@
53 54 1000P_0402_50V7K
55 55 56 56
+3VALW 2
DOCKVIN 57 57 58 58 DOCKVIN
59 GND GND 60
1

FOX_QL11293-H212CR-FR
R471 DOCK@
10K_0402_5%
need change to reverse type connector
2

<44> CONA#
1

DOCK_PRESENT 2 Q36 DOCK@

MMBT3904_SOT23
3

+5V
C333 DOCK@
DOCK_PRES_GND 10U_0805_10V4Z

1 1 1
DOCK@ C318 @ C295
0.1U_0402_16V4Z 1000P_0402_50V7K
3 3
2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 46 of 60
A B C D E
 A B C D E F G H I J

B+

1
+5VALW to +5V Transfer R341

1 +3VALW to +3VS Transfer 330K_0402_5% 1

2
+5VALW +3VALW SYSON#
+5V +3VS

1
U39 0.1U_0402_16V4Z U17 0.1U_0402_16V4Z D
8 D S 1 8 D S 1 <34,44,51> SYSON 2
B+ C758 1 7 2 1 7 2 G Q16
D S D S

1
10U_0805_10V4Z 6 3 1 1 C438 6 3 1 1 S 2N7002_SOT23

3
D S D S

1
5 4 10U_0805_10V4Z 5 4 C459 C455 R306
D G D G
1

C760 C759 R549

R545 2 SI4800DY_SO8 10U_0805_10V4Z 2 SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%
330K_0402_5% 2 2 470_0402_5% 2 2 B+

2
2
2

1
SUSON D

1
D RUNON 2 SUSP R406
1
2 2 SYSON# G 2
1

D R546 G Q11 330K_0402_5%

S

3
SYSON# 2 S Q41 2N7002_SOT23

2
G 470_0402_5% 2N7002_SOT23 SUSP
<52,55> SUSP
S
3

1
Q40 D
2N7002_SOT23 1 2
<34,44,45,51,52,54> SUSP#
C755 G Q27
0.01U_0402_16V7K S 2N7002_SOT23

3
2

FM3 FM1 FM2 FM5 FM6 FM4

1 1 1 1 1 1
3 3
+5VALW to +5VS Transfer +1.8V to +1.8VS Transfer
CF3 CF8 CF4 CF6 CF12 CF14 CF7 CF1 CF13
+1.8V
+1.8VS G71@
+5VALW +5VS U5 0.1U_0402_16V4Z

1
8 D S 1
U25 0.1U_0402_16V4Z 1 7 2
D S

1
8 1 C373 6 3 CF10 CF5 CF9 CF2 CF11
D S D S 1 1
C515 1 7 2 G71@ 5 4 C379 C377 R154
B+ 10U_0805_10V4Z D S 10U_0805_10V4Z D G G71@ G71@
6 D S 3 1 1

1
2 G71@ SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%
5 4

1
D G C561 C552 R347 2 2

2
1

2 SI4800DY_SO8 10U_0805_10V4Z
R398 2 2 470_0402_5%
4 4

1
330K_0402_5% D H15 H3 H16 H19 H20 H12 H7 H14 H22 H13 H8
2

RUNON 2 SUSP HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
G
2

RUNON S Q7

3
1

D G71@

1
1

2 SUSP 2N7002_SOT23
1

D R395 G
SUSP 2 S Q18
3

G 470_0402_5% 2N7002_SOT23 H11 H2

Q21 S HOLEA HOLEA
3

2N7002_SOT23
1
C557

1
0.01U_0402_16V7K
2
5 H5 H10 H4 H9 5
HOLEA HOLEA HOLEA HOLEA

1
+2.5VS +1.8V +1.5VS +VCCP H17 H18 H6 H21 H23 H24
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

R137 R131 R522 R346

1
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
6 6
1 2

1 2

1 2

1 2

D D D D
2 SUSP 2 SYSON# 2 SUSP 2 SUSP
Q5 G G G G
2N7002_SOT23 S S Q4 S Q37 S Q17
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

+VGA_CORE +0.9VS
1

R536 R68

7 470_0402_5% 470_0402_5% 7
1 2

1 2

D D
2 SUSP 2 SUSP
G G
S Q38 S Q3
3

2N7002_SOT23 2N7002_SOT23

8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuit
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 47 of 60
A B C D E F G H I J
 5 4 3 2 1

PD27
@ SBM1040-13_POWERMITE3
Detector/Precharge
2
DOCK_VIN 1
3

PJP1
@ JUMP_43X118
1 1 VIN
2 2
Vin Detector : Titan Vin Detector : Altima
PJP2
ADPIN @ JUMP_43X118
18.234 17.841 17.449 14.698 14.285 13.879
D D
PL1
1 1 2 2 PD31
17.597 17.210 16.813 13.818 13.411 13.000
FBM-L18-453215-900LMA90T_1812 EC31QS04
2
ADPIN 1 2 ADPIN2 1 2 1 V_Bat <46,49>
3
PR1
4 PD1 1M_0603_0.5%
@ SBM1040-13_POWERMITE3 1 2

1000P_0402_50V7K
VIN
VS VIN

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1

1
PC2

PC4

0.01U_0402_25V7Z
3

PC1

PC3

1
PR3 PR4

1
PC5
2
PR2 10K_0805_5% 1K_0402_5%
82.5K_0603_0.1% 1 2 ACIN <44,50>

2
PR5

2
8
1
22K_0603_1%
N1 1 2 N2 3

P
PCN1 + PACIN
O 1 PACIN <49>

0.047U_0603_50V7K

19.6K_0603_0.1%
ACES_88290-0400M N3 2 -

1
1

1
PC6

PR6
PU1A PR7

4
PC7 LM393M_SO8 PZD1 10K_0402_5%
PR8 1000P_0402_50V7K RLZ4.3B_LL34

2
1 2

2
B+
1K_1206_5%
VIN PR9
10K_0402_5%
PR10 PD2 2 1
C
1 2 N4 2 1
RTCVREF C

1 1K_1206_5% 1N4148_SOD80 3.3V

Titan: PR5= 22K; PR6= 19.6K
PJP27 PR11 PR12 Altima:PR5= 47K; PR6= 27K
PD3 47_1206_5% 1 2
1N4148_SOD80 @ JUMP_43X39
2

2 1 N58 1K_1206_5%
2 1
N5

BATT+ 2 1
2

VS
PD4
PR215 1N4148_SOD80
47_1206_5%
1

CHGRTCP 3 1 2 1
0.22U_1206_25V7K
1

0.1U_0603_25V7K
1

PR13
PC8

PC9

100K_0603_1%
2

PR15 PR16
2

PR14 PQ1 10K_0402_5% 1M_0603_0.5%

1 2 N6 TP0610K-T1-E3_SOT23 1 2 2 1
<42> EC_PWR_ON# VL
22K_0603_1%
VS B+
ACIN: Titan
1

RTCVREF PD5

1
B PR17 B
<49> ACON 2 1
PR18
Precharge detector
PR19 PR20 PU2 200_0603_5% RB751V_SOD323 280K_0603_1%
@ 510_0603_5% @ 510_0603_5% G920AT24U_SOT89
14.724 14.333 13.945
3.3V
2

13.280 12.933 12.531

2
8
1 2 N7 1 2 3 2 N8
CHGRTC OUT IN PD6 5 N10

P
+
1

1000P_0402_50V7K
PC10 N9
<50,56> MAINPWON 2 1 7 O ACIN: Altima
1

GND

1.5M_0603_1%
6 N11
-
1

1
PR256 1U_0805_50V4Z RB751V_SOD323
2

1
1

1000P_0402_50V7K
0.1U_0603_25V7K

PR22

PC12
47K_0603_1% PC11 PU1B
Precharge detector

4
1

PC14
4.7U_0805_6.3V6K LM393M_SO8 PR21
2

PC13
200K_0603_1%
12.384 12.000 11.624
2

2
2

2
10.927 10.600 10.223

N12
PJP4
PJP5 @ JUMP_43X39 PR23

1
@ JUMP_43X118 VL D 47K_0402_5%
+0.9VGAP 1 1 PR24 2 N13 1 PACIN
BATT
2 2 +0.9VGA
+2.5VSP
2 2 1 1 +2.5VS PJP15 10K_0402_5% G
2

1
+1.8VSP @ JUMP_43X118 2 1 S Precharge detector

3
PJP6 PJP7 1 1 PQ2
@ JUMP_43X118 @ JUMP_43X118 2 2 +1.8VS
2N7002_SOT23
7.558 7.333 7.112
4.7U_0805_6.3V6K

1 1 +5VALWP
+5VALWP 2 2 +5VALW 1 1 2 2 +1.5VS
220U_D2_4VM

+1.5VSP 1 2 6.108 5.933 5.704

1

PC152

PJP8 PJP9 + PQ3

@ JUMP_43X118 @ JUMP_43X118 Titan: PR21= 200K DTC115EUA_SC70
2
PC151

1 1 2 2 1 1 2 2 +1.2VS

3
+3VALWP +3VALW +1.2VSP 2 Altima:PR21= 300K
A PJP10 PJP11 A
@ JUMP_43X118 @ JUMP_43X118
+1.8VP +1.8V
1 1 2 2 1 1 2 2 +VGA_CORE
+VGA_COREP

PJP12 PJP13
@ JUMP_43X118 @ JUMP_43X118
+1.05VSP +VCCP
1 1 2 2 1 1 2 2 Security Classification Compal Secret Data
Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title
PJP14
@ JUMP_43X118
DCIN / Precharge
+0.9VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.9VSP 1 1 Size Document Number Rev
2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom LA-2841 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

PD32

1
EC31QS04
2 B+ Charger
<46,48> V_Bat

P2 65W Iadp=0~3.0A
90W Iadp=0~4.2A
B++

100U_25V_M
PQ49 PQ4 1

PC209
PL18
AO4407_SO8 AO4407_SO8 P3 FBM-L18-453215-900LMA90T_1812 +
VIN 8 1 1 8 PR26
D D
7 2 2 7 2 1 1 2 1 8
2

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
6 3 3 6 2 7
5 5 0.02_2512_1% 3 6

1
15K_0603_5%

5
1

4
PR27

PC15

PC16

PC17

PC18
PQ5

4
AO4407_SO8

3
1

0.1U_0603_25V7K
PQ54 65W:1.40V(-1 level); 1.30V (+1 level)
2

47K

200K_0402_5%
DTA144EUA_SC70 90W:2.05V(-1 levle); 1.83V (+1 level)

PR28
PR248 N64

DIS
2 47K

PC206
47K_0402_5% PR29
1 2 VIN
2

2
1

2
2
PU3 47K_0603_5%
1 24 PR30
<44> ADP_I

1
-INC2 +INC2

1
2.2_0603_5%
N65 2 N14

1
PR31
PQ53
65W==>1.202V 2
PR32
1 2 OUTC2 GND 23
10K_0603_5%
DTC115EUA_SC70 90W==>1.667V 10K_0402_1% PC19 2200P_0402_50V7K

2
3887+INE2 3 22 3887CS 1 2
3

+INE2 CS

31.6K_0603_1%
ACOFF#
1

3
2
1
2 3887-INE2 4 21 3887VCC 1 2
-INE2 VCC(o)

1
2N7002_SOT23

PR34
G PR33 PC21 PQ6
S 150K_0402_1% 2200P_0402_25V7K PC20 AO4407_SO8
3

10K_0402_1%
0.1U_0402_16V7K
PQ52

ACOFF# 1 2 1 2 N16 1 23887FB25 20 3887OUT 0.1U_0603_25V7K 4

FB2 OUT

1
PR35

2
PC22
N15
PD9 6.8K_0402_1% PC23 2
1SS355_SOD323 5.0V 3887VREF 6 19 3887VH 1 2
ACOFF <44>

2
VREF VH

PR36
PQ7

2
1

1
D

2N7002_SOT23

0.1U_0402_16V7K
C 0.1U_0603_25V7K PC26 0.1U_0603_25V7K DTC115EUA_SC70 C
PACIN 1 2 2 1 2N171 23887FB17 18 1 2
<48> PACIN

5
6
7
8

3
FB1 VCC

PC24
G PR38

2
PR37 S PC25 1K_0603_1% PR39
3
3K_0603_5% PQ8 1500P_0402_50V7K 3887-INE1 8 17 3887RT 1 2
-INE1 RT 68K_0603_5%

N19
<48> ACON
3887+INE19 16 3887-INE3 PL2
+INE1 -INE3 15U_PLFC1045P-150A_3.7A_20%
PR42 1 2 2 1
65W PR34=31.6K 2 1 3887OUTC1
10 15 3887FB3 1 2N181 2
BATT+
PR41 OUTC1 FB3 47K_0603_1% PR40
90W PR34=20.0K 10K_0603_1% PC27 0.02_2512_1%

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
3887OUTD11 14 ACON 1500P_0402_50V7K
OUTD CTL

1
PD10 PD11

PC28

PC29

PC30
<44> IREF 1 PR43 2 EC31QS04 EC31QS04
12 13 3887+INC1

2
174K_0603_1% -INC1 +INC1

2
1

IREF=1.096*Icharge PR44 0.1U_0402_16V7K MB3887_SSOP24

1

IREF=0.438~3.069V
PC31

100K_0603_1%
2

2 1
4.2V 2 1
Battery OVP voltage : PR45 PR46
49.9K_0603_0.1% 150K_0603_0.1%
4S2P : 18V--> BATT_OVP= 2.0V
B B
(BAT_OVP=0.1112*VMB)
CC=0.4~2.8A
3S2P/3S4P : 13.5V--> BATT_OVP= 2.0V BATT_Charge Voltage Select
(BAT_OVP=0.14753 *BATT+) 4S2P CV=16.8V PR45 = 49.9K_0603_0.1% PR46 =150K_0603_0.1%
3S2P/3S4P CV=12.6V PR45 = 150K_0603_0.1% PR46=300K_0603_0.1%
VS BATT++
<44> AIR_ACIN
1

PR47 +3VALWP
340K_0603_1%
0.01U_0402_25V7Z

3887CS 3887CS
2

1
1

PR48
N20
PC32

PU4B 47K_0603_5%
2

1
LM358A_SO8 PR50 D

2
PR49 PR51 10K_0603_5% N26 2 PQ10
PU4A 499K_0603_1% PQ9 4.22K_0603_1% 5 N23 2 1 G
+ RTCVREF

1
LM358A_SO8 DTC115EUA_SC70 2 2 1N247 S 2N7002_SOT23
2

3
0
8

6 N25 2 1
- VIN
RLZ4.3B_LL34

3 N22
P

+
1

1 PR52 (17V+-5%)
<44> BATT_OVP 0
2

2 42.2K_0603_1% 2
<44> FSTCHG
3

-
G

PZD2
1

PR53 PQ11
4
22K_0402_5%

PR55 10K_0603_5% PR54 DTC115EUA_SC70

2

2
1
PR56

A 105K_0603_0.5% 10.2K_0603_1% A
1

3
PC33
2

N21 0.01U_0402_25V7Z
2

2
1

PR57
0_0603_5%
Security Classification Compal Secret Data
2

BATT_OVP Select Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title

Charger
4S2P PR57 = 0_0603_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3S2P/3S4P PR57 = 40.2K_0603_1% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

B+ +3.3VALWP/+5VALWP

D D
1

PJP25
1

@ JUMP_43X118
2

PC179 PC180
2

0.1U_0603_25V7K 0.1U_0603_25V7K
2 1 BST5B BST3B 2 1

3
VS P2
B+++
PD24
DAP202U_SOT323

2
@ 0_0805_5%

0_0805_5%
PR255

PR254
LDO5 VL
2200P_0402_50V7K

B+++

1
4.7U_1206_25V6K

4.7U_1206_25V6K

PR216
1

2
PC183

PQ41 0_0402_5%

1
PC181

PC182

1 8 DH5A 1 2 DH5 PR217

D2 G2

47_0402_5%
2 7 0_0402_5% 1999_V++ PQ42
2

D2 D1/S2/K

1
3 G1 D1/S2/K 6 1 D2 G2 8

0_0805_5%

10_1206_5%

PR218
4 5 PC184 2 7

1
S1/A D1/S2/K D2 D1/S2/K

1
10_1206_5%

2200P_0402_50V7K
PR251
0.1U_0402_16V7K 3 6

2
G1 D1/S2/K

4.7U_1206_25V6K

4.7U_1206_25V6K
PR219
PR241 4 5

1
S1/A D1/S2/K

1
PR239

PC187
AO4912_SO8 0_0805_5%

PC185

PC186
0.1U_0603_25V7K
LX5 @ AO4912_SO8

2
2
VL

2
PR220

4.7U_1206_25V6K
0_0402_5%
2VREF_1999

+5VALWP

1U_0603_10V6K
1

1PC191
DH3A

1
499K_0402_1% 118K_0402_1%

499K_0402_1% 200K_0402_1%
4.7U_0805_6.3V6K

PC188
C PL16 C

1999_V+

1999_VCC

2
PC189
10U_LF919AS-100M-P3_4.5A_20%

2
1

PR221

PR222
PC190
DL5 LX3

2
PR223
2

2
0_0402_5%

2 1

2 1
18

20

13

17

PR224
BST5A 14

TON

VCC
LD05

V+

1
BST5

PR225
5 ILIM3
ILIM3
16
+5VALWP DH5

1
1

1
15 PL17
LX5 PU5 ILIM5 10U_LF919AS-100M-P3_4.5A_20%
19 DL5 ILIM5 11
21 OUT5 MAX8734EEI_QSOP28
@ 10.2K_0402_1%

FB5 9 28 BST3A
PR258 @ 0_0402_5% FB5 BST3 DH3
1 26

2
N.C. DH3
2

1999_V+ 2REF_1999 1 2 24 DL3

DL3
PR226

1999_SHDN 6 27
SHDN# LX3
@SKUL30-02AT_SMA
150U_D2E_6.3VM_R18

1 4 ON5 OUT3 22
1

1
47K_0402_5%
PC192

PD25

1 2 3 ON3
+ PR257 0_0402_5% 7 FB3
1

FB3
PR227

1999_SKIP 12 2 +3VALWP
SKIP# PGOOD
2

@ 3.57K_0402_1%
PRO#
LDO3
2REF_1999 8

GND
2

REF
2

2
0_0402_5%

2VREF_1999
PR229

PR230
PR228
1

@SKUL30-02AT_SMA
10K_0402_5%

23

25

10

150U_D2E_6.3VM_R18
PR231 1
PC193 <44,48> ACIN

1
0.22U_0603_16V7K

PD26

PC194
0_0402_5%
1

1
@ 1U_1206_25V7K ACIN 1 1999_PRO 1 2 +
PC195

2
B B
2

2
0_0402_5%
PR232
VL LDO3P 1 2 LDO3

1
1
1999_ON

4.7U_0805_6.3V6K
PR240
806K_0603_1%

PC196
0_0805_5%
1

2
PR233

+3VALWP 1 2
LDO3P PR252
@ 0_0805_5%
2

PR234
0_0402_5%
2

2 1
<48,56> MAINPWON PR242
100K_0402_5%
1

PC197
1
RHU002N06_SOT323

0.047U_0603_16V7K
1

D
2

2 N60
PQ46

G
S
3

RHU002N06_SOT323

RHU002N06_SOT323
1

D D
2 ACIN 2
EC_ON <42,44>
PQ47

PQ48

G G
S S
3

A A

Security Classification Compal Secret Data

Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title
+3V/+5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

D
+1.8VP/+1.5VALWP/+2.5VS D

PJP18
@ JUMP_43X118

IS6227A_B+ 2 1 B+
2 1

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
1

4.7U_1206_25V6K

4.7U_1206_25V6K
PC61
PR83

1
PC59

PC60

PC62

PC63

PC64
51_1206_5% +5VALWP

2
2
PR84

0.1U_0603_25V7K
DAP202U_SOT323
2.2_0603_5%

1
4.7U_0805_6.3V6K
PC67

1
PC65

PD17

PC66
2.2U_0805_10V6K

ISL6227A_VIN

1
1 2

ISL6227A_VCC
2
2

3
8
7
6
5

5
6
7
8
BOOT1.5A
PQ16 PQ58

BOOT1.8A
D
D
D
D

D
D
D
D
SI4800BDY_SO8 PC68 PC69 SI4800BDY_SO8
0.01U_0402_25V7Z 0.01U_0402_25V7Z

14

28
+1.8VP PU6

G
S
S
S

S
S
S
C C
2 1SOFT1.8 12 17 SOFT1.52 1

VIN

VCC
PL4 SOFT1 SOFT2
1
2
3
4

4
3
2
1
4.7UH_PLC1045P-4R7A_5.5A_30% PC70 PR85 PR86 PC71 PL5 +1.5VSP
0.1U_0603_25V7K 0_0402_5% 0_0402_5% 0.1U_0603_25V7K 3.3UH_PLC1045P-3R3A_6.1A_30%
1 2 2 1 1 2BO0T1.86 BOOT1 BOOT2 23 BOOT1.5
1 2 2 1 1 2

4.7U_0805_6.3V6K
PR87 PR88
8
7
6
5

5
6
7
8

220U_D2_4VM
0_0402_5% 0_0402_5% 1

1
4.7U_0805_6.3V6K

220U_D2_4VM_R25

1 PQ17 UG1.8A 1 2 UG1.8 5 24 UG1.5 1 2 UG1.5A

D
D
D
D

D
D
D
D
UGATE1 UGATE2

PC73
0.01U_0402_25V7Z

SI4800BDY_SO8 PQ59 +
1

0_0402_5%

0.01U_0402_25V7Z
10.5K_0402_1%

+ PHASE1.8 4 25 PHASE1.5 SI4810DY-T1-E3_SO8

2
PHASE1 PHASE2
1

@ 0_0402_5%
PC75

PC72
G

1
2
S
S
S

S
S
S

6.81K_0402_1%
PC74

PR89

PC76

PR90

PR93 PR94
2

1
2

PR91

PC77
2.43K_0603_1% 2.43K_0603_1%
2

1
2
3
4

4
3
2
1

PR92
1 2 ISEN1.8 7 22 ISEN1.5 1 2
2

ISEN1 ISEN2
1

2
LG1.8 2 27 LG1.5

2
LGATE1 LGATE2

3 PGND1 PGND2 26

VOUT1.8 9 20 VOUT1.5
VSEN1.8 VOUT1 VOUT2 VSEN1.5
10 VSEN1 VSEN2 19
8 21 EN1.5
EN1 EN2
15 PG1A PG2/REFA 16

GND

DDR
OC1.8 11 18 OC1.5
OCSET1 OCSET2
@ 0_0402_5%

0_0402_5%
1 2 EN1.8 1 2
1

1
<34,44,47> SYSON SUSP# <34,44,45,47,52,54>
10K_0402_1%

10K_0402_1%
ISL6227BCA-T_SSOP28

13
1

1
PR97

PR98

PR99

PR100
PR95 PR96
1

B 0_0402_5% PR101 PR102 0_0402_5% B

1
73.2K_0603_1% 73.2K_0603_1%
PC78
2

2
@ 0.1U_0402_16V7K PC79
2

2
@ 0.1U_0402_16V7K

(400mA,40mils ,Via NO.= 1)

APL5508_SOT89
PJP19 +2.5VSP
@JUMP_43X39 PU7

+3VS 1 2 VIN2.5 2 3
1 2 IN OUT
4.7U_0805_6.3V6K

10U_1206_25VAK
1U_0603_10V6K

PQ18
1

GND
PC82
PC80

PC81

@ SI3456DV-T1_TSOP6
1
2

2
D

6
S

5 4
2
1
G

PR103
3

@ 47K_0603_5%
A SUSP# N32 A
1 2
1

PC83
2

@ 0.1U_0603_25V7K
Security Classification Compal Secret Data
Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title
1.8V/1.5V/2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

PL6
FBM-L18-453215-900LMA90T_1812

MAX8575_B+ 1 2 B+
+1.05V_VCCPP/+0.9VSP

0.01U_0402_25V7Z

10U_1206_25V6M
6.81K_0402_1%
PR105 1

1
0_0402_5%

1
PC86

PR104

PC84
MAX8575_IN 1 2 PC85
D SUSP# <34,44,45,47,51,54> 0.1U_0603_25V7K D

2
2

1
2
PC87
@ 0.1U_0603_16V7K

SI4800BDY_SO8
MAX8575_OCSET

D 5
D 6
D 7
D 8
PQ19

G
S
S
S
PU8

4
3
2
1
PC88 10 9 PR106
3300P_0402_50V7K OCSET IN 0_0402_5% +1.05VSP
2 1 MAX8575_SS 2 SS DH 8 DH1.05 1 2 DH1.05A PL7
3.3UH_PLC1045P-3R3A_6.1A_30%
FB1.05 1 7 LX1.05 1 2
FB LX

+5VS 1 2 MAX8578_VCC 3 5 DL1.05

VCC DL

4.7U_0805_6.3V6K
7.15K_0402_1%
1

5
6
7
8

1
SI4810BDY_SO8
4.7U_0805_6.3V6K

PR108

330U_D2_2.5VM
PR107 4 6 BST1.05 2 1
C GND BST C

1
PC91

PR109

PC90
30_0402_5%
0_0402_5% +

D
D
D
D

PC201
PQ20
MAX8578EUB_10UMAX PC89
1

0.1U_0603_25V7K

2
PR110 2

2
G
S
S
S
866_0402_1%

4
3
2
1
2

1 2DL1.05A 1 2

N33
2 1
PR111 PC92
PD18 4.7_0402_5% 0.047U_0603_25V7M
1SS355_SOD323
1 2

1
+1.8V +1.8VP PR112
750_0603_1% PC93
0.1U_0402_10V6K

2
2

PJP20
2

@ JUMP_43X118
1

B B
1

PU9
VIN0.9 1 6 +3VALW
VIN VCNTL

1U_0603_16V6K
2 GND NC 5
1

2
1

PC95
PC94 3 7
PR113 VREF NC
2

1
10U_1206_6.3V7K 1K_0402_1% 4 8
VOUT NC
9
2

TP
VREF0.9
APL5331KAC-TR_SO8
PR114
1

510K_0402_5% D
+0.9VSP
1 2 2 PQ21 PC96
<47,55> SUSP G 2N7002_SOT23 PR115 0.1U_0402_16V7K
2
0.1U_0402_16V7K

10U_1206_6.3V7K

S 1K_0402_1%
3
1

1
510K_0402_5%

2
1

@ PC97

PC98
PR253

A A
2

Security Classification Compal Secret Data

Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title
1.05V/0.9V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 52 of 60
5 4 3 2 1
 8 7 6 5 4 3 2 1

+CPU_B+ PL8
CPU CORE
FBM-L18-453215-900LMA90T_1812
1 2 B+

0.1U_0603_25V7K

2200P_0402_50V7K

4.7U_1206_25V6K
H H

100U_25V_M
10U_1206_25VAK
1

PC99
1

1
PC100

PC103
+

PC101

PC102
2

2
2

+CPU_B+

+5VS

D 5
D 6
D 7
D 8

D 5
D 6
D 7
D 8
SI4684DY-T1-E3_SO8

SI4684DY-T1-E3_SO8
2

1U_0603_16V6K

PQ22

PQ43
PR116

1
PC104
10_0603_5% PR117 PC105
2.2_0603_5% 0.22U_0603_10V7K

4 G

4 G
3 S
2 S
1 S

3 S
2 S
1 S
0.01U_0402_25V7K
2 1N 37 1 2

2
PU10
G 5 VCC BOOT 1N 36 PR235 PL9 G
0_0603_5%
6 8 6208A_UG 2 1 6208A_UGA 0.36UH_MPC1040LR36_24A_20%
+5VS FCCM UGATE

1
PC106
2 7 CPU_PHASE1 1 2 +CPU_CORE
+3VS PWM PHASE

2
4.7_1206_5%
3 4

2
GND LGATE

D 5
D 6
D 7
D 8

D 5
D 6
D 7
D 8

2
SI4856ADY-T1-E3_SO8

SI4856ADY-T1-E3_SO8
PR118
ISL6208CRZ-T_QFN8 10_0402_1%

PQ24

PR119
PR120 PC107

PQ23
10K_0402_1% 0.22U_0603_10V7K

1
2
10_0603_5%
PR124 1 2 2 1

N42 1
2

4 G

4 G
3 S
2 S
1 S

3 S
2 S
1 S
1.91K_0603_1%

2
680P_0603_50V8J
PR121
PR236 PR122

1
1 @ 0_0402_5% 5.11K_0603_1% 2 PR123 1

1
ISL6260_VDD 2 1
VGATE <29,44>
1U_0603_10V6K

PC108
@ NC

1
1

F F

ISL6260_PGOOD

2
PC109

@ 1U_0603_10V6K
VSUM VO

1
ISL6260_VIN
2

PC208
N 59 6208A_LG

2
1

+CPU_B+
0_0402_5%
PR125

PC110
0.01U_0402_25V7Z +5VS
2 1 ISL6260_NTC 19

20

18

39

40
2

0.1U_0603_25V7K

2200P_0402_50V7K

4.7U_1206_25V6K
ISL6260CRZ-T_QFN40

D 5
D 6
D 7
D 8

D 5
D 6
D 7
D 8
1U_0603_16V6K

10U_1206_25VAK
SI4684DY-T1-E3_SO8

SI4684DY-T1-E3_SO8
VSS

3V3
VDD

VIN

PGOOD

1
PQ45
PC115

PC111

PC114
PC112

PC113
2 PR126 1 ISL6260_VRTT 4
<4> H_PROCHOT# VR_TT#

PQ25
0_0402_5%

2
4 G

4 G
3 S
2 S
1 S

3 S
2 S
1 S
2 PR127 1 PH1 ISL6260_RBIAS 3 27 ISL6260_PWM1
150K_0402_5% 470KB_0402_5%_ERTJ1VR103J RBIAS PWM1 PR129 PC117
E E
2 PR1281 N 56 2 1 ISL6260_NTC 5 2.2_0603_5% 0.22U_0603_10V7K
NTC
4.22K_0402_1% PC116 2 1N 39 1 2
2 1 ISL6260_SOFT 6 23 ISL6260_ISEN1 PU12
SOFT ISEN1
5 VCC BOOT 1N 38 PR237 PL10
0.022U_0402_16V7K PU11 0_0603_5%
2 PR1301 ISL6260_VID0 28 6 8 6208B_UG 2 1 6208B_UGA 0.36UH_MPC1040LR36_24A_20%
<5> CPU_VID0 ISL6260_VID1 VID0 FCCM UGATE
<5> CPU_VID1 2 PR131 1 0_0402_5% 29 VID1
0_0402_5% 2 PR132 1 ISL6260_VID2 30 26 ISL6260_PWM2 2 7 CPU_PHASE2 1 2 +CPU_CORE
<5> CPU_VID2 ISL6260_VID3 VID2 PWM2 PWM PHASE
<5> CPU_VID3 2 PR133 1 0_0402_5% 31 VID3

2
4.7_1206_5%
SI4856ADY-T1-E3_SO8

SI4856ADY-T1-E3_SO8
0_0402_5% 2 PR134 1 ISL6260_VID4 32 3 4
<5> CPU_VID4 VID4 GND LGATE

D 5
D 6
D 7
D 8

D 5
D 6
D 7
D 8

2
2 PR135 1 0_0402_5% ISL6260_VID5 33 PR136
<5> CPU_VID5 0_0402_5% ISL6260_VID6 VID5 ISL6260_ISEN2
2 PR137 1 34 22 ISL6208CRZ-T_QFN8 10_0402_1%

PQ27
<5> CPU_VID6 VID6 ISEN2

PQ26

PR138
0_0402_5% PR140 PC118
2 PR139 1 ISL6260_DPRSTP 37 10K_0402_1% 0.22U_0603_10V7K

1
<4,28> H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1

N43 1
4 G

4 G
3 S
2 S
1 S

3 S
2 S
1 S
2 PR141 1 ISL6260_DPRSLPVR 36
<7,29> DPRSLPVR DPRSLPVR

2
680P_0603_50V8J
2 PR142 1 499_0402_1% ISL6260_PSI 1
D
<5> H_PSI# 0_0402_5% PSI# PR143 2 PR144 1 D
2 PR145 1 ISL6260_PGD 2 24 ISL6260_FCCM 5.11K_0603_1%
<44> PGD_IN PGD_IN FCCM

1
0_0402_5% @ NC

PC119
2 PR146 1 ISL6260_CLK 38

1
<15> CLK_ENABLE# 0_0402_5% CLK_EN#

2
<44> VR_ON 2 PR148 1 ISL6260_VRON 35 PR147 VSUM VO
0_0402_5% VR_ON 0_0402_5%
2 1 ISL6260_VSEN 12 25 ISL6260_PWM3 2 1 +5VS 6208B_LG
<5> VCCSENSE PR149 0_0402_5% PC120 VSEN PWM3
1000P_0402_50V7K ISL6260_RTN 13
RTN
2 1
21 ISL6260_ISEN3 2 1
ISEN3
2

+CPU_CORE2 1 PC199 11
PR150 @ 10_0402_1% 0.082U_0603_25V7K VDIFF PR151
ISL6260_VCIFF

0_0402_5%
1

2 1 10 FB
PR153 PR152
0_0402_5% PC121 7 ISL6260_OCSET 2 1
1000P_0402_50V7K OCSET 11.5K_0402_1%
2 1 9
C <5> VSSSENSE COMP C
ISL6260_FB

2 1 PC126 PR156 17 VSUM

VSUM
3K_0402_1%

1800P_0402_50V7K 0_0402_5% 8 VW
1
1000P_0402_50V7K

PR154 2 1 N 45 1 2 N 34 2 1
PR158
DROOP

@ 10_0402_1%
ISL6260_COMP

PR155
DFB

180_0603_1% 1 PR157 2
VO

2
4.53K_0402_1%

0.22U_0603_16V7K

PC129

1.2K_0402_1%
2
2
PR159
ISL6260_VW

ISL6260_DROOP 14

15

16

PC130

1 2 N 57 2 1
2

N35

@
ISL6260_DFB

10KB_0603_5%_ERTJ1VR103J
0.1U_0402_16V7K

PC128 PR160
PC132 0.022U_0402_16V7K 68.1K_0402_1% VO
1 2

220P_0402_25V8K
1
PC134

2 1
1

B
@ 1K_0402_1%

PC133 PR166 PR167 B

2

1000P_0402_50V7K 6.19K_0603_1% 1K_0402_1%

PH2

PR165

2 1 2 1

2 1
2

PR164 PC136
6.98K_0402_1% 2 1

330P_0402_50V7K
1

PC200
0.1U_0402_16V7K
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 53 of 60
8 7 6 5 4 3 2 1
 5 4 3 2 1

+VGA_COREP/+1.8VSP

D D

PJP21
@ JUMP_43X118

IS6227B_B+ 2 1 B+
2 1

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
1

4.7U_1206_25V6K

4.7U_1206_25V6K
PC140
PR171

1
PC138

PC139

PC141

PC142

PC143
+5VALWP
51_1206_5%

2
2
PR172

1
4.7U_0805_6.3V6K

0.1U_0603_25V7K
DAP202U_SOT323
2.2_0603_5%

PC144

1
PC145

ISL6227B_VIN
2

1
PD22
PQ31
AO4912_SO8

ISL6227B_VCC
2
PC146

SI4800DY-T1-E3_SO8
2.2U_0805_10V6K 8 1
G2 D2

8
7
6
5
1 2 7 2

3
D1/S2/K D2
6 3

D
D
D
D
BOOT_V1.8 D1/S2/K G1
5 D1/S2/K S1/A 4

BOOT_VGA
PQ32 PC147 PC148

G
S
S
S
C 0.01U_0402_25V7Z 0.01U_0402_25V7Z C

14

28
+VGA_COREP PU14
1
2
3
4
2 1SOFT_VGA 12 17 SOFT_V1.82 1

VIN

VCC
PL12 SOFT1 SOFT2 +1.8VSP
1.4UH_SSF-13056-1R4_15.5A_+-20% PC149 PR173 PR174 PC150 PL13
0.1U_0603_25V7K 0_0402_5% 0_0402_5% 0.1U_0603_25V7K 3.3UH_PLFC0745-3R3_4.8A_30%
2 3 2 1 1 2N49 6 BOOT1 BOOT2 23 N50 1 2 2 1 1 2
SI4810DY-T1-E3_SO8

PR175 PR176
8
7
6
5

8
7
6
5
SI4810DY-T1-E3_SO8

0_0402_5% 0_0402_5% +1.8VS

4.7U_0805_6.3V6K

PQ34

1 1 UG_VGAA 1 2 UG_VGA 5 24 UG_V1.8 1 2UG_V1.8A

D
D
D
D

D
D
D
D

UGATE1 UGATE2
PQ33
330U_D2_2.5VM

@330U_D2_2.5VM

0.01U_0402_25V7Z
1

@ 0_0402_5%
2.26K_0402_1%
PC153

PC154

0.01U_0402_25V7Z
+ + PHASE_VGA 4 25 PHASE_V1.8
PHASE1 PHASE2
1

0_0402_5%
PC155

1
S
S
S

S
S
S

10.2K_0402_1%
PR177

PC156

PR178

PR181 PR182
2

1
2 2

PR179

PC157
1.33K_0603_1% 1.33K_0603_1%
2

1
2
3
4

1
2
3
4

PR180
1 2 ISEN_VGA 7 22 ISEN_V1.81 2
2

ISEN1 ISEN2
1

2
LG_VGA 2 27 LG_V1.8

2
LGATE1 LGATE2

3 PGND1 PGND2 26

VOUT_VGA 9 20 VOUT_V1.8
VSEN_VGA VOUT1 VOUT2 VSEN_V1.8
10 VSEN1 VSEN2 19
8 EN1 EN2 21 1 2 1 2 SUSP# <34,44,45,47,51,52>
15 PG1B PG2/REFB 16
PR250 PR183

GND

DDR
OC_VGA 11 18 OC_V1.8 @ 0_0402_5% @ 0_0402_5%
OCSET1 OCSET2
0_0402_5%

@ 0_0402_5%
SUSP# 1 2 EN_VGACORE EN_VGA 1 2 +3VALWP
1

1
10K_0402_1%

10K_0402_1%
B ISL6227BCA-T_SSOP28 B

13
1

1
PR186

PR187

PR188

PR189
PR184 PR185
1

@ 0_0402_5% PR190 PR191 100K_0402_5%

68K_0603_1% 68K_0603_1%
PC158
2

2
EN_VGA 1 2 @ 0.1U_0402_16V7K
2

2
EN_VGA
EN_VGA# <55>
PR192

RHU002N06_SOT323
0_0402_5%

1
D
2 1 2 +3VALWP

PQ55
G
S PR249

3
100K_0402_5%

RHU002N06_SOT323

1
D
2 1 2 SUSP# <34,44,45,47,51,52>

PQ56
G
S PR193

3
0_0402_5%

1
PC159
@ 0.1U_0402_16V7K

2
A A

Security Classification Compal Secret Data

Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 54 of 60
5 4 3 2 1
 5 4 3 2 1

+5VALW +1.2VSP/+0.9VSP

D
S
6
4 5 PQ36

2
2 @ SI3445DV_TSOP6
1

2
PJP22

G
D @ JUMP_43X39 D

3
+1.2VSP

1
PL14

1
5UH_SPC-06704-5R0A GP_2.9A_30%

D
PHASE_V1.2

S
6 1 2
VIN_V1.2 4 5
2

22U_1206_6.3V6M

10U_1206_6.3V7K
1 1

1
22U_1206_6.3V6M

220U_D2_4VM
EC31QS04

@ EC31QS04

191K_0402_1%
G
1 1

1
@ 470P_0402_50V8J
PD29

PD30

PR243

PC166
PD28 PQ57 +

3
1

1
PC161

PC162

10K_0402_5%
RB751V_SOD323 SI3445DV_TSOP6

HMBT2222A_SOT23

PC202

2
1
2 2 2

PR244

PC165
C

1N63 1

2
PQ50
1 2 2 VS
B

0.1U_0603_25V7K
PR245 E

3
1K_0603_5%

PC204
PC203
2200P_0402_50V7K

2
N61

8
3
E 3 FB_V1.2 PR246

P
PQ51 N62 + 330K_0402_1%
2 1 O
2SA1036K_SOT23 B 2 REF_V1.2 1 2
- 2VREF_1999

G
C PU15A

1
LM393M_SO8

22P_0402_50V8J
C C

PC210
VS PC205

1
4700P_0402_25V7K

SN7002N_SOT23
PR247 PR196

1
499K_0402_1% D 0_0402_5%

PQ37
PU15B 2 N46 1 2 EN_VGA# <54>
LM393M_SO8 5 G

2
+
7 O S

3
- 6

4 G

+1.8VS

B B
2

PJP24
2

@ JUMP_43X118
1

PU16
1

@ APL5331KAC-TR_SO8
VIN_V0.9 1 VIN VCNTL 6 +3VALW

@ 1U_0603_16V6K
2 GND NC 5
1

2
1

PC170
PC169 3 7
PR201 VREF NC
2

@ 10U_1206_6.3V7K @ 1K_0402_1% 4 VOUT NC 8 1

9
2

TP
VREF_V0.9
@ 0.1U_0402_16V7K
@ 2N7002_SOT23

PR202
1

D
@ 1K_0402_1%

@ 0_0402_5% +0.9VGAP
@ 10U_1206_6.3V7K
PQ39

SUSP 1 2 N48 2
<47,52> SUSP
PR203

PC171

G
2

S
3
1

1
2

PC173

PC172
A A
@ 0.1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/2 Deciphered Date 2006/03/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA1.2V/VGA0.9V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 55 of 60
5 4 3 2 1
 5 4 3 2 1

D D

BATT++ BATT+
Battery Connect/OTP

BATT+
2 1

PL15
FBM-L18-453215-900LMA90T_1812

1
PC174 PC175

2
1000P_0402_50V7K 0.01U_0402_25V7Z

PCN2

1 PR204
BATT+ 100_0402_5%
2 SMD 1 2 EC_SMD_1 <44,45>
SMD
3 SMC 1 2
SMC EC_SMC_1 <44,45> PH1 under CPU botten side :
PR205
Res 4
100_0402_5%
CPU thermal protection at 90 +-3 degree C
TS 2 BATT_TEMP
C
8 G Temp 5 1 BATT_TEMP <44> Recovery at 50 +-3 degree C C
7 6 PR206
G GND 1K_0402_5%

1 2
SUYIN_200045MR006G110ZR +3VALWP
PR207
6.49K_0402_1%
VL
VS

0.1U_0603_25V7K
PJPB1 battery connector

<48,50>
MAINPWON
1
SMART

PC176
PH3
Batte ry: 100K_0603_1%_TH11-4H104FT VL

2
1.BATT+ CPU
2.SMBD

N53
PR208
3.SM BC 470K_0402_1%

1
4.R es 1 2

1
PR209
5. Temp PR210 470K_0402_1%
6.GND 0_0402_5%
PR211

2
8
215K_0603_1% PU17A

1
N52 N54 D
1 2 3

P
+ N55 PQ40
O 1 2
B OTPREF G 2N7002_SOT23 B
1 2 2 -

G
VL PR212 S

3
470K_0402_1% LM393M_SO8

4
1
1

1
PR213

1
PC177 20K_0603_1% PR214
0.22U_0603_16V7K 470K_0402_1%

2
PC178

2
1000P_0402_50V7K VS

8
PU17B
5

P
+
O 7
6 -

G
LM393M_SO8

4
A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 56 of 60
5 4 3 2 1
 1 2 3 4 5

Version change list (P.I.R. List) Page 1 of 1

Item Modify list Reason for change Rev. PG# Modify by
1
Add R579 and R580 for EC PA/PR detec EC team request Rev0.2 P44 6/6 '05

2
BOM del C591 220U_D2 for +VCCP bypass capacitance Cost down Rev0.2 P6 6/6 '05

3
U44 pin5 change from +5VAMP to +5V Design modify Rev0.2 P40 6/6 '05

4
U44 pin3 change from GNDA to GND Design modify Rev0.2 P40 6/6 '05

5
JP21 50pin contact to U31 F25pin support system memory throttling Rev0.2 P13 6/6 '05
1 1

6
JP24 50pin contact to U31 H26pin support system memory throttling Rev0.2 P14 6/6 '05

7
Add D26 Add RTC Battery life Rev0.2 P28 6/6 '05

8
BOM del R51 Change NB strap pin CFG9 to Normal Operation Rev0.2 P11 6/6 '05

9
Change R562 from 649K_0402 to 649_0402_1% BOM error fix LAN can't link Rev0.2 P35 6/6 '05

10
Change R558 from3.3K_0402 to 200_0402_5% BOM error fix LAN can't link Rev0.2 P35 6/6 '05

11
U24 contact to CPUSB# Reserve new card detect input Rev0.2 P44 6/6 '05

12
BOM del R307 no need EC control new card reset Rev0.2 P44 6/6 '05

13
Add R582 @0_0402 Reserve Rev0.2 P35 6/6 '05

14
Cancel U12 pin3 contact to +3VLAN Design modify for LAN function fix LAN can't link Rev0.2 P35 6/6 '05
IFPAB_PLLVDD 、 PLLVDD 、 VID_PLLVDD change from 3.3V to 2 .5V G72 、 G73 power modify
15
Rev0.2 P20 6/6 '05

16
PEX_CFG 0~2 change from 100 to 001 Overridden CFG modify Rev0.2 P26 6/6 '05

17
Add JP34 for mini-PCIE card ME update Rev0.2 P37 6/6 '05

18
Del BOM R359,R349,R361,D9,D10,Q23 For TI 7412 modify request Rev0.2 P32 6/7 '05

19
Change MSBS_SDCMD_SMWE_FIXED# to MSBS_SDCMD_SMWE# For TI 7412 modify request Rev0.2 P32 6/7 '05

20
Change SDCLK_SMRE_FIXED# to SDCLK_SMRE# For TI 7412 modify request Rev0.2 P32 6/7 '05

21
Change SDWP#_SMCE_FIXED# to SDWP#_SMCE# For TI 7412 modify request Rev0.2 P32 6/7 '05
2 2

22
Change SM_RB_FIXED# to SM_RB# For TI 7412 modify request Rev0.2 P32 6/7 '05

23
Change R554,R556,R557,R559 from 10K to 2.2K For TI 7412 modify request Rev0.2 P32 6/7 '05

24
Del R369,Q20,Q9,C446,JP29,JOPEN1,JOPEN2 Cancel TV tuner function Rev0.2 P41 6/7 '05

25
Change LINK_LED100# contact to U41 pin27 Customer request for LAN link LED state Rev0.2 P35 6/8 '05

26
Add R583,R584 75 ohm contact to JP19 and RJ45_GND LAN modify Rev0.2 P35 6/8 '05

27
Swap DQSA0~7/DQSA#0~7 and DQSC0~7/DQSC#0~7 Schematic error modify Rev0.2 P19 6/8 '05

28
Add R585 LID_SW# 10K pull-high reserve LID_SW# floating Rev0.2 P44 6/13 '05

29
U6 pin D23 SLP_S4# contact to U24 pin35 EC need detect SLP_S4# for S4 state Rev0.2 P44 6/13 '05

30
BOM update add R388 DOCK_MICR need pull-high to +CODEC_REFC Rev0.2 P38 6/13 '05

31
Change WL_PRIORITY contact to JP18 pin3 and BT_PRIORITY contact pin define swap Rev0.2 P37 6/14 '05
to JP18 pin5.

32
BOM add R587,R588,R589,R590 0 ohm for NV72 CLK swap pin rework Rev0.2 P19 6/14 '05

33
JP17 footprint update DB1 footprint error, fix can't TV-out Rev0.2 P17 6/14 '05

34
Del R587,R588,R589,R590 0 ohm for NV72 chipset modify Rev0.3 P19 6/17 '05

35
Add R586,R587 UMA or Discrrte PCBA detect Rev0.3 P44 6/27 '05

36
Change R145,R146 from 88.7K to 88.7 ohm BOM error Rev0.3 P18 6/28 '05

37
3 Change C419,C421 form 33P to 22P_0402 improve TV out quility. Rev0.3 P15 6/28 '05 3

38
Add R588 TI recommend(It can avoid the small noise Rev0.3 P32 6/30 '05
form this SPKROUT pin)

39
JP26 footprint update ME change new USB connector Rev0.3 P41 6/30 '05

40
JP3 footprint update ME change new CRT connector Rev0.3 P17

41
Add R589 Dual layout for 9LP306 and SLG8LP462. Rev0.3 P15 7/05 '05

42
BOM add C591 220U_D2 for +VCCP bypass capacitance change 220U location with C595 Rev0.3 P06 7/06 '05

43
BOM del C595 220U_D2 for +VCCP bypass capacitance For cost down Rev0.3 P11 7/06 '05

44
U24(EC) pin91 add ACZ_RST# input fix into xp codec out popo noise Rev0.3 P44 7/06 '05

45
Add C790,C791,C792,C793,C794,C795,C796 100P_0402 For EMI Rev0.3 P42 7/06 '05

46
Add R590,Q46 Switch PCBEEP path Rev0.3 P29,40 7/07 '05

47
Add C797 reserve For EMI Rev0.3 P37 7/07 '05

48
Change R94,R141 to @ and change R96,R142 form @ to 128@ For NVDIA change request Rev0.3 P19 7/08 '05

49
Change R139,Q6 to @ and change R145 form 87_0402 to 124_0402, For NVDIA change request Rev0.3 P18 7/08 '05
R84 from 130_0402 change to 124_0402

50
Add screw hold H23, H24 ME drawing modify Rev0.3 P47 7/08 '05

51
R36 pin1 change contact to ACTLED#,R43 pin1 change contact to Change LAN LED state, Amber LED indicates activity, Rev0.3 P35 7/09 '05
LINK_LED100# Green LED indicates the link is present
4 4

52
Add R591 10K_0402 and Q47 fix mute LED power on turn on Rev0.3 P38 7/11 '05

53
BOM del R383 4.7K pull-high EC program this pin as push-pull output Rev0.3 P42 7/13 '05

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 57 of 60
1 2 3 4 5
 1 2 3 4 5

Version change list (P.I.R. List)

Item Modify list Reason for change Rev. PG# Modify by Page 2 of 3
54
BOM del R101,C161,R467,R88 nvdia recommend Rev0.3 P18 7/13 '05

55
BOM del R78,R468,R111,R117,R63,R475,R477 nvdia recommend Rev0.3 P26 7/13 '05

56
BOM del R108,add R112 nvdia recommend(change to PEX_CFG[2..0]=0x010b) Rev0.3 P26 7/18 '05

57
BOM add C599 add 220U cap for 1.8V power decoupling Rev0.4 P11 8/18 '05

58
BOM add R455 add 51_0402 resister for intel Yonah B0 sightings Rev0.4 P04 8/18 '05
1 1
update

59
Add Q48,Q49,Q50,R593,R594 modify WLED control circuit for OTS:0164892 issue Rev0.4 P37 8/22 '05

60
Del D3 modify WLED control circuit for OTS:0164892 issue Rev0.4 P41 8/22 '05

61
Del R440,R432,Q30 modify WLED control circuit for OTS:0164892 issue Rev0.4 P16 8/22 '05

62
Add R592 add R592 150 ohm for WLED# current limit Rev0.4 P37 8/22 '05

63
JP9 Pin 14 contact to +5VS change SPDIF LED power from +5V to +5VS Rev0.4 P42 8/22 '05

64
Add Q51 Prevent TPS2231 pin2 +3VALW leakage to +3VS Rev0.4 P34 8/29 '05

65
JP5 Pin 25 contact to +3VALW switch board need +3VALW provide lie switch power Rev0.4 P42 8/23 '05

66
BOM change R554/R557/R556 to 100K, change R559 to 22K TI 7412 pull-high recommend Rev0.4 P32 8/23 '05

67
JP3 change new part change CRT conn from top side to bottom side for Rev0.4 P17 8/24 '05
DFX request

68
Del C764,R552,R553, Add D28,change U40 to G993 fan control Fan control circuit change to G993 Rev0.4 P04 8/24 '05

69
BOM del R47 Intel WW31 document update Rev0.4 P11 8/29 '05

70
Add R595/R596/R597/R598/R599 SD card signal add 33 ohm damping resister Rev0.4 P32 8/30 '05

71
Add R81/R77 10K_0402 NV72 A1 chip recommend JTAG_TCK pull-high and Rev0.4 P18 8/29 '05
JTAG_N pull-down

72
Del clock generators difference clock 49.9ohm termination ICS9LP306 clock generators update Rev0.4 P15 8/29 '05

73
2 Change clock generators difference clock 33ohm damping to 10ohm ICS9LP306 clock generators update Rev0.4 P15 8/29 '05 2

74
Change R266 from 475 ohm to 2.4K ohm ICS9LP306 clock generators update Rev0.4 P15 8/29 '05

75
Add D29/D30/D31/D32/D33/D34/D35/D36 SD card signal add diode for Voltage clamp Rev0.4 P32 8/30 '05

76
Move C8/C11/C10/C3/C4/C5/C2/C13/C14/C34/C35/C1 for layout ME update limit area for CPU Rev0.4 P06 8/30 '05

77
Change R591 from 10K ohm to 100 ohm Fix OTS:163350 calgary's mute LED can't display Rev0.4 P38 8/30 '05

78
JP34 pin50 change contact from PM_EXTTS#1 to PM_EXTTS#0 Intel WW31 document update Rev0.4 P14 8/30 '05

79
U31 pinH6 change contact from PM_EXTTS#1 to DPRSLPVR Intel WW31 document update Rev0.4 P07 8/30 '05

80
D26 pin2 change contact from +3VALW to LDO3 Add RTC battery life Rev0.4 P28 8/30 '05

81
BOM change R562 from 649 ohm to 619 ohm and change U12 to new LAN performance modify Rev0.4 P35 8/30 '05
part

82
Add R600 100 ohm and DEL C608 @ HP recommend Rev0.4 P37 8/30 '05

83
Add R601 100 ohm HP recommend Rev0.4 P41 8/30 '05

84
Reserve C810~C821 0.1u cap For EMI Rev0.4 P42 8/30 '05

85
Add L32 and C822 on SPDIF signal For EMI Rev0.4 P42 8/30 '05

86
Add C802 /C803 /C804 /C805 1000P for For EMI Rev0.4 P15 8/30 '05
CLKREQA#/CLKREQB#/CLKREQC#/CLKREQD#

87
U40 pin5,6,7,8 contact to GND schematic update for SI2 fan can't full trun on Rev0.5 P04 10/26 '05
issue
3 3

88
change C599 from 220U to 330U Steady the 1.8V Rev0.5 P11 10/26 '05

89
Add R103 40.2ohm nvdia recommend Rev0.5 P21 10/28 '05

90
change R510,R75,R533,R168 from 120ohm to 499ohm for NV73 only nvdia recommend Rev0.5 P22~25 10/26 '05

91
straps table PEX_CFG[2:0] from 010 to 001 and PCI_DEVID[3:0] nvdia recommend Rev0.5 P26 10/26 '05
NV73M from 1010 to 1011

92
Add C825 15P_0402 for MSCLK_SDCLK_SMELWP# signal For EMI Rev0.5 P32 10/26 '05

93
Add C823 1000P_0402 for +VCC_SD For EMI Rev0.5 P32 10/26 '05

94
Add C824 1000P_0402 for +VCC_SM_XD For EMI Rev0.5 P32 10/26 '05

95
Add C826 1000P_0402 for JP32 pin4 For EMI Rev0.5 P32 10/26 '05

96
change PCM_SPK pull down R588 from 43K to 10K TI recommend Rev0.5 P32 10/26 '05

97
D29,D30,D31,D32 pin1 contact to +VCC_MS schematic update for SI2 MS card can't work issue Rev0.5 P32 10/26 '05

98
Add R607 22ohm and @ C827 10P Reserve Rev0.5 P32 10/26 '05

99
U18 pinG6 contact to +3VS TI recommend Rev0.5 P33 10/26 '05

100
Add @ R606 110ohm Reserve Rev0.5 P35 10/26 '05

101
Change Q46 to U45 analog switch design change Rev0.5 P40 10/26 '05

102
Change U38 pin3,4 form +5VALW to +5V design change Rev0.5 P41 10/26 '05

103
4 Change Q2 from AO3413 to AO3419 Rev0.5 P41 10/26 '05 4

104
Add D38~D45 for KB ESD solution For ESD request Rev0.5 P42 10/26 '05

105
AIR_ACIN change contact to U24 pin81 and add R605 for BID design change Rev0.5 P44 10/26 '05
define, add D37.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 58 of 60
1 2 3 4 5
 1 2 3 4 5

Version change list (P.I.R. List) Page 3 of 3

Item Modify list Reason for change Rev. PG# Modify by
106
Add D46 ESD Rev1.0 P17 12/08 '05

107
RESERVE Q52 / C828 / R608 CONTROL RTC RESET Rev1.0 P28 12/08 '05

108
ADD R612 CIR OUTPUT IS OPEN-DRAIN Rev1.0 P42 12/08 '05

109
CANCEL C811 / C812 AND ADD D47 ESD Rev1.0 P42 12/08 '05

110
CANCEL Q45 AND ADD U48 / C830 FIX ODD CAUSE BOOT LATE ISSUE Rev1.0 P43 12/08 '05
1 1

111
CANCEL D37 AND RESERVE U47 / C51 / R611 IMPROVE EC RESET SIGNAL Rev1.0 P44 12/08 '05

112
RESERVE U46 / C829 / R609 / Q53 / R610 CONTROL WRITE SIGNAL OF FLASH ROM Rev1.0 P45 12/08 '05

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 59 of 60
1 2 3 4 5
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date B.Ver#

1 Solve the oscillate of +3VALWP when plug adapter. 48 Change PC11 from 10U_0805_10V to 0.1U_0603_25V. 2005.06.01
D D

2 Adjust VGA power rail sequence. 54 Add PQ55, PQ56 and PR249 2005.06.21

3 To protect PQ21, because SUSP change to 18.5V from 5V. 52 Add PR253 and change PR114 to 510K_0402_5%. 2005.08.10

4 To save S5 power consumption. 50,48 Add PR254, PR13, PR14, PQ1 and PC8. 2005.08.15
Reserve PR255.

5 To solve EMI issue. 53,49 Add PR117,PR129,PR119,PR138,PC108 and PC119. 2005.08.15

Change PJP16 to PL18 and PR30 from 0_0402 to 2.2_0603.

6 To speed up CP mode response. 49 Change PR32 to 10K; PR35 to 6.8K and PC21 to 2200P. 2005.08.23

7 Reserve capacitor to reduce noise. 49 Reserve PC209. 2005.08.27

8 To speed up C4 return to C0. follow Intel recommend. 53 Change PR141 from 0_0402_5% to 499_0402_1%. 2005.08.29
C C

9 To pull up +1.8V power plan to 1.846V. 51 Change PR89 from 10.2K to 10.5K. 2005.10.01

10 To filter high frequency from AirCard. 55 Add PC210 22P_0402_50V. 2005.11.25

B B

A A

Security Classification Compal Secret Data

Issued Date 2005/03/22 Deciphered Date 2006/03/22 Title
Power PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2841 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 15, 2005 Sheet 60 of 60
5 4 3 2 1