Impresso no Brasil Sujeito a Alteraes Todos os Direi 4806 727 17327 s o d a v r e s e R s o t

DVDR3380/55 DVD-Video Recorder

CLASS 1
LASER PRODUCT
06/2006
a n i g P o d e t n o C
Especi? 2 s a c i n c T s e a c
2 s i e n i a P s o d o a z i l a c o L
4 a n a r u g e S e d s e u r t s n I
6 s a c i n c e M s e u r t s n I
9 e r a w m r i F o a z i l a u t A
1 1 o c o l B m e a m a r g a i D
2 1 s e x e n o C e d a m r g a i D
Painel analgico- Formas de ondas 13
5 1 t u o y a L - o c i g l a n a l e n i a P
6 1 t u o y a L - l a t i g i D l e n i a P
Painel analgico- Entrada-Sada Vdeo 17
Painel analgico- udi ADC/DAC 18
Painel analgico- Processador de udio Multi 19
Painel analgico PSU e Interfaces 20
1 2 s t u o y a L - o c i g l a n a l e n i a P
3 2 y a l p s i D - l a t n o r F l e n i a P
Painel Frontal Entrada de udio/vdeo 24
5 2 t u o y a L l a t n o r F l e n i a P
6 2 y b d n a t S l a t n o r F l e n i a P
Painel Digital- Processador Traseiro 27
8 2 a i r m e M - l a t i g i D l e n i a P
Painel Digital- Camada Fisca 29
Painel Digital- Processador Entrada de Vdeo 30
1 3 s e c a f r e t n I - l a t i g i D l e n i a P
2 3 t u o y a L
Unidade Fonte de Alimentao 34
5 3 C I e d o i r c s e d e o t i u c r i C
6 5 a d i d o l p x E a t s i V
2 DVDR3380
1. Especificao Tcnica e Conexes
1.1 Localizao dos Paineis
1.2 Geral:
Alimentao : 127V /37
: 110V - 240V /55
: 220V - 240V /75/97
Consumo : 25 W (tipico)
Consumo Standby : < 3 W
1.3 RF Tuner
Teste equipamento: Fluke 54200 TV Sinal gerado
Teste streams: Philips Standard teste padro
1.3.1 Sistema
NTSC-M
1.3.2 RF - Loop Through:
Relao Frequncia : 45 - 860 MHz
Ganho: (Entrada ANT - Sada ANT ): -6dB
Interferncia de rdio / entrada max.
tenso,em 75, 3 mtodo tom (
-40dB) : Sem limite
1.3.3 Modulador:
Modulao de Vdeo : 80%15%
Resposta de Frequncia : 0 3dB, 0...4.2MH
Modulao de udio tom 1kHz : 12kHz, tol. 4kHz
1.3.4 Receiver:
PLL sintonia comAFC para melhor recepo
Relao de Frequncia : 55 - 805 MHz
Sensitividade em 40 dB S/N : 60dBV em 75
(video unweighted)
1.3.5 Desempenho de Vdeo:
Canal 25 / 503,25 MHz,
Teste padro: standard teste padro.
Nvel RF 74dBV
Medio na Sada de Cinch
Resposta de Frequncia : 0.1 - 3.58 MHz -1 3dB
1.3.6 Desempenho de udio:
Desempenho Analgico de udio - HiFi:
Resposta de Frequncia em Cinch (L+R)
sada : 100 Hz - 10 kHz / 0
3dB
S/N de acordo com DIN 45405, 7, 1967
e PHILIPS standard teste padro
sinal de vdeo : 45dB
Distoro de harmnia (1 kHz, 25
kHz deviation) : 1.5%
1.3.7 Sintonia
Procura de Sintonia Automtica
Tempo de scanning sem antena : typ. 3 min.
Nvel stop (vision carrier) : 37dBV
Sintonia mxima durante erro de
operao : 100 kHz
Sintonia Manual
Seleo manual no modo STORE
Painel Digital
Motor Bsico
Painel Analgico
Painel PSU
Painel Frontal
(Atrs do Painel Frontal)
3 DVDR3380
1.4 Entradas e Sada Analgicas
1.4.1 Entrada Externa (Traseira)
Video - Y/C (Hosiden)
de acordo IEC 933-5
Sobrepor nvel DCno pino 4 (carga 100k):
< 2.4V detectado como taxa de aspecto 4:3
> 3.5V detectado como taxa de aspecto 16:9
Tenso de entrada Y : 1 Vpp 3dB
Impedncia de entrada Y : 75
Tenso de entrada C : burst 300 mVpp 3dB
Impedncia de entrada C : 75
Video Cinch
Tenso de entrada : 1 Vpp 3dB
Impedncia de entrada : 75
Audio Cinch
Tenso de entrada : 2.2 Vrms max.
Impedncia de entrada : > 10k
1.4.2 Conectores de Entrada Frontal Audio/Video
Audio
Tenso de entrada : 2 Vrms max.
Impedncia de entrada : > 10k
Video - Cinch
Tenso de entrada : 1 Vpp 3dB
Impedncia de entrada : 75
Video - YC (Hosiden)
de acordo IEC 933-5
Sobrepor nvel DCno pino 4 (carga 100 k):
< 2.4V detectado como taxa de aspecto 4:3
> 3.5V detectado como taxa de aspecto 16:9
Tenso de entrada Y : 1 Vpp 3dB
Impedncia de entrada Y : 75
Tenso de entrada C : burst 300 mVpp 3dB
Impedncia de entrada C : 75
1.4.3 Sada 1
Component Video Cinch Y/Pb/Pr / Progressive Scan
de acordo EIO-770-1-A, EIA-770-2-A
Audio - Cinch
Tenso de sada : 2 Vrms max
Impedncia de sada : < 2k
1.4.4 Sada 2
Video - Y/C (Hosiden)
Tenso de sada Y : 1 Vpp 3dB
C : burst 300 mVpp 1dB
Impedncia de sada Y, C : 75
Video - Cinch
Tenso de sada : 1 Vpp 1dB
Impedncia de sada : 75
Audio - Cinch
Tenso de sada : 2 Vrms max
Impedncia de sada : < 1k
1.5 Desempenho de Vdeo DVD
Todas as sada carregada com 75 Ohm
SNR medio total da largura da faixa sem compensao.
1.5.1 Todas as Sadas
SNR : > 48dB
Largura da faixa : 4.2 MHz - 3dB
1.6 Desempenho do udio do CD
1.6.1 Sada Traseira Cinch
Tenso de sada do modo canal 2 : 2Vrms 1dB
Canal sem balano (1kHz) : <1dB
Crosstalk 1kHz : >100dB
Crosstalk 20Hz-20kHz : >87dB
Resp. de frequncia 20Hz-20kHz : 0.2dB max
Taxa sinal/rudo (A-compensado) : >90dB
Relao dinmica 1kHz : >83dB
Distoro e rudo 1kHz : >83dB
Distoro e rudo 20Hz-20kHz : >75dB
Distoro intermodulao : >70dB
Mute : >95dB
Atenuao da banda de sada: : >40dB acima de 30kHz
1.7 Sada Digital
1.7.1 Coaxial
CDDA / LPCM : de acordo IEC60958
MPEG1, MPEG2, AC3 audio : de acordoIEC61937
DTS : de acordo IEC61937
correo 1
1.8 Entrada de Vdeo Digital (IEEE 1394)
1.8.1 Aplicaes Standards
De acordo com a implementao:
IEEE Std 1394-1995
IEC 61883 - Part 1
IEC 61883 - Part 2 SD-DVCR (02-01-1997)
Especificaes do uso digital usando VCR de 6.3 mm
fita magntica - dec. 1994
Acordo de conexo mecnica:
Anexo A do 61883-1
1.9 Dimenses e Peso
Tamanho do p : 5.5mm
Aparato de bandeja fechada : WxDxH:360x43x322mm
Peso em embalagem : 3 kg
Peso com embalagem : 4 kg
1.10 Sada Energia Laser & Comprimento da Onda
1.10.1 DVD
Sada de energia durante leitura : 1.0mW
Sada de energia durante escrita : 30mW
Comprimento da onda : 650nm
1.10.2 CD
Sada de energia : 1.0mW
Comprimento da onda : 780nm
1.11 Velocidade da escrita
Tipo do Disco(Funo) Veloc. Rotativo Disco
Veloc. Leitura CD 7X CAV (25Hz)
Veloc. Leitura DVD 4X CAV (40Hz)
Veloc. Escrita DVD+RW 2.4X ZCAV
Veloc. Escrita DVD+R 2.4X ZCAV
4 DVDR3380
2.1 Instrues de Segurana
2.1.1 Segurana geral
Os regulamentos de segurana requerem que durante um reparo:
Conecte a unidade aos cabos principais um transformador
de isolamento.
Recoloque os componentes de segurana, indicados pelo sm-
bolo , somente pelos componentes idnticos aos originais.
Qualquer outra substituio de componente (com exceo
do tipo original) pode aumentar o risco de fogo ou choque
eltrico.
Os regulamentos de segurana requerem que depois de um
reparo, voc deve retornar a unidade na sua condio original.
Preste ateno, particularmente, nos seguintes pontos:
Distribua os os e cabos corretamente, e repare-os com os
acampamentos montados do cabo.
Verique a isolao da conduo dos os principais para danos
externos.
Verique a resistncia eltrica DC entre os os dos plugs princi-
pais e o lado secundrio:
1. Desplugue os cabos principais, e conecte um o entre os
dois pinos do plugue principal.
2. Ajuste os os do interruptor principal na posio ON
(mantenha o cabo dos os principais plugados!)
3. Mea o valor da resistncia entre os os dos plugues princi-
pais e do painel frontal, controle e boto de chassis.
4. O reparo ou a unidade correta quando a resistncia est
sendo medida de menos de 1 M.
5. Verique isto, antes de retornar a unidade ao cliente / usu-
rio (ref. UL- padro no. 1492).
6. Mude a unidade para OFF, e remova o o entre os dois
pinos do plugue principal.
2.1.2 Segurana de laser
Essa unidade emprega um laser. Somente pessoal de servio
qualicado pode remover a tampa, ou tente prestar servios de
manuteno nesse dispositivo (devido a possvel ferimento nos
olhos).
Unidade do dispositivo de Laser
Tipo: laser semi-condutor GaAlAs
Comprimento de onda: 650 nm (DVD)
780nm (VCD/CD)
Energia de sada: 20 mW (DVD+RW writing)
: 0.8 mW (leitura de DVD)
: 0.3 mW (leitura de VDC/CD)
Divergncia do feixe: 60 graus
Figura 2-1
Nota: o uso dos controles ou do ajuste ou o desempenho do pro-
cedimento excepo daqueles especicado nisto, podem resul-
tar na exposio perigosa da radiao. Evite a exposio direta ao
feixe.
2.2 Cuidados
2.2.1 Geral
Todos os ICs e muitos outros semicondutores so suscet-
veis as descargas eletrostticas (ESD, ") a manipulao
descuidada durante o reparo pode reduzir a vida drasticamente.
Certique-se que durante o reparo, voc est no mesmo
potencial que a massa do aparelho por uma pulseira com resis-
tncia. Mantenha os componentes e ferramentas na mesma
potncia.
Equipamentos de proteo disponveis ESD:
- Kit completo ESD3 (pequenas TABLEMAT, WRISTBAND, caixa
de conexo, cabo de extenso e o terra) 4822 310 10671.
- Vericador Wristband 4822 344 13999
Tenha cuidado durante a medida da seo viva da tenso. O
lado primrio da fonte de energia (pos. 105), incluindo o dissi-
pador de calor, carrega a tenso viva dos os principais quando
voc conecta o aparelho nos os principais (mesmo quando o
aparelho est desligado!). possvel tocar nas trilhas e nos
componentes de cobre nesta rea preliminar desprotegida,
quando voc prestar servios de manuteno no aparelho.
O pessoal de servio deve tomar precaues para evitar tocar
esta rea ou componentes desta rea. Um lightning stroke e
uma listra marcada impressa no painel de ao, indica o lado
preliminar da fonte de alimentao.
Nunca substitua mdulos ou componentes enquanto a unidade
estiver ligada.
2.2.2 Laser
O uso de instrumentos pticos com este produto ir aumentar o
perigo de atingir o olho.
Apenas o pessoal de servio qualicado pode remover a tampa
ou tentar prestar servio de manuteno a esse dispositivo,
devido a possvel ferimento nos olhos.
A manipulao do reparo deve ocorrer tanto quanto possvel
com um disco carregado dentro do aparelho
O texto abaixo colocado dentro da unidade, no protetor de
tampa do laser:
Figura 2-2
2.2.3 Notas
Dolby
Manufaturado sob licena do Dolby Laboratories. "Dolby", "Pro
Logic" e o smbolo duplo-D so marcas resgistradas do Laborat
rio Dolby.
1992-1997 Laboratrio Dolby, Inc. Todos os direitos reservados.

Figura 2-3
Trusurround
TRUSURROUND, SRS e o smbolo (g. 2-4) so marcas registra
das do Laboratrio SRS, Inc. A tecnologia TRUSURROUND
manufaturada sob licen do laboratrio SRS, Inc.
Figura 2-4
CLASS 1
LASER PRODUCT
CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRLING VED BNING UNDG UDSTTELSE FOR STRLING
ADVARSEL SYNLIG OG USYNLIG LASERSTRLING NR DEKSEL PNES UNNG EKSPONERING FOR STRLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRLNING NR DENNA DEL R PPNAD BETRAKTA EJ STRLEN
VARO! AVATTAESSA OLET ALTTIINA NKYVLLE JA NKYMTTMLLE LASER STEILYLLE. L KATSO STEESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEFFNET NICHT DEM STRAHLAUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS DOUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
2. Informaes de segurana, Notas Gerais & Exigncia de Sem Clumbo
5 DVDR3380
Vdeo Plus
"Video Plus+" e "Plus Code" so marcas registradas do Gemstar
Development Corporation. O sistema "Video Plus+" fabricado
sob a licena da Gemstar Development Corporation.
Figura 2-5
Microvision
Este produto incorpora tecnolgia de proteo de cpia que
o metdo de proteo exigido da certicado U.S de patentes e
outros proprietrios intelectuais da prpria Macrovision Corpora-
tion.
O uso desta tecnolgia de proteo de cpia deve ser autorizada
pela Macrovision Corporation e permitido para casa e outros
limites somente com autorizao da Macrovision Corporation. A
desmontagem probida.
2.3 Solda sem chumbo
A Philips CE est produzindo aparelhos sem chumbo (PBF) de
1.1.2005 para frente.
Identicao: A linha principal de um tipo de prato d um nmero
de srie de 14 dgitos. Os dgitos 5 e 6 referem-se ao ano de
produo, os dgitos 7 e 8 referem-se semana de produo (no
exemplo abaixo, 1991 na semana 18).
Apesar do logo especial sem chumbo (que nem sempre indi-
cado), ONE MUST TREAT todos os aparelhos de sua data pra
frente de acordo com as regras descritas abaixo.

Com a tecnologia sem chumbo, algumas regras devem ser respei-
tadas pelo workshop durante o reparo:
Use apenas ferramentas de solda sem chumbo Philips SAC305
com o cdigo de pedido 0622 149 00106. Se a pasta de solda sem
chumbo necessria, por favor contate o fabricante do equipa-
mento de solda. No geral, o uso de pasta de solda em workshops
deve ser evitada pois a pasta no facilmente manuseada nem
armazenada.
Use apenas ferramentas de solda aplicveis para ferramenta de
solda sem chumbo. A ferramenta de solda deve:
- Alcanar na ponta da ferramenta a temperatura de pelo menos
400
o
- Estabilizar o ajuste de temperatura na ponta da solda.
- Troque a ponta de solda para diferentes aplicaes.
Ajuste sua ferramenta de solda para que a temperatura de 360
o

- 380
o
seja alcanada e estabilizada na juno da solda. O tempo
de aquecimento da juno da solda no deve exceder ~ 4s. Evite
temperaturas acima de 400
o
, ou ento "wear-out" das pontas
ir aumentar drasticamente e o uxo- uido ser destrudo. Para
evitar "wear-out" de pontas, desligue o equipamento no usado
ou reduza a temperatura.
Misturar parte/ ferramenta de solda sem chumbo com partes/
ferramentas de solda com chumbo possvel mas a PHILIPS
recomenda que se evite isso. Se no puder ser evitado, cuidado-
samente limpe a solda da antiga ferramenta e re-solde com uma
nova ferramenta.
Use apenas peas originais listadas no Manual de Servio. Mate-
riais padro no listados (comodities) devem ser comprados em
companhias externas.
Informaes especiais para ICs BGA sem chumbo: estes ICs
sero entregues no chamado pacote a seco para proteger o IC
contra umidade. Este pacote s pode ser aberto pouco antes de
ser usado (soldado). Ou ento o corpo do IC ca molhado dentro
e durante o tempo de aquecimento a estrutura do IC ser destru-
da por causa da alta temperatura dentro do corpo. Se o pacote for
aberto antes do uso,, o IC deve ser esquentado por algumas horas
(em torno de 90
o
) Para secar (pense na proteo ESD!). NO RE-
USE BGAs de modo algum!
Para produtos produzidos ante de 1.1.2005, contendo ferramenta
de solda com chumbo e componentes, toda a lista de peas ser
avaliada at o m do perodo de servio. Para reparo destes
aparelhos, nada muda.
No website www. atyourservice.ce.Philips.com voc encontra mais
informaes sobe:
(De) Solda BGA (+ instrues de operao bancria).
Pers de aquecimento dos BGAs e outros ICs usados em apare-
lhos Philips.
Voc encontra estas e mais informaes tcnicas em magazine,
captulo workshop news.
Para questes adicionais, por favor, contate o help desk local.
3. Instruo de Uso
Veja o Manual no GIP.
6 DVDR3380
4.2 Desmontagem do Motor Bsico (Drive D4.5)
1) Remova os 7 parafusos para soltar a tampa Superior 240 .
2) Remova os parafusos para soltar o painel Motor Bsico
1001 como mostra a figura 4-3.
Figura 4-3: Solte os parafusos do Motor Bsico
3) Remova os 4 parafusos para soltar a placa de proteo do
Painel Motor Bsico.
4) A posio de Servio do Painel de Motor Bsico como mostra a fig. 4-4
aps remover a placa de proteo PCBA.
Figura 4-4: Posio de Servio do Motor Bsico
Nota : Os nmeros das posies refere-se a Vista Explodida.
4.1 Desmontagem da Tampa da Bandeja DVD
Manualmente
1) Insira uma chave de fenda no vo na parte inferior do
aparelho e empurre na direo como mostra a figura 4-1
para destravar antes de retirar o carregador 1001.
Figura 4-1: Destravar o Carregador
2) Remova a Tampa da Bandeja 110 como mostra a Figura 4-2 .
Figura 4-2: Remova a Tampa da Bandeja
4. Instrues Mecnicas
Folha
Isolante
7 DVDR3380
4.3 Desmontagem do Painel Digital
1) Remova os 4 parafusos para soltar o Painel Digital 1004
como mostra a Figura 4-5.
Figura4-5: Remova o Painel Digital Board
2) Psoio de Servio do Painel Digital Board dado na Figura 4-6.
Figura 4-6: Psio de Servio do Painel Digital
4.4 Desmontagem do Painel Analgico
1) Solte os parafusos do painel traseiro no Painel Analgico.
Remova os parafusos do Painel Analgico como mostra a
Figura 4-7.
Figura 4-7: Remova os parafusos do Painel Analgico
2) A Posio de Servio do Painel Analgico dado na Fig.4-8.
Figura 4-8: Posio de Servio do Painel Analgico
Folha
Isolante
Parafusos
(atrs do cabo FFC )
8 DVDR3380
4.5 Desmontagem do Painel PSU
1) Remova os 3 parafusos e solte o Painel PSU
1007 como mostra a Figura 4 9 .
2) Posio de Servio do Painel PSU dado na Figura 4-10.
Figura 4-9: Solte os parafusos do Paine PSU
Figura 4-10: Posio de Servio de PSU
9 DVDR3380
5. Atualizando Firmware
5.1 Atualizando Firmware
A. Preparao para atualizaro firmware:
1. Unzip o arquivo zip
2. Cpie os arquivos diferentes da pasta para gravar separado em um CD-R/CDRW .
3. Inicie o software da Gravao do CD e crie um projeto novo CD (disco de dados) com as funes seguintes:
Sistema de arquivo: Joliet
Formato: MODE 2: CDROM XA
Modo de gravao: Seo Simples (Faixa nica), CD Finalizado
Nota: Um nome de arquivo longo preciso para preparao da atualizao do disco.
4. Coloque o arquivo no diretrio raiz do novo projeto CD.
5. Grave os dados em um CDRs ou CD-RWs virgem
B. Procedimento para aplicar a atualizao do Drive:
1. Abra a bandeja e carregue o CDROM Atualizado com o Arquivo Atualizado do Drive
2. A bandeja fechada e o aparelho mostra:
DRV UPG
3. O OSD mostra
Loader Software Upgrade Disc detected . Select OK to start upgrading or CANCEL to exit.
4. Clique na tecla OK.
5. O aparelho mostra:
DRIVE UPGRADING
Com o display OSD
Upgrading Software . Please Wait . Do not switch off the power.
O processo inteiro leva menos de 5 minutos.
Nota: No pressione nenhuma tecla ou interrompa a alimentao durante o processo de atualizao, desta forma
o aparelho apresentar defeito.
6. Quando a atualizao estiver completa a bandeja abrir automaticamente e o aparelho mostrar:
Loader Upgrade process has completed successfully . Press <OK> to reboot system.
7. A bandeja abre e mostrar:
DRV OK
8. Pressione <OK> e o aparelho muda para standby .
C. Procedimento para aplicar a atualizao do software:
1. Abra a bandeja e carregue o CDROM de Atualizao com Arquivo Atualizado do Software.
2. A bandeja fecha e o aparelho mostrar:
Upgrading SW
3. A OSD mostrar
Software Upgrade Disc detected . Select OK to start upgrading or CANCEL to exit .
4. Clique na tecla OK .
5. O aparelho mostrar:
Upgrading SW
e o OSD mostrar
Upgrading Software . Please Wait . Do not switch off the power.
O processo inteiro leva menos de 5 minutos.
Nota: No pressione nenhuma tecla ou interrompa a alimentao durante o processo de atualizao, desta forma
o aparelho apresentar defeito.
10 DVDR3380
6. Quando a atualizao estiver completa a bandeja abrir automaticamente e o aparelho mostrar:
System is successfully upgraded . Remove disc from tray and reset system.
7. A bandeja abre e o aparelho mostrar:
SW DONE
a bandeja abre automaticamente para o usurio remover o CD-ROM.
8. Pressione <OK> e mude para standby .
D. Como ler a verso firmware para confirmar a atualizao:
1. Ligue o aparelho
2. Assegure-se que nenhum disco foi inserido para carregar, caso haja, abra a bandeja remova o disco e feche a bandeja.
3. Pressione <0> <0> <0> <9> seguidamente.
4. Pressione a tecla <OK>
5. O TV conectado ao aparelho mostrar:
DVDR3380_AP_V03_07,Region: 3, Drive 45.04.05.04
Build 0091 Apr 19 2006 , 10:08:29 Stroke: 97
11 DVDR3380
DIAGRAMA EM BLOCO
Front Keyboards
CVBS-YUV-Y/C
AUDO PCM 2S
AUD_BCK
AUD_WCK
AUD_DA(0)
AUD_SPDFO
AUD_MUTE
AUDO ENCODER 2S
YUV-YC-CVBS
ANALOG AUDO / VDEO
D_CVBS
D_C
D_Y
D_V
D_Y1
D_U
A_VR
A_UB
A_YG
TUNER
NPUT/OUTPUT
PROCESSNG &
SOURCE
SELECTON
ANALOG BOARD
AR
AL
CVBS
5
1
3
1202
1207
1205
1405
1536
CVBS
AUDO R
AUDO L
AR
AL
CVBSFN
ADC
7
9
5
20
24
22
26
28
30
SDRAM
FLASH
VDEO NPUT
PROCESSNG
DGTAL AUDO
RS232
SERVCE
1502
1521
DG.VDEO
2
3
5
16
7
18
5
3
1
S-VDEO
CVBS
RF N - ANTENNA
RF OUT - TV
PHY
DGTAL AUDO OUT
DOMNO DMN-8602
MPEG 2, AC3 CODEC
EEPROM
DGTAL AUDO
2C
AUD_MCK
BUFFER
DAC
AUD_DATA0[0]
AUD_WCKO
AUD_BCKO
14
12
11
9
AUD_MCK0
ANALOG VDEO
1103
Supply Lines
N5 D
N
G
V5 D
N
G
D
N
G
V21
D
N
G
3
V3
3
V3
3
V3
3
V3
1106
1 12
V5 -
D
N
G
N
O
V5+
D
N
G
D
N
G
V21+
D
N
G
3
V3+
3
V3+
3
V3+
3
V3+ 1501
1 12
CONTROL UNT SLAVE
MCROPROCESSOR
CONTROL LNES
CONTROL LNES SCK,D_FM,D_HOST,RDY_FM,ATN_FM,HOST_RESET
DE BUS DE BUS
1107
A/V OUT
DIGITAL BOARD - DIMENSION
DVD+RW ENGINE D4.5 OPEN
TRAY CONTROL
SERVO
READ
WRTE
DSC
40
LASER
1600-1
V5+
D
N
G
D
N
G
V 21+
1600-2
1571
AUDO L/R
CONTROL LNES
1105
(LOOPTHRU)
AUD_DATAO[1:3] *
* Where AUD_DATA[1:3] refers to pinout 20,21,23 respectively
1101
1102
Power Supply Unit
MANS
AC
1552
1109
DV_in
Y
B
T
S
V
2
1
D
N
G
Y
B
T
S
V
5
3
V
3
D
N
G
Y
B
T
S
V
2
1
D
N
G
Y
B
T
S
V
5
3
V
3
D
N
G
Y
B
T
S
V
2
1
D
N
G
L
A
F
P
D
N
G
Y
B
T
S
N
5
Y
B
T
S
N
G
V
Y
B
T
S
V
2
1
D
N
G
L
A
F
P
D
N
G
Y
B
T
S
N
5
Y
B
T
S
N
G
V
6 1
1 5
1513
1201
20
24
22
26
28
30
N-EXT
OUT1
AUDO L/R
Y
Pb
Pr
CVBS
AUDO L/R
12 DVDR3380
DIAGRAMA DE CONEXES
Ana|og board
Va|rs
vl Z.rr
1 VAlN3_L
2 VAlN3_N
2p
8002
P3A 80 rr P3A
Pl 2rr Pl 2rr
1 v0N_3T8Y 1 v0N_3T8Y
2 5N_3T8Y 2 5N_3T8Y
3 0N0_A 3 0N0_A
1 P0wER_FAlL 1 lPFAlL
5 0N0_A 5 0N0_A
12vA_3T8Y 12vA_3T8Y
6p 6p
8003
P3 3T8Y 80 rr P3 3T8Y
vl 3.9rr 30N 3.9rr
1 12v_3T8Y 1 12v_3T8Y
2 0N0_0 2 0N0_0
3 5_3T8Y 3 5_3T8Y
1 3v3_3T8Y 1 3v3_3T8Y
5 0N0_0 5 0N0_0
5p 5p
8008
FAv FC0V C0V Al0 vl0 0l0_P3 P3 000 220 rr
FFC 1rr FFC 1rr FFC 1rr FFC 1rr FFC 1rr Pl 2rr El 2.5rr
FAuRlN 11 12v3T8Y 1Z 0N0 18 0N0 30 08_P8 1 3v30 1 12vl
5 0N0 13 v0N_3T8Y 1 3CL 1Z A8CK 29 0N0 2 3v30 2 0N0
1 FAuLlN 12 PwRFAlL 15 30A 1 AwCK 28 00_Y 3 3v30 3 0N0
3 0N0 11 PwRCTL 11 R0Y_FV 15 0N0 2Z 0N0 1 3v30 1 5vl
2 FCv83lN 10 5v3T8Y 13 0_FV 11 A0A 2 0R_PR 5 0N0
1 0N0 9 NC 12 0_l03T 13 0N0 25 0N0 12v0
8 l03TR3T 11 0N0 12 AVCK 21 0Y Z 0N0
Z ATN_FV 10 FP3CK 11 0N0 23 0N0 8 0N0
R0Y_FV 9 ATN_FV 10 08CK 22 0C 9 5v0
5 0N0 8 l03TR3T 9 0N0 21 0N0 10 l00_0N
1 0_l03T Z AlN3w0 8 0wCK 20 0Cv83 11 0N0
3 0_FV AlN3w1 Z 00A 19 0N0 12 NC
2 FP3CK 5 F83 0N0 18 TuCv83
1 0N0 1 83C2_1 5 0VCK 1Z 0N0
3 83C2_2 1 0N0 1 RCv83lN
2 TuN0ET1 3 3P0lF0 15 0N0
1 TuN0ET0 2 0N0 11 RYlN
1 AVuTE 13 0N0
12 RClN
11 0N0
10 FCv83lN
9 FClN
8 0N0
Z FYlN
0N0
5 AR_PR
1 0N0
3 A8_P8
2 0N0
1 A0_Y
6p 14p 17p 18p 30p 12p 4p
8010 8011 800Z 8005 800 8001
280 rr 280 rr 180 rr 110 rr 110 rr 180 rr
Frt r 0gt r 000
1202 1109 1551 153 1521 1501 15Z1 8009
FAv FC0V C0V Al0 vl01 / vl02 0l0_P3 000_l0E 220 rr 000_l0E
FFC 1rr FFC 1rr FFC 1rr FFC 1rr FFC 1rr Pl 2rr l0E 2.51rr l0E 2.51rr
1 FAuRlN 1 12v3T8Y 1 0N0 1 0N0 1 8Po0 1 3v3 1 R3TN 21 0VAR0 1 R3TN 21 0VAR0
2 0N0 2 v0N3T8Y 2 3CL 2 8CKl 2 0N0 2 3v3 2 0N0 22 0N0 2 0N0 22 0N0
3 FAuLlN 3 PwRFAlL 3 30A 3 wCKl 3 0Y0 3 3v3 3 00[Z| 23 0l0wN 3 00[Z| 23 0l0wN
1 0N0 1 PwC0NTR0L 1 R0Y_FV 1 0N0 1 0N0 1 3v3 1 00[8| 21 0N0 1 00[8| 21 0N0
5 FCv83lN 5 5v3T8Y 5 0_FV 5 0Al 5 RPr0 5 0N0 5 00[| 25 0l0RN 5 00[| 25 0l0RN
0N0 0N0 0_l03T 0N0 0N0 12v 00[9| 2 0N0 00[9| 2 0N0
Z l03TR3T Z 0N0 Z VCKl Z 3Yo Z 0N0 Z 00[5| 2Z l0R0Y Z 00[5| 2Z l0R0Y
8 ATN_FV 8 FP3CK 8 0N0 8 0N0 8 0N0 8 00[10| 28 C3EL 8 00[10| 28 C3EL
9 R0Y_FV 9 ATN_FV 9 8CK0 9 3C0 9 5v 9 00[1| 29 0VACKN 9 00[1| 29 0VACKN
10 0N0 10 l03TR3T# 10 0N0 10 0N0 10 NC 10 00[11| 30 0N0 10 00[11| 30 0N0
11 0_l03T 11 AlN3EL0 11 wCK0 11 Cv830 11 0N0 11 00[3| 31 lNTR0 11 00[3| 31 lNTR0
12 0_FV 12 AlN3EL1 12 0A00 12 0N0 12 NC 12 00[12| 32 l0C31 12 00[12| 32 l0C31
13 3CK 13 F8lN 13 0N0 13 Cv83_Tu 13 00[2| 33 0A1 13 00[2| 33 0A1
11 0N0 11 83C2_1 11 VCK0 11 0N0 11 00[13| 31 P0lA0N 11 00[13| 31 P0lA0N
15 83C2_2 15 0N0 15 Cv83_RE 15 00[1| 35 0A0 15 00[1| 35 0A0
1 TuN0ET1 1 3P0lF0 1 0N0 1 00[11| 3 0A2 1 00[11| 3 0A2
1Z TuN0ET0 1Z 0N0 1Z 3Y_RE 1Z 00[0| 3Z C30N 1Z 00[0| 3Z C30N
18 VuTE 18 0N0 18 00[15| 38 C31N 18 00[15| 38 C31N
19 3C_RE 19 0N0 39 0A3PN 19 0N0 39 0A3PN
20 0N0 20 Keyp|r 10 0N0 20 Keyp|r 10 0N0
21 Cv83_FR 40p 40p
22 3C_FR
23 0N0
21 3Y_FR
25 0N0
2 RPrl
2Z 0N0
28 8Pol
29 0N0
30 0Yl
9p 14p 17p 18p 30p 12p 40p 40p
P3 l00
l0E_P3u
1 12vE
2 0N0
3 0N0
1 5vE
4p
8012
0010 1201 1513
3T8Y lEEE1391 100 rr lEEE1391
0lPVATE Pl 2rr Pl 2rr
1 KEY1 1 TP8N 1 TP8-
2 KEY2 2 TP8 2 TP8
3 0N0 3 0N0
1 TPAN 1 TPA-
5 TPA 5 TPA
0N0 0N0
4p 6p 6p
8100, core W|l| lrorl pare|
180 rr
ty r
101
3T8Y
0lPVATE
1 KEY1
2 KEY2
4p
13 DVDR3380
PAINEL ANALGICO - FORMAS DE ONDAS
I143 Y_OUT I142 C_OUT I144 CVBS_OUT I137 D_C
I138 D_Y I139 D_VR I140 D_YG I141 D_UB
I213 AIA_R_RE1/AIA_R_RE2 I212/I214 I241 ALDAC (PIN 18 7206) I242 (PIN 15 7206)
I150 DIGITAL_OUT 7304MSP XTAL_IN 7304MSP XTAL_OUT
14 DVDR3380
PAINEL ANALGICO - FORMAS DE ONDAS
AUD_BCKI T537 AUD_BCKO T541 AUD_DAI(0) T539 AUD_DAO(0) T543
AUD_MCKI T540 AUD_MCKO T544 AUD_WCKI T538 AUD_WCKO T542
VOA_RPr T521 VOA_BPb T518
VOA_CVBS T524
VOA_GY T520
VOA_SC T523
VOA_SY T522
15 DVDR3380
PAINEL ANALGICO- LAYOUT
3380_APAC_TPOINT.pdf 2006-05-03
16 DVDR3380
PAINEL DIGITAL- LAYOUT
Digital_Layout_3139_243_34432_pg3.pdf 2006-05-03
17 DVDR3380
ESQUEMA ELTRICO- PAINEL ANALGICO - ENTRADA/SADA DE VDEO
F
G
H
I
1111-AD2
1111-BC2
1111-CE2
1112F2
1113G2
1114F2
1121I6
2141 H9
2142 H11
2143 I11
2151 C12
2152 D12
2153 D12
2154 G12
2155 I12
2156 I12
3111 D4
3112 E4
1131-2 F13
arYC in
Pb out-Blue
1132-CD13
%
1
1132-B B13
Front A/Vin
1132-A C13
1122 I6
1131-1 H13
D
E
F
G
H
I
A
B
C
D
E
11
#8:Usedfor3380and3390
9 10 1 2 3 4 5 6 7 8
2139 F11
2140 G9
4113 G5
4114 G5
4115 E5
4116 G5
4117 H5
4118 H5
4119 H5
4121 B11
4122 D11
4123 E9
4124 F11
3114 I4
3115 I4
CVBSout
#0:Notused
%
1
3113 E4
B
C
3122B8
3123B9
3124C11
3125D10
3126D10
3127E9
3128E8
3129E9
3130F10
3131F10
3132F11
2137E9
2136E9
2138F11
2134D11
2133C11
2135D11
2132 C10
4111 C5
4112 D5
I141H8
I142D12
I143D12
I144B12
I145H13
I146F13
I147H13
I148H13
I149F2
I150F13
%
1
3116I4
3121B9
I112D3
I113E3
I11F3
I11F3
I116G3
I117G3
I118G3
I119G3
I120H2
I121H2
I123H2
6112E
101B
6111E3
RearCVBS in
%
1
102B6
12G9
126H11
I139H8
I10H8
Y
I12H2
I12H6
I126H6
I127H6
I128H6
I129H6
I130H7
I131H7
I132H7
Prout -Red
I103B7
I111C2
I11E13
C
%
1
I136H7
I13H7
%
1
I138H8
I13H7
I133H7
Y out -Green
C
6121D12
6122D12
6123D11
612D12
7111B9
7112C10
7113E9
711F10
711G9
7116H10
I102B
3133G9
%
1
Tunerin
313H9
313H8
3138I11
3137H10
3136I10
I137H7
1
1 2 3 6 7 8 9 10
#4:Usedfor3400
6113 E3
611 E
11 12
from /toDigital Board
Videi/
Digital out-Black
Y/Cout
%
1
Rear YUV in
Y
12 13
2101B
2102B
2103B6
210B6
2111C3
2112E3
2113E3
211E
211I3
2116I3
2117I3
2121C
2131B10
1
A
13
%
1
GND
115
2
1
1
2
p
0
0
1
2
1
1
3
R
5
7
GND
GND
R
0
6
1
4
3
1
3
9
3
1
5V 5V_V
5101
10u
5V_V
6
3
1
3
R
0
6
1
100n
2131
2132
100n
2
5
1
2
p
0
0
1
150R
GND
GND
3121
150R
3137
R
0
3
3
2
3
1
3
GND
7
6
5V_V
4123
3
4
5
1132-B
MSP-801V1-02-01-BNFELF
MSP-801V1-02-01-B N FELF
1132-A
1
2
p
0
0
1
1
1
1
2
4121
R
5
7
5
1
1
3
4119
2
2
1
3
R
0
6
1
2141
100n
GND
GND GND
R
0
3
3
9
2
1
3
2
1
C-
4
8
3
X
Z
B
3
2
1
6
3
0
1
2
V
6
1
9
0
1
151
150
5VN_V
117
112
113
4124
R
0
3
3
8
3
1
3
5
0
0
1
5
1
1
2
GND
150R
3127
5VN_V
5
0
0
1
1
5
1
2
1
4
1
143
0
4
1
4111
GND
4113
4
1
1
2
0
9
1
5
0
0
1
3
1
1
2
4118
4117
GND
7116
BC847BW
5
4
6
GND
3
1
2
MSD-244V-88NFELF
RED_BLACK
1131-2
MSD-244V-88NFE LF
GREEN_BLUE
1131-1
146
4
1
1
6
2
1
C-
4
8
3
X
Z
B
190 2121
6
1
1
2
5
0
0
1
5V_V
n
0
0
1
4
0
1
2
5V_V 4
2
1
6
2
1
C-
4
8
3
X
Z
B
111
100n
2134
4114
GND
100n
2135
4122
148
2
0
1
2
n
0
0
1
114
10u
1
0
1
2
5102
5VN_V
GND
V
6
1
u
0
1
3130
5V_V
5VN
3125
150R
150R
GND
R
5
7
3
1
1
3 8
2
1
3
R
0
6
1
7 8 9
GND
GND
5
2
6
2
7
2
8
2
9
2
3 0
3
4 5 6 6
1
7
1
8
1
9
1
2 0
2
1
2
2
2
3
2
4
2
1
2
1
1
7
C
2-
S
0
3
W
L
H
1 0
1
1
1
2
1
3
1
4
1
5
1
GND
2
1
C-
4
8
3
X
Z
B
3
1
1
6
4112
145
GND
p
0
0
1
3
5
1
2
p
0
0
1
7
1
1
2
6
7
8
9
118
1
2
3
4
5
4115
1112
HLW9S-2C7
6
103
1
2
3
4
5
8
1113
LPR6520-P910F
GND
MSP-801V1-02-01-B NFELF
1132-C
7114
BC847BW
7
2
1
2
1
1
6
2
1
C-
4
8
3
X
Z
B
8
3
1
R
5
7
6
1
1
3
2
1
C-
4
8
3
X
Z
B
1
1
1
6
5V_V
4 5 6 7 8 9 8
1
9
1
2 0
2
1
2
2
2
3
2
4
2
3 1 0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
4
2
1
3
R
0
3
3
7
C
2 -
S
4
2
W
L
H
2
2
1
1
GND
RES
BC847BW
7115
2
1
C-
4
8
3
X
Z
B
2
1
C-
4
8
3
X
Z
B
1
2
1
6
4116
2
2
1
6
GND
GND
GND
2133
100n
1
3
1
GND
4125
6
5
1
2
100n
2140
p
0
0
1
7
3
1
142
5
3
1
6
3
1
102
5
5
1
2
p
0
0
1
144
GND
3133
150R
100n
2138
7111
BC847BW
6
1
3
1
3
R
0
6
1
1
2
3
4
5
4
5
1
2
p
0
0
1
1114
HLW6S-2D7LF
147
5VN_V
GND
GND
4126
GND
124 0
3
1
4
3
1
BC857BW
7112
GND
3
3
1
MSP-801V1-02-01-B NFE LF
1
2
3
4
5
7
6
1111-A
GND
MSP-801V1-02-01-B NFE LF
1111-B
2139
100n
R
5
7
4
1
1
3
GND
GND
GND
R
5
7
1
1
1
3
GND
GND
GND
5
3
1
3
R

3
3
149
GND
GND
5
2
1
2
3
1
2142
1n
7113
BC847BW
12
R

3
3
3
2
1
3
119
R

6
1
6
2
1
3
121
123
9
2
1
8
2
1
2143
1n
2136
6
2
1
1n
1111-C
MSP-801V1-02-01-BNFE LF
GND
8
5VN_V
2137
100n
VA_G(
GND
5VN_V
5VN_V
116
VO_S(
FR_CVBS_N
AA_L_FR
AA_R_FR
RE_S(_N
RE_SC_N VA_SC_RE
VA_SC_FR
VA_RPr
VA_BPb
DGTAL_AUDO
RE_CVBS_N
RE_(_N
RE_Pb_N
RE_Pr_N
VO_Pb
VO_(
V0_CVBS
VO_SC
VOA_G(
VOA_RPr
VOA_S(
VOA_SC
VOA_CVBS
VA_CVBS_RE
VA_S(_RE
VA_CVBS_FR
VA_S(_FR
FR_SC_N
FR_S(_N
VA_CVBS_TU
VOA_BPb
TUN_CVBS
3139_243_33332_130_1_a2.pdf 2006-03-01
18 DVDR3380
PAINEL ANALGICO UDIO ADC/DAC

NR
SFOR
VNL
MSSEL
VREF
VRN
VDDA VRP
SYSCLK
PWON
SDA
CDN
CCLK
SCL
AD0
CS
VQ
VBAS
GND
SDN
AMUTEC
BMUTEC
AOUTA
AOUTB
DEM
SCLK
LRCK
MCLK
RST
DF0
DF1
VL VD VA_H VA
G4
0
3
2
VDD
VEE VSS
1
0
3
2
1
4X
0
3
0
1
G
H
I
D
3
5 6 7 8 9 3
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
D4
D4
D4
3B7
C
Audio-L out
3 4 5 6 7 8 9
44 D
45 C
46 C
47 C
3 4
A"dio in"! anaIog(AIA)
)
D
OI
A(I
a !i
g i
d !
"
!
"
o / !
"

ni
o i
d
"
A
3 F
5 E
D3
D3
3 D3
4 D3
5 C4
6 C4
7 C4
8 C4
9 C4
65 G3
66 G4
7 F8
7 F8
3 C7
33 D7
34 D7
35 B9
Rear audio in 1
Audio-R out
36 B9
37 C9
38 C9
4 C9
4 D9
43 D
95 B5
96 B5
3D5
3D5
5 F
5 F3
53 F4
54 E4
55 F4
56 F5
57 F5
58 F6
59 F6
6 F6
6 G6
6 G3
63 G3
64 G3
36 D
37 D
3F
3F
73 G8
74 G8
75 F
76 G
)
D
OI
A(I
ati
gi
dt
#
pt
#
o/t
#
p
ni
oi
d
#
A
2281 H4
2282 I5
2283 I6
2284 I8
2291 B2
2292 B2
2293 B3
2294 B4
3237 G2
3238 G2
3239 H2
3241 F8
3203 D5
3204 D5
3205 D6
3206 D6
2422 026 05383
3207 D6
3208 D6
3211 C8
3212 D8
3213 C9
3214 D9
3215 C10
3260 I3
3261 H3
3262 I4
3263 I5
3223 F2
3224 E3
3225 G4
3226 G4
3227 G4
3228 G6
3229 F5
3231 G2
3232 G2
3233 G2
3234 G2
3235 G2
3236 G2
6204 F10
6205 G10
7201 C7
7202-1D8
3242 F8
3243 G8
3244 G8
3245 F9
3246F10
3247G9
3248G10
3249F11
3250G11
3251H7
3252H7
3253I9
3254I9
I206 D11
I211 C2
I212 C2
I213 C2
3264I5
3265B11
5201B2
5202B3
5203B5
5211B11
5212E5
6201I7
6202F9
6203H9
I242 F12
I243 F12
7202-2 C8
7203C12
7204F2
7205F3
2422 026 05462
Rear audio in 2
d r
a
o
B l
a ti
g i
D
ot /
m
o r f
7206G5
7207F9
7208F10
7209G9
7210G10
7211H7
7212H8
7214H4
I201 B2
I202 B4
I203 B5
I204 F4
I205 F5
I214 D2
I215 C2
I221 G1
I222 G1
A#dioADC/DAC
I223 G1
I224 G1
I225 G1
I226 G1
I227 G1
I228 G1
I229 G1
I230 H1
I231 H1
I241 F12
2K2
3245
22R
5V_A
6.3V
3233
2254 100u
4
5
p
0
0
1
6
7
2
2
3
1
2
6
LPR6520-J440G
1205
229
K
0
0
1
4
0
2
3
100R
3250
2
7
2
2
0
n
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1203
HLW18S-2C7
1
K
0
0
1
1
0
2
3
GND
p
3
3
3
6
2
2
3
1
2
GND
LPR6520-J920G
1201
4
9
2
2
n
0
0
1
3V3_A
241
GND
231
221
2233 47u 6.3V
100n 2234
BAS316
1u0 2209
6202
2271
D
N
G
5V_A
22u 16V
p
0
0
1
4
0
2
2
3V3_A
3V3_A
206
u
0
0
1
1
1
2
5
205
2
3
1
5
4
7214
74LVC1G125GW
5V
12V
K
0
0
1
2
0
2
3
p
3
3
2
6
2
2
6.3V
2242
47u
n
0
0
1
6
4
2
2
3243
680R
1u0 2208
3235
2212 1u0
22R
100K 3225
100n 2256
GND
1
1
2
3
0
K
1
22n 2259
5VN_A 5VN
1
3
2
1K0
3223
3
4
2
2
7210
BC817-25W
n
0
0
1
22R 3237
3V3_A
3249
230
100R
5VN_A
228
GND
2235 47u 6.3V
13
22R 3231
4
10
2
1
1
1
7
1
12
5
0
2
7206
19
18
15
14
9
8
7
6 6
1
3
CS4351
192 kHz DAC

100n 2236
0
K
1
7
1
2
3
9
1
3
2
4
5
5
1
0
1
12
UDA1361TS
ADC

24-BT AUDO
7203
11
13
14
7
6
8
6
1
GND
227
GND
226
p
3
3
4
6
2
2
n
0
0
1
2
9
2
2
BC857BW
7207
GND
7205
1
3
2
V
3.
6
u
7
4
4
4
2
2
BC807-25W
5VN_A
K
0
0
1
3
0
2
3
16V 47u 2260
GND
GND
3V3
V
6
1
u
7
4
3
5
2
2
GND
GND
K
5
1
4
4
2
3
3232
GND
204
10K
22R
3214
5V_A
K
0
1
8
2
2
3
0
n
1
4
7
2
2
5
0
2
3
K
0
0
1
K
0
0
1
8
0
2
3
5V_A
3241
680R
2281 100n
3239 22R
6201 BAS316
3260
4
243
1K0
LM833
7202-1
NULL
3
2
1
8
GND
GND
K
0
0
1
6
0
2
3
470R 3261
1u0
3V3_A
GND
2207
2232 100n
p
0
0
1
5
7
2
2
47u 2258 16V
p
0
0
1
2
0
2
2
214
GND
GND
GND
K
5
1
7
4
2
2
n
0
0
1
2
4
2
3
3
2 K
0
0
1
4
5
2
3
PDTC124EU
7211
1
p
3
3
5
6
2
2
5V
5VSTBY
4K7
3251
224
5
15
2
11
4
13
3
10
9
6
6
1
7 8
12
1
14
7201
HEF4052B
MDX
10u
5202
3V3_A
10K
3213
BC847BW
1
3
2
GND GND
7204
GND
2205 1u0
6203
BAS316
GND
100n 2238
9
K
3
2K2
3247
4
2
2
3
n
0
0
1
1
5
2
2
242
1u0 2211
100n 2255
2257 1K0
3246
100n
223
222
213
2206 1u0
p
0
0
1
1
0
2
2
100n 2261
K
7
4
6
1
2
3
1u0 2210
5VN_A
GND
GND
0
K
1
2
1
2
3
3238
GND
5VN_A
22R
2282 8n2
4
8
2
2
n
2
2
BC817-25W
1
3
2
7212
1
3
2
GND
7208
7
u
4
PDTA124EU
6
6
2
2
211
212
2237 47u 6.3V
215
K
7
4
5
1
2
3
7
0
2
3
1
9
2
2
V
6
1
u
0
1
K
0
0
1
5201
10u
3
5
2
3
K
2
2
2273
3262
16V 22u
75R
n
0
0
1
2
5
2
2
3248
1K0
3V3_A
225
R
2
2
5
6
2
3
202
5VSTBY
5V_A
GND
201
6205
BAS316
6204
BAS316
R
0
5
1
4
6
2
3
GND
7209
BC857BW
V
3.
6
0
m
1
5
4
2
2
22K
3252
K
0
1
2
2
2
3
GND
GND
47u
2241
7
8
4
6.3V
LM833
NULL
7202-2
5
6
3263
GND
120R
K
0
1
7
2
2
3
V
6
1
u
0
1
3
9
2
2
22R 3234
2
1
2
5
u
2
2
p
0
9
3
GND
GND
3
8
2
2
203
9
2
2
3
7
R
4
5VSTBY
6.3V 47u 2231
3236 22R
6
2
2
3
K
0
1
GND
V
6
1
n
0
0
1
6
9
2
2
5
9
2
2 u
0
1
6
4
5
5203
10u
1202
LPR6520-J440G
3
1
2
GND
GND
4K7
3221
GND
3
0
2
2
p
0
0
1
AOD_WCK
AOD_MCK
AD_WCK
AD_BCK
AD_MCK
AD_DAT
AD_DAT
AA_R_RE2
AA_L_RE2
AA_R_RE1
AA_L_FR
AO_MUTE
DGTAL_AUDO
AA_L_RE1
AOD_SPDF
AA_R_FR
AA_L_MSP
AA_R_MSP
AA_R_RE1
AA_L_RE1
AA_L_RE2
AA_R_RE2
AOD_SPDF
AMUTEC
BMUTEC
AOD_BCK
AOD_WCK
AOD_MCK
AOD_DAT
AD_BCK
AD_WCK
AD_MCK
AOD_BCK
AO_MUTE
AOD_DAT
AKLL
RSA2
RSA1
POWER_FAL
3139_243_33332_130_2_a2.pdf 2006-03-01
19 DVDR3380
PAINEL ANALGICO TUNER E PROCESSADOR DE UDIO MULTI (MSP)
DSPEAKERL
D/A
D/A
2SL/R
HEADPHONER
DENT
NC
SCART
LOUDSPEAKERR
A/D
D/A
DEMODULATOR
S1...
FM1
FM2
2SL/R
NCAM B
NCAM A
SCARTL
HEADPHONEL
DENT
LOUDSPEAKER
A/D
D/A
SCARTL
SCARTR
DFP
SCARTR
SwtchngFacltes
T
M
T
M
T
M
T
M
5311 D3
5312 E3
5321 C13
5322 G11
6311 C13
3313 G3
3314 G2
3315 G3
3316 G4
3326 E6
4311 E2
4312 G2
5301 C2
2321 B11
2322 B11
2323 B12
2324 B12
2325 B12
2326 D13
2327 D13
2328 E12
2329 E13
7302 G3
73031 E5
73032 E5
7304 C8
I301 D2
I301 C3
I303 E3
I311 G12
I312 G12
2302 C3
3317 E4
3318 E4
3319 F4
3320 F4
3321 E6
3322 C7
3323 C7
3324 C13
3325 C13
2317 F4
2318 E5
2319 F4
C
2330 F12
2331 F13
2332 G11
2333 G12
2334 G12
2335 D7
2336 D7
3311 E2
3312 E2
2303 C4
2304 C4
2310 E2
2311 E2
2312 E3
2313 E3
2314 F2
2315 F3
2316 F4
D
E
F
G
H
I
A
B
C
11 12 13
A
B
3 4 5 6 7 8 9 10
7 8 9 10
D
11 12 13
1 2
1301 G12
1302 D1
1 D1
2301 C3
E
F
G
H
I
1 2 3 4 5 6
uner n #uIti soun proessor
LM393D
5
6 7
8
4
7303-2
3312 100
2319
100n
V
6
1
u
0
1
3
2
3
2
K
0
1
6
2
3
3
SCL
7
SDA
SF_OUT
10
13
VDEO_OUT
11
VT
301
AUDO_OUT
2
B+
4
1
6
1
5
1
7
1
3
NC
4
NC
NC
12
6 R
E
N
U
T
TCSN9082PA26F(H)
1303
8
AFT_OUT
AS
5
9
1
2
3
2
u
0
1
V
6
1
4312
303
302
5V_FV
P
O
T
F
E
R
V
2
4
N
_
L
A
T
X
5
T
U
O
_
L
A
T
X
6
312
30
SC2__L 37
SC2__" 38
STBYQ
11
N
E
T
S
E
T
4
P
T
7
1
F
E
R
V
9
2
2
F
E
R
V
5
2
3
2
4
2
8
2
2
3
RESETQ
22
SC1_N_L 40
SC1_N_R 41
SC1_OUT_L 31
SC1_OUT_R
2C_CL
12
2C_DA
13
2S_CL
14
2S_DA_N1
17
2S_DA_N2
21
2S_DA_OUT
16
2S_WS
15
MONO_N 43
1
M
_
L
P
A
C
4
3
DACM_L 27
DACM_R 26
S
S
V
D
0
2
DVSUP
19
0
O
_
R
T
C
_
D
9
1
O
_
R
T
C
_
D
8
AGNDC
36
S
S
V
H
A
5
3
P
U
S
V
H
A
3
3
ANA_N+ 2
ANA_N- 3
G
S
A
9
3
S
S
V
A
4
4
P
U
S
V
A
MSP3425G
7304
L
C
_
R
D
A
8
1
L
E
S
_
R
D
A
0
1 5301
476
563 2335
18M432
1301
3320
n
0
0
1
10K
311
2
3
3
2
3323 100R
4
1
3
2
V
0
5
7
6
4
5322
5V
106
33VSTBY
V
0
1 1
0
3
2 6
0
2
2
3
1
3
3
2
K
2
5V_FV
8
3
6
4
3
3
2
5V_FV
2
0
3
2
n
0
0
1
4K7 3317
5V_FV
8
3
6
3
3
3
2
4311
5V_FV
V
0
5 7
1
3
2 2
6
2
2312 106 16V
n
0
0
1
4
2
3
2
5
1
3
2
n
0
1
100R 3322
5
2
3
2
V
6
1
6
7
4
5
1
3
3
226
R
0
0
1
5V
5312
1
2
3
3
K
0
1
3
12
NC
SCL
6
7
SDA
SF_OUT
10
VDEO_OUT
13
VT
11
AFT_OUT
AS
5
AUDO_OUT
9
2
B+
1
BB+
4
1
6
1
5
1
7
1
NC
1302
TCSM0601PD25F(H)
R
E
N
U
T
8
3
2 1
8
4
7303-1
LM393D
n
0
3
3
5V
V
F
_
V
5
6
1
3
2
6
0
1
1
2
3
5
n
0
0
1
4
0
3
2
0
n
1
1
3
3
2
1
1
3
6
6
1
3
S
A
B
5V
5V_FV
7302
BC857BW
668 5311
8V
n
0
0
1
9
2
3
2
100n
5V
V
F
_
V
5
2313
n
0
0
1
1
1
3
2
0
n
1
0
3
3
2
6
2
3
2
6
0
1
V
6
1
3325 10K
R
5
7
6
1
3
3
3318 10K
3319
2336 1u0
27K
100R 3311
7
2
3
2
n
0
0
1
V
6
1
u
0
1
0
1
3
2
2
2
3
2
n
0
0
1
7
K
4
4
2
3
3
u
0
1
3
0
3
2
5V_FV
V
6
1
3314
100R
8
2
3
2
V
0
5
7
u
4
100n 2318
TUN_DET0
TUN_DET1
TUN_CVBS
RSA2
RSA1
AA_L_MSP
AA_R_MSP
SCL_5V
SDA_5V
SCL_5V
SDA_5V
3139_243_33332_130_3_a2.pdf 2006-03-01
20 DVDR3380
PAINEL ANALGICO - PSU E INTERFACES
1408F13
1409H13
1413H3
1414C6
1415E7
1 2 3 4
342710

C
5 6 7
G
H
I
r
a
o
bl
ati
gi
d
ot
n
oit
a
ci
n
u
m
m
o
C
4415F4
2419C6
2421G6
1410E13
14113
1412E4
3410C3
3411C3
3412C3
L = Standby
3413C4
3414D3
3415D3
3416D4
3417E4
3418F3
3419H3
3420I3
34216
3422C7
3423C7
34247
3425D7
3426D8
7420C7
3428C9
3429G3
D
E
F
3434H7
3435 H7
3436H8
3437G7
3438H9
3439H5
3441F10
3442E10
3443F10
3444E10
3445E10
3446F10
3451H10
3452H10
3453H11
3454H11
4411G5
4412G6
4413B4
4414B4
4416F4
4417I3
2422H8
2423G8
2431E11
5412F7
6411D8
6412C10
= On
6413C10
6421F9
6422H6
7411B3
7412C4
7413C3
7414D3
7415D4
7416F3
7417G3
7418I3
7419B7
I435D13
7421C8
7422C7
3431F6
3432G6
3433G6
7426G3
7431F7
7441H10
D
D
O

o
t
dr
a
o
bt
n
orf
ot
n
oit
a
ci
n
u
m
m
o
C
SUandin!erfaces
1405D13
7442H10
I401 D1
4418I3
4419E7
5411G6
I405 D1
I406 C6
I407 C6
d
r
a
o
B
l
a
ti
gi
D

o
t
I408 C6
I409 D6
I410 D6
I413 D8
I415 B10
I421 A13
I422 B13
I423 B13
I424 B13
I425 B13
I426 B13
I427 B13
I431 C13
I432 C13
I433 C13
I434 D13
7423B10
7424F11
7425E11
2413F2
2414I2
2415D6
2416D7
2417C9
D
D
H

o
t
1406E13
1407F13
I
1401D1
1402C5
1403A13
1404C13
I450 F13
I451 F13
I452 F13
I402 D1
I403 D1
I404 D1
I471 H13
I479 H13
I480 H13
I481 H13
I482 I13
I483 I13
A
B
C
D
E
F
G
H
2418E6
N
A
F
ot
2411B2
2412C3
I491G9
Fr MCU
I436 D13
I441 E13
I442 E13
12
I464 G13
I465 G13
I467 G13
13
A
11
8 9 10 11 12 13
1 2
7
1
4
2
3 4 5 6 7 8 9 10
n
0
0
1
467
5VH
8V
479
3
4
4
3
7
K
4 450
12VBE
402
9
1
4
2
V
0
5
0
u
1
5VE
4416
4418
4415
4414
4417
4413
2
1
4
4
GND
12VSTBY
4419
3418
10K
BC847BW
12V
7420
1
2
BC327-25
7425
2
B2B-EH-A
1410
1406
B2B-EH-A
1
1
2
4
6
6
1
3
S
A
B
1
2
4
3
K
0
0
1
3
K
3
4
4
4
3
431
5
3
4
3
R
0
0
1
3439
1K0
GND
5VH
D
N
G
5
2
4
3
K
7
4
GND
S2306DS
7416
12V
12V
K
7
4
3
1
4
3
7
K
4
2
4
4
3
1
2
3
4
410
B4B-EH-A
1405
GND
u
0
3
3
1
1
4
2
3
1
4
6
6
1
3
S
A
B
3454
1K0
423
3V3
GND
V
2
1
6411
BZX384-C6V8
10K
3429
BC847BW
7424
GND
GND
1K0
3453
V
0
5
u
0
1
8
1
4
2
405
T 125mA 1414
2
2
4
6
2
V
8
C -
4
8
3
X
Z
B
3431
100R
6
3
4
426
7414
S3443DV
1
2
5
0
R
1
5
4
4
3
2
V
8
C-
4
8
3
X
Z
B
2
1
4
6
432
GND
422
33VSTBY
424
8
K
1
4
3
4
3
K
0
2
2
GND
12VH
2
2
4
3
7415
BC847BW
4411
451
434
u
0
0
1
435
5
1
4
2
19
2
3
4
5
6
7
8
9
1
10
11
12
13
14
15
16
17
18
HLW19S-2C7
1407
442
5VSTBY
BSH103
7442
425
406
483
1
2
3
4
5
6
PDTC124EU
7421
1402
B6B-PH-K
V
0
5
u
0
0
1
2
2
4
2
12VE
464
421
8
9
471
1
10
11
12
2
3
4
5
6
7
B12P-PH-K
1403
5V
413
STS9NF30L
12VSTBY
5V
7418
0
2
4
3
7417
S2306DS
6
1
4
2
n
0
0
1
K
8
1
S2306DS
7411
403
3441
68R
8
2
4
3
7
K
4
5VN
1
5
4
3
7
K
4
7
K
4
2
5
4
3
u
0
6
5
4
1
4
2
1000mA T
33VSTBY
4
5
1412
B5P-VH
1401
1
2
3
465
2A T 1413
491
GND
427
3
2
4
2
p
0
9
3
3V3BE
V
2
1
3V3BE
480
407
GND
V
0
1
u
0
0
1
1
2
4
2
3
K
3
436
2
1
4
3
10K
3419
12VH
12VE
K
0
2
2
0
1
4
3
GND
12V
3
2
4
3
3
K
3
5VBE
12VBE
5VBE
0
K
1
BSH103
6
4
4
3
GND
7441
5
R
1
2
3
4
3
K
7
4
4
2
4
3
VGNSTBY
4
1
4
3
K
7
4
K
2
2
8
3
4
3
3V3
452
u
0
6
5
3
1
4
2
GND
6
3
4
3
K
2
2
GND
12
13
14
2
3
4
5
6
7
8
9
1
10
11
415
HLW14S-2C7
1409
7
1
4
3
33"B%
12"
K
7
4
433
500mA 1411
125mA 1415
3K3
3415
3416
3K3
5
6
7
8
9
441
12
13
14
15
16
17
2
3
4
1408
HL#17-2C7
1
10
11
K
0
0
1
1
1
4
3
3
3
4
3
5

1
1K5
3426
5412
BC337-25
7422
1m0
BC847B#
7413
H
"
2
1
12"
481
482
"
5
2
u
0
1
1
3
4
2
R
3427
PDTC124EU
7412
1404
B4B-EH-A
1
2
3
4
409
408
5VSTBY
5VE
7423
BC547B
401
2
1
4
2
V
0
5
2
u
2
7419
S2306DS
5V
404
3437
47K
S 7
SWC 1
SWE 2
TMC 3
VCC
6
7426
S2306DS
7431
MC34063AD
REGULATOR
REFERENCE
OSC
PK
Q
R
S
CN_NEG 5
DCOL 8
GND 4
33u
5411 AN_SEL1
5V_VH
12V_P
TUN_DET1
POWER_FAL
VGN_P
FBS
5VN_P
5VSTBY
3V3_VH
12V_VH
HDM_NT
8SC2_1
TUN_DET0
DFM
SDA_3V3
8SC2_2
AN_SEL0
ATNFM
POWER_FAL
HDD_ON
SCKFM
DFM
DHOST
RDYFM
ATNFM
HOSTRST#
SCL_5V
SDA_5V SDA_3V3
SCL_3V3
FAN
HOSTRST#
SCKFM
DHOST
RDYFM
SCL_3V3
HDD_ON
FAN
STBYn
VGNSTBY
12VSTBY
STBYn
STBYn
3139_243_33332_130_4_a2.pdf 2006-03-01
21 DVDR3380
PAINEL ANALGICO - LAYOUT - PARTE PRINCIPAL (VISTA SUPERIOR)
3380_APAC_TOPLAYR.pdf 2006-05-03
22 DVDR3380
PAINEL ANALGICO- LAYOUT -PARTE PRINCIPAL (VISTA INFERIOR)
TopView_AnalogBd_Hmc_32694.pdf 2005-11-18
23 DVDR3380
PAINEL FRONTAL - DISPLAY
P
LE

P
CTRL
RER
X
XT
KEY_R
FM
SCK
D
D_HOST
SCK1
POWER_FAL
R
VLOAD
1
2
3
C
1
2
3
4 POWER_CTL
VDD
VSS
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
RDY
RESET
2
1
2
ATN
HOST_RESET
1
F113F13
F114F13
F115E9
F117F10
6117 H5
7100 A3
7101 B2
7102 B3
7103 C1
7105 H13
F100B6
F101B9
F102E13
F103E13
F104E13
F105E13
F106F13
F107F13
F108F13
F110F13
F111F13
F112F13
6104D9
6105D9
6106D9

6107D10
6108D10
6109D10
6111E3
6112F3
6113F3
6114G3
6115G3
6116H3
3116D13
3117D13
3118E13

3119F10
3120F10
3121G2
3122G9
3123G2
3124H10
3125H2
3126H6
3127B9
3128B9
3129B10
3130B10
3131B10
5100B1
5101E3
6100B1
6101A5
6102D8
6103D9
3100A3
3101A2
3102A4
3103 A10
3104 A3
3105 A10
3106 A2
3107 A4
3108 B10
3109 B1
3110 B4
3111 B5
3112 B6
3113 B6
3114 B1
3115 C2
C
D
E
2103B1
2104B5
2105B1
2106B1
2107B2
2108F10
2109F11
2110F9
2111G2
2112G11
2113G12
2114G12
2115G12
2116G13
2117G2
2118G2
2119H10
2120H3
2121I9
2122I3
2123I3
2124I12
10 11 12 13
A
B
C
D
E
F
G
H
I
A
B
2100 A4
2101 B4
2102 B5
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9
F121 H3
F122 H12
F123 I12
F
G
H
I
0010 E3
1100 A6
1101 F1
1102 F2
1103 F2
1104 F1
1105 F2
1106 F2
1107 E10
1108 F10
1109 F13
2101
22u
F119F10
F120H5
122
50V
F123
F120
F119
F121
F105
1108
F117
F111
32K768
F113
F108
F106
F107
F110
5
1
1
3
0
K
1
4
0
1
6
6
1
3
S
A
B
6
1
3
S
A
B
3
0
1
6
0
u
1 2110
5101
K
2
8
0
3
1
3
K
2
8
9
2
1
3
8
2
1
3
K
2
8
K
2
8
7
2
1
3
3105
GND
10R
3104
470R
3112
F102
10R
2120
2n2
330R
10K 3125
3126
n
0
0
1
EVQ11L05R
5
0
1
2
n
0
0
1
4
2
1
2
1106
2
2
1
2
2106
V
3 .
6
0
m
1
220n
2K7
3117
3116
2K7
3
1
1
2
GND
GND
n
0
0
1
BAS316
6100
1
0
1
3
R
0
3
3
GND
2
0
1
2
n
7
4
EVQ11L05R
1102
WH02D-1
0010
1 2
EVQ11L05R
1101
6K8
3114
2117 2n2
n
0
0
1
6
1
1
2
n
0
0
1
5
1
1
2
F115
BAS316
6112
47K
1 27
28
52
51
50
2
3
3122
46
47
48 44
12
5
4
8
11
20
21
22
23
7
49
13
41
42
43
45
35
16
36
37
38
39
40
17
18
19
15
24
25
26
29
30
31
32
33
34
6
9
10
14
n
0
1
9
1
1
2
3100
330R
BC847BW
7103
3
P
8
1
4
P
7
1
5
P
6
1
6
P
5
1
7
P
4
1
8
P
3
1
9
P
2
1
0
1
1
1
P
9
2
1
P
8
3
1
P
7
4
1
P
6
5
1
P
5
6
1
P
4
7
1
P
2
P
9
1
2
2
1
1
F
1 2
2
1
F
1
2
F
1
3
2
3
2
2
F
C
N
1
2
1
P
0
2
0
1
P
1
1
G
1
9
2
8
2
G
2
G
3
7
2
G
4
6
2
5
2
G
5
4
2
G
6
G
7
3
2
G
8
3 1
1100
HUV-08SS65T
1107
2
35V 22u
2104
6
1
3
S
A
B
9
0
1
6
6
1
3
S
A
B
7
0
1
6
6
1
3
S
A
B
8
0
1
6
6
1
3
S
A
B
6
0
1
6
GND
GND
10K 3121
2118 2n2
3123 10K
9
0
1
2
p
2
2
8
0
1
2
p
2
2
1n0
2107
GND
6114
BZX384-C6V8
K
0
1
2
0
1
3
0
0
1
2
n
7
4
BAS316
6113
6
1
3
S
A
B
5
0
1
6
1
2
1
2
n
0
0
1
N
N
T
E
K
6
1
8
L
T
L
7
1
1
6
0
K
1 0
1
1
3
R
0
7
4
3109
6115
BAS316
BAS316
6111
3103
10R
2
0
1
6
6
1
3
S
A
B
3108
GND
GND
10R
F104
GND
F103
BC847BW
7101
3106
33R
F100
GND
GND
OUT
VS
7105
TSOP4836ZC1
GND
5100
u
0
0
1
7102
EVQ11L05R
2SB1132
2
3
4
5
6
7
8
9
1103
1
10
11
12
13
14
F101
HLW14S-2C7
1109
2103
220n
EVQ11L05R
1104
7100
GND
2SD1664
GND
BAT54 COL
6116
n
0
0
1
4
1
1
2
3113 10R
2K7
3118
3
2
1
2
GND
n
0
1
K
0
7
2
4
2
1
3
GND
3119
100R
V
6
1
u
0
0
1
2
1
1
2
BZX384-C6V8
6101
470R
3107
K
7
4
0
2
1
3
2n2 2111
K
2
8
1
3
1
3
F114
1105
EVQ11L05R
GND
F112
RC
HOST_RESET
VGNSTBY
10R 3111
POWER_CTL
RDY_FM
ATN_FM 5VSTBY
D_FM
12VSTBY
5VSTBY
KEY_B
5VLP
GND
POWER_FAL
VGNSTBY
D_HOST
5VLP
SCK
5VSTBY
POWER_FAL
RC
VGNSTBY
KEY_A
KEY_B
KEY_C
KEY_C
KEY_A
5VLP
SCK
D_FM
D_HOST
RDY_FM
ATN_FM
HOST_RESET
5VSTBY
12VSTBY
5VSTBY F2
VGNSTBY
2
F
3139_243_33314_130_1_a3.pdf 2006-02-28
24 DVDR3380
PAINEL FRONTAL - ENTRADA UDIO /VDEO
ANOTAES:
2214 E2
2215 C1
3211 B2
3212 B2
3213 C1
F203 B1
F204 B1
F205 B1
F206 C1
F209 B3
F211 B3
F212 B3

1 2 3
1 2 3
A
B
C
D
E
A

B
C
D
E
1200 D3
1201 D1
1202 B3
1203-1 B1
1203-2 B1
1203-3 C1
2211 B3
2212 C3
2213 C1
5
6 AV_GND
HLW6R-2C7
1202
1
2
3
4
6
1
2
3
4
5
5
6
AV_GND
1200
CSS5004-7A01E
1201
S6B-PH-K
1
2
3
4
F212
AV_GND
3211
AV_GND
600R
R
5
7
3
1
2
3
1u0
GND
2211
2214
AV_GND
470p
F209
AV_GND
F203
GND
470p
2212
1u0
2215
F205
3
1
2
2
p
0
0
1
1203-3
RED
8
6
7
AV_GND
1203-2
WHTE 5
3
4
F204
F211
600R
3212
F206
AV_GND
1203-1
YELLOW
LPV8529-0100F
1
2
AL
TPB0-
TPB0+
TPA0-
TPA0+
AR
CVBS
3139_243_33314_130_2_a4.pdf 2006-02-28
25 DVDR3380
PAINEL FRONTAL - LAYOUT SUPERIOR (SMD + COMPONENTES) E INFERIOR (COMPONENTES)
Front_Layout_3139_243_33312_pg1.pdf 2006-05-03
Front_Layout_3139_243_33312_pg2.pdf 2006-05-03
26 DVDR3380
PAINEL FRONTAL - STANDBY PAINEL FRONTAL - STANDBY - LAYOUT SUPERIOR E INFERIOR
3 4
1 2
A
B
F301 D2
I300 D3
C
D
F
G
1302 C1
1303 C4
D
3
G
E
F
C
2301 D2
E

6300 D2
6301 D2
F300 D2
1 2
4
A
B
1302
WH02D-1
1
2
F301
1303
EVQ11L05R
GND
F300
2
n
2
1
0
3
2
1
0
3
6
8
V
6
C
-
4
8
3
X
Z
B
8
V
6
C
-
4
8
3
X
Z
B
0
0
3
6
3139_243_33314_130_3_a4.pdf2006-02-28
Front_Layout_3139_243_33312_pg4.pdf 2006-05-03
Front_Layout_3139_243_33312_pg5.pdf 2006-05-03
27 DVDR3380
PAINEL DIGITAL- PROCESSADOR TRASEIRO
SCL
ADR
0
1
2 SDA
WC
GPOEXT39
CS6
GPOEXT40
CS7
SO
CS10
GPOEXT24
GPOEXT25
GPOEXT37
GPOEXT38
GPOEXT42
GPOEXT41
SP_MSO
UART1_RX
SCL
SDA
SO_SP_CS0
SO_SP_CS1
SO_RTX1
SO_RRX
SO_UART2_RX
SO_UART2_TX
SO_UART1_CTS
SO_UART1_RTS
SO_SP_CLK
SO_SP_CS2
SO_SP_MOS
SO_UART1_TX
HMST_CS0_8BT HMST_ALE
HMST_DTACK
0
1
2
3
5
4
HMST_CS
HMST_GPO
HMST_UWE
0
1
2
3
5
4
HMST_OE
LWE
MA6:15
MDATA0:15
HMST_AD
MA22:26
MA1:5
HMST_ADDRH
0
1
2
3
4
HMST_ADDRLO
PCMCA_OR
PCMCA_OW
HMST_UDS
HOST_PO_0
0
1
2
3
4
HMST_LDS
HMST_RST
HMST_WR
HOST_OC_0
HMST_WAT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5
4
3
2
1
0
11
12
13
14
15
ATAP_DATA
ATAP_ADDR
ATAP
DOR
DOW
DMAACK
RESET
0
1
2
3
4
DMARQ
NTRQ
ORDY
6
7
8
9
10
DAC5_OUT
DAC6_OUT
TD
TDO
TMS
TRST
TCK
DAC1_OUT
DAC2_OUT
DAC2_OUT_B
DAC3_OUT
DAC4_OUT
DAC4_OUT_B
1394
1394_PHY_DATA
1394
1394
LNK_ON
PHY_CLK
PHY_CTL0
PHY_CTL1
0
1
2
3
4
5
6
7
LPS
LREQ
GPOEXT35
BYPASS_PLL
CK
MCONFG0
CLKX
CLK0_DAC
DMNUS_0
DPLUS_0
SDRAM_DQ
SDRAM_DQS
0
1
2
3
SDRAM_DQM
SDRAM_A
SDRAM
CAS
CKE
CLK0
CLK0
CLK1
CLK1
WE
RAS
3
2
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
21
22
23
24
25
26
27
28
29
30
31
SDRAM_ RE F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AGND GND GND
F
E
R
V
AVDD VDD
0
_
D
D
V
A
_
B
S
U
VDD25
0
0
V
5
_
S
A
B
D
D
V
D
_
C
A
D
0
_
D
D
V
_
C
A
D
3
_
D
D
V
_
C
A
D
D
D
V
F
E
R
VDDP D
D
V
L
A
T
X
S
S
V
L
A
T
X
0
_
D
N
G
A
_
B
S
U
S
S
V
F
E
R
1
S
S
V
D
_
C
A
D GND
GPOEXT33
AO_D
GPO6
0
1
SCLK
MCLKO
EC958
FSYNC
3
2
1
0
A_MCLKO
SCLK
FSYNC
AO_MCLK
A_MCLK
A_D
CS8
CS9
AO
A
GPOEXT32
1
2
3
4
5
6
7
8
9
VGPOEXT 0:7
VO_D
V_D
V_CLK0
5
6
7
2
0
4
VO_CLK
1
3
V_VSYNC0 PEC
0
I
A
B
C
D
E
F
G
H
I
1101 B11
1111 G10
2101 B10
2102 B11
2105 H12
2108 F1
2109 F1
2120 B6
2121 F8
2122 G9
2123 G9
2124 G9
2125 G9
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6
Back-end FIash (BEF)
)
DI
V( I
ati
gi
D t
u
p
nI
o
e
di
V
)
A
O
V (
g
oI
a
n
A t
u
pt
u
O
o
e
di
V
C
D
E
F
G
H
2127 G9
2128 G9
2129 G10
2130 G10
2131 H9
2141 G8
2142 G9
2143 G9
2144 G9
2145 G9
2146 G9
2147 G9
2151 F5
2152 G5
2153 G5
2126 G9
Back-end Processor
Back-end Front-end Interface (IDE)
: DA0
2173 G5
2174 G5
2175 G5
2176 G6
2181 G7
2182 G7
Fc: DM3
2183 G7
2191 G8
2199 G11
3101 A1
3102 A1
3103 A1
3104 C1
3121 A6
3122 B6
3123 B6
3124 A8
3125 B8
3131 C9
3132 C9
7 8 9 10 11 12 13
A
B
3143 D7
3144 D8
3145 D7
3146 D8
3147 D7
3148 D8
Communication (COM)
3149 E7
3150 E8
3151 E7
3152 E8
3153 E7
3154 E8
3155 E7
3156 E8
3161 A11
3162 A13
3163 B11
3164 C11
3165 C11
3166 C11
3167 C11
3168 I13
2154 G5
2155 G5
2156 G6
2157 G6
2158 G6
2161 G7
2162 G8
2171 G5
2172 G5
3173-1 G1
3173-2 G1
3173-3 G1
3173-4 H1
3174-1 H1
3174-2 H1
COM_VCR
3174-3 H1
3174-4 H1
3175-1 H1
3175-2 H1
3175-3 H1
3175-4 H1
3176-1 H1
3176-2 H1
3176-3 H1
3176-4 H1
3177-1 I1
3177-2 I1
3177-3 I1
3177-4 I1
3178-1 I1
3133 C9
3134 C10
3135 C10
3136 C10
3137 C8
3138 C8
3139 C8
3141 D7
3142 D8
3182-3 G4
3182-4 H4
3183-1 G4
3183-2 G4
3183-3 H4
3183-4 G4
3184-1 G4
3184-2 G4
3184-3 F4
3184-4 G4
3185-1 H4
3185-2 I4
3185-3 I4
3185-4 H4
3186-1 H4
3186-2 H4
3186-3 H4
3186-4 H4
3187-1 I4
3187-2 I4
3169 I13
3171-1 G1
3171-2 G1
3171-3 G1
3171-4 G1
3172-1 G1
3172-2 G1
3172-3 G1
3172-4 G1
3194 H12
3195 H12
3196 H12
3197 G12
3198 G12
3199 G11
)
D
O
V( I
a ti
g i
D t
u
p t
u
O
o
e
d i
V
5121 F8
5131 H9
5141 G8
5151 F5
5161 F7
5162 F7
5171 G5
5181 G7
6101 C3
7101-1 D4
7101-10 I7
7101-2 A4
7101-3 B12
7101-4 A2
7101-5 E12
3178-2 I1
3178-3 I1
3178-4 H1
3181-1 G4
3181-2 G4
3181-3 H4
3181-4 G4
3182-1 G4
3182-2 H4
IEEE1394 Link - PhysicaI (LNK)
7101-7 A7
7101-8 F2
7101-9 A12
7105 I12
7111-1 G12
7111-2 H13
T101 B1
T102 B1
T103 B1
T104 B1
T105 B1
T106 B1
T111 G11
T112 G11
T113 E5
T114 H11
T121 A11
T122 B11
T131 F5
T132 G5
T133 F7
3187-3 I4
3187-4 H4
3188-1 I4
3188-2 I4
3188-3 I4
3188-4 I4
3191 H8
3192 G12
3193 H12
BES_CLK1#
T134 G7
Back-end SDRAM (BES)
Audio (AUD)
T135 F8
T136 F9
T137 G9
T138 H9
7101-6 D2
LNK_DATA(3)
COM_SCL
VD_NT
1
5
1
2
AUD_DAO(0)
2K2 3151
V
5
2
u
0
1
2K2
5151
BLM31
3149
3181-2 22R 2 7 3172-2 47R 2 7
BES_A(7)
BEF_MA(2)
n
0
0
1
3
5
1
2
BES_DQ(12)
DE_NTRQ
COM_SDA
LNK_CTL0
BAV99
6101
n
0
0
1
5
2
1
2
1
4
1
2 u
2
2
3155 2K2
V
0
5
2
3
6
5
8
4
7 (2Kx8)

EEPROM
7105
M24C16-RDW6
1
10K
3194
9
9
1
2
4K7
0
n
1
3197
4K7
3196
DE_DA(2)
COM_DFM
BEF_HD(3)
BEF_HD(8)
BES_DQ(9)
3156 2K2
BEF_HD(2)
AUD_BCK
DE_ORDY
4 5
BEF_MA(1)
VOA_SC
3172-4 47R
BES_A(1)
VD_D(1)
DE_DMARQ
4 5
BES_DQM(3)
BES_WE#
22R 3183-4
4 5
1 8
47R 3174-4
3171-1 47R
n
0
0
1
2
6
1
2
n
0
0
1
6
7
1
2
AUD_BCKO
AUD_MCKO
4K7 3162
2109 100n 100n 2108
LNK_DATA(0)
BES_DQ(29)
DE_CS0#
4 5
1 8
22R 3188-4
3182-1 22R
3 6
n
0
0
1
3
2
1
2
3182-3 22R
4
BLM18P
5181
1111
1
2
3
1 8
)7(
D
H_
F
E
B
B4B-PH-K
3177-1 47R
47R 3176-4 4 5
7111-2
BC847BS
5
3
4
3183-3 3 6
1
3
1
3
22R
1 8
K
0
1
BEF_MA(5)
BEF_CS0#
47R 3172-1
1 8
BES_DQS(1)
COM_USBM
BES_DQM(1)
47R 3175-1
Y7
H3 H2
U10
W8
BES_DQ(18)
BES_DQ(28)
W3
U9
V6
V12
W9
V8
Y9
W15
V14
U8
V7
U7
W6
W7
U6
Y8
Y3
Y11
Y5
Y4
Y6
Y2
V13
U11
Y13
W12
W10
W5
U5
W4
V5
V4
W14
Y12
V11
V9
Y10
W11
V10
U13
U12
Y14
W13
7101-7
DMN-8602

HOST
NFC
10K 3137
6
5
1
2
3148
BES_DQ(17)
n
0
0
1
1
0
1
2
2K2
BES_DQ(4)
DE_DMACK#
p
8
1
5161
BLM18P
n
0
0
1
4
2
1
2
VD_CLK0
AUD_DA(0)
BEF_HD(13)
3 6
n
0
0
1
8
5
1
2
47R 3175-3
DE_DD(5)
U15
W19
Y19
U17
U16
V18
V15
U14
Y18
Y17
Y15
W16
V16
Y16
W18
W17
COM_RDYFM
DMN-8602
7101-3

SERE-O
3147
BES_DQ(10)
BES_DQ(0)
T101
2K2
3 6
VOA_GY
22R 3187-3
n
0
0
1
0
3
1
2
47R 3173-3 3 6
3 6
T113
22R 3184-3
3182-2 2 7
B6
D6
DE_DD(2)
22R
A1
A2
B4
A3
A4
B5
A5
A6
B7
A7
C6
7101-4
DMN-8602

JTAG
DAC
2K2 3154
4 5
COM_SCL
COM_SDA
n
0
0
1
3
4
1
2
BES_DQ(7)
47R 3171-4
M2
N2
U3
R2
T2
W1
V2
T3
Y1
P3
R1
R4
U1
W2
P4
P2
N4
N3
M4
M3
7101-6
V3
T4
V1
U2
U4
T1
R3
P1

ATAP
DMN-8602
COM_ATNFM
BES_RAS#
COM_USBPO
BES_A(2)
BEF_OE#
4 5
K
0
1
5
3
1
3
47R 3177-4
H1
F1
G4
G3
G2
T105
7101-9

MSC
G1
E1
3174-3 47R 3 6
DMN-8602
n
0
0
1
1 8
LNK_LPS
6
4
1
2
4 5
47R 3178-1
22R 3185-4
BES_DQS(2)
1
8
1
2
V
6
1
u
0
2
2
1 8
2K2 3146
1
3
1
2
22R 3184-1
n
0
0
1
47R 2 7
BES_DQ(24)
VD_D(2)
BEF_HD(12)
K3
K2
3175-2
M1
N1
L1
J3
K1
J2
L2
L4
L3
J1
K4
DE_DD(12)

PHY-LNK
DMN-8602
7101-5
J4
LNK_DATA(2)
3192
10K T114
3
9
1
3
K
0
1
5
9
1
3
8
K
6
22R 3124
3187-2 22R 2 7
1 8
3 6
3176-1 47R
3188-3 22R
2K2 3152
DE_DD(13)
p
8
1
2
0
1
2
10K 3161
BES_CLK1
5
T102
47R 4
47R 3178-3 3 6
3178-4
T106
n
0
0
1
9
2
1
2
6
n
0
0
1
2
5
1
2
3185-3 22R 3
BES_CKE
BES_CS0#
BES_DQM(2)
1 8
n
0
0
1
1
6
1
2
BES_CLK0
3188-1 22R
2K2 3145
5121
BLM31
2K2 3141
DE_DD(10)
DE_DD(11)
7
K
4
6
6
1
3
BES_A(9)
LNK_DATA(1)
BES_DQ(25)
AUD_WCKO
BES_CLK0#
VD_D(5)
BEF_HD(5)
n
0
0
1
7
5
1
2
22R 3121
VD_D(6)
BES_DQ(27)
4
7
1
2
D16
N19
n
0
0
1
K17
J19
K19
H20
F20
D18
M20
J20
F19
C18
N17
A20
B20
C19
M17
B19
C20
L19
L18
L17
K18
G18
G17
F18
N20
F17
E19
E18
E17
A18
B18
A19
D20
M18
M19
H19
J17
J18
H18
H17
G20
G19
R18
T18
T20
V20
U19
W20
P20
N18
L20
K20
E20
T19
U18
V19
U20
Y20
R20
P18
P19
P17
R19
BES_CAS#
DMN-8602
7101-8

SDRAM
R17
3187-1 1 8
2K2
22R
3142
BES_DQ(19)
2 7
BES_DQ(14)
LNK_DATA(6)
K
0
1
3184-2 22R
3
3
1
3
n
0
0
1
2
7
1
2
n
0
0
1
3
7
1
2
BES_A(8)
BEF_HD(7)
DE_DD(9)
3
8
1
2
n
0
0
1
2
8
1
2
n
0
0
1
3 6
3138 10K
47R 3172-3
BEF_HD(6)
)1(
D
H_
F
E
B
VOA_SY
BES_DQ(5)
COM_USBP
3168
COM_SCL
BEF_HD(11)
22R
BEF_MA(22)
BES_A(4)
VOA_BPb
BEF_WE#
DE_CS1#
BES_A(15)
BEF_MA(3)
LNK_CTL1
BES_DQ(30)
COM_USBOC
VOA_RPr
BES_DQ(23)
BES_DQ(13)
)4(
D
H_
F
E
B
2K2 3150
5
n
0
0
1
2
4
1
2
3186-4 22R 4
9
T
0
1
T
9
E
0
1
E
9
1
D
7
1
T
7
1
V
1
C
2
E
2
F
6
1
L
6
1
M
4
H 5J
5
K
1
1
E
2
1
E
2
1
T
1
1
T
5
L
5
M
2
1
H
3
1
H
8J
2
C
1
B
3
F
4
F
7
1
D
6
1
C
6
1J
6
1
K
3
1
M
8
N
9
N
0
1
N
1
1
N
2
1
N
3
1
N
9
H
0
1
H
1
1
H
9
L
0
1
L
1
1
L
2
1
L
3
1
L
8
M
9
M
0
1
M
8
H
1
1
M
2
1
M
1
1J
2
1J
3
1J
8
K
9
K
0
1
K
1
1
K
2
1
K
7
1
C
3
1
K
8
L
4
E
2
D
5
1
D
5
D
5
C
2
B
3
B
5
1
C
9J 0
1 J
DMN-8602
7101-10
SUPPLY
3
E
3
C
4
D
3
D
1
D
4
C
DE_DD(6)
BES_DQ(31)
BES_A(5)
BEF_HD(9)
) 0(
D
H _
F
E
B
K
0
1
2
3
1
3
T104
DE_DD(7)
T122
5
BEF_HD(14)
3181-4 22R 4
3139
3163
BES_DQS(0)
LNK_DATA(5)
10K
8
DE_DD(15)
1M0
3174-1 47R 1
n
0
0
1
8
2
1
2
3 6
BES_DQS(3)
BES_A(10)
AUD_WCK
3176-3 47R
5
BES_DQ(21)
3184-4 22R 4
47R 3176-2 2 7
VD_D(9)
BES_A(3)
DE_DA(1)
2K2
2 7
3153
6
1
22R 3185-2
BC847BS
7111-1 2
BES_DQ(20)
BES_A(14)
BEF_HD(10)
DE_DD(3)
DE_DD(4)
DE_DD(8)
BLM18P
5131
B14
)2(
D
H_
F
E
B
C13
A16
A12
A17
B15
B16
B17
A14
B13 A13
A15

7101-2
DMN-8602
AUDO C14
D14
D13
DE_DD(1)
VD_VSYNC
VOA_CVBS
COM_FPR
BES_DQ(1)
3165 22R
7
K
4
22R 3164
7
6
1
3
T133
T134
T131
T132
COM_DHOST
VD_D(7)
BEF_HD(15)
22R 1 8
DE_RST#
2 7
3185-1
u
0
3
3
1
2
1
2
3178-2 47R
2 7
V
6
1
47R 3177-2
n
0
0
1
7
2
1
2
T111
T112
LNK_LNKON
T103
47R 3174-2 2 7
3 6
VD_D(8)
BEF_ALE
3177-3 3 6
22R 3181-3
1 8
47R
5
22R 3186-1
3173-4 47R 4
47R 3171-2 2 7
22R
3181-1 1 8
3122
22R
22R
T121
100n
3169
LNK_DATA(7)
BES_DQ(16)
2105
T137
T138
T135 T136
22R 4 5
) 3(
D
H _
F
E
B
4 5
3182-4
3187-4 22R
VD_D(4)
n
0
0
1
1
9
1
2
2 7
)5(
D
H_
F
E
B
DE_DD(14)
22R 3188-2
10K 3125
BES_DQ(3)
DE_DOW#
n
0
0
1
6
2
1
2
100R
3199
LNK_DATA(4)
BES_A(6)
DE_DD(0)
AUD_MCK
COM_FPSCK
13M5 AT-49
1101
2K2 3144
VD_D(3)
LNK_LREQ
LNK_RST#
n
0
0
1
5
7
1
2
BEF_HD(4)
BES_DQ(2)
BES_DQ(26)
BEF_HD(0)
n
0
0
1
5
5
1
2
K
0
1
VD_D(0)
BES_DQ(6)
5
6
3
1
3
3175-4 47R 4
n
0
0
1
4
5
1
2
BES_DQ(11)
BES_DQM(0)
BES_DQ(22)
3186-2 22R 2 7
10K 3123
D7
C7
D8
C8
B8
D9
C9
B9
B11
C11
D11
D10
B12
C12
D12
A11
A10
A8
7101-1
DMN-8602
VDEO
A9
B10
C10
BES_VREF
DE_DA(0)
BES_A(0)
3
0
1
3
0
K
1
0
K
1
2
0
1
3
1
0
1
3
0
K
1
5171
BLM18P
47R 1 8 3173-1
BEF_HD(1)
BES_DQ(8)
) 6(
D
H _
F
E
B
1K0
3198
3 6
BLM31
5141
8
22R 3186-3
3183-1 1
n
0
0
1
7
4
1
2
22R
47R 3173-2 2 7
3191
1K2 1%
n
0
0
1
2
2
1
2
3 6
n
0
0
1
4
4
1
2
BES_A(12)
3171-3 47R
LNK_CLK
AUD_SPDFO
n
0
0
1
5
4
1
2
BES_A(11)
BES_DQ(15)
1
7
1
2
V
5
2
u
0
1
2K2 3143
K
0
1
4
3
1
3
BEF_MA(4)
BLM18P
5162
0
K
1
4
0
1
3
DE_DOR# TU_OUT_0
2120
COM_SDA
22R 2 7
100n
TRST#
COM_TUNDET1
COM_TUNDET0
3183-2
VCR_CLK
VCR_CSN
TDO
TU_OUT_7
TU_OUT_6
TU_OUT_5
TU_OUT_4
TU_OUT_3
TU_OUT_2
TU_OUT_1
VO_CLK
TCK
TMS
3V3BE
TD
3V3BE
AUD_DAO(2)
3V3BE
LNK_PD
AUD_MUTE
SYSRST#
HDM_RSTN
3V3BE
5VBE
3V3BE
VCR_DA_N
VP_SDA
VP_SCL
3V3BE
VCR_DA_OUT
HDM_NT
1V8BE
2V5BE
3V3V
3V3BE
1V8D
2V5S
3V3BE
3V3BE
3V3BE
3V3BE
3V3BE
AUD_DAO(1)
AUD_DAO(3)
VD_RST#
3V3A
5VBE
1V8D 3V3V R
3
V
3
U
3
V
3
2V5S 3V3P 1V8C A
3
V
3
2V5S
1V8C
1V8BE
3V3P
3V3BE
3V3A
3V3BE
5VBE
3V3R
3V3BE
3V3U
3V3BE
3139_243_33442_130_1_a2.pdf2006-02-14
28 DVDR3380
PAINEL DIGITAL - MEMRIA
VSS
9
14
13
VSSQ
VDDQ
D
A
DQS
L
U
VDD
7 1
0
NC
10
11
AP
3
7
8
9
11
4
5
6
1
2
3
CLK
DM
U
L
VREF
10
CLK
4
BA
CS
5
2
CAS
WE
15
RAS
0
CKE
6
12
8
1
0
EN
C1
1D
VSS
9
14
13
VSSQ
VDDQ
D
A
DQS
L
U
VDD
7 1
0
NC
10
11
AP
3
7
8
9
11
4
5
6
1
2
3
CLK
DM
U
L
VREF
10
CLK
4
BA
CS
5
2
CAS
WE
15
RAS
0
CKE
6
12
8
1
0
EN
C1
1D 19

1
2
3
4
5
6
7
8
9
1
11
12
13
14
15
16
17
18
19
VSS
VDD

A
D
5
2
4
RB
E
CE
7
6
WE
3
1
RP

BYTE
21/11
C
A1
8
9
1
11
12
13
14
15
7211 C6
7231 C9
7292 F4
7293 H4
7294 H8
T201 D3
T202 D3
T203 F3
Memory
G
2214 B5
2215 A7
2216 B7
2217 B7
2218 B7
2219 B7
2220 D4
2221 D4
2231 B9
2232 B9
2233 B9
2234 B9
3294 H8
3295 I6
3296 H8
4291 H7
4292 H7
4293 H7
4294 I8
5201 B2
5291 F2
7201 C2
2 3 4 5 6 7 8 9 10 11 12 13
H
I
2201 D2
2202 D2
2203 D4
2204 D4
2205 D3
2211 B5
2212 B5
2213 B5
1 2
1
3 4 5 6 7 8
Back-end FIash (BEF)
Back-end SDRAM (BES)
F
G
H
I
A
B
C
D

E
F
2235 A10
2236 B10
2237 B10
2238 B10
2239 B10
2240 D8
9 10 11 12 13
A
B
C
D
E
2260 C13
2261 C13
2262 C13
2263 C13
2264 C13
2265 D13
2266 D13
2267 D13
2268 D13
2269 D13
2282 F13
2283 G13
2284 G13
2291 G2
2292 F4
2293 H4
2294 F8
3251-1 A12
3251-2 A12
3251-3 A12
2241 D8
2251 A13
2252 A13
2253 B13
2254 B13
2255 B13
2256 B13
2257 B13
2258 B13
2259 C13
3257-2 B12
3257-3 B12
3257-4 B12
3259-1 C12
3259-2 C12
3259-3 C12
3259-4 C12
3261-1 C12

2270 E13
2271 E13
2272 E13
2273 E13
2274 E13
2275 E13
2276 F13
2277 F13
2278 F13
2281 F13
3265-1 D12
3265-2 D12
3265-3 D12
3265-4 D12
3267-1 D12
3267-2 D12
3267-3 D12
3267-4 D12
3269-1 E12
3269-2 E12
3269-3 D12
3269-4 D12
3271-1 E12
3271-2 E12
3271-3 E12
3271-4 E12
3273-1 E12
3273-2 E12
3251-4 A12
3253-1 B12
3253-2 B12
3253-3 B12
3253-4 B12
3255-1 B12
3255-2 B12
3255-3 B12
3255-4 B12
3257-1 B12
7
3273-3 E12
3273-4 E12
3275-1 F12
3275-2 F12
3275-3 F12
3275-4 E12
3277-1 F12
3277-2 F12
3277-3 F12
3277-4 F12
3281-1 F12
3281-2 F12
3281-3 F12
3281-4 F12
3283 G12
3284 G12
3285 G12
3286 G12
3261-2 C12
3261-3 C12
3261-4 C12
3263-1 D12
3263-2 C12
3263-3 C12
3263-4 C12
3257-2 7 2
BES_DQS(2)
BES_DQS(3) BES_RAS#
BES_CAS#
BES_CE
BES_DQ(6)
BA(19)
BES_A(12)
BES_DQ(1)
8
100n 2281
3253-1 47R 1
BES_A(14)
BEF_HD(6)
47R 3261-4 4 5
4293
BES_DQ(27)
BEF_HD(9)
BES_DQ(14)
100n 2256
2255 100n
47 3294
BEF_HD(7)
BES_DQ(24)
2263 100n
BES_CE
BES_A(9)
BES_A(9)
BES_A(10)
47R 3285
2274 100n
BA(8)
BES_A(7)
BES_CS0#
BES_CLK1#
BES_VREF
BES_D(30)
BES_D(31)
47R 3275-3 3 6
2212 100n
100n 2239
BES_D(8)
BES_A(3)
BES_DM(2)
100n 2277
BEF_HD(5)
T203
BEF_HD(8)
BES_D(15)
BES_VREF
BES_D(17)
BES_A(5)
2 7
BES_D(13)
BES_D(26)
BEF_MA(22)
BES_A(2)
3251-2 47R
BES_D(5)
BES_D(22)
BES_A(4)
BES_A(5)
3296 4K7
BES_D(23)
BES_A(11)
BES_CKE
n
0
0
1
0
4
2
2
BES_CLK0#
BA(21)
BEF_MA(1)
1 8
BES_D(22)
BES_D(29)
47R 3257-1
BES_D(28)
BES_DS(0)
BES_D(18)
BES_D(12)
BEF_HD(7)
BES_WE#
BES_A(14)
BES_CS0#
2214 100n
47R 3265-1 1 8
BES_D(9)
BES_D(10)
BES_A(1)
3275-1 1 8
BES_D(31)
47R
8 VTT
BEF_HD(12)
50V 22u
2231
6 AVN
2
D
N
G
C
N
1
7 PVN
5
Q
D
D
V
4 VREF
3 VSENSE
BES_DQ(19)
LP2995
7201
BES_DQ(30)
BA(13)
BA(14)
BES_DQ(16) BES_DQ(21)
BES_A(6)
BES_A(7)
BES_DQ(20)
BES_WE#
BA(15)
n
0
0
1
4
0
2
2
4 5
BES_DQS(2)
BA(16)
3265-4 47R
47R 3 6
BES_DQS(1)
2 7
BES_A(15)
BES_A(8)
3267-3
BES_A(0)
47R 3261-2
BEF_HD(11)
100n
BES_DQ(26)
BES_CLK0
4
6
21
BA(19)
2266
5
5
1
6
49
4
3
8
4
6
6
6 2
1
2
5
8
5
42
23
47
51
1
8
1
3
3 3 9
5
1
54
56 20
16
14
17
19
25
43
50
53
59
60
62
63
65
5
7
8
10
11
13
26
27
22
44
45
46
24
2
4
57
30
28
41
31
32
35
36
37
38
39
40
7211
EDD1216AATA-5C-E
DDR

2Mx16
SDRAM
29 BES_A(0)
BES_DQM(0)
BES_CAS#
2270 100n
47R 2 7
BES_RAS#
BES_DQ(7)
3255-2
BEF_MA(2)
2293 100n
BES_A(12)
3
0
2
2
BES_DQ(6)
V
6
1
u
0
3
3
BES_DQ(13)
BA(16)
100n 2234
47R 3251-1 1 8
BES_VREF
BES_DQ(15)
2 7
4291
3 6
47R 3259-2
2 7
3281-3 47R
47R 3281-2
BES_DQ(12)
100n 2232
BEF_HD(12)
BES_DQM(0)
BES_DQ(11)
BES_DQ(17)
BES_DQ(18)
BES_DQ(19)
BES_DQ(1)
BES_DQ(21)
BES_A(2)
BA(9)
BES_A(15)
BA(11)
2233 100n
47R 3273-2 2 7
1
9
2
2
V
5
2
u
0
1
BES_RAS#
BES_A(5)
BES_A(6)
BES_A(9)
2283 100n
BA(20)
BES_A(3)
4292
47R 3277-2 2 7
BES_A(7)
BES_A(8)
BES_DQ(24)
BES_DQ(25)
2278 100n
BES_DQ(16)
100n 2276
2271 100n
n
0
0
1
5
0
2
2
4 5
BES_DQ(10)
BES_DQ(11)
3271-4 47R
7
BEF_HD(0)
BEF_HD(2)
BES_DQ(9)
47R 3269-2 2
3 6
BES_DQ(20)
BES_DQ(2)
BES_DQ(3)
BES_DQ(4)
47R 3255-3
3269-1 47R 1 8
47R 3267-4 4 5
15
14
13
12
0
2
BES_DQ(14)
7
8
9
0
1
11
1
19
18
17
16
74LVC573ADB
7292
2
3
4
5
6
BES_A(11)
BA(15)
3259-3 47R 3 6
BES_A(10)
47R 3271-1 1 8
BEF_HD(10)
BES_DQ(28)
BES_DQ(29)
BES_DQ(25)
BES_DQ(3)
BA(17)
BES_DQ(23)
100n 2265
1 8
BES_DQ(2)
3259-1 47R
100n 2269
2267 100n
100n 2268
1 8
BA(10)
3281-1 47R
BES_DQM(1)
2219 100n
2252 100n
BES_A(11)
4 5
100n 2251
BA(7)
BES_CLK1
3255-4 47R
3 6
BA(14)
BES_DQM(2)
BEF_MA(5)
3261-3 47R
BEF_MA(4)
100n 2254
47R 3 6
BEF_MA(3)
1 8
3277-3
3267-1 47R
100n 2262
n
0
0
1
1
2
2
2
BEF_HD(10)
8
BES_A(2)
100n 2264
BES_A(4)
3273-1 47R 1
BEF_HD(6)
100n 2294
4 5
BES_DQ(5)
BEF_HD(4)
BEF_HD(1)
BA(21)
47R 3253-4
BES_A(14)
4294
3 6
BES_DQM(3)
BES_CLK1#
BES_DQ(0)
BES_A(15)
47R 3251-3
BES_DQS(0)
4 5
n
0
0
1
2
0
2
2
2253 100n
3251-4 47R
4 5
BES_A(10)
3263-4 47R
n
0
0
1
1
4
2
2
BES_DQ(4)
T201
BA(20)
n
0
0
1
0
2
2
2
3 6
BA(18)
4 5
3269-3 47R
BES_DQ(0)
BES_DQS(3)
3275-4 47R
4 5
BA(12)
BES_VREF
47R 3273-4
3273-3 47R 3 6
BES_A(12)
BES_A(8)
BES_CLK0#
BES_CLK0
100n 2217
BEF_HD(13)
BES_A(4)
100n 2292
BA(8)
3284 47R
2235 100n
BEF_HD(8)
47R 3283
100n 2284
BES_A(6)
BEF_HD(1)
BEF_HD(2)
100n 2215
BEF_HD(9)
BEF_HD(14)
BEF_HD(11)
BEF_ALE
3 6
BES_DQ(8)
7
47R 3271-3
3271-2 47R 2
3286 47R
BEF_HD(3)
BEF_OE#
BEF_CS0#
2238 100n
3253-3 47R 3 6
47R 3253-2 2 7
5291
BLM18P
0
2
BA(12)
BA(11)
BA(10)
0
1
11
1
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
2
5
8
5
4
6
21
7293
74LVC573ADB
9
5
1
5
5
1
6
49
4
3
8
4
6
6
6 2
1
50
53
42
23
47
51
1
8
1
3
3 3
13
54
56 20
16
14
17
19
25
43
57
59
60
62
63
65
5
7
8
10
11
40
26
27
22
44
45
46
24
2
4
29
30
28
41
31
32
35
36
37
38
39
BES_DQS(1)
SDRAM
2Mx16

DDR
EDD1216AATA-5C-E
7231
BEF_HD(5)
BEF_HD(15)
22u 50V
100n 2213
BA(18)
BA(13)
2211
BES_DQ(7)
BES_DQ(27)
BA(17)
1 8
T202
BEF_HD(3)
BES_A(3)
3261-1 47R
2275 100,
-
2
2
1
0
2
2
V
0
5
2 7
BES+A(0)
BES+WE#
100, 2257
47R 3267-2
47R 3263-1 1 8
BES+CS0#
2216 100,
100, 2273
BEF+HD(14)
BES+DQM(3)
BA(7)
2260 100,
4 5
BEF+HD(0)
BA(6)
3 6
3257-4 47R
BES+CAS#
47R 3257-3
3295 10K
BES+A(1)
BEF+HD(4)
BES+DQM(1)
1 8
100, 2272
3277-1 47R
7
5201
BLM31
3275-2 47R 2
BES+CLK1
BEF+HD(13)
BES+A(1)
BEF+HD(15)
7
2
6
4
11
42
44
30
32
13
14
10
28
15
12
7
3
34
36
39
41
43
45
33
35
38
40
22
21
20
19
18
8
7
47
26
29
31
5
4
3
2
1
48
17
16
9
23 2M381M316
[FLASH]
25
24
6
47R 3265-3 3 6
M29W160ET70N6F
7294
3265-2 47R 2 7
47R 3259-4 4 5
4 5
1 8
47R 3281-4
BEF_ALE
47R 3255-1
2237 100n
100n 2236
3 6
BEF_WE#
BA(9)
2 7
47R 3263-3
3263-2 47R
4 5
100n 2218
5
47R 3269-4
47R 3277-4 4
2261 100n
BA(6)
2282 100n
2258 100n
100n 2259
3V3F
BA{BA(621)}
3V3F
3V3F
S)SRST#
2V5D
VTT 2V5D
S)SRST#
3V3F
3V3F
2V5D
2V5D
VTT
2V5BE
2V5D
2V5D 2V5D
3V3F
3V3F
3V3BE
3139_243_33442_130_2_a2.pdf 2006-02-14
29 DVDR3380
PAINEL DIGITAL - CAMADA FISCA IEEE1394
0
1
R
0
1
FLTER
DGND
LKON
D
PC
CTL
D
D
V
L
L
P
S
H
_
D
N
G
AGND
DVDD
D
N
G
L
L
P
AVDD
TPA+
TPA-
TPB+
TPB-
7
6
5
4
3
2
1
0
1
0
LREQ
SYSCLK
RESET
PD
TPBAS 0
1
C
2
XO
SO
LPS
TESTM
SE
SM
CPS
X
12 13
1
I
A
B
C
D
E
F
G
H
I
1351 D5
2301 D6
2302 D6
2303 D6
2 3 4 5
1 2 3 4 5 6 7 8 9 10 11
IEEE1394 PhysicaI Layer
B
C
D
E
F
G
H
IEEE1394 Link - PhysicaI (LNK)

)
Y
H
P ( t r
o
p
s
n
a r
T - I
a
ci
s
y
h
P
4
9
3
1
E
E
EI
3302 F5
3303 G8
3304 G8
3305 E8
3306 F7
3307 F7
3308 F7
6 7 8 9 10 11 12 13
A
T302 E7
T303 E7
T304 E7
T305 E7
T306 E7
T307 E7
T308 F7
2304 D6
2305 D7
2306 D7
2307 D7
2321 G5
2341 G9
2343 G9
2351 D5
2352 E5
2361 E5
3301 E5
T313 E7
T314 E7
T315 F6
T316 F6
T331 C6
T351 E6
T352 E6
3321 F5
3322 G5
3331 F5
3332 F5
3341 F9
3342 F9
3343 F9
3344 F9
3345 G9
3351 E5
3360 E5
3361 E5
3362 E5
4361 E6
5301 C6
7301 D6
T301 E7
T309 E7
T310 F6
T311 F7
T312 E7 T309
Y_TB
10 3303
3305 68R
5301
B18
T315
680R 3307
1
22
30
29
28
27
31
42
43
18 12
1
4
0
4
33
34
37
23
24
4
4
5
4
38
39
9
4
19
13
48
16
17
5
6
7
8
9
10
11
4
1
6
4
7
4
1
2
6
2
2
3
6
3
5
2
5
3
20
2
3
15
4
TRNCVR
RBTR

1RTCB
TSB41B1
7301
10 3301
T304
3362 10
100u
2301
N_T1 T302
6.3V
T312
N_T0
1 56 3331
N_CT1
T351
3302 10
N_R!

1
1

5
5
4
3
3
N_S
p
0
2
2
3
4
3
2
2
4
3
3

1
R
6
5
100n 2302
33p 2351
T308
2307 100n
100n 2361
10 3361
3
4
3
3

1
R
6
5
%303
T316
LNK_DATA(5)
3306 680R
T314
PHY_TPA+
0
/
1
1
4
3
2
n
0
0
1
1
2
3
2
100R 3321
0
M
1
1
5
3
3
3304 10K
T311
LNK_DATA(6) T307
7
K
4
2
2
3
3
LNK_CTL0
LNK_PD
T313
100n 2305
100n 2304
750R 3332
24M576 AT-49
1351
1%
%
1
R
6
5
4
4
3
3
T310
T331
T301
T306
T352 2352 33p
LNK_DATA(3)
PHY_TPA-
PHY_TPB-
3308 680R
LNK_DATA(7)
LNK_DATA(2)
LNK_DATA(4) T305
LNK_CLK
4361
LNK_LNKON
2306 100n
%
1
R
6
5
1
4
3
3
3360 1K0
2303 100n
3V3
3V3
LNK_RST#
3V3
3V3
3V3BE
3V3
3V3
3139_243_33442_130_3_a2.pdf 2006-02-14
30 DVDR3380
PAINEL DIGITAL - PROCESSADOR DE ENTRADA DE VDEO

V
8
1
A
_
4
H
C
D
D
V
3
3
A
_
3
H
C
D
D
V
8
1
A
_
3
H
C
D
D
V
3
3
A
_
2
H
C
Y
GPO<0:14>
RED
GREEN
BLUE
VBLK
FSO
D
N
G
8
1
A
_
2
H
C
D
N
G
3
3
A
_
2
H
C
D
N
G
8
1
A
_
3
H
C
D
N
G
3
3
A
_
3
H
C
D
N
G
8
1
A
_
4
H
C
F
E
R
_
D
N
G
8
1
A

S
H
_
D
N
G
D
N
G
A
D
N
G
8
1
A
_
1
H
C
D
N
G
3
3
A
_
1
H
C
PDN
OVDD
D
D
V
8
1
A
_
1
H
C
K
DVDD
D
D
V
3
3
A
_
4
H
C
D
N
G
8
1
A
_
L
L
P OGND
CL
V_1_A
V_1_B
V_1_C
V_2_A
V_2_B
V_2_C
V_3_A
V_3_B
V_3_C
V_4_A
D
D
V
8
1
A
_
L
L
P
EEB
DA
XAL1
XAL2
D
D
V
8
1
A
_
2
H
C
D
D
V
3
3
A
_
1
H
C
V
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VA_SC_RE_3
VA_CVBS_TU_3
VA_RPr_3
VA_SY_RE_3
VA_SY_FR_3
VA_GY_3
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31 DVDR3380
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T583 G5
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T587 G5
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T590 H5
T591 H5
T592 H5
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T545 B12
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T527 B8
T528 B8
T529 B8
T530 B8
T531 B8
T532 C8
T533 C8
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T537 A12
T538 A12
T539 A12
T540 A12
T541 A12
T542 A12
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3579-4 H6
3580 H6
3581 H6
3582 H6
3583 H6
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3584-2 I6
3584-3 I6
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PHY_TPA-
COM_SCL
3511-4 33R
3541 22R
DE_DD(14)
COM_RDYFM
7
K
4
8
6
5
3
VA_SC_FR
T576
COM_DHOST
DE_NTRQ
1K0 3561
p
2
2
2
4
5
2
T562
DE_DD(5)
DE_DD(10)
VOA_BPb
VOA_CVBS
T506
33R 2 7
DE_DA(0)
DE_RST#
3576-2
3579-4 4 5
T517
DE_DA(2)
COM_SDA
33R
DE_DD(7)
3560 1K0
DE_DMARQ
AUD_WCKO
3557 22R
22p 2581
6
2578 22p
33R 3574-3 3
T511
T607
3 6
T528
3573-3 33R
n
0
0
1
5
9
5
2
0
6
7
T
A
B
5
0
5
6
PHY_TPA+
T509
T566
12
2
3
4
5
6
7
8
9
1501
B12P-PH-K
1
10
11
8 6
T628
L5973D
7521
4
5
7 9
3
1
2
T692

T691
33R
T550
3509
BLM31
5518
V
6
1
u
0
2
2
1
1
5
2
2582 22p
COM_USBOC
BLM31
AUD_MUTE
5521
7
15K 3505
3575-2 33R 2
p
2
2
7
4
5
2
3562
22R 3591
22R
22R 3593
VA_SY_RE
T526
3571 10K
VA_CVBS_FR
3 6
T564
33R 3579-3
PHY_TPB-
3594 22R
AUD_WCK
T547
22R 3538
AUD_MCKO
3592 22R
3574-1 1 8 33R
3508 33R
VA_SC_RE
3518 33R
T600
DE_DD(15)
33R 3511-1
n
0
0
1
7
1
5
2
T613
5
2
5
3
0
K
1
2574 22p
2585 22p
2580 220p
22p 2573
1
2
3
4
5
6
AUD_DA(0)
1513
B6B-PH-K
T571
T611
22R 3535
T533
T572
3514 33R
T529
2576 220p
T548
T549
22R 3539
1
2
5
2
V
6
1
u
0
3
3
T559
COM_USBP
p
2
2
8
4
5
2
COM_DFM
24
3
4
5
6
7
8
9
15
16
17
18
19
2
20
21
22
23
1
10
11
12
13
14
T636
HLW24S-2C7
1537
PHY_TPB+
DE_DD(12)
AUD_BCKO
n
0
0
1
0
2
5
2
DE_DD(3)
CHASSS1
V
6
1
u
0
2
2
8
1
5
2
DE_DD(9)
2
2
5
3
%
1
K
2
1
T567
T543
3 6
AUD_MCK
T545
3576-3 33R
8
33R 3572
33R 3579-1 1
T575
22R 3503
33R 3507
3504 22R
1 8
T577
33R 3584-1
T693
T522
T531
T614
1K0
3524
9
3536 22R
35
36
37
38
39
4
40
5
6
7
8
26
27
28
29
3
30
31
32
33
34
16
17
18
19
2
20
21
22
23
24
25
40FLZ-RSM2-R-TB(LF)(SN)
1511
1
10
11
12
13
14
15
T592
n
0
0
1
3
1
5
2
DE_DMACK#
CHASSS4
7
p
2
2
9
4
5
2
33R 3573-2 2
n
0
0
1
6
2
5
2
1
2
5
3 R
0
4
2
T612
%
1
T695
T696
T694
22p 2575
n
0
0
1
9
1
5
2
2
0
5
3
K
0
1
COM_USBM
3 6
AUD_DAO(0)
T557
5
33R 3575-3
3575-4 33R 4
VA_RPr
DE_DA(1)
COM_USBPO
T632
CHASSS2
T504
1%
T579
3523
5K6
T589
3534 22R
T629
3583 680R
2
3
4
5
6
7
8
9
1
10
11
12
13
14
15
16
17
T620
1552
HLW17S-2C7
VOA_RPr
T641
T642
T623
VA_CVBS_RE
10K 3501
T553
33R 3519
T595
4 5
n
0
0
1
2
2
5
2
3584-4 33R
T505
T596
7515
LD29150DT25R
2
1 3
2
0
5
6
0
6
7
T
A
B
0
6
7
T
A
B
1
0
5
6
n
0
0
1
8
0
5
2
6
0
5
2
n
0
0
1
7
0
5
2
n
0
0
1
n
0
0
1
CHASSS3
T615
6
1
5
2
p
2
2
2
6
5
2
p
2
2
1
6
5
2
3564 22R
3566 22R
DE_ORDY
T637
22R
T622
T558
3540
33R 3513
T621
T634
T555
DE_DOR#
T631
T630
T586
1
0
5
4
T534
7
3531 22R
COM_FPSCK
3579-2 33R 2
T582
COM_ATNFM
T583
T633
5514 BLM31
COM_TUNDET1
7522
BC847B
COM_FAN
COM_8SC2_2
COM_8SC2_1
COM_FBN
COM_ANSEL1
5V
12V
HDM_RSTN
AUD_DAO(1)
AUD_DAO(3)
AUD_DAO(2)
HOSTRST#
VCR_DA_N
VCR_DA_OUT
VCR_CLK
VCR_CSN
HDM_RSTN
COM_TUNDET0
COM_ANSEL0
VO_CLK
HDM_NT
SYSRST#
1V8BE
2V5BE
HOSTRST#
COM_SDA
COM_SCL
AUD_BCKO
AUD_MCKO
AUD_SPDFO
AUD_WCKO
AUD_DAO(0)
3V3
TU_OUT_3
TU_OUT_4
TU_OUT_5
TU_OUT_6
TU_OUT_7
5V
3V3
5V
5VN
5VBE
3V3BE
5VBE
5VBE
5V
V
5
5V
3V3BE
5VBE
TU_OUT_0
TU_OUT_1
TU_OUT_2
3139_243_33442_130_5_a2.pdf 2006-02-14
32 DVDR3380
PAINEL DIGITAL - LAYOUT PARTE PRINCIPAL ( SUPERIOR)
TopView_DigitalBd_32683.pdf 2005-11-18
33 DVDR3380
PAINEL DIGITAL- PARTE PRINCIPAL (INFERIOR)
BottomView_DigitalBd_32683.pdf 2005-11-18
34 DVDR3380
UNIDADE FONTE DE ALIMENTAO - ESQUEMA ELTRICO
35 DVDR3380
8.1 Painel PSU
8.1.1 Geral

Figura 8-1 Layout do painel PSU
O painel PSU provm as seguintes conexes para o resto do aparelho:
Conector A: Fonte/Sinal para o painel analgica con. 1401
Serve como alimentao para o Painel Digital.
Conector B: Fonte/Sinal para Painel Analgico con. 1402
Serve como 12VBE para o Painel Digital, alimentado apenas por
acionamento das linhas Standby do transistor 7421 (Painel Anal-
gico)
S O cabo eltrico dever estar desconectado do aparelho antes
da realizao dos procedimentos mencionados abaixo:
A PSU projetada com proteo de curto-circuito que ir desligar
a fonte de alimentao. Quando isso acontecer, a tenso armaze-
nada no capacitor C1 e C40 ir impedir que a fonte de alimenta-
o ligue, consequentemente eles devem ser descarregados com
uma chave de fenda com isolante de alta tenso, antes que a PSU
funcione normalmente novamente.
Nota: Durante este processo de descarga dos capacitores, poder
ocorrer fascas, o que tpico de alta tenso armazenada no capa-
citor C1 e C40.
8. Circuito e Descries de IC
Pin no. Supply / Signal Remarks
1 12V
2 GND
3 5V
4 3.3V
5 GND
Pin no. Supply / Signal Remarks
1 VGN
2 5N
3 GND
4 IP_FAIL HIGH>4.0v = power good
LOW<4.0v =power fail
5 GND
6 12V
36 DVDR3380
8.2 Painel Frontal (Painel - Display + Chave)
8.2.1 Geral
O painel consiste das seguintes partes:
Driver de Controle FIP
Frontend (udio e Vdeo)
VFD Gerador de tenso de aquecimento
8.2.2 Driver de Controle FIP (IC 7105: UPD16316GB)
O ncleo do Display Frontal + Teclado o Driver de Controle FIP,
isto liga uma fonte 5V e responsvel pelas seguintes funes:
Interagir com o chip Domino no Painel Digital
Avaliao da matriz teclado dentro do Painel Frontal
Decodicar os comandos do controle remoto do receptor de
infra vermelho
Ativao e controle do display
Ativao do Wake-Up Temporizador
Segue duas frequncias de pulsos de disparo:
5MHz para operaes normais
32.768KHz para tempo real no relgio
8.2.3 Interface com Domino chip
Este comunica-se com o Domino Host no painel digital via inter-
face serial sincronizada 6-os. O Host sempre o mestre para
gerar a comunicao clock com o Driver de Controle FIP sem se
relacionar com a direo da transferncia de dados.
8.2.4. Avaliao da matriz do teclado
A tecla matriz usada no painel frontal. O slave P faz o esca-
neamento da tecla com FIP9 - FIP24 (pino 23-26 e 29-40) como
sada e KEY_A-KEY_C (pino 41-43) como entrada. Cada tecla
atribuda a um cdigo de tecla baseado nas portas de entrada e
sada, e o Driver de Controle FIP ir avaliar pelo cdigo da tecla.
8.2.5. Receptor IR e avaliao de sinal.
O receptor IR no painel frontal contm um amplicador seletiva-
mente controlado assim como um fotodiodo. O fotodiodo trans-
forma a recepo da transmisso de infra vermelho para pulsos
eltricos, os quais so amplicados e demodulados. Na sada do
receptor IR, uma sequncia de pulso com o nvel TTL, que corres-
ponde a curva envelope do comando IF do controle remoto pode
ser medido. Esta sequncia de pulso alimentada no Driver de
Controle FIP para processos posteriores via pino 13.
8.2.6. Display Florescente a vcuo [1203: HUV-08SS65T]
O VFS totalmente controlado e dirigido pelo Driver de Controle
FIP.
8.2.7. VFD Gerador de tenso de aquecimento
O circuito oscilador fornecido pela [5100, 2101, 2102 & 7100]
fornece o transistor do sinal da onda do seno [7101, 7102 & 7103]
para gerar 50% duty-cycle 48Khz AC formas de ondas para o
lamento do VFD.
8.2.8. Ativao do temporizador Wake-up
Durante o modo Standby, o Driver de Contole FIP fornece um
servio de despertador (POWER_CTL-linhas mudam para alto),
ento o Domino Host (no painel digital) inicia e pede pela razo do
Wake-up.
8.3. Painel Analgico
8.3.1. Geral
A PCBA consiste das seguintes partes:
Controle de ventilao
Tuner frontend
udio ADC/DAC
8.3.2. Controle de ventilao
O laser no OPU do driver muito sensvel as temperaturas. Por
esta razo, um circuito de controle de ventilao [7802 & 7803] foi
instalado no painel. O ventilador est ligado quando o aparelho
est no modo ATIVO, e desligado quando a bandeja est aberta.
Quando o aparelho est no modo Standby, o ventilador desli-
gado. O controle do ventilador vm do painel digital.
8.3.3. Tuner Frontend [1100 : TMQZ2]
O painel analgico suporta 2 possveis unidades de Tuner Fron-
tend chamadas:
1101 - PAL BG, DK e I Broadcast System
1100 - NTSC-M Broadcast System
Contm uma entrada RF para conexo com antena e sada RF
que fornece um RF loop through para conexo com TV.
O Frontend (Tuner e IF-demodulador) so controlados por 12C
(SCL_5V- e SDA_5V-) linhas providas pelo Domino Host no painel
digital.
O processamento de vdeo completo feito nesta unidade e a
sada de vdeo (CVBS) feita do pino [VIDEO_OUT] via transis-
tor pino 13 como CVBS_TV-line para o circuito de vdeo I/O. O
componente de udio-IF SIF1 so feitos do pino [SIF_OUT] pino
10 por demodulao pelo processador Multi-sound (MSP).
Demodulador de udio
A demodulao de udio feita pelo MSP3425 [7304], que
tambm totalmente controlado via barramento 12C pelo Domino
Host. Os sinais de udio so disponveis no pino 30 e pino 31
e alimentados como AIA_R_MSP & AIA_L_MSP line para o udio
I/O para processamentos posteriores.
37 DVDR3380
8.3.4 Roteador de udio
Figura 8- 2 udio Analgico IO
1
U
D
A
1
3
6
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38 DVDR3380
O processameto de udio sempre feito em stereo (isso signica
separao entre os canais direito e esquerdo) e a troca completa
realizada usando HEF4052, que um duplo multiplexer quatro por
um e MSP3415G, processador Multi-sound.
a) Trajeto de gravao
A seleo completa de sinal de udio para gravao feita por
HEF4052 [7201], que um duplo multiplexer quatro por um. As
linhas de entrada para o seletor [7301] so providas pelo MSP
[7304] (AIA_LMSP/AIA_R_MSP) ou entrada de cinch traseiro (Ext
AIA_R_RE1AIA_L_RE1) ou a entrada de cinch frontal (AIA_RFR/
AIA_L)FR). O [7201] controlado via sinais RSA 1- e RSA 2- provm
do MSP [7500]. O MSP atua como uma porta expansora do Driver
de Controle FIP. O Op-Amp na sada [7201] necessrio para
razes de desempenho e atua tambm como um driver. Os sinais
selecionados ALADC* e ARADC* so diretamente alimentados
pelo udio-ADC. Como existe tambm uma quinta entrada (DV-in),
os correspondentes sinais de udio (ALDAC*/ARDAC*) do painel
digital so distribudos via MSP [7304] e sada como AIA_R_FR/
AIA_L_FR para seletor [7201]
b) Sada de cinch
O Multiplexer (HEF7201) seleciona sinais de poucas fonte, cha-
madas Cinch Frontal de Entrada (AIA_R_RE1/AIA_L_RE1) Cinch
Frontal de Entrada (AIA_R_FR/AIA_L_FR) e MSP (AIA_L_MSP/
AIA_R_MSP). O multiplexer controlado via sinais RSA 1 e RSA 2
vindos do MSP.
c) Trajeto de sada digital de udio.
Adiconado sada analgica o aparelho tambm equipado com
sada de udio digital via plug cinch [1131]. O sinal gerado no
painel digital e distribudo via cabo de interface de udio e conec-
tor [1600] para o painel analgico. Aqui o DAOUT-line primeiro
passa por um inversor 6-fold [7700] usado como um driver e para
razes de performance (reduo de rudo, jittler, etc.).
8.3.5. Audio ADC/DAC
A converso de sinais analgicos de udio (ALADC*/ARADC*)
do seletor de gravao [7201] feita via AID_DAT [7203]. Este IC
pode processar sinais de entrada at 2Vrms utilizando resistores
externos em srie com os pinos de entrada. Todos os sinais de
clock exigidos so gerados no painel digital e somente os dados
de udio (AID_DAT) so distribudos do analgico para o painel
digital para processos posteriores.
A transformao de udio digital para analgico feita por CS4351
[7206]. Todos os sinais clock necessrios provm do painel digital
e dados de udio digital, (D_DATA0-line) so convertidos em sinais
analgicos (pino 15 e 18). Os sinais de sada da parte udio DAC
(AOUTA/AOUTB) so diretamente distribudas para os soquetes
cinch traseiros. Para evitar plops e outros rudos audveis, existe
na sada um estgio mute implementado para cada canal. A ativa-
o da funo mute feita via AMUTEC e BMUTEC (mute digital
de silncio) do udio DAC e tambm a linha AKILL que uma
combinao de D_KILL do painel digital e POWER_FAIL da fonte
de alimentao.
*Nota: ALADC refere-se ao VINL do IC7203
ARADC refere-se ao VINL do IC7203

39 DVDR3380
8.3.6 Roteamento de vdeo
Figura 8-3 Vdeo Analgico IO
V
i
d
e
o

I
O

T o d i g i t a l b o a r d
Y
_
R
E
A
R
C
V
B
S
_
R
E
A
R
C
_
F

N
Y
_
F

N
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A
R

N
-
1
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(
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U

(
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U

(
P
b
)
V
i
d
e
o

I
O

N
A
F
T
A
T o d i g i t a l b o a r d
A
_
V
R
E
A
R

N
-
E
X
T
1
Y
V

(
P
r
)
U

(
P
b
)
R
E
A
R

O
U
T
1
Y
V

(
P
r
)
U

(
P
b
)
F r o m d i g i t a l b o a r d
V

A
_
R
P
r
V

A
_
B
P
b
V

A
_
G
Y
V
O
A
_
S
Y
V
O
A
_
S
C
C
V
B
S
F R O N T N
Y
/
C
Y
_
R
E
A
R
C
_
R
E
A
R
W
S
R

t
o

C
U
C
V
B
S
_
R
E
A
R
C
V
B
S
R E A R N - E X T 2
A
_
Y
C
V
B
S
_
F

N
A
_
U
C
_
R
E
A
R

D
_
C
V
B
S
T
U
N
E
R
R E A R O U T 2
C
V
B
S
R
_
O
U
T
R E A R O U T
S - C O N N
Y
/
C
W
S
R
O

C
R
_
O
U
T
V
Y
_
O
U
T
C
V
B
S
_
T
V
40 DVDR3380
A mudana das variadas entradas de sinais de vdeo so feitas
pelo Processador de Entrada de Vdeo no painel digital. Estes
sinais so diretamente distribudos para o painel digital pelo
conector 1122 no painel analgico.
8.4. Painel Analgico
O painel digital baseado na alta integrao LSI Domino chip
BGA (Ball Grid Array), DMN-8652. Este IC contm 2 chips internos
ATAPI controlado e integrado a um codicador de vdeo, e fornece
suporte interno para no-simultneo progressivo e interlaada
sada de vdeo. Um funo camada de link 1394 tambm
integrada, exigindo somente um dispositivo externo simples da
camada fsica. O painel codica e multiplexa vdeo analgicos e
descompressa udio digital (I2S) em corrente MPEG2.
Esta corrente MPEG2 formatada para gravao pelo DVD+RW.
Na reproduo, o painel ir decodicar o vdeo MPEG2 em vdeo
analgico. Adicionando, uma corrente DV pode ser recebida via
IEEE 1394 (i-link), e transformada para o formato MPEG2.

8.4.1 Modo de gravao
Figura 8-4 Bloco Domnio
(1) analogue CVBS / YC and RGB/YUV
(2) analogue CVBS, YC, RGB/YUV
DDR SDRAM
16M X 16Bit
TO/FROM FRONTEND PART
ATAP

VP
TVP5146
1394
TSB41AB1
DMN 8652
7101
1FH VDEO
OUT
(2)
DG. AUDO OUT

2
S AUDO OUT

2
S AUDO N
1FH VDEO N
(1)

2
C
7401
TU656
CLOCK
7304
1512
For DV-in version only
FROM POWER SUPPLY
5V 12V 3V3
1394
CONNECTOR
FLASH
16M Bit
7211/7231
7294
13.5MHz
41 DVDR3380
Parte Vdeo
Os sinais de entrada de vdeo digital do DV no painel frontal so
distribudos do conector 1521 via IEEE 1394 PHY IC [7301] para o
chip Domino [7101]
O Processador de Entrada de Vdeo codica o vdeo analgico
para a corrente de vdeo digital (fotmato CCIR656). A corrente de
sada, chamada VID_D ( 9 : 0 ), ento distribuda para o chip
Domino. Este IC codica e decodica a corrente de vdeo digital
em/para o formato MPEG2.
Parte udio
udio I2S enviada painel analgico para o chip Domino via
conector 1536.
O chip Domino comprime o dado de udio I2S em uma corrente de
udio MPEG1-L2/AC3.
Front-end I2S
O chip Domino interage diretamente com o motor bsico via ATAPI
conector 1571.
Isto armazena as correntes de dados que vem (ou vo) do motor
bsico.
No chip Domino, a corrente de vdeo MPEG2 e a corrente de
udio AC3 so enviadas para o motor bsico para gravao por
barramento ATAPI.
8.4.2. Modo Reproduo
Durante a reproduo, os dados do motor bsico vo diretamente
para o chip Domino via interface ATAPI. O chip Domino tem as
seguintes sadas:
Vdeo analgico CVBS, YC e sadas RGB no conector 1521
udio I2S (formato PCM) no conector 1536
udio SPDIF (sada digital de udio) no conector 1536

8.4.3. Interface Motor Bsico
O painel digital est equipada com um barramento IDE (ATAPI)
para conexo com o motor bsico.
O chip Domino tem um complexo sistema, que necessrio para
suportar a execuo do processo nas diferentes frequncias
assim como na decodicao de vdeo, decodicao de udio
ou dispositivos perifricos I/O etc. Para assegurar uma iniciao
sincronizada de todos os registros e o estado das mquinas, todos
os PLLs so trocados para suas frequncias padro 27MHz.
Ento quando a unidade de controle carregada foi corretamente
inicializada e uma vez capturou todos os parmetros carregados,
ajusta os PLLs as suas frequncias funcionais. Graas a um
mecnismo de bloqueio do clock, o chaveamento da frequncia
grtis.
Sistema de Clocks:
DMN-8652 (7101, pino A1 e A2) : 13.5MHz fornecidos pelo xtal
1101
DMN-8652 1394-LINK (7101, pino K1) : 49.152MHz fornecidos
pelo 1394-PHY
TVP5146 (7401, pino 74 e 75) : 14.31818MHz fornecidos pelo
xtal 1461
SDRAM (7211 e 7231, pino 45 e 46) : 150MHz fornecidos pelo
DMN-8652
TSB41AB1PHP IEEE 1394 PHY IC (7301, pino 42 e 43) :
24.576MHz fornecidos pelo xtal 1351
8.4.4 Distribuio de clock
Figura 8-5 Dominio_Clock
FRONTEND NTERFACE

VP
TVP5146
DMN 8652
7101
7401
7301
1934 PHY
24.576 MHz
14.31818MHz
13.5 MHz
7211
SDRAM
7231
SDRAM
150 MHz
42 DVDR3380
8.4.5. Fonte de alimentao
O painel digital no tem energia no modo Standby. O sinal de con-
trode STBY no painel digital habilita a PSU e a energia no painel
digital.
STBY = Baixo: o painel digital est desligada no modo Standby.
STBY = Alto: a fonte de alimentao para o painel digital est
habilitada.
O 3V3, +5V +12V vem da PSU, enquanto as seguintes tenses
so geradas no painel digital:
O ncleo da tenso 1.8V gerado no painel por um regulador
de tenso baixo 2A [7521]
A fonte 2.5V da SDRAM gerada por um regulador linear de
sada baixa ultra rpida[7515]
A fonte 1.25V DDR gerada pelo regulador [7201]

8.4.6. Memria
FLASH IC7294 : esta memria contm os parmetros de carga e
aplicaes rmware.
Conceito Reset no painel digital
O resto do circuito [7595] cuida para que dispositivos diferentes
no painel digital seja reinicializado na ordem correta. A energia no
circuito reset fornece os seguintes resets (delay 1 ):
SYS_RST# para o chip Domino [7101] e memria FLASH
[7294]
O chip Domino ento gera outros sinais de reset (delay 2) via
seus GPIOs:
VID_RST# para resetar o VIP [7401]
LINK_RST# para resetar o IEEE 1394 DV PHY IC [7301]
IDE_RST#_1 para resetar o Motor bsico

8.4.8. Conector I/O
Conector udio IO (item 1563)
O conector de udio IN/OUT (AIO) utilizado para intercambiar os
sinais de udio digital entre os paineis analgico e digital.
Conector Vdeo IO (item 1521)
O conector de vdeo IN/OUT (VIO) utilizado para intercambiar os
sinais de vdeo anlogos entre os paineis analgico e digital.
8.4.7 Reset
Figura 8-6 Dominio_Reset
DMN 8652
Delay t
1
Basic Engine
VAD8041
Delay t
2
VP (TVP5146)
Delay t
2
PD1394P25BD
Delay t
2
FLASH MEMORY
Delay t
1
POWER ON
RESET & LOW
VOLTAGE
DETECTON
NCP303LSN30
C7595
HOSTRST
5V Supply
FRONT
MCROPROCESSOR
RSTn
SYSRST#
LNK_RST#
VD_RST#
VP_RST#
DE_RST#_1
43 DVDR3380
8.5. Descrio do IC
8.5.1. Painel Analgico
IC7304 - Famlia Processador de udio Multistand

Diagrama em bloco
Figura 8-7

DCTRI/O-1
DCTRI/O-0
SC1OUTR
SC1OUTL
I2SDAOUT
DACMR
DACML
26
27
16
30
31
8
9
ANAIN
ANAIN-
I2SDAIN1
I2SDAIN2
ASG
SC1INL
SC1INR
SC2INL
SC2INR
MONOIN
ADRSEL
I2CCL
I2CDA 13
12
10
43
37
38
40
41
39
21
17
2
3
18
A
D
R

C
L
I
2
S

W
S
X
T
A
L

I
N
I
2
S

C
L
X
T
A
L

O
U
T
14 15 5 6
A
V
S
S
44
A
H
V
S
S
A
G
N
D
C
D
V
S
S
V
R
E
F
1
V
R
E
F
2
V
R
E
F
T
O
P
R
E
S
E
T
Q
S
T
A
N
D
B
Y
Q
T
E
S
T
E
N
T
P
7 4 11 22 42 25 29 20 36 35
C
A
P
L

M
34
D
V
S
U
P
A
V
S
U
P
A
H
V
S
U
P
33 19 1
N
.
C
.
23 24 28 32
N
.
C
.
N
.
C
.
N
.
C
.
De-
Modulator
Pre-
processing
Source
select
Pre-
processing
ADC
ADC Prescale
SCART
DSP
input
select
Loud-
speaker
sound
proeessing
Loud-
speaker
sound
proeessing
DAC
DAC
SCART
Output
select
X'tal
Oscillator
I
2
S
Control
I
2
C
Control
ADR BUS
44 DVDR3380
CONFIGURAO DO PINO
IC7206 - 192KHz Stereo- DAC com 2vrms line-out
DIAGRAMA EM BLOCO
Figura 8-8
Figura 8-9
PMQFP44 package
CAPL_M
AHVSS
AGNDC
SC2_N_L
SC2_N_R
ASG
SC1_N_L
SC1_N_R
VREFTOP
MONO_N
AVSS
RESETQ
2S_DA_N2
DVSS
DVSUP
ADR_CL
2S_DA_N1
2S_DA_OUT
2S_WS
2S_CL
2C_DA
2C_CL
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
AHVSUP
DACM_L
DACM_R
VREF2
NC
NC
ANA_N1
ANA_N
TESTEN
XTAL_N
XTAL_OUT
AVSUP
TP
D_CTR_/O1
D_CTR_/O0
ADR_SEL
STANDBYQ
MSP 34x5G
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
FCM
Serial
nterlace
nterolation
Filter with
volume Control
nternal voltaqe
Relerence
External
Mute
Control
BAC
Serial Audio nut
Lelt and Riqht
Mute Controls
2 vrms Line Level
Riqht Channel
0utut
2 vrms Line Level
Lelt Channel 0utut
Reset
1.8 v to 8.8v
BAC
Reqister/hardware
Conliquration
L
e
v
e
l

T
r
a
n
s
l
a
t
o
r
hardware or
2
C/SF
Control Bata
Multibit
Modulator
8.8 v
O v to 12 v
nterolation
Filter with
volume Control
Am
+
Filter
Am
+
Filter
Auto Seed Mode
Betect
Multibit
Modulator
45 DVDR3380
DESCRIO E CONFIGURAO DO PINO
Pin Name # Pin Description
SDIN 1 SeriaI Audio Data Input (nput) - nput for two's complement serial audio data.
SCLK 2 SeriaI CIock (nput) - Serial clock for the serial audio interface.
LRCK 3 Left / Right CIock (nput) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK 4 Master CIock (nput) - Clock source for the delta-sigma modulator and digital filters.
VD 5 DigitaI Power (nput) - Positive power supply for the digital section.
GND 6
16
Ground (nput) - Ground reference.
RST 10
Reset (nput) - Powers down device and resets all internal resisters to their default settings when
enabled.
VA 11 Low VoItage AnaIog Power (nput) - Positive power supply for the analog section.
VBIAS 12 Positive VoItage Reference (Output) - Positive reference voltage for the internal DAC.
VQ 13 Quiescent VoItage (Output) - Filter connection for internal quiescent voltage.
VA_H 17 High VoItage AnaIog Power (nput) - Positive power supply for the analog section.
VL 20 SeriaI Audio Interface Power (nput) - Positive power for the serial audio interface
BMUTEC
AMUTEC
14
19
Mute ControI (Output) - Control signal for optional mute circuit.
AOUTB
AOUTA
15
18
AnaIog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris-
tics table.
ControI Port
Definitions
SCL/CCLK 7 SeriaI ControI Port CIock (nput) - Serial clock for the control port interface.
SDA/CDIN 8 SeriaI ControI Data (nput/Output) - nput/Output for
2
C data. nput for SP data.
AD0/CS 9
Address Bit 0 / Chip SeIect (nput) - Chip address bit in
2
C Mode. Control Port enable in SP mode.
Stand-AIone
Definitions
DIF0
DIF1
8
7
DigitaI Interface Format (nput) - Defines the required relationship between the Left Right Clock, Serial
Clock, and Serial Audio Data.
DEM 9 De-emphasis (nput) - Selects the standard 15s/50s digital de-emphasis filter response for 44.1 kHz
sample rates
SDIN VL
SCLK AMUTEC
LRCK AOUTA
MCLK VA_H
VD GND
GND AOUTB
DIF1(SCL/CCLK) BMUTEC
DIF0(SDA/CDIN) VQ
DEM(AD0/CS) VBIAS
RST VA
1
2
3
4
5
6
7
8
9
10 11
12
17
18
19
20
13
14
15
16
46 DVDR3380
IC7203 - 96KHz Amostragem de 24-bit stereo audio ADC
DIAGRAMA EM BLOCO
Figura 8-10
DESCRIO E CONFIGURAO DO PINO
dth
UDA1361TS
MGT451
1
V
NL ADC
3$
DGTAL
NTERFACE
DC-CANCELLATON
FLTER
DECMATON
FLTER
CLOCK
CONTROL
3
16
V
NR ADC
3$
13
DATAO
11
BCK
12
WS
6
SFOR
7
PWON
14
MSSEL
15
10
V
SSD
9
V
DDD
V
SSA
5
V
RP
4
V
RN
2
V
ref
8
SYSCLK
V
DDA
SYMBOL PIN DESCRIPTION
V
NL
1 left channel input
V
ref
2 reference voltage
V
NR
3 right channel input
V
RN
4 negative reference voltage
V
RP
5 positive reference voltage
SFOR 6 data format selection input
PWON 7 power control input
SYSCLK 8 system clock 256, 384, 512 or 768f
s
V
DDD
9 digital supply voltage
V
SSD
10 digital ground
BCK 11 bit clock input/output
WS 12 word select input/output
DATAO 13 data output
MSSEL 14 master/slave select
V
SSA
15 analog ground
V
DDA
16 analog supply voltage
handbook, halfpage
UDA1361TS
MGT452
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
NL
V
ref
V
NR
V
RN
V
RP
SFOR
PWON
SYSCLK
V
DDD
V
SSD
BCK
WS
DATAO
MSSEL
V
SSA
V
DDA
47 DVDR3380
8.5.2 Painel Digital
IC7301 - IEEE 1394a-2000 um cabo Transceiver/Arbiter
DIAGRAMA EM BLOCO
Figura 8-11
Received Data
Decoder/Retimer
Link
Interface
I/O
Arbitration
and ControI
State Machine
Logic
Bias VoItage
and
Current
Generator
Transmit Data
Encoder
CabIe Port
CrystaI
OsciIIator,
PLL System,
and CIock
Generator
TPA+
CPS
TPA-
TPB+
TPB-
XI
XO
FILTER0
FILTER1
LPS
ISO
C A

S SCL
LRE
CTL0
CTL1
D0
D1
D
D
D
D
D
D
PC0
PC1
PC
C/L O
R0
R1
TPBIAS
PD
RESET
Sada CNA est apenas disponvel no pino 64 PAP
48 DVDR3380
CONFIGURAO DOS PINO
DIAGRAMA TERMINAL PHP
Figura 8-12
14 15
AGND
AV
DD
R1
R0
AGND
TPBAS
TPA+
TPA-
TPB+
TPB-
AGND
AV
DD
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
SYSCLK
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
17 18 19 20
47 46 45 44 43 48 42 40 39 38 41
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
TSB41AB1
P
L
L
G
N
D
P
L
L
V
F

L
T
E
R
1
F

L
T
E
R
0
L
R
E
Q
D
G
N
D
D
G
N
D
D
V
T
E
S
T
M
S
E
S
M
C
/
L
K
O
N
P
C
1
P
C
2

S
O
C
P
S
D
V
R
E
S
E
T
X
O
X

D
G
N
D
L
P
S
P
C
0
D
D
D
V
D
D
D
D
D
D
49 DVDR3380
DESCRIO DO PINO
TERMINAL
TYPE I/O DESCRIPTION
PHP NO.
TYPE I/O DESCRIPTION
26, 32, 36 Supply - Analog circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
25, 35 Supply - Analog circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001
F. Lower frequency 10 F filtering capacitors are also recommended. These
supply terminals are separated from PLLV
DD
and DV
DD
inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.
15 CMOS /O Bus manager contender programming input and link-on output. On hardware reset,
this terminal is used to set the default value of the contender status indicated during
self-D. Programming is done by tying the terminal through a 10-k resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
f the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-k series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PE (port-event interrupt) register bit is 1, or
c) any of the CTO (configuration-time-out interrupt), CPS
(cable-power-status interrupt), or STO (state-time-out
interrupt) register bits are 1 and the RPE (resuming-port
interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: f an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.
N/A CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming
bias voltage.
20 CMOS Cable power status input. This terminal is normally connected to cable power
through a 400-k resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DV
DD
supply if application does not require it to be used.
2
3
CMOS /O Control /Os. These bidirectional signals control communication between the
TSB41AB1 and the LLC. Bus holders are built into these terminals.
NAME
AGND
AV
DD
C/LKON
CNA
CPS
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
4
5
6
7
8
9
10
11
CMOS /O Data /Os. These are bidirectional data signals between the TSB41AB1 and the
LLC. Bus holders are built into these terminals.
50 DVDR3380
TERMINAL
TYPE I/O DESCRIPTION
PHP NO.
TYPE I/O DESCRIPTION
14, 46, 47 Supply - Digital circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
21, 44, 45 Supply - Digital circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and
0.001 F. Lower frequency 10 F filtering capacitors are also recommended.
These supply terminals are separated from PLLV
DD
and AV
DD
inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.
38
39
CMOS /O PLL filter terminals. These terminals are connected to an external capacitor to form
a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1 F 10% capacitor is the only external
component required to complete this filter.
19 CMOS Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. f an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the SO terminal should
be tied low to enable the differentiation logic. f no isolation barrier is implemented
(direct connection), or T bus holder isolation is implemented, the SO terminal
should be tied high to disable the differentiation logic. For additional information
refer to T application note Galvanic solation of the EEE 1394-1995 Serial Bus,
SLLA011.
13 CMOS Link power status input. This terminal monitors the active/power status of the link
layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-k resistor either to the V
DD
supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than
2.6 s (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6 s). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. n the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. f the LPS input remains low for more than 26 s (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
48 CMOS LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.
16
17
18
CMOS Power class programming inputs. On hardware reset, these inputs set the default
value of the power class indicated during self-D. Programming is done by tying
these terminals high or low. Refer to Table 9 for encoding.
NAME
DGND
DV
DD
FLTER0
FLTER1
SO
LPS
LREQ
PC0
PC1
PC2
PD 12 CMOS Power-down input. A high on this terminal turns off all internal circuitry except the
cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
EEE 1394a-2000 suspend/resume LPS and C/LKON features.)
51 DVDR3380
TERMINAL
TYPE I/O DESCRIPTION
NAME PHP NO.
TYPE I/O DESCRIPTION
41 Supply - PLL circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
40 Supply - PLL circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001
F. Lower frequency 10 F filtering capacitors are also recommended. This supply
terminal is separated from DV
DD
and AV
DD
inside the device to provide noise
isolation. t should be tied at a low-impedance point on the circuit board.
33
34
Bias - Current setting resistor terminals. These terminals are connected through an
external resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 k1.0% is required to meet the EEE Std
1394-1995 output voltage limits.
37 CMOS Logic reset input. Asserting this terminal low resets the internal logic. An internal
pullup resistor to V
DD
is provided so only an external delay capacitor is required for
proper power-up operation (see power-up reset in the Application nformation
section). The RESET terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard
logic input, and may also be driven by an open-drain type driver.
23 CMOS Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal may be tied to GND through a 1-k pulldown resistor or
it may be tied to GND directly.
24 CMOS Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to GND.
1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data
transfers, to the LLC.
22 CMOS Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to V
DD
.
30 Cable /O Twisted-pair cable A differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
29 Cable /O
positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.
28 Cable /O Twisted-pair cable B differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
27 Cable /O
positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.
31 Cable /O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for
proper operation of the twisted-pair cable drivers and receivers, and for signaling
to the remote nodes that there is an active cable connection.
PLLGND
PLLV
DD
R0
R1
RESET
SE
SM
SYSCLK
TESTM
TPA+
TPA-
TPB+
TPB-
TPBAS
X
XO
42
43
Crystal - Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel
resonant fundamental mode crystal. The optimum values for the external shunt
capacitors are dependent on the specifications of the crystal used (see crystal
selection in the Application nformation section). When an external clock source is
used, X should be the input and XO should be left open, and the clock must be
supplied before the device is powered on.
52 DVDR3380
IC7401 - 4x10bit Decodicador de Vdeo Digital com microvision
DIAGRAMA EM BLOCO
Figura 8-13
CONFIGURAO DO PINO
Figura 8-14
Composite and S-Video Processor
Y/C
Separation
5-Iine
Adaptive
Comb
Luma
Processing
Chroma
Processing
ADC1
ADC2
ADC3
ADC4
M
U
X
Component
Processor
CVBS/Y
C
Y/G
Pb/B
Pr/R
Gain/Offset
CoIor
Space
Conversion
C
Y
Output
Formatter
Y[9:0]
YCbCr
VBI
Data
SIicer
Copy
Protection
Detector
C[9:0]
Host
Interface
Timing Processor
with Sync Detector
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
CVBS/
Y/G
CVBS/
Pb/B/C
CVBS/
Pr/R/C
CVBS/Y
CVBS/Y/G
AnaIog Front End
SampIing
CIock
GPIO
FSS
H
S
/
C
S
V
S
/
V
B
L
K
F
I
D
A
V
I
D
X
T
A
L
1
X
T
A
L
2
D
A
T
A
C
L
K
R
E
S
E
T
B
G
L
C
O
D
R
D
G
D
B
F
S
O
P
W
D
N
S
C
L
S
D
A
YCbCr
22 23
C_6/GPO/RED
C_7/GPO/GREEN
C_8/GPO/BLUE
C_9/GPO/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
OGND
OVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V_1_B
V_1_C
CH1_A33GND
CH1_A33VDD
CH2_A33VDD
CH2_A33GND
V_2_A
V_2_B
V_2_C
CH2_A18GND
CH2_A18VDD
A18VDD_REF
A18GND_REF
CH3_A18VDD
CH3_A18GND
V_3_A
V_3_B
V_3_C
CH3_A33GND
CH3_A33VDD
25 26 27 28
PFP PACKAGE
(TOP VIEW)
79 78 77 76 75 80 74 72 71 70 73
29 30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
V

_
1
_
A
C
H
1
_
A
1
8
G
N
D
C
H
1
_
A
1
8
V
D
D
P
L
L
_
A
1
8
G
N
D
P
L
L
_
A
1
8
V
D
D
X
T
A
L
2
X
T
A
L
1
V
S
/
V
B
L
K
/
G
P

O
H
S
/
C
S
/
G
P

O
F

D
/
G
P

O
C
_
0
/
G
P

O
C
_
1
/
G
P

O
D
G
N
D
D
V
D
D
C
_
2
/
G
P

O
C
_
3
/
G
P

O
C
_
4
/
G
P

O
C
_
5
/
G
P

O
G
N
D

O
V
D
D
C
H
4
_
A
3
3
V
D
D
C
H
4
_
A
3
3
G
N
D
V

_
4
_
A
C
H
4
_
A
1
8
G
N
D
C
H
4
_
A
1
8
V
D
D
A
G
N
D
D
G
N
D
S
C
L
S
D
A

N
T
R
E
Q
D
V
D
D
D
G
N
D
P
W
D
N
R
E
S
E
T
B
F
S
S
/
G
P

O
A
V

D
/
G
P

O
G
L
C
O
/

2
C
A

O
V
D
D

O
G
N
D
D
A
T
A
C
L
K
53 DVDR3380
DESCRIO DO PINO
TERMINAL
I/O DESCRIPTION
NAME NUMBER
I/O DESCRIPTION
AnaIog Video
V_1_A
V_1_B
V_1_C
V_2_A
V_2_B
V_2_C
V_3_A
V_3_B
V_3_C
V_4_A
80
1
2
7
8
9
16
17
18
23

V_1_x: Analog video input for CVBS/Pb/B/C

V_2_x: Analog video input for CVBS/Y/G
V_3_x: Analog video input for CVBS/Pr/R/C
V_4_A: Analog video input for CVBS/Y
Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)
can be supported.
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F.
The possible input configurations are listed in the input select register at
2
C subaddress 00h (see
Section 2.11.1).
CIock SignaIs
DATACLK 40 O Line-locked data output clock.
XTAL1 74
External clock reference input. t may be connected to an external oscillator with a 1.8-V compatible clock
signal or a 14.31818-MHz crystal oscillator.
XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.
DigitaI Video
C[9:0]/
GPO[9:0]
57, 58,
59, 60,
63, 64,
65, 66,
69, 70
O
Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also,
these terminals can be programmable general-purpose /O.
For the 8-bit mode, the two LSBs are ignored.
D_BLUE 58 Digital BLUE input from overlay device
D_GREEN 59 Digital GREEN input from overlay device
D_RED 60 Digital RED input from overlay device
FSO 57 Fast-switch overlay between digital RGB and any video
Y[9:0]
43, 44,
45, 46,
47, 50,
51, 52,
53, 54
O
Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.
For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.
MisceIIaneous SignaIs
FSS/GPO 35 /O
Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)
and the composite video input.
Programmable general-purpose /O
GLCO/2CA 37 /O
Genlock control output (GLCO). Two Genlock data formats are available: T format and real time control
(RTC) format.
During reset, this terminal is an input used to program the
2
C address LSB.
NTREQ 30 O nterrupt request
PWDN 33
Power down input:
1 = Power down
0 = Normal mode
RESETB 34 Reset input, active low
54 DVDR3380
TERMINAL
I/O DESCRIPTION
NAME NUMBER
I/O DESCRIPTION
Host Interface
SCL 28
2
C clock input
SDA 29 /O
2
C data bus
Power SuppIies
AGND 26 Analog ground. Connect to analog ground.
A18GND_REF 13 Analog 1.8-V return
A18VDD_REF 12 Analog power for reference 1.8 V
CH1_A18GND
CH2_A18GND
CH3_A18GND
CH4_A18GND
79
10
15
24
Analog 1.8-V return
CH1_A18VDD
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD
78
11
14
25
Analog power. Connect to 1.8 V.
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
3
6
19
22
Analog 3.3-V return
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
4
5
20
21
Analog power. Connect to 3.3 V.
DGND
27 32 42
56 68
Digital return
DVDD
31 41 55
67
Digital power. Connect to 1.8 V.
OGND 39 49 62 Digital power return
OVDD 38 48 61 Digital power. Connect to 3.3 V or less for reduced noise.
LL_A18GND 77 Analog power return
LL_A18VDD 76 Analog power. Connect to 1.8 V.
Sync SignaIs
HS/CS/GPO 72 /O
Horizontal sync output or digital composite sync output
Programmable general-purpose /O
VS/VBLK/GPO 73 /O
Vertical sync output (for modes with dedicated VSYNC) or VBLK output
Programmable general-purpose /O
FD/GPO 71 /O
Odd/even field indicator output. This terminal needs a pulldown resistor.
Programmable general-purpose /O
AVD/GPO 36 /O
Active video indicator output
Programmable general-purpose /O
55 DVDR3380
IC7595 - Sries Detector de Tenso com Atraso Programvel
DIAGRAMA EM BLOCO
Figura 8-15
CONFIGURAOE DESCRIO DO PINO
PINOS CONECTORES E DIAGRAMA

VISTA SUPERIOR


Figura 8-16
NCP303LSNxxT1
Open Drain Output Configuration
V
ref
2 nput
3 Gnd 5 C
D
R
D
1 Reset Output
1
3
N.C.
Reset
Output
2
nput
Ground
4
C
D
5
x
x
x
Y
W
xxx = 302 or 303
Y = Year
W = Work Week
56 DVDR3380
VISTA EXPLODIDA DO APARELHO
Figura 9-1

3
1
3
9

2
4
9

3
5
8
6


2
0
0
6
-
0