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MPU CPU Sound WhiteStar (Atmel Based)
MPU CPU Sound WhiteStar (Atmel Based)
P [ 25:0 ]
P_A [ 19:1 ]
[ 2, H-5: 2, E-5:
+3.3V+3.3V+3.3V +3.3V 2, C-5: 2, A-4: U37 U36 U21 U17
P0 2, A-3 ] P_A1 1 P_A20 P_A1 1 P_A20 P_A1 1 P_A20 P_A1 1 P_A20
J3 P1 P_A2
12
11
A0 VPP P_A2
12
11
A0 VPP P_A2
12
11
A0 VPP P_A2
12
11
A0 VPP
P2 10 A1 A1 A1 A1
JTAG P_A3
A2
P_A3 10
A2
P_A3 10
A2
P_A3 10
A2
1K
1K
1K
1K
P3 P_A4 9 P_A4 9 P_A4 9 P_A4 9
P_A5 8
A3 13 P_D0 P_A5 8
A3 13 P_D0 P_A5 8
A3 13 P_D8 P_A5 8
A3 13 P_D8
A4 D0 A4 D0 A4 D0 A4 D0
1X7
P5 P_A6 7 14 P_D1 P_A6 7 14 P_D1 P_A6 7 14 P_D9 P_A6 7 14 P_D9
P6 P_A7 A5 D1 15 P_D2 P_A7 A5 D1 15 P_D2 P_A7 A5 D1 15 P_D10 P_A7 A5 D1 15 P_D10
1
2
3
4
5
6
7
6 6 6 6
A6 D2 A6 D2 A6 D2 A6 D2
5 5
P7
R434
R435
R436
R508
P_A8 5 17 P_D3 P_A8 5 17 P_D3 P_A8 5 17 P_D11 P_A8 5 17 P_D11
1-5I +3.3V P8 P_A9 A7
27 1-5E D3 18 P_D4 P_A9
1-5D 27
A7 D3 18 P_D4 P_A9 27
A7 D3 18 P_D12 P_A9 27
A7 D3 18 P_D12
1-5J 1-5H 1-5F
R470 J_RST
1-5G
P9 P_A10 26
A8 D4 19 P_D5 P_A10 26
A8 D4 19 P_D5
1-5C
P_A10 26
A8 D4 19 P_D131-5B P_A10 26
A8 D4 191-5A P_D13
+3.3V P_A11 A9 D5 20 P_D6 P_A11 A9 D5 20 P_D6 P_A11 A9 D5 20 P_D14 P_A11 A9 D5 20 P_D14
[ 2, A-2 ] 23 23 23 23
TDO
100 P11 A10 D6 A10 D6 A10 D6 A10 D6
VDD CORE
TMS
TDI
JP3 1 P12
P_A12
P_A13
25
4 A11 D7
21 P_D7 P_A12
P_A13
25
4 A11 D7
21 P_D7 P_A12
P_A13
25
4 A11 D7
21 P_D15 P_A12
P_A13
25
4 A11 D7
21 P_D15
VDD IO P13 P_A14 A12 P_A14 A12 P_A14 A12 P_A14 A12
TCK 28 28 28 28
Jumper
R433 A13 A13 A13 A13
[*] [ 1, J-1 ]
P24 / BMS 2 P_A15 29 P_A15 29 P_A15 29 P_A15 29
1X3
A14 A14 A14 A14
NWDOVF [ 2, 3-A ]
P17 P_A18 30 P_A18 30 P_A18 30 P_A18 30 [ 1, I-4: 2, C-2 ]
3 P18 A17 A17 A17 A17
P_A19 31
A18
24 ROE1 P_A19 31
A18
24 ROE2 P_A19 31
A18
24 P_A19 31
A18
24 ROE2
P19 OE OE OE OE
NRST [ 2, F-5 ]
VDD [ 2, C-3 ]
NCS3 [ 2, I-2 ]
P20 +5V +5V +5V +5V
VDD IO CORE VDD IO R437 VDD IO 16 32 16 32 16 32 16 32
P25 / MCKO
GND VCC GND VCC GND VCC GND VCC
100K
27C040 27C040 27C040 27C040
C413 100nF
P23
C412 100nF
C415 100nF
C410 100nF
C434 47pF
C414 47pF
C435 47pF
C411 47pF
NCS1
NCS0
P24 ROE1
MCKI
P25 [ 2, C-3 ]
P23
P_D [ 15:8 ] P_D [ 15:8 ]
P_D [ 7:0 ] P_D [ 7:0 ] P_D [7..0]
Y1 +3.3V
TP11
[ 2, F-2 ]
NWAIT 1 4 -5A
OE VCC AO/NLB [ 2, G-2 ] Test Point
TO ATMEL
U7 AOR NS CN3 NS
2
GND OUT
3
R502
MCKI 10 U35 NS R12 NS
R112 NS 1 POT 1A
33 A0 100K 2 POT 1B
NS
C76 10uF 2.2K
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P_A1 R-INPUT
100
4 4
[ 2, C-2 ] P_A3 7 7 4
33 P_A4 A3
6 1-4E 11 P_D0 VOL VS +5A 5
6 2
NS
RXD1
NCS1
1-4H
MCKI
A4
VDD IO
TDI
P25
1-4I
GND
P23
1-4J
D0
P27
NRST
VDD IO
NWDOVF
TCK
TDO
P24
NWAIT
GND
GND
NCS0
TMS
NWR1 / NUB
NWRO / NWE
NRD / NOE
P26
VDDCORE
1-4F 1-4C 6
P_A5 12 P_D1 CREF GND
TO XILINX
P_A6
5
A5 D1 13 P_D2 R13 NS 1-4A
NS C77NS10uF
4 C45 1X6
A6 D2 TDA8199
P_A7
P_A8
3
25
A7
A8
D3
15
16
P_D3
P_D4
C79
10uF
+
C46
.1uF
NS C52
.1uF
.1uF
100K
NS VOLUME
P_A9 24 D4 17 P_D5
1 P21 75 P21 / TXD1 / NTRI [ 2, I-5 ] A9 D5 R25
A0 / NLB 2 A0 / NLB 74 P_A10 21 18 P_D6 +
P_A1 GND P20 P20/ SCK1 P_A11 23
A10 D6 19 P_D7 -5A -5A
3 73
P_A2 4 A1 P19 72
P19 P_A12 2 A11 D7 R316 2.2K
P_A3 A2 P18 P18 P_A13 26
A12
5 71 A13
P_A4 6 A3 P17 70
P17 P_A14 27 0
P_A5 A4 P16 P16 P_A15 1
A14
7 69 P15 / RXD0 [ 2, F-5 ] A15
P_A6 8 A5 P15 68 20
P_A7 A6 P14 P14 / TXD0 [ 2, I-5 ] CS
9 67 P13 / SCK0
10 A7 P13 66 VDD IO 22 R14
VDD IO VDD IO P12 P12 / FIQ OE
P_A8
P_A9
11
A8 U402 GND 65 +5V 22K
12
A9 P11 64 P11 / IRQ2 VDD 14 28 R19 NSC100 10uFNS R100 NS R101 NS
ATMEL
P_A10 13 63 P10 / IRQ1
GND VCC
P_A11 14 A10 P10 62 CORE
P_A12 A11 VDD IO 27256/27512 100K + 22K 470
15 61
P_A13 A12 AT91R40008 VDD CORE NRD / NOE C75 2200pF NS R102
C418 100nF
16 60
C419 47pF
C417 100nF
C416 47pF
A13 P9 P9 / IRQ0 +
P_A14 17
18 A14
GND
PQFP100 P8
P7
59
58
P8
P7
/ TIOB2
/ TIOA2
+3.3V [ 2, C-1: 1, G-1: 1, I-4 ]
U100 1 22K
C101
22uF
NS
19
GND P6 57 P6 / TCLK2 +12V VIN 2 NS
100K
Jumper
P_A15 20
A15 P5 56 P5 / TIOB1 JP4 1X3 5 VIN
P_A16
P_A17
21
22 A16 P4
P3
55
54
P4 / TIOA1 / SST0 [ 4, J-2 ]
P3 / TCLK1
1 3
+VS
NSOUT 4
P_A18 23 A17
A18 GND 53 NCS1 NCS0 NS -VS
P_A19 24
A19 GND 52 2
+
C102 C106 D100 3 TDA2030A NS NS
3 3
R510
P_A20 25 51 R103
P28 / A20 / CS7 A20 / P2 P2 / TIOB0
22K
100uF .1uF 1N4004 D101
VDD CORE
1-3J P28 / 1-3I 1-3H 1-3G 1-3F 1-3E 1-3D 1-3C 1-3B 1 1-3A
CS7 NS NS 1N4004
VDD IO
VDD IO
+3.3V+3.3V+3.3V+3.3V -12V
NS NS
GND
D10
D12
D13
D14
D15
P30
P31
D11
P29
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
P0
P1
100K
100K
100K
100K
NS100uF NSC105
R9
C104 C103 C122
[ #, X-Y ] coming [ #, X-Y ] going +
from ... to ... .1uF .1uF .1uF
0
The circuit(s) continue at the address shown [ #-XY ].
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
R476
R477
R478
R479
VDD CORE VDD IO R21 C107 10uF R104 R105
R315
VDD IO + 470
P3 +5A 4.7K 22K
P30 / A22 / CS5
P_D10
P_D12
P_D13
P_D14
P_D15
P_D11
R106
P_D0
P_D1
P_D2
P_D3
P_D4
P_D5
P_D6
P_D7
P_D8
P_D9
P_A22 [ 2, C-1 ] P6
P9 C34 .1uF C50 2200pF + C108
P31 / A23 / CS4 P13 U101 1 10K 22uF CN4
TP20 + R17 +12V VIN 2
5 VIN 1 1+
Test Point P_D [ 15:8 ] C35 10uF +VS
P_D12
P_D13
P_D14
P_D15
2.2K 2 1-
P_D0
P_D1
P_D2
P_D3
VDD 4
OUT 3 2+
CORE VDD IO VDD IO -VS 4 2-
+ KEY PIN 5
C109 C110 D102 3 TDA2030A 5
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
R107 3+
U26 6
C423 100nF
C425 100nF
100uF .1uF
C421 100nF
1N4004
C420 47pF
C422 47pF
C424 47pF
+5A D103 1
8
1N4004
7 3-
4
GND VDD
5 U30B 1X7
1 8 6
V+ -12V
1-2J BCK AOR SPEAKER
2 2
7
R441
R442
R443
R444
R445
R446
R447
R448
R449
R450
R451
R452
R453
R454
R455
R456
3 7 5
B
1-2H 1-2G 1-2F
1-2E DATA VREF 1-2D 1-2C C112 + C113
1-2B C111 C123 1-2A
1-2I
100uF .1uF .1uF .1uF
2
WS AOL
6 LM833 V- R22
R8
+3.3V TDA1543 4 -5A 47K
1K
R24 C114 10uF R108 R109
P_D [ 7:0 ]
C80 47K + 39K 470
+3.3V R110
+3.3V +3.3V 2200pF +
P_A [ 16:1 ] P_D [ 15..0 ] C115
[ 2, J-2: 2, C-3 ] U8 [ 2, F-2 ]
WS
[ 2, C-2 ]
C48 2200pF C78 10uF U102 1 33K 22uF
C426 100nF
100K
100K
100K
R458
J I H G F E D C B A
J I H G F E D C B A
VDD IO +3.3V
TP1 D [7..0] [ 3, A-2 & 4, J-2 ]
U405 +3.3V Test Point +3.3V U404
+5V
3
VIN
+3.3V R462 R463 R464
[ 1, F-5 ] P16
P16
P17
18
17 B0 A0
2
3
D0
D1
[ 1, F-5 ] P17 B1 A1
2 R504 R505 R506 R507 100K 100K 100K [ 1, F-5 ] P18 P18
P19
16
15 B2 A2
4
5
D2
D3
DATA
VOUT 100K 100K 100K 100K [ 1, F-5 ] P19 B3 A3
1
R465
TP2
Test Point [ 1, F-5 ] P20
P20
P23
14
13 B4 A4
6
7
D4
D5
BUS
ADJ [ 1, F-5 ] P23 B5 A5
LT1086 C427
+
C428 100 [ 1, F-5 ] P0
P0
P0 [ 1, F-5 ] P24
P24
P25
12
11 B6 A6
8
9
D6
D7
OF 68B09E
5 5
[ 1, F-5 ] P25 B7 A7
.1uF 1000uF
2-5J 2-5I 2-5H U403 2-5G 2-5F 2-5E 2-5D
TP3 TP5 2-5C 20
2-5B 1
Test Point Test Point +5V 10 VCC DIR 19
2-5A
4 2-4J
1
NS
S1
2-4I
4
Test Point
2-4H
VDDCORE 1
2-4G
U219
8
2-4F
8MHZ
2-4E 2-4D
+5V 2-4C
X_P11
2-4B
P11
2-4A
[ 1, F-5 ] 4
VDDCORE VOUT C2- Q# X_P12 P12 [ 1, F-5 ]
2 NS 3 2
C1- GND 7
+ C431+ C432+ C433 3 6
+ C430 +3.3V
SW200 C1+ C2+
1.0 uF 10uF 1.0uF 1.0uF
4 5
+3.3V VIN SHDN/SS
[ #, X-Y ] coming [ #, X-Y ] going
LT1503 from ... to ...
C445 C446 C447 C448 C449 C450 C451
R501 NS +5V + C442 .1uF .1uF .1uF .1uF .1uF .1uF .1uF The circuit(s) continue at the address shown [ #-XY ].
S2 10K 10uF # = Sheet Number (3-5), X = Column Grid, Y = Row Grid
1 4 +3.3V
GROUND POSTS
RESET ZG2 ZG7
2 3
TEST PADS 1 2 1 2
SW200 1X2 1X2
+5V
+5V ZG3 ZG8
1 2 1 2 +3.3V +3.3V
R400
NS 4.7K
1X2 1X2
R313 U413 +5V [ #, X-Y ] coming [ #, X-Y ] going ZG4 ZG10 U414
from ... to ...
3 3
0 1 8
2-3J 2 PBRST VCC 7 2-3I 2-3H The2-3G
circuit(s) continue at the address shown [ #-XY2-3F]. 2-3E 1 2 1 2 2-3D 2-3C 2-3B 2-3A
TD ST 6 BSEL [ 3, J-2 ] 1X2 1X2 [ 1, A-5 ] ROE2 1
I/O1 VCC4 51
3
4
TOL RST 5
RESET# [ 3, A-2: 4, J-2: 2, A-2] # = Sheet Number (3-5), X = Column Grid, Y = Row Grid 2
NC1 I/O30 52
NWDOVF [ 1, H-4 ]
GND RST IORESET [ 3, A-2 ]
NS NS DS1232 1
ZG5
2 1
ZG11
2
3
4
I/O/GTS1
I/O/GTS2
I/O31
I/O32
53
54
P5
P6
[ 1, F-5 ]
[ 1, F-5 ]
R314 R475 5
VCC1 I/O33 55
SNDSTB [ 3, A-2 ]
1X2 1X2 6 56
0 0 [ 1, J-2: 2, J-2 ] P_A1 I/O2 I/O34
7 57
ZG6 8
NC2 VCC5 58
P_D0
9
I/O3 I/O35 59
Q#
1 2
NS 1X2
P_D15
P_D14
10
11
I/O4
I/O5
I/O36
I/O37 60
61
RST_IN
RST_OUT
U412 P_D1
P_D2 12
I/O6
I/O7
I/O38
GND5 62
1 13 63
P_A5
2
A4 A5 44 P_A6 P_D13
14
I/O8 I/O39 64 [ 3, E-3 ]
P_A4 A3 A6 43 P_A7
[ 1, A-4 ]
P_D12
15
I/O9 I/O40 65
INT#
[ 1, G-5 ]
P_A3 3
A2 A7 42 P_A8 ROE1 I/O10 I/O41 J_RST
4 41 [ 1, E-2 ] SND_DATA 16 66 [ 3, C-1: 4, J-2 ]
P_A2 A1 OE# 40 NRD/NOE [ 1, G-1: 1, I-4, 2, C-1 ] 17
I/O11 I/O42 67
DPSW
P_A1 5
A0 BHE# 39 NWR1/NUB [ 1, H-4 ] [ 1, E-2 ] WS I/O12 I/O43 RESET# [ 2, H-3: 3, A-2: 4, J-2 ]
[ 1, E-2 ] SND_CLK 18 68
[ 1, I-4 ] NCS3
P_D0
6
7
CS#
I/O0
BLE#
I/O15 38 P_D15
A0/NLB [ 1, E-4 ] MOUNTING HOLES 19
I/O13
NC3
I/O44
GND6 69
8 20 70 X_P11
P_A [16:1] P_D1
9
I/O1 I/O14 37 P_D14 P_D [15..0] P_D3
21
I/O14 I/O45 71 X_P12
[ 1, J-2: 2, C-3 ] P_D2 I/O2 I/O13 36 P_D13 [ 1, A-4: 1, F-2 ] MH1 MH4 22
GND1 I/O46 72
P_A1 P_D3 10
I/O3 I/O12 35 P_D12 P_D0 8MHZ 23
I/O/GCK1 I/O47 73
D0
P_A2 +3.3V 11
VDD VSS 34 P_D1 1 1 1 1 [ 1, F-4 ] 40MHZ I/O/GCK2 NC8
P_A3
P_A4 P_D4
12
13
VSS
I/O4
NS VDD 33
I/O11 32
+3.3V
P_D11
P_D2
P_D3
2 2 2 2
P_D5
24
25
GND2
I/O15
I/O48
GND7
74
75
D1
14 26 76
P_A5 P_D5
15
I/O5 I/O10 31 P_D10 P_D4 27
VCC2 I/O49 77
D2
P_A6 P_D6 I/O6 I/O9 30 P_D9 P_D5 I/O/GCK3 I/O50 D3
ADDRESS 2-2J 16
I/O8 29 DATA 28
I/O16 I/O51 78
2 2
P_A7 [ 1, I-4: P_D7 I/O7 P_D8 P_D6 Mounting Hole Mounting Hole P_D11
29 79
D4
17 28 2-2F P_D4 I/O17 I/O52 D5
P_A8 1, J-1: NWR0/NWE WE# NC 2-2H27 2-2G P_D7
BUS P_A9 2, C-2 ] 2-2IP_A16 18
19
A15 A8 26 P_A9 P_D8 BUS 2-2E
MH2 MH5
2-2D 2-2C
P_D10 30
31
I/O18
2-2B
NC9 80
81
2-2A
4
MTG_SLOT TOOLING HOLES JTAG 5 XTDI
XTMS
Sheet 2 of 4
6 SIZE REV.
C283
.1uF
C284
.1uF
C285
.1uF
C286
.1uF
C287
.1uF
C288
.1uF
C289
.1uF
C291
.1uF
C292
.1uF
C436
.1uF
C437
.1uF
C438
.1uF
C439
.1uF
C440
.1uF
C441
.1uF
C443
.1uF
C444
.1uF TH1 TH2 TH3
1x6
D A
CPU/Sound Bd. II w/ ATMEL Processor
SPI Part Nº: 520-5300-00
NOTES: R ALL RESISTOR VALUES ARE IN OHMS ( W ), 1/4W, 5%, UNLESS OTHERWISE SPECIFIED. NS: Not Stuffed Prepared By: CES Inc. Edited By: SPI Inc.
R ALL CAPACITOR VALUES ARE IN MICROFARADS ( mF ), UNLESS OTHERWISE SPECIFIED. R 0.1 mF BYPASS CAPACITORS FOR ALL INTEGRATED CIRCUITS (ICs). Model: RHT SCH1008 Dated: 06/13/03
J I H G F E D C B A
J I H G F E D C B A
D3
[ #, X-Y ] coming [ #, X-Y ] going U212
from ... to ... A0 +5V
The circuit(s) continue at the address shown [ #-XY ]. JP1 8K 2 32K
A1
10
9 A0
A1
D0
D1
11
12
D0
D1
1N4004
A2 8 13 D2
1K
1K
1K
1K
1K
1K
1K
1K
1K
# = Sheet Number (3-5), X = Column Grid, Y = Row Grid 1 3
R306 A3 7 A2 D2 15 D3
+5V +5V A4 A3 D3
1X3
10K A5
6
5 A4 D4 16
17
D4
D5 CN6
A6 4 A5 D5 18 D6
5 5
Jumper A6 D6 1
R278
R279
R280
R281
R282
R283
R284
R285
R286
3-5J 3-5I 3-5H 3-5G
A7
A8
3
25 A7 D7 19 D7
3-5F 3-5E 3-5D U206 3-5C 3-5B
2
+5V +5V A9 24 A8 D0 2 18 R287 39K
3-5A 3
A10 21 A9 D1 3 A0 B0 17 R288 39K 4
A11 23 A10 D2 4
A1 B1 16 R289 39K KEY PIN 5 5
A12 2 A11 D3 5
A2 B2 15 R290 39K 6
R414 26 A12 20 RAMCS# D4 6
A3 B3 14 R291 39K 7
A13 CS A4 B4 8
10K
10K
10K
10K
10K
220 1 D5 7 13 R292 39K
A14 22 E# D6 8 A5 B5 12 R293 39K 9
L201 D200 OE D7 9
A6
A7
B6
B7
11 R294 39K 10
11
+5V 28
R/W 27 RW RW R295 220
VCC 1 +5V 12
1N5817 DIR
C247 470pF
C248 470pF
C249 470pF
C250 470pF
C251 470pF
C252 470pF
C253 470pF
C254 470pF
R301
R302
R303
R304
R305
14 SWLO
RED U211 D201 GND 19
OE VCC
20 1X12
LED XA0 2 3 D0 VBATT 10
Q0 D0 62256 GND
XA1 D1
1
5 4 1N5817
Q1 D1
1
XA2 6 7 D2
Q2 D2
1X2
XA3 9 8 D3 BAT1 74HC245
XA4 Q3 D3 D4 x3 AA C290
12 13
XA5 15
Q4 D4 14 D5 4.5V .1uF MPIN
CELLS
2
16
Q5 D5 17 BAT3
Q6 D6
19
Q7 D7 18 J1
2
+5V C255
20 11
VCC CLK .1uF
10 1 A15 A15
R432 RAMCS#
GND OE
BSEL
10K
74LS374
D [ 7:0 ]
4 3-4J 3-4I
R431
10K
+5V
+5V
3-4H 3-4G
RW
3-4F 3-4E 3-4D
RW
3-4C
U207
3-4B
3-4A
4
D0 18 2
R299 D1 17 B0 A0 3
NS 10K
U210 U209 +5V
D2
D3
16
15
B1
B2
A1
A2 4
5
R300 B3 A3
XA5 1 12 A0 A0 8 31 D0 D4 14 6
VPP A0 11 A1 A1 9 A0 D0 30 D1 D5 13 B4 A4 7
0 +5V A1 10 A2 A2 10
A1 D1 29 D2 D6 12 B5 A5 8
32 A2 9 A3 A3 11
A2 D2 28 D3 D7 11 B6 A6 9
VCC A3 8 A4 A4 A3 D3 D4 B7 A7
16
GND
A4 7 A5 A5
12
13
A4 D4 27
26 D5
R296 R297 +5V 1 RW CN1
A5 6 A6 A6 14 A5 D5 25 D6 10K 10K 20 DIR 2 1
A6 5 A7 A7 15
A6 D6 24 D7 VCC 4 3
D0 13 A7 27 A8 A8 16
A7 D7 10 19 6 5
D0 A8 A8 GND OE
C256 470pF
C257 470pF
C258 470pF
C259 470pF
C260 470pF
C261 470pF
C262 470pF
C263 470pF
D1 14 26 A9 A9 17 8 7
D2 15 D1 A9 23 A10 A10 18
A9 7
D2 A10 A10 VCC +5V 74HC245 10 9
D3 17 25 A11 A11 19 12 11
D4 18 D3 A11 4 A12 A12 20
A11 2 14 13
D5 19 D4 A12 28 A13 A13 A12 NMI 4 INT# 16 15
21
D6 20 D5 A13 A14 22
A13 FIRQ 3 18 17
D6 29 A14 IRQ
MPIN
D7 21 XA0 A15 23 20 19
D7 A14 3 XA1 A15 39 +5V
E# 22 A15 2 XA2 TSC 1 IOPORT 2x10
[ 2, C-5 ] E# CS A16 30 XA3 38 GND
ROMCS# 24 A17 31 XA4 AVMA AVMA 36 LIC
3 3
OE A18 AVMA R298
RW RW 32 34 E
3-3J 3-3I 3-3H
27C040
3-3G 3-3F 6 R/W
3-3E
BA
E
Q
35 Q 10K3-3D 3-3C U208 3-3B 3-3A
5 40 2 18
XA [ 5:0 ] 33 BS HALT 37 3 A0 B0 17
BUSY RST 4 A1 B1 16
A2 B2
XA0
A [ 15:0 ]
68B09E 5 15
6 A3 B3 14
7 A4 B4 13
8 A5 B5 12
9 A6 B6 11
A7 B7
RESET#
1
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
+5V DIR +5V
20
VCC
[ 2, 3-A ] INT# IOPORT 19 10
OE GND
C264
C265
C266
C267
C268
C269
C270
C271
[ 2, C-4 ] E 74HC245
IOSTB
Q Q
[ 2, C-4 ] E FIRQ
XA0 TP12
BSEL Test Point A0
[ 2, H-3 ] BSEL
A10 A10
ROMCS#
D [7..0] [ 2, A-5: 4, J-2 ]
A0 [ 2, C-2 ]
3-2J
SNDSTB [ 2, A-3 ]
2 D7
U215B
3-2I
R312 L200
3-2H
AVMA 2
U215A
5 VMA
3-2G
10
GND
U213
VCC
3-2F
20
+5V
3-2E
3-2D 3-2C 3-2B RESET# [3-2A
2, A-2: 2, H-3: 4, J-2 ]
IORESET [ 2, H-3 ]
2
12 9 A15 1
D Q 8
+5V D Q 6 I1
BSEL Q 330 Q 3 Q A14 2
I2 01
19 ROMCS# ROMCS# R412
11 RED A13 3 18 RAMCS# RAMCS# IORESET
CLK +5V CLK +5V I3 I/02 Q10
RESET# LED E# 4
I4 I/03
17 IOPORT IOPORT 2N3904
13
CLR VCC 14
+5V
1
CLR VCC 14
Q 5 16 A9 A9 1K
R413
[ #, X-Y ] coming [ #, X-Y ] going
10 7 4 7
VMA 6 I5 I/04 15 A10 A10
+5V PRE GND PRE GND I6 I/05 10K from ... to ...
RW 7
I7 I/06
14 SNDSTB SNDSTB
74AHCT74 74AHCT74 A11 8 13 XA0 XA0
A12 9 I8 I/07 12 IOSTB IOSTB The circuit(s) continue at the address shown [ #-XY ].
A0 11 I9 08 # = Sheet Number (3-5), X = Column Grid, Y = Row Grid
I10
R310
U216B PRES
PAL16V8Q
MPIN MPIN
A0 12 9 0 MPIN [ 4, J-2 ]
POUT 11
D Q
Q
8 R311 NS
CLK +5V 0
13 14
+5V 10
CLR VCC
PRE GND
7 U214
A8 1
A Y0 15 SWLO SWLO
74AHCT74 A9 2
Y1 14 DPSW DPSW [ 2, A-2: 4, J-2 ]
TP17 A10 3 B 13 BSEL BSEL DPSW
Test Point C Y2 12 SWSTB SWSTB
Y3 SWSTB [ 4, J-2 ] Sheet 3 of 4 :
U216A PLASMA_RESET A12 6
G1 Y4
11 SWM SWM SWM [ 4, J-2 ]
4 10 PLIN PLIN Program Memory
1 1
A7 5 G2A Y5 9 POUT POUT PLIN [ 2, A-5: 4, J-2 ] 3-1A
3-1J 2 5 PSTB G2B Y6 3-1E 3-1D POUT [ 4, J-2 ] 3-1B
+5V D Q 3-1I 3-1H 3-1G 7 3-1F STATUS STATUS 3-1C
STATUS [ 4, J-2 ] ®
6 Y7 +5V Schematic Set
3 Q
CLK +5V 8 16 Sheet 3 of 4
GND VCC
POUT 1 14
4
CLR VCC 74LS138 SIZE REV.
7
PRE GND
PLIN
74AHCT74 PRES [ 4, J-2 ]
D A
PSTB PRES
PSTB [ 4, J-2 ]
PLIN
RESET#
CPU/Sound Bd. II w/ ATMEL Processor
SPI Part Nº: 520-5300-00
NOTES: R ALL RESISTOR VALUES ARE IN OHMS ( W ), 1/4W, 5%, UNLESS OTHERWISE SPECIFIED. NS: Not Stuffed Prepared By: CES Inc. Edited By: SPI Inc.
R ALL CAPACITOR VALUES ARE IN MICROFARADS ( mF ), UNLESS OTHERWISE SPECIFIED. R 0.1 mF BYPASS CAPACITORS FOR ALL INTEGRATED CIRCUITS (ICs). Model: RHT SCH1008 Dated: 06/13/03
J I H G F E D C B A
J I H G F E D C B A
+5V
D408
+5V
10K
10K
10K
10K
10K
10K
10K
10K
1N4004
560
560
560
560
560
560
560
560
NS
NS
NS
NS
NS
NS
NS
NS
NS
R200
R201
R202
R203
R204
R205
R206
R207
R423
R424
R425
R426
R427
R428
R429
R430
D [ 7..0 ] D [ 7..0 ]
NS220 U200
5 CN8
4-5J 4-5I R208
R209
R210
R211
220
220
220
4-5H 18 4-5G
17 B0
16 B1
15 B2
A0
A1
A2
2
3
4
5
D0
D1
D2
D3 ADC
4-5F
ADC
4-5E 4-5D
R234 Q1
4-5C 4-5B
4-5A
5
1 R212 220 14 B3 A3 6 D4
2 R213 220 13 B4 A4 7 D5 1K 2N3904
3 R214 220 12 B5 A5 8 D6
4 R215 220 11 B6 A6 9 D7 R235 Q2
5 B7 A7
470pF
470pF
470pF
470pF
470pF
470pF
470pF
470pF
2N3904
6
7 NS +5V 20
10 VCC DIR
GND OE
1
19 PLIN
RESET# RESET#
U203 +5V
1K
R236
CN5
8 RESET# 1 20 Q3
(MR#)CLR# VCC 1
9
74HC245 SWSTB 11
CP 2N3904 KEY PIN 2 2
+5V
NS
NS
NS
NS
NS
NS
NS
NS
1K
C201
C202
C200
C203
C204
C206
C207
C205
10
11 3
D0 3 2
12 D1 4 (D0)1D 1Q(Q0) 5 R237 4
Q4
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
13 D2 7 (D1)2D 2Q(Q1) 6
5
14 D3 8 (D2)3D 3Q(Q2) 9 1K 2N3904 6
15 D4 13 (D3)4D 4Q(Q3) 12
7
(D4)5D 5Q(Q4) R238 8
16
17 +5V U201 D5
D6
14
17 (D5)6D 6Q(Q5)
15
16
Q5 9
RESET# (D6)7D 7Q(Q6) 1K 2N3904
R216
R217
R218
R219
R220
R221
R222
R223
18 20 1 D7 18 19 1X9
19 VCC (MR#)CLR# 11 POUT (D7)8D 8Q(Q7)
20 CP 10 R239 SWITCH
3 GND Q6
21 2
1Q(Q0) (D0)1D
D0
2N3904 COLUMNS
22 5 4 D1 74HCT273 1K
23 6 2Q(Q1) (D1)2D 7 D2
24 9 3Q(Q2) (D2)3D 8 D3 R240
25 12 4Q(Q3) (D3)4D 13 D4
Q7
26 15 5Q(Q4) (D4)5D 14 D5 1K 2N3904
4 4
16 6Q(Q5) (D5)6D 17 D6
4-4J 4-4I 4-4H 7Q(Q6) (D6)7D 4-4G 4-4E 4-4D R241 4-4C 4-4B
.01uF
.01uF
.01uF
.01uF
.01uF
.01uF
.01uF
.01uF
2X13 19 18 D7 4-4F
Q8
8Q(Q7) (D7)8D 4-4A
C209 470pF
C211 470pF
C213 470pF
C215 470pF
C208 470pF
C210 470pF
C212 470pF
C214 470pF
10 1K 2N3904
GND
C221
C222
C223
C224
C225
C226
C227
C228
74HCT273
+5V
4.7K
4.7K
470
+5V
10K
10K
10K
10K
10K
10K
10K
10K
NS
R242
R243
R409
PSTB
R244
R245
R246
R247
R248
R249
R250
R251
PRES
PLIN
+5V
C229 470pF
C230 470pF
C408 470pF
10K
10K
10K
10K
10K
NS
U204 SW300
D0 2 18 1 16
D1 3 A0 B0 17 2 15
R224
R225
R226
R227
R228
U202 D2
D3
4
5
A1
A2
B1
B2
16
15
3
4
14
13
3 3
R229 220 18 2 D3 A3 B3
174-3GB0 A0 D4 6 14 5 12
R230 220 3 D4 A4 B4
16 B1 A1
4-3I 4-3H 4-3E
D5 7 13 4-3D 4-3C
4-3J 4-3F 6 11 4-3B 4-3A
R231 220 4 D5 A5 B5
15 B2 A2 D6 8 12 7 10
R232 220 5 D6 A6 B6
14 B3 A3 D7 9 11 8 9
R233 220 6 D7 A7 B7
MPIN 13 B4 A4 7 D2
C217 470pF
C219 470pF
C216 470pF
C218 470pF
C220 470pF
12 B5 A5 1 20
SST0 8 D1
DPSW DIR VCC +5V SW DIP8
11 B6 A6 19 10
[ #, X-Y ] coming going BUSY B7 A7
9 D0 OE GND
[ #, X-Y ] +5V
from ... to ... 74HC245
20 1
The circuit(s) continue at the address shown [ #-XY ]. +5V 10 VCC DIR 19 STATUS
3.3K
GND OE
# = Sheet Number (3-5), X = Column Grid, Y = Row Grid 74HC245
R410
[ 3, C-1 ] STATUS +5V
[ 3, C-1 ] POUT VREF
[ 2, H-3: 3, A-2 ]
[ 2, A-5: 3, C-1 ]
RESET# V+ 3 U400A
PLIN
3.3K
SWSTB SWSTB 5
[ 3, C-1 ] SWSTB 2
[ 2, A-2: 3, C-1 ] DPSW A 4 VREF
[ 3, C-1 ] SWM DPSW DPSW +5V
+
[ 3, C-1 ] MPIN +5V C409
[ 1, G-3 ] SST0 V- 12 LM339AN 22uF
U400B
R411
560
560
560
560
560
560
560
560
[ 2, A-2 ] BUSY V+ 3
[ 3, C-1 ] PRES 7
[ 3, C-1 ] PSTB 1
B 6 VREF
-12V +5V
4-2J
+5V
2 2
R401
R402
R403
R404
R405
R406
R407
R408
D [7..0] D [7..0] V- 12 LM339AN
4-2I FB2 FB1 4-2H 4-2G 4-2F
4-2E
V+ 3 U400C 4-2D 4-2C
R415
4-2B
D400
4-2A
VR1 + 14
9
220 1N4148
-5A C30 C29 C 8 VREF
3 2 R416 D401
3 2 1000uF .001uF
7905C
V- 12 LM339AN +5V 220 1N4148 CN7
1
V+ 3 U400D R417 D402
10
1 11 220 1N4148
C125 .1uF
FB4 FB3 13
D VREF R418 D403
9
8
10
C40 C49
CN2 +5V +5V 220 1N4148
7
6
+ +5VDC V- 12 LM339AN R419 D404 5
22uF .1uF C38 C31 + C37 1
U401A KEY PIN 4 4
D1 .1uF 470uF .001uF -12VDC 2 V+ 3
220 1N4148 3
5
10K
10K
10K
10K
10K
10K
10K
10K
1N4004 3
2 R420 D405 2
4 A 1
KEY PIN 5 5 4 VREF 1N4148
220
6 R421 D406 1X10
+12VDC 12 LM339AN +5V
V-
1X6
U401B 220 1N4148
R260
R261
R262
R263
R264
R265
R266
R267
+12V V+ 3 SWITCH
POWER 7 R422 D407 ROWS
VR2 1
B VREF 220 1N4148
+5A FB6 FB5 6
C400 .1uF
C401 .1uF
C402 .1uF
C403 .1uF
C404 .1uF
C405 .1uF
C406 .1uF
C407 .1uF
3 1
3 1 +5V LM339AN
7805C + V- 12
2
C39 C81 C51
U205 V+ 3 U401C Sheet 4 of 4 :
.1uF 470uF .001uF 9
Switch Connectors
1 1
2 D0 2 18 18 14 4-1A
4-1J 4-1I D1 3 A0 B0 17 17 4-1E C 4-1D VREF 4-1C 4-1B
4-1H
A1 4-1G
B1 4-1F 8 ®
D2 4
A2 B2
16 16 Schematic Set
D3 5 15 15
LM339AN +5V
D4 6 A3 B3 14 14 V- 12 Sheet 4 of 4
D5 7 A4
A5
B4
B5
13 13 V+ 3 U401D
+ D6 8 12 12 11 SIZE REV.
C47 C59 D2 A6 B6
.1uF 22uF 1N4004
D7 9
A7 B7
11 11 13
D 10 VREF D A
1 20
DIR VCC +5V
SWM 19
OE GND
10
V- 12 LM339AN CPU/Sound Bd. II w/ ATMEL Processor
SPI Part Nº: 520-5300-00
74HC245
NOTES: R ALL RESISTOR VALUES ARE IN OHMS ( W ), 1/4W, 5%, UNLESS OTHERWISE SPECIFIED. NS: Not Stuffed Prepared By: CES Inc. Edited By: SPI Inc.
R ALL CAPACITOR VALUES ARE IN MICROFARADS ( mF ), UNLESS OTHERWISE SPECIFIED. R 0.1 mF BYPASS CAPACITORS FOR ALL INTEGRATED CIRCUITS (ICs). Model: RHT SCH1008 Dated: 06/13/03
J I H G F E D C B A
U401
CN6 SW300
CN7
1 9 GND 1 12 ON KSD08H
R407 U401 C405 1 10
CN5
LM339AN
R421 R420
SWITCH COLUMNS D3 DEDICATED SWITCH IN 1 2 3 4 5 6 7 8 C406 R419 SWITCH ROWS
Q4 Q5 U204
1
1 1 C225 R427 R286 R295 C255 U205 C404 D405 D402 D400
U206
U203
U203
R238
R237 Q3 Q6
C224 R426 U206 R278 R294 C247 R251 U204 R267 U205 R422 D406 D403 D401 ( -- ) SIZE AA 1.5V ( + )
1 1 C226 R428 R279 R293 C248 R250 D407 D404
74HC245
74HC245
R266 C291 C407 R401
74HC245
74HCT273
R239
R236 Q2 Q7
C223 R425 R280 R292 C249 R249
R265 U400 C401 R406 R403
R402 BAT1
LM339AN
1 1 C227 R429 R281 R291 C250 R248 R416 R408 R404
R240 R264 ( -- ) SIZE AA 1.5V ( + )
U400
C222 R424 R282 R290 C251 R247 R417 C402 R405 GND
NOTE
Q1 Q8 R263
R235
1 1 C228 R430 R283 R289 C252 R246 R415 C400
R262
R241 C221 R423 R284 R288 C253 R245 R418 C403
R261
•
R234 D408 C274 R285 R287 C254 R244 C272 C292
NOTE
C275
U403 U404 GND
TE
R260 C273
R411 ( -- ) SIZE AA 1.5V ( + )
U403 R466
U404 ST
•
R410 +
+
R468 R478 C416
R469
R433
D104 C117 + LED1 C409
DS1233
C124
•
U209
•
VBATT
74HC245
74HC245
L201 E Q
D105 C120 R507
TEST
R476 R462
R479
R477 C417
D201
U406 U406 TP7
U407 U209
NO
U212
U407 TP5
C422
C423
U102 U405 U214 U213
R111
NO
TE
+ + U210
+
U212
+
C429
U214 U213
LT1086
C442
74LS74
C115
U405
C116
U210
TE
R480
•
R504 + R464
PAL16V8Q
6264 \ MS62256
74LS138
C427 C438 C441 C9 R455
•
+ JP3
+
C118
C444 R453
•
C114 + C433 EPROM
+
68B09E
C428 R451
NOTE
011
150318
C119 GND_SIGNAL
CPU GAME
R108 + R449
+
C430
27C040
C431 R447
•
R22 + + U219 FLASH C24
NOTE
R109
+
+
R445
NOTE
TS1EST TP4
R110 R24 C432 + R443
+
+
• • TP3
F1 +3.3V C413 P2 C286
NOTE R441
TEST
C123
R106 C80 P1
+ TP8 1 C414 R463
CN4
SQ3300S
LED2 U402 C425
40.000M
P0
00041N
TP2 C287
•
PLE
D102 C110 R456
•
R465 Y1
R434
R435
R436
C443
7
R454
ST J2
C113 R297
U101
D103
U402 R452
SP3
C424
TE
1
R107
R296 R301
Xilinx 1
7 JTAG R509R502 ATMEL R450 L201
1MB C290 R431
+ + JTAG R448
+
DS1232
R508
R470
C447
C448
U412 C410
TP1 R444 +5V
C111
C418 C415
1
+ +
C420
+
C419
C107 C112 U414 R313
C412
C284 R306
C411
R437
C449 C445
C450
C421
RESET
R104 R21 TE U215
R314
SP1
74AHCT74
R312
NOTE •
U8
C451
74HC245
1
C439
R102 C105
TP20
C440
C285
R458
ATMEL
C446
D100
+ NCS1 NCS0 R305
+
R103
C102
+ U7 U37 U36 JP2 U21 U17 C281 1 2
+
C101
NOTE
U7 U37 U36 U21 U17 U211
C200 R215 R207
•
+
+
PLASMA CNTLR
C104
U211
C103
C100
M27C0400I-I2FI
M27C0400I-I2FI
M27C0400I-I2FI
M27C0400I-I2FI
R19 C209 R217
VOICE ROM 4
VOICE ROM 3
VOICE ROM 2
VOICE ROM 1
R303
74LS374
•
R100 R14
NCS1
JP4
R300
U216 U201 C208 R216
27C040
27C040
27C040
27C040
74AHCT74
74HCT273
POT1
NOTE
R316
R510
+ R409
TDA8199
25 26
+
•
+ + + C49 U208 U202
C45 C283 U207 C289
+
C214 R222
C35 C59 C40
+ D1
8MB 8MB 8MB 8MB CN8
+
74HC245
74HC245
+
74HC245
U26 D2
VR1 C4 C3 C2 C1
C268 C257 C230 R243
1543
TDA
+
+ C51 FB2
520-5300-00
+
19
C81 FB3 C280 C279 C276
1
AOL C436
FB6 C29 GND 1 REV A CN1
Q10 FIRQ PLASMA_RESET GND
+
R17 AOR + 6 1
C79 10 2
FB5 FB1 R412 R413
CN2 CN9
TES
T
TE
–12
GND
+5V
+12
20
ES
TE
ST
T
ST
T
•
14.67” X 9.125”
•
•
•
16 3 C430, C431, C433 (near U403, U404) 1.0uF, ##v, Radial Lytic Cap.
17 1 125-5017-00 C35 10uF, 16v, Radial Tant. Cap.
Capacitors*
18 4 125-5017-00 C78, C79, C107, C114 (C76, C77, C100: NS) 10uF, 25v-35v, Radial Lytic Cap.
19 2 125-5015-00 C109, C112 (C102, C104: NS) 100uF, 25v, Radial Lytic Cap.
20 1 125-5014-00 C409 22uF, 16v, Radial Lytic Cap.
21 4 125-5020-00 C40, C59, C108, C115 (C101: NS) 22uF, 25v, Radial Lytic Cap.
22 2 125-5012-00 C116, C119 220uF, 25v, Radial Lytic Cap.
23 2 125-5019-00 C31, C81 470uF, 25v, Radial Lytic Cap.
24 39 125-5028-00 C208>C215, C216>C220, C229, C230, C247>C254, 470pF (471), Cer. Cap.
C256>C263, C264>C271 (C200>C207, C408: NS)
25 2 125-5037-00 C30, C428 1000uF, 16v, Radial Lytic Cap.
26 17 C427, C429, C436>C441, C443, C445>C451 SMT .1uF Cap.
27 2 C432, C442 (near U403 & U404) SMT 10uF Cap.
28 9 C411, C414, C416, C419, C420, C422, C424, C434, C435 SMT 47pF Cap.
29 10 C410, C412, C413, C415, C417, C418, C421, C423, C425, C426 SMT 100nF Cap.
30 7 112-5003-00 D1>D3, D102>D105, D408 (D100, D101: NS) 1N4004, Diode
& LEDs*
Diodes
Resistors / Transistors*
A watchdog is used to monitor the CPU and the 5v supply. If the 5v supply is below 4.75 the watchdog will hold
the CPU/Sound Board & I/O Board in reset. The watchdog must be fed at a rate of 250ms or faster. The signal
used to feed the watchdog comes from the EPROM Bank select signal used to load U211.
The I/O Interface CN1 is buffered by two (2) HC245 Chips (U207 & U208). The CPU’s reset line is buffered by
Q10 and fed over to the I/O through CN1. An I/O Strobe Signal is fed through CN1-15 and is used to notify the I/O
that a valid address is being sent.
Switches:
The Switch Matrix consists of eight (8) 2N3904 Transistors(Q1-Q8) which pull one of 8 strobes ‘low’ to activate a
Single Column of switches. The Switch Return Signals are fed into CN7 [SWITCH ROWS] and are highly filtered
and compared to a 2.5v reference voltage. The Switch Return Voltage must be below 2.5v to make a Valid Switch
Closure. If false switches are appearing, check that none of the 2N3904 Transistors are permanently pulling the
strobe line low. Only one strobe from CN5 [SWITCH COLUMNS] should be low at any time. CN6 [DEDICATED
SWITCH IN] is a Dedicated Bank of Input Switches. Switches connected to CN6 are connected to ground instead
of a strobe and may be read at any time.
Plasma Interface:
The data path for communication to and from the Plasma Controller Board is 8 bits wide. There are separate
Input and Output Busses. Data going out to the controller comes from the CPU’s Data Bus through U201 and
onto CN8-Pins 11-18. Status back from the Plasma Controller comes in on CN8-Pins 22-26 and is fed into U202
for input to the CPU’s Data Bus. Two control signals that go out to the Plasma Controller are PRES [TP17:
PLASMA RESET] and CN8-Pin 19 [PSTB - Plasma Strobe]. The Plasma Reset is software controllable through
U216/B and also has a test point "Plasma Reset". The Plasma Strobe Signal to the controller is generated from
U216/A and is used to latch data into the Plasma Controller.
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