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5 4 3 2 1 01 BOM Zoro_SL (ZRW) SKL ULT SYSTEM BLOCK DIAGRAM D
5
4
3
2
1
01
BOM
Zoro_SL (ZRW) SKL ULT SYSTEM BLOCK DIAGRAM
D
IV@
: iGPU
D
EV@
: Optimus
VRAM
GPU
DDR3L-SODIMM CHA
Dual Channel DDR III
1066/1333/1600 MHZ
DDR3
GT@ : N16S-GT / GC6
GM@ : N16V-GM / WO GC6
DR@ : For Dual Rank ( VRAM 8 pcs)
SKY LAKE ULT 15W
N16S-GT
P18~P19
KBL@
P12
PCIE1-4
N16V-GM
TPM@
: Keyboard backlight
: TPM
PCI-E x4
MCP 1356pins
TX/RX
TPM_N@: For TPM 2.0
DDR3L-SODIMM CHB
IMC
TPM_l@ : For TPM 1.2
DC+GT3e
X'TAL 27MHz
P13
CLK
8M@
: 8M FLASH ROM
42 mm X 24 mm
P14~P19
4M@
: 4M FLASH ROM
SATA - HDD
SATA0
GS@ :G-SENSOR
EDP
P25
SATA
eDP Conn.
TDI@
: TOUCH PAD I2C
P21
eDP
TSU@
: TOUCH SCREEN USB
SATA ODD
SATA1
TSI@
: TOUCH SCREEN I2C
P25
GT3@
DDI2
ITE6516
VGA Conn.
NAC@
: GT3 CPU
: Non IOAC
P21
P20
IOAC@
: For IOAC
DP
C
DDI1
C
PS8201
HDMI Conn.
Cardreader
CONN. 2in 1
Integrated PCH
P22
USB2-8
P22
RTS5170
USB3-1 & USB3-2
P28
(cardreader)
P28
USB3.0/2.0
USB2-7
USB2-1 & USB2-2
CCD(Camera)
P21
USB3 Port MB side
CN13 -> USB3 port 2 ( up )
CN16 -> USB3 port 1 ( down )
USB2.0
P28
USB2-6
CLK
Touch Screen
P21
PCI-E x1
PCIE-6
USB2-5
Blue Tooth
MINI CARD
P26
WLAN+BT
I/O board
X'TAL
P26
USB2-4
32.768KHz
USB2 IO*1
I/O Board Conn.
RTL8111H
RJ45
PCIE-5
P28
P23
X'TAL 24MHz
10/100/1G
P23
DMIC_CLK0
DMIC_DATA0
CLK
P6
BATTERY
RTC
X'TAL 25MHz
Azalia
P2~P10
I2C_0
B
B
IHDA
SPI
LPC
SPI ROM
8M+4M
P7
EC
Int. D-MIC
ALC255
TPM(option)
D-MIC
BQ24780RUYR
G5316RZ1D
Thermal Protection
AUDIO CODEC
IT8987
P25
Batery Charger
P30
+1.35VSUS
P35
Discharger
P40
P24
P24
P29
TPS51225
MDV1528Q
UP1658RQKF
+3V/+5V
P31
+5V_S5/+3V_S5/+3V/+5V
P31
+VGPU_CORE
P41
RT8237CZQW
ISL95859HRTZ-T
RT8068AZQW
+1V_S5
P32
+VCORE/VCCSA/VCCGT
P38
P42
+1.05V_GFX/+3V_GFX
+1.5V_GFX
K/B
Universal HP
Speaker*2
LED
Touch PAD
HALL
Fan Driver
NB681GD-Z
BL
K/B Con.
SENSOR
P24
P24
P27
(Fan
signal) P27
Con.
P27
P27
P27
P17
+VCCOPC/+VCCEOPIO
P33
A
A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Dr-Bios.com
PROJECT :
PROJECT :
PROJECT :
ZRW
ZRW
ZRW
P7
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Block Diagram
Block Diagram
Block Diagram
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
1
1
1
of
of
of
48
48
48
5
4
3
2
1
5 4 3 2 1 02 Skylake ULT (DISPLAY,eDP) SKL_ULT U35A D D E55 C47
5
4
3
2
1
02
Skylake ULT (DISPLAY,eDP)
SKL_ULT
U35A
D
D
E55
C47
EDP_TXN0
(22)
INT_HDMITX2N
EDP_TXN0
(21)
DDI1_TXN[0]
EDP_TXN[0]
F55
C46
EDP_TXP0
(22)
INT_HDMITX2P
EDP_TXP0
(21)
eDP Panel
DDI1_TXP[0]
EDP_TXP[0]
E58
D46
+3V
EDP_TXN1
(22)
INT_HDMITX1N
EDP_TXN1
(21)
DDI1_TXN[1]
EDP_TXN[1]
F58
C45
EDP_TXP1
(22)
INT_HDMITX1P
EDP_TXP1
(21)
DDI1_TXP[1]
EDP_TXP[1]
F53
A45
(22)
INT_HDMITX0N
DDI1_TXN[2]
EDP_TXN[2]
G53
B45
CRT_AUXN
R533
*100K_4
(22)
INT_HDMITX0P
DDI1_TXP[2]
EDP_TXP[2]
F56
A47
(22)
INT_HDMICLK-
DDI1_TXN[3]
EDP_TXN[3]
G56
B47
CRT_AUXP
R532
*100K_4
(22)
INT_HDMICLK+
DDI1_TXP[3]
EDP_TXP[3]
C50
E45
EDP_AUXN
(20)
CRT_TXN0
DDI2_TXN[0]
EDP_AUXN
EDP_AUXN
(21)
DDI
D50
EDP
F45
EDP_AUXP
(20)
CRT_TXP0
EDP_AUXP
(21)
DDI2_TXP[0]
EDP_AUXP
C52
(20)
CRT_TXN1
DDI2_TXN[1]
D52
B52
DP_UTIL
R546
*0_4
PCH_BRIGHT
(20)
CRT_TXP1
DDI2_TXP[1]
EDP_DISP_UTIL
A50
R553
*0_4
DDI2_TXN[2]
ITE FAE suggest CAP
should be at PCH side.
B50
G50
DDI2_TXP[2]
DDI1_AUXN
D51
F50
+3V
DDI2_TXN[3]
DDI1_AUXP
C51
E48
CRT_AUX#_C
C671
*short_4
CRT_AUXN
(20)
DDI2_TXP[3]
DDI2_AUXN
F48
CRT_AUX_C
C670
*short_4
CRT_AUXP
(20)
DDI2_AUXP
G46
CRT_CLK
R577
2.2K_4
DDI3_AUXN
DISPLAY SIDEBANDS
F46
CRT_DATA
R152
2.2K_4
DDI3_AUXP
Rev:D change to shortpad
HDMI_DDCCLK_SW
L13
KBSMI#
R780
20K/F_4
(22)
HDMI_DDCCLK_SW
+3V_S5
GPP_E18/DDPB_CTRLCLK
HDMI_DDCDATA_SW
L12
+3V_S5
L9
INT_HDMI_HPD
EC_SCI#
R781
20K/F_4
(22)
HDMI_DDCDATA_SW
INT_HDMI_HPD
(22)
GPP_E19/DDPB_CTRLDATA
+3V_S5
GPP_E13/DDPB_HPD0
L7
CRT_HPD
+3V_S5
CRT_HPD
(20)
GPP_E14/DDPC_HPD1
CRT_CLK
N7
L6
R567
*short_4
+3V_S5
Rev:D add
GPP_E20/DDPC_CTRLCLK
+3V_S5
KBSMI#
(29)
GPP_E15/DDPD_HPD2
CRT_DATA
N8
N9
R571
*short_4
GPP_E21/DDPC_CTRLDATA
+3V_S5
+3V_S5
GPP_E16/DDPE_HPD3
EC_SCI#
(29)
L10
EDP_HPD
EDP_HPD
(21)
+3V_S5
GPP_E17/EDP_HPD
N11
+3V_S5
GPP_E22/DDPD_CTRLCLK
N12
R12
PCH_BLON
(25)
PCH_ODD_EN
+3V_S5
PCH_BLON
(21)
GPP_E23/DDPD_CTRLDATA
EDP_BKLTEN
R11
PCH_BRIGHT
PCH_BRIGHT
(21)
EDP_BKLTCTL
24.9/F_4
R154 EDP_RCOMP
E52
U13
PCH_VDDEN
+VCCIO
EDP_RCOMP
EDP_VDDEN
EDP_VDD_EN
(21)
1 OF 20
eDP_RCOMP
Trace length < 100 mils
CRT_HPD
R564
100K_4
REV SKL_ULT/BGA = 1
?
EDP_HPD
R563
100K_4
Trace width = 20 mils
C
C
Trace spacing = 25 mils
+1V_VCCST
100k pull-down on PCH side
1K_4
R529
CPU_THRMTRIP#
49.9/F_4
R788
CATERR#
H_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches
U35D
SKL_ULT
Rev:E Stuff only for C2 build Debug
Ramp will remove
CATERR#
D63
(29)
H_PECI
TP65
CATERR#
H_PECI
A54
PECI
H_PROCHOT#
R531
499/F_4
H_PROCHOT#_R
C65
(29,30,36)
H_PROCHOT#
JTAG
PROCHOT#
THRMTRIP#
R530
100/F_4
CPU_THRMTRIP#
C63
Avoid 125Mhz
THERMTRIP#
A65
B61
XDP_TCK0
SKTOCC#
PROC_TCK
D60
XDP_TDI_CPU
CPU MISC
PROC_TDI
XDP_BPM#0
C55
A61
XDP_TDO_CPU
TP89
BPM#[0]
PROC_TDO
+VCCIO
BPM#[0:7]
XDP_BPM#1
D55
C60
XDP_TMS_CPU
TP90
BPM#[1]
PROC_TMS
XDP_BPM#2
B54
B59
XDP_TRST#
Trace Length
1~6 inches
MP remove(Intel)
TP64
BPM#[2]
PROC_TRST#
XDP_BPM#3
C56
Length match < 300 mils
TP62
PCH JTAG
BPM#[3]
R465
1K_4
H_PROCHOT#
B56
XDP_TCK1
PCH_JTAG_TCK
A6
+3V_S5
D59
XDP_TDI
GPP_E3/CPU_GP0
PCH_JTAG_TDI
A7
A56
+1V_VCCST
+3V_S5
PCH _JTAG_TDO
R539
*short_4
XDP_TDO
JTAG_TCK,JTAG_TMS
Trace Length < 9000mils
Change to +1V_VCCST 11/6
GPP_E7/CPU_GP1
PCH_JTAG_TDO
DGPU_PW_CTRL#
BA5
+3V_S5
C59
XDP_TMS
(4)
DGPU_PW_CTRL#
GPP_B3/CPU_GP2
PCH_JTAG_TMS
AY5
+3V_S5
C61
GPP_B4/CPU_GP3
PCH_TRST#
A59
PCH_TRST#
R549
*short_4
XDP_TRST#
JTAGX
SM_RCOMP[0:2]
R635
49.9/F_4
AT16
TCK,TMS
Trace Length < 9000mils
PROC_POPIRCOMP
R646
49.9/F_4
AU16
PCH_JTAGX
R517
*short_4
XDP_TCK0
XDP_TDO_CPU
R559
51_4
Trace length < 500 mils
Trace width = 12~15 mils
Trace spacing = 20 mils
PCH_OPIRCOMP
R158
49.9/F_4
H66
XDP_TMS
R514
51_4
OPCE_RCOMP
R162
49.9/F_4
H65
XDP_TDI
R515
51_4
Rev:D change to shortpad
OPC_RCOMP
PCH _JTAG_TDO
R538
51_4
PCH_JTAGX
R513
*1K_4
4 OF 20
REV SKL_ULT/BGA = 1
?
B
B
XDP_TRST#
R535
*51_4
XDP_TCK0
R558
51_4
XDP_TDO
R795
0_4
XDP_TDO_CPU
XDP_TCK1
R537
*51_4
PCH_TRST#
51_4
XDP_TDI
R796
0_4
XDP_TDI_CPU
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches
R534
XDP_TMS
R797
0_4
XDP_TMS_CPU
2/16
,XDP_TCK1,XDP_TMS
If use Intel DCI USB 3.0 fixture need to short
don't need pull up or pull down
1. XDP_TDO <--> XDP_TDO_CPU
2. XDP_TDI
<--> XDP_TDI_CPU
Rev:F add
5/29 XDP_TCK0 R558 Stuff
3. XDP_TMS <--> XDP_TMS_CPU
+1V_VCCST
CPU thermal trip
IMVP_PWRGD_3V
2
Q31
+1V_VCCST
U33
+3V
FDV301N
1
5
NC
VCC
+1V_VCCST
R485
2
C628
R74
10K_4
(36)
IMVP_PWRGD
A
0.1u/16V_4
1K_4
A
A
3
4
R488
GND
Y
IMVP_PWRGD_3V
(8)
*1K_4
74AUP1G07GW
THRMTRIP#
1
3
SYS_SHDN#
(31,40)
Q5
MMBT3904-7-F
R478
*0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Dr-Bios.com
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
2
2
2
of
of
of
48
48
48
5
4
3
2
1
HDMICRT
12
2
1
3
5 4 3 2 1 03 Change Data and DQS to interleave. SKL ULT (DDR3L)
5
4
3
2
1
03
Change Data and DQS to interleave.
SKL ULT (DDR3L)
SKL ULT (DDR3L)
?
SKL_ULT
?
U35B
SKL_ULT
U35C
D
AU53
D
M_A_CLK0#
(12)
DDR0_CKN[0]
M_A_DQ0
AL71
AT53
(12)
M_A_DQ0
M_A_CLK0
(12)
DDR0_DQ[0]
DDR0_CKP[0]
M_A_DQ1
AL68
AU55
M_B_DQ0
AF65
AN45
(12)
M_A_DQ1
M_A_CLK1#
(12)
(13)
M_B_DQ0
M_B_CLK0#
(13)
DDR0_DQ[1]
DDR0_CKN[1]
DDR1_DQ[0]/DDR0_DQ[16]
DDR1_CKN[0]
M_A_DQ2
AN68
AT55
M_B_DQ1
AF64
AN46
(12)
M_A_DQ2
M_A_CLK1
(12)
(13)
M_B_DQ1
M_B_CLK1#
(13)
DDR0_DQ[2]
DDR0_CKP[1]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_CKN[1]
M_A_DQ3
AN69
M_B_DQ2
AK65
AP45
(12)
M_A_DQ3
(13)
M_B_DQ2
M_B_CLK0
(13)
DDR0_DQ[3]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_CKP[0]
M_A_DQ4
AL70
BA56
M_B_DQ3
AK64
AP46
(12)
M_A_DQ4
M_A_CKE0
(12)
(13)
M_B_DQ3
M_B_CLK1
(13)
DDR0_DQ[4]
DDR0_CKE[0]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_CKP[1]
M_A_DQ5
AL69
BB56
M_B_DQ4
AF66
(12)
M_A_DQ5
M_A_CKE1
(12)
(13)
M_B_DQ4
DDR0_DQ[5]
DDR0_CKE[1]
DDR1_DQ[4]/DDR0_DQ[20]
M_A_DQ6
AN70
AW56
M_B_DQ5
AF67
AN56
(12)
M_A_DQ6
(13)
M_B_DQ5
M_B_CKE0
(13)
DDR0_DQ[6]
DDR0_CKE[2]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_CKE[0]
M_A_DQ7
AN71
AY56
M_B_DQ6
AK67
AP55
(12)
M_A_DQ7
(13)
M_B_DQ6
M_B_CKE1
(13)
DDR0_DQ[7]
DDR0_CKE[3]
DDR1_DQ[6]/DDR0_DQ[22]
DDR1_CKE[1]
M_A_DQ8
AR70
M_B_DQ7
AK66
AN55
(12)
M_A_DQ8
(13)
M_B_DQ7
DDR0_DQ[8]
DDR1_DQ[7]/DDR0_DQ[23]
DDR1_CKE[2]
M_A_DQ9
AR68
AU45
M_B_DQ8
AF70
AP53
(12)
M_A_DQ9
M_A_CS#0
(12)
(13)
M_B_DQ8
DDR0_DQ[9]
DDR0_CS#[0]
DDR1_DQ[8]/DDR0_DQ[24]
DDR1_CKE[3]
M_A_DQ10
AU71
AU43
M_B_DQ9
AF68
(12)
M_A_DQ10
M_A_CS#1
(12)
(13)
M_B_DQ9
DDR0_DQ[10]
DDR0_CS#[1]
DDR1_DQ[9]/DDR0_DQ[25]
M_A_DQ11
AU68
AT45
M_A_ODT0
M_B_DQ10
AH71
BB42
(12)
M_A_DQ11
M_A_ODT0_DIMM
(12)
(13)
M_B_DQ10
M_B_CS#0
(13)
DDR0_DQ[11]
DDR0_ODT[0]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_CS#[0]
M_A_DQ12
AR71
AT43
M_A_ODT1
M_B_DQ11
AH68
AY42
(12)
M_A_DQ12
M_A_ODT1_DIMM
(12)
(13)
M_B_DQ11
M_B_CS#1
(13)
DDR0_DQ[12]
DDR0_ODT[1]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_CS#[1]
M_A_DQ13
AR69
M_B_DQ12
AF71
BA42
M_B_ODT0
(12)
M_A_DQ13
(13)
M_B_DQ12
M_B_ODT0_DIMM
(13)
DDR0_DQ[13]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_ODT[0]
M_A_DQ14
AU70
BA51
M_A_A5
M_B_DQ13
AF69
AW42
M_B_ODT1
(12)
M_A_DQ14
(13)
M_B_DQ13
M_B_ODT1_DIMM
(13)
DDR0_DQ[14]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_ODT[1]
M_A_DQ15
AU69
BB54
M_A_A9
M_B_DQ14
AH70
(12)
M_A_DQ15
(13)
M_B_DQ14
DDR0_DQ[15]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR1_DQ[14]/DDR0_DQ[30]
M_A_DQ16
BB65
BA52
M_A_A6
M_B_DQ15
AH69
AY48
M_B_A5
(12)
M_A_DQ16
(13)
M_B_DQ15
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
M_A_DQ17
AW65
AY52
M_A_A8
M_B_DQ16
AT66
AP50
M_B_A9
(12)
M_A_DQ17
(13)
M_B_DQ16
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
M_A_DQ18
AW63
AW52
M_A_A7
M_B_DQ17
AU66
BA48
M_B_A6
(12)
M_A_DQ18
(13)
M_B_DQ17
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
M_A_DQ19
AY63
AY55
M_B_DQ18
AP65
BB48
M_B_A8
(12)
M_A_DQ19
M_A_BS#2
(12)
(13)
M_B_DQ18
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
M_A_DQ20
BA65
AW54
M_A_A12
M_B_DQ19
AN65
AP48
M_B_A7
(12)
M_A_DQ20
(13)
M_B_DQ19
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
M_A_DQ21
AY65
BA54
M_A_A11
M_B_DQ20
AN66
AP52
(12)
M_A_DQ21
(13)
M_B_DQ20
M_B_BS#2
(13)
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
M_A_DQ22
BA63
BA55
M_A_A15
M_B_DQ21
AP66
AN50
M_B_A12
(12)
M_A_DQ22
(13)
M_B_DQ21
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
M_A_DQ23
BB63
AY54
M_A_A14
M_B_DQ22
AT65
AN48
M_B_A11
(12)
M_A_DQ23
(13)
M_B_DQ22
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
M_A_DQ24
BA61
M_B_DQ23
AU65
AN53
M_B_A15
(12)
M_A_DQ24
(13)
M_B_DQ23
DDR0_DQ[24]/DDR0_DQ[40]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
M_A_DQ25
AW61
AU46
M_A_A13
M_B_DQ24
AT61
AN52
M_B_A14
(12)
M_A_DQ25
(13)
M_B_DQ24
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
M_A_DQ26
BB59
AU48
M_B_DQ25
AU61
(12)
M_A_DQ26
M_A_CAS#
(12)
(13)
M_B_DQ25
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR1_DQ[25]/DDR0_DQ[57]
M_A_DQ27
AW59
AT46
M_B_DQ26
AP60
BA43
M_B_A13
(12)
M_A_DQ27
M_A_WE#
(12)
(13)
M_B_DQ26
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
M_A_DQ28
BB61
AU50
M_B_DQ27
AN60
AY43
(12)
M_A_DQ28
M_A_RAS#
(12)
(13)
M_B_DQ27
M_B_CAS#
(13)
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
M_A_DQ29
AY61
AU52
M_B_DQ28
AN61
AY44
(12)
M_A_DQ29
M_A_BS#0
(12)
(13)
M_B_DQ28
M_B_WE#
(13)
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
M_A_DQ30
BA59
AY51
M_A_A2
M_B_DQ29
AP61
AW44
(12)
M_A_DQ30
(13)
M_B_DQ29
M_B_RAS#
(13)
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
C
M_A_DQ31
AY59
AT48
M_B_DQ30
AT60
BB44
C
(12)
M_A_DQ31
M_A_BS#1
(12)
(13)
M_B_DQ30
M_B_BS#0
(13)
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
M_A_DQ32
AY39
AT50
M_A_A10
M_B_DQ31
AU60
AY47
M_B_A2
(12)
M_A_DQ32
(13)
M_B_DQ31
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
M_A_DQ33
AW39
BB50
M_A_A1
M_B_DQ32
AU40
BA44
(12)
M_A_DQ33
(13)
M_B_DQ32
M_B_BS#1
(13)
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
M_A_DQ34
AY37
AY50
M_A_A0
M_B_DQ33
AT40
AW46
M_B_A10
(12)
M_A_DQ34
(13)
M_B_DQ33
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
M_A_DQ35
AW37
BA50
M_A_A3
M_B_DQ34
AT37
AY46
M_B_A1
(12)
M_A_DQ35
(13)
M_B_DQ34
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_MA[3]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
M_A_DQ36
BB39
BB52
M_A_A4
M_B_DQ35
AU37
BA46
M_B_A0
(12)
M_A_DQ36
(13)
M_B_DQ35
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_MA[4]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
M_A_DQ37
BA39
M_B_DQ36
AR40
BB46
M_B_A3
(12)
M_A_DQ37
(13)
M_B_DQ36
DDR0_DQ[37]/DDR1_DQ[5]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_MA[3]
M_A_DQ38
BA37
AM70
M_A_DQS#0
M_B_DQ37
AP40
BA47
M_B_A4
(12)
M_A_DQ38
M_A_DQS#0
(12)
(13)
M_B_DQ37
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQSN[0]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_MA[4]
M_A_DQ39
BB37
AM69
M_A_DQS0
M_B_DQ38
AP37
(12)
M_A_DQ39
M_A_DQS0
(12)
(13)
M_B_DQ38
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQSP[0]
DDR1_DQ[38]/DDR1_DQ[22]
M_A_DQ40
AY35
AT69
M_A_DQS#1
M_B_DQ39
AR37
AH66
M_B_DQS#0
(12)
M_A_DQ40
M_A_DQS#1
(12)
(13)
M_B_DQ39
M_B_DQS#0
(13)
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQSN[1]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQSN[0]/DDR0_DQSN[2]
M_A_DQ41
AW35
AT70
M_A_DQS1
M_B_DQ40
AT33
AH65
M_B_DQS0
(12)
M_A_DQ41
M_A_DQS1
(12)
(13)
M_B_DQ40
M_B_DQS0
(13)
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQSP[1]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQSP[0]/DDR0_DQSP[2]
M_A_DQ42
AY33
BA64
M_A_DQS#2
M_B_DQ41
AU33
AG69
M_B_DQS#1
(12)
M_A_DQ42
M_A_DQS#2
(12)
(13)
M_B_DQ41
M_B_DQS#1
(13)
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQSN[1]/DDR0_DQSN[3]
M_A_DQ43
AW33
AY64
M_A_DQS2
M_B_DQ42
AU30
AG70
M_B_DQS1
(12)
M_A_DQ43
M_A_DQS2
(12)
(13)
M_B_DQ42
M_B_DQS1
(13)
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQSP[1]/DDR0_DQSP[3]
M_A_DQ44
BB35
AY60
M_A_DQS#3
M_B_DQ43
AT30
AR66
M_B_DQS#2
(12)
M_A_DQ44
M_A_DQS#3
(12)
(13)
M_B_DQ43
M_B_DQS#2
(13)
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQSN[2]/DDR0_DQSN[6]
M_A_DQ45
BA35
BA60
M_A_DQS3
M_B_DQ44
AR33
AR65
M_B_DQS2
(12)
M_A_DQ45
M_A_DQS3
(12)
(13)
M_B_DQ44
M_B_DQS2
(13)
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQSP[2]/DDR0_DQSP[6]
M_A_DQ46
BA33
BA38
M_A_DQS#4
M_B_DQ45
AP33
AR61
M_B_DQS#3
(12)
M_A_DQ46
M_A_DQS#4
(12)
(13)
M_B_DQ45
M_B_DQS#3
(13)
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQSN[3]/DDR0_DQSN[7]
M_A_DQ47
BB33
AY38
M_A_DQS4
M_B_DQ46
AR30
AR60
M_B_DQS3
(12)
M_A_DQ47
M_A_DQS4
(12)
(13)
M_B_DQ46
M_B_DQS3
(13)
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQSP[3]/DDR0_DQSP[7]
M_A_DQ48
AY31
AY34
M_A_DQS#5
M_B_DQ47
AP30
AT38
M_B_DQS#4
(12)
M_A_DQ48
M_A_DQS#5
(12)
(13)
M_B_DQ47
M_B_DQS#4
(13)
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQSN[4]/DDR1_DQSN[2]
M_A_DQ49
AW31
BA34
M_A_DQS5
M_B_DQ48
AU27
AR38
M_B_DQS4
(12)
M_A_DQ49
M_A_DQS5
(12)
(13)
M_B_DQ48
M_B_DQS4
(13)
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQ[48]
DDR1_DQSP[4]/DDR1_DQSP[2]
M_A_DQ50
AY29
BA30
M_A_DQS#6
M_B_DQ49
AT27
AT32
M_B_DQS#5
(12)
M_A_DQ50
M_A_DQS#6
(12)
(13)
M_B_DQ49
M_B_DQS#5
(13)
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR1_DQ[49]
DDR1_DQSN[5]/DDR1_DQSN[3]
M_A_DQ51
AW29
AY30
M_A_DQS6
M_B_DQ50
AT25
AR32
M_B_DQS5
(12)
M_A_DQ51
M_A_DQS6
(12)
(13)
M_B_DQ50
M_B_DQS5
(13)
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR1_DQ[50]
DDR1_DQSP[5]/DDR1_DQSP[3]
M_A_DQ52
BB31
AY26
M_A_DQS#7
M_B_DQ51
AU25
AR25
M_B_DQS#6
(12)
M_A_DQ52
M_A_DQS#7
(12)
(13)
M_B_DQ51
M_B_DQS#6
(13)
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR1_DQ[51]
DDR1_DQSN[6]
M_A_DQ53
BA31
BA26
M_A_DQS7
M_B_DQ52
AP27
AR27
M_B_DQS6
(12)
M_A_DQ53
M_A_DQS7
(12)
(13)
M_B_DQ52
M_B_DQS6
(13)
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQ[52]
DDR1_DQSP[6]
M_A_DQ54
BA29
M_B_DQ53
AN27
AR22
M_B_DQS#7
(12)
M_A_DQ54
(13)
M_B_DQ53
M_B_DQS#7
(13)
DDR0_DQ[54]/DDR1_DQ[38]
DDR1_DQ[53]
DDR1_DQSN[7]
M_A_DQ55
BB29
AW50
DDR0_ALERT#
M_B_DQ54
AN25
AR21
M_B_DQS7
(12)
M_A_DQ55
(13)
M_B_DQ54
M_B_DQS7
(13)
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_ALERT#
DDR1_DQ[54]
DDR1_DQSP[7]
M_A_DQ56
AY27
AT52
TP_DDR0_PARITY#
M_B_DQ55
AP25
(12)
M_A_DQ56
(13)
M_B_DQ55
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_PAR
TP21
DDR1_DQ[55]
M_A_DQ57
AW27
M_B_DQ56
AT22
AN43
DDR1_ALERT#
(12)
M_A_DQ57
(13)
M_B_DQ56
DDR0_DQ[57]/DDR1_DQ[41]
DDR1_DQ[56]
DDR1_ALERT#
M_A_DQ58
AY25
AY67
M_B_DQ57
AU22
AP43
TP_DDR1_PARITY#
(12)
M_A_DQ58
+VREF_CA_CPU
(13)
M_B_DQ57
DDR0_DQ[58]/DDR1_DQ[42]
DDR_VREF_CA
DDR1_DQ[57]
DDR1_PAR
TP18
M_A_DQ59
AW25
AY68
M_B_DQ58
AU21
AT13
CPU_DRAMRST#
(12)
M_A_DQ59
+VREFDQ_SA_M3
(13)
M_B_DQ58
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_VREF_DQ
DDR1_DQ[58]
DRAM_RESET#
M_A_DQ60
BB27
DDR CH - A
BA67
M_B_DQ59
AT21
AR18
SM_RCOMP_0
(12)
M_A_DQ60
+VREFDQ_SB_M3
(13)
M_B_DQ59
DDR0_DQ[60]/DDR1_DQ[44]
DDR1_VREF_DQ
DDR1_DQ[59]
DDR_RCOMP[0]
M_A_DQ61
BA27
M_B_DQ60
AN22
AT18
SM_RCOMP_1
(12)
M_A_DQ61
(13)
M_B_DQ60
DDR0_DQ[61]/DDR1_DQ[45]
DDR1_DQ[60]
DDR_RCOMP[1]
M_A_DQ62
BA25
AW67
DDR_VTT_CTRL
M_B_DQ61
AP22
AU18
SM_RCOMP_2
(12)
M_A_DQ62
(13)
M_B_DQ61
DDR0_DQ[62]/DDR1_DQ[46]
DDR_VTT_CNTL
DDR1_DQ[61]
DDR_RCOMP[2]
B
+3V_S5
M_A_DQ63
BB25
M_B_DQ62
AP21
B
(12)
M_A_DQ63
(13)
M_B_DQ62
DDR0_DQ[63]/DDR1_DQ[47]
DDR1_DQ[62]
M_B_DQ63
AN21
DDR CH - B
(13)
M_B_DQ63
2 OF 20
+1.35VSUS
DDR1_DQ[63]
REV SKL_ULT/BGA = 1
3 OF 20
?
R682
SKL_ULT/BGA
REV = 1
?
*100K_4
M_B_A[15:0]
M_B_A[15:0]
(13)
M_A_A[15:0]
M_A_A[15:0]
(12)
R621
*10K_4
1
3
DDR_VTTT_PG_CTRL
(35)
DDR0_ALERT#
Q35
DDR1_ALERT#
*DTC144EU
REV:E connect to GND
Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
DRAM COMP
SM_RCOMP_0
120/F_4
R685
DRAMRST
SM_RCOMP_1
80.6/F_4
R678
+1.35VSUS
SM_RCOMP_2
100/F_4
R681
A
R679
A
470_4
CPU
DRAM
CPU_DRAMRST#
R670
*short_4
DDR3_DRAMRST#
(12,13)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
C750
*0.1u/16V_4
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
3
3
3
of
of
of
48
48
48
5
4
3
2
1
2
12
12

Dr-Bios.com

5 4 3 2 1 04 SKL ULT (SIDEBAND ) GPIO H_PECI (50ohm) Route on
5
4
3
2
1
04
SKL ULT (SIDEBAND )
GPIO
H_PECI (50ohm)
Route on microstrip only
SKL_ULT
U35F
Spacing >18 mils
Trace Length: 0.4~6.125 iches
Add GPU Power Control Siganls
LPSS
ISH
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches
AN8
+3V_S5
(41)
VGPU_EN
GPP_B15/GSPI0_CS#
P2
AP7
+3V_S5
+3V_S5
GPP_D9
(14)
DGPU_HOLD_RST#
GPP_B16/GSPI0_CLK
P3
AP8
+3V_S5
+3V_S5
GPP_D10
(42)
DGPU_PWR_EN
GPP_B17/GSPI0_MISO
P4
GSPI0_MOSI
AR7
+3V_S5
+3V_S5
GPP_D11
P1
D
GPP_B18/GSPI0_MOSI
D
+3V_S5
GPP_D12
AM5
+3V_S5
(16)
DGPU_PWROK
GPP_B19/GSPI1_CS#
M4
AN7
+3V_S5
+3V_S5
GPP_D5/ISH_I2C0_SDA
(15,17)
GC6_FB_EN
GPP_B20/GSPI1_CLK
N3
AP5
+3V_S5
+3V_S5
GPP_D6/ISH_I2C0_SCL
(17)
DGPU_EVENT#
GPP_B21/GSPI1_MISO
+3V_S5
GSPI1_MOSI
AN5
+3V_S5
GPP_B22/GSPI1_MOSI
N1
+3V_S5
GPP_D7/ISH_I2C1_SDA
N2
AB1
+3V_S5
+3V_S5
GPP_D8/ISH_I2C1_SCL
(27)
ACCEL_INTA
GPP_C8/UART0_RXD
2.2K_4
R167
I2C0_SDA
Touch PAD
AB2
+3V_S5
(25)
ODD_PRSNT#
GPP_C9/UART0_TXD
AD11
2.2K_4
R166
I2C0_SCL
TPD_INT#_D
W4
+3V_S5
+1.8V_S5
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_C10/UART0_RTS#
AD12
*2.2K_4
R165
I2C1_SDA
AB3
+3V_S5
+1.8V_S5
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
(21)
TP_INT_PCH
GPP_C11/UART0_CTS#
*2.2K_4
R169
I2C1_SCL
Touch Screen
UART2_RXD
AD1
+3V_S5
Reserve UART FFC connector for Win 7 debug
GPP_C20/UART2_RXD
U1
UART2_TXD
AD2
+3V_S5
+3V_S5
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_C21/UART2_TXD
U2
PU 2.2K for touch pad I2C bus(400 KHz)
AD3
+3V_S5
UART2 for RMT
UART2_RTS#
+3V_S5
+3V_S5
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_C22/UART2_RTS#
U3
UART2_CTS#
AD4
+3V_S5
+3V_S5
GPP_D15/ISH_UART0_RTS#
GPP_C23/UART2_CTS#
U4
+3V_S5
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPU Control PU/PD
AC1
+3V
I2C0_SDA
U7
+3V_S5
+3V_S5
GPP_C12/UART1_RXD/ISH_UART1_RXD
UART2_RXD
R275
*49.9K/F_4
(27)
I2C0_SDA
GPP_C16/I2C0_SDA
AC2
I2C0_SCL
U6
Touch PAD
+3V_S5
+3V_S5
GPP_C13/UART1_TXD/ISH_UART1_TXD
UART2_TXD
R280
*49.9K/F_4
(27)
I2C0_SCL
GPP_C17/I2C0_SCL
AC3
+3V_S5
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
UART2_RTS#
R283
*49.9K/F_4
AB4
*EV@10K_4
R220
VGPU_EN
*IV@10K_4
R196
I2C1_SDA
U8
+3V_S5
+3V_S5
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
UART2_CTS#
R290
*49.9K/F_4
(21)
I2C1_SDA
GPP_C18/I2C1_SDA
U9
Touch Screen
I2C1_SCL
+3V_S5
(21)
I2C1_SCL
GPP_C19/I2C1_SCL
AY8
*10K_4
R257
DGPU_PWR_EN
*100K_4
R256
+3V_S5
GPP_A18/ISH_GP0
BA8
AH9
+1.8V_S5
+3V_S5
GPP_A19/ISH_GP1
GPP_F4/I2C2_SDA
BB7
+5V
*10K_4
R204
GC6_FB_EN
*10K_4
R199
AH10
+1.8V_S5
+3V_S5
GPP_A20/ISH_GP2
GPP_F5/I2C2_SCL
BA7
+3V_S5
GPP_A21/ISH_GP3
AY7
1A-1 20131015 For GC6 NV DG GC6_FB_EN PD.
AH11
+1.8V_S5
+3V_S5
GPP_A22/ISH_GP4
CN3
GPP_F6/I2C3_SDA
AW7
AH12
+1.8V_S5
+3V_S5
GPP_A23/ISH_GP5
GPP_F7/I2C3_SCL
AP13
+3V
+3V_S5
GPP_A12/BM_BUSY#/ISH_GP6
1
AF11
+1.8V_S5
UART2_RXD
GPP_F8/I2C4_SDA
2
AF12
+1.8V_S5
UART2_TXD
GPP_F9/I2C4_SCL
3
7
R208
10K_4
DGPU_HOLD_RST#
UART2_RTS#
4
8
UART2_CTS#
6 OF 20
5
SKL_ULT/BGA
REV = 1
6
?
DGPU_PW_CTRL#
UMA Only
*UART Function
high
C
C
low
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
SKL_ULT
U35G
HDA
C742
*10p/50V_4
AUDIO
+3V
R667
33_4
HDA_SYNC_R
BA22
(24)
PCH_AZ_CODEC_SYNC
HDA_SYNC/I2S0_SFRM
R644
33_4
HDA_BCLK_R
AY22
(2)
DGPU_PW_CTRL#
(24)
PCH_AZ_CODEC_BITCLK
HDA_BLK/I2S0_SCLK
R645
33_4
HDA_SDO_R
BB22
SDIO/SDXC
(24)
PCH_AZ_CODEC_SDOUT
HDA_SDO/I2S0_TXD
BA21
(24)
PCH_AZ_CODEC_SDIN0
HDA_SDI0/I2S0_RXD
R127
EV@100K_4
DGPU_PW_CTRL#
R115
IV@1K_4
AY21
+3V_S5
AB11
HDA_SDI1/I2S1_RXD
SD GPI
GPP_G0/SD_CMD
DGPU_PWROK
R110
*10K_4
R660
33_4
HDA_RST#_R
AW22
+3V_S5
AB13
(24)
PCH_AZ_CODEC_RST#
HDA_RST#/I2S1_SCLK
SD GPI
GPP_G1/SD_DATA0
J5
+3V_S5
AB12
GPP_D23/I2S_MCLK
+3V_S5
SD GPI
GPP_G2/SD_DATA1
DGPU_PWROK PD on GPU side
AY20
+3V_S5
W12
I2S1_SFRM
SD GPI
GPP_G3/SD_DATA2
C739
AW20
+3V_S5
W11
I2S1_TXD
SD GPI
GPP_G4/SD_DATA3
*10p/50V_4
+3V_S5
W10
SD GPI
GPP_G5/SD_CD#
AK7
+1.8V_S5
+3V_S5
W8
GPP_F1/I2S2_SFRM
SD GPI
GPP_G6/SD_CLK
AK6
+1.8V_S5
+3V_S5
W7
GPP_F0/I2S2_SCLK
SD GPI
GPP_G7/SD_WP
DGPU_PW_CTRL#
VGA H/W
Setup
Reserve connect to DMIC (acer request 1/14)
AK9
+1.8V_S5
GPP_F2/I2S2_TXD
Signal
Menu
AK10
+1.8V_S5
BA9
GPP_F3/I2S2_RXD
+3V_S5
GPP_A17/SD_PWR_EN#/ISH_GP7
BB9
GPP_A16/SD_1P8_SEL
UMA Only
1
UMA
Hidden
UMA boot
+3V_S5
R769
*33_4
DMIC_CLK0_R
H5
AB7
200/F_4
R174
(24)
DMIC_CLK0_L
GPP_D19/DMIC_CLK0
+3V_S5
SD_RCOMP
R770
*33_4
DMIC_DATA0_R
D7
(24)
DMIC_DATA0_L
GPP_D20/DMIC_DATA0
+3V_S5
SG/Optimise
0
GPU
Hidden
GPU boot
D8
AF13
Strapping
GPP_D17/DMIC_CLK1
+3V_S5
+1.8V_S5
GPP_F23
C8
GPP_D18/DMIC_DATA1
+3V_S5
SPKR
R624
*20K_4
SPKR
AW5
(24)
SPKR
GPP_B14/SPKR
+3V_S5
545659-103
Skylake-U Strapping Table
7 OF 20
+3V_S5
Touchpad INT
SKL_ULT/BGA
REV = 1
?
Pin Name
Strap description
Sampled
Configuration
note
TPD_INT#_D
TDI@100K_4
R177
0
= *Disable Top Swap (iPD 20K)
B GPP_B14 (SPKR)
Top-Block Swap override
PCH_PWROK
R625
*1K_4
SPKR
+3V
B
1
= Enable Top Swap Mode
0
= *Disable No Reboot (iPD 20K)
+3V
GPP_B18
No reboot
PCH_PWROK
R619
*1K_4
GSPI0_MOSI
+3V
1
= Enable No Reboot Mode
(GSPI0_MOSI)
S5
S5
0
= *Disable Intel ME Cryp to TLS(iPD 20K)
GPP_C2
TLS Confidentiality
RSMRST#
R160
*10K_4
1
3
TPD_INT#_D
+3V_S5
SMBALERT#
(7)
(27,29)
TPD_INT#
1
= Enable Intel ME Cryp to TLS
(SMBALERT#)
Q20
0
= *SPI (iPD 20K)
TDI@2N7002K
GPP_B22
Boot BIOS Strap Bit (BBS)
PCH_PWROK
R207
*1K_4
GSPI1_MOSI
+3V
1
= LPC
R164
*0_4
(GSPI1_MOSI)
0
= *LPC is selected for EC (iPD 20K)
GPP_C5
eSPI or LPC
RSMRST#
R586
*1K_4
+3V_S5
SML0ALERT#
(7)
1
= eSPI selected for EC
(SML0ALERT#)
SPI0_MOSI
Reserved
RSMRST#
(iPU 15 ~ 40K)
SPI0_MISO
Reserved
RSMRST#
(iPU 15 ~ 40K)
GPP_B23
Reserved
RSMRST#
(iPD 20K)
(SML1ALERT#
/PCHHOT#)
SPI0_IO2
Reserved
RSMRST#
(iPU 15 ~ 40K)
A SPI0_IO3
Reserved
RSMRST#
(iPU 15 ~ 40K)
A
0
= *Enable security in the Flash
HDA_SDO /
Flash Descriptor Security
Override / Intel ME Debug Mode
change location to near CPU to prevent impact HDA_SDO signal
Description (iPD 20K)
PCH_PWROK
I2S_TXD0
1
= Disable Flash Descriptor Security (Override)
HDA_SDO_R
R737
1K_4
ME_WR#
(29)
GPP_E19
0
= *Port B is not detected (iPD 20K)
Display Port B Detected
PCH_PWROK
(DDPB_CTRLDATA)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
1
=Port B is detected
0
= *Port C is not detected (iPD 20K)
Dr-Bios.com
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
GPP_E21
Display Port C Detected
PCH_PWROK
1
=Port C is detected
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
(DDPC_CTRLDATA)
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
4
4
4
of
of
of
48
48
48
5
4
3
2
1
2
5 4 3 2 1 +VCCCORE ? SKL_ULT +VCCCORE U35L Backside cap CPU POWER 1
5
4
3
2
1
+VCCCORE
?
SKL_ULT
+VCCCORE
U35L
Backside cap
CPU POWER 1 OF 4
Primary side cap
A30
G32
05
VCC_A30
VCC_G32
A34
G33
S0
VCC
VCC_A34
VCC_G33
C184
A39
G35
0.55V~1.5V
VCC_A39
VCC_G35
C243
C233
C226
C203
C219
C224
C236
C255
C251
A44
G37
C666
C645
C144
C650
C659
C150
VCC_A44
VCC_G37
1U/6.3V_2
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
AK33
G38
2+2 peak 24A
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
VCC_AK33
VCC_G38
AK35
G40
2+2 TPY 17A
VCC_AK35
VCC_G40
AK37
G42
Backside cap
VCC_AK37
VCC_G42
Primary side cap
AK38
J30
2+3e peak 24A
VCC_AK38
VCC_J30
AK40
J33
2+3e TPY 17A
VCC_AK40
VCC_J33
AL33
J37
VCC_AL33
VCC_J37
C214
C245
AL37
J40
C679
C667
C674
C664
C673
C675
C663
C678
VCC_AL37
VCC_J40
C676
C258
C259
C647
C651
C657
C257
AL40
K33
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
VCC_AL40
VCC_K33
1U/6.3V_2
1U/6.3V_2
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
AM32
K35
VCC_AM32
VCC_K35
AM33
K37
VCC_AM33
VCC_K37
AM35
K38
Backside cap
VCC_AM35
VCC_K38
AM37
K40
+VCCCORE
VCC_AM37
VCC_K40
D
AM38
K42
R96
100/F_4
100 ohm Near CPU
D
VCC_AM38
VCC_K42
G30
K43
VCORE_SENSE
(36)
VCC_G30
VCC_K43
C189
C252
C222
C235
VCORESS_SENSE
(36)
+1V_VCCST
C273
C272
C282
C289
TP12
K32
E32
SVID
Layout note: need routing together
RSVD_K32
VCC_SENSE
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
E33
R98
100/F_4
VSS_SENSE
and ALERT need between CLK and DATA.
TP20
AK32
RSVD_AK32
B63
H_CPU_SVIDART#
Backside cap
+VCCOPC
VIDALERT#
AB62
A63
S0
1.0V
3A
H_CPU_SVIDCLK
VCCOPC_AB62
VIDSCK
P62
D64
H_CPU_SVIDDAT
R138
C814
C815
C816
C817
C818
C819
For 2+3e CPU
VCCOPC_P62
VIDSOUT
V62
100/F_4
1000P/50V_4
*1000P/50V_4
*1000P/50V_4
*1000P/50V_4
*1000P/50V_4
*1000P/50V_4
VCCOPC_V62
C212
C196
C201
C262
C215
C227
G20
+VCCSTG
VCCSTG_G20
C246
+1.8V_PRIM
H63
+1.8V_PRIM
VCC_OPC_1P8_H63
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
C174
Sx
1U/6.3V_2
R172
GT3@100/F_4
G61
1.8V
50mA
H_CPU_SVIDDAT
+VCCOPC
H_CPU_SVIDDAT
(36)
VCC_OPC_1P8_G61
1U/6.3V_4
Backside cap
R634
GT3@0_4
AC63
(33)
+VCCOPC_SRC
VCCOPC_SENSE
R636
GT3@0_4
AE63
(33)
681_AGND
GT3 CPU
Place PU resistor
close to CPU
VSSOPC_SENSE
+1V_VCCST
REV:F add 1000p
C181
C228
C269
C237
C209
C285
R176
GT3@100/F_4
AE62
VCCEOPIO
C200
AG62
S0
1.0V
3A
VCCEOPIO
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
AL63
Place PU resistor
close to CPU
R134
+VCCEOPIO
VCCEOPIO_SENSE
For 2+3e CPU
AJ62
54.9/F_4
VSSEOPIO_SENSE
100 ohm near CPU
H_CPU_SVIDART#
R552
220_4
VR_SVID_ALERT#_VCORE
(36)
12 OF 20
Backside cap
REV SKL_ULT/BGA = 1
?
+VCCOPC_SRC
R633
GT3@0_4
+VCCEOPIO
681_AGND
R632
GT3@0_4
?
SKL_ULT
+VCCGT
U35M
H_CPU_SVIDCLK
For 2+3e CPU
H_CPU_SVIDCLK
(36)
C708
C709
GT3@10u/6.3V_4
GT3@10u/6.3V_4
CPU POWER 2 OF 4
Primary side cap
N70
VCCGT
A48
N71
VCCGT
VCCGT
1.0V_CPU 3A
A53
R63
Backside cap
VCCGT
VCCGT
A58
R64
C199
C190
C702
C690
C248
C697
C696
S0
VCCGT
VCCGT
VCCGT
+VCCOPC
A62
R65
0.55~1.5V
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
47u/6.3V_8
VCCGT
VCCGT
A66
R66
+1.8V_PRIM
Backside cap
VCCGT
VCCGT
C688
C684
C681
C685
C683
C689
AA63
R67
VCCGT
VCCGT
Primary side cap
C682
AA64
2+2 peak 31A
2+2 TPY 15A
R68
VCCGT
VCCGT
C687
C686
GT3@10u/6.3V_4
GT3@1U/6.3V_2
GT3@1U/6.3V_2
GT3@1U/6.3V_2
GT3@1U/6.3V_2
GT3@1U/6.3V_2
GT3@1U/6.3V_2
AA66
R69
For 2+3e CPU
VCCGT
GT3@10u/6.3V_4
GT3@10u/6.3V_4
AA67
VCCGT
R70
2+3e peak 56A
VCCGT
VCCGT
AA69
R71
2+3e TPY 17A
C693
C705
C178
C706
C171
C707
C210
VCCGT
VCCGT
AA70
T62
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
47u/6.3V_6
For 2+3e CPU
VCCGT
VCCGT
AA71
U65
C
VCCGT
VCCGT
C
R565
AC64
U68
VCCGT
VCCGT
Primary side cap
GT3@0_6
AC65
U71
E3A C210 change to 47u/6.3v_6
+1.8V_S5
+1.8V_PRIM
+VCCGT
VCCGT
VCCGT
AC66
W63
Backside cap
VCCGT
VCCGT
AC67
W64
AC68
VCCGT
VCCGT
W65
VCCGT
VCCGT
AC69
W66
C692
C704
C202
C694
C691
C703
VCCGT
VCCGT
AC70
W67
22u/6.3V_6
22u/6.3V_6
47u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
VCCGT
VCCGT
C186
C185
C155
C158
C232
C218
C151
C161
C223
C148
AC71
W68
VCCGT
VCCGT
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
J43
W69
J45
VCCGT
VCCGT
W70
E3A C202 change to 47u/6.3v_6
VCCGT
VCCGT
J46
W71
VCCGT
VCCGT
J48
Y62
Backside cap
J50
VCCGT
VCCGT
+VCCGT
VCCGT
Primary side cap
J52
S0
VCCGTX
VCCGT
C197
C194
C193
C188
C241
C240
C239
C198
C204
C206
J53
AK42
0.55~1.5V
VCCGT
VCCGTX_AK42
J55
AK43
VCCGT
VCCGTX_AK43
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
J56
AK45
2+2 X
J58
VCCGT
VCCGTX_AK45
AK46
C303
C310
C277
C302
C307
C274
C275
C276
VCCGT
VCCGTX_AK46
J60
AK48
2+3e peak 6A
2+3e TPY 4A
GT3@22u/6.3V_6
GT3@22u/6.3V_6
22u/6.3V_6
GT3@22u/6.3V_6
GT3@22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
GT3@22u/6.3V_6
VCCGT
VCCGTX_AK48
K48
AK50
VCCGT
VCCGTX_AK50
K50
AK52
VCCGT
VCCGTX_AK52
C205
C195
K52
AK53
REV:F Stuff C277,C274,C275
VCCGT
VCCGTX_AK53
K53
AK55
VCCGT
VCCGTX_AK55
1U/6.3V_2
1U/6.3V_2
K55
AK56
For 2+3e CPU
K56
VCCGT
VCCGTX_AK56
AK58
VCCGT
VCCGTX_AK58
K58
AK60
VCCGT
VCCGTX_AK60
K60
AK70
VCCGT
VCCGTX_AK70
L62
AL43
VCCGT
VCCGTX_AL43
L63
AL46
VCCGT
VCCGTX_AL46
Backside cap
L64
AL50
VCCGT
VCCGTX_AL50
L65
AL53
VCCGT
VCCGTX_AL53
L66
AL56
VCCGT
VCCGTX_AL56
L67
AL60
VCCGT
VCCGTX_AL60
L68
AM48
C291
C279
C281
C324
C316
C280
C290
C317
VCCGT
VCCGTX_AM48
L69
AM50
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
GT3@10u/6.3V_4
VCCGT
VCCGTX_AM50
L70
AM52
+VCCGT
VCCGT
VCCGTX_AM52
L71
AM53
VCCGT
VCCGTX_AM53
M62
AM56
VCCGT
VCCGTX_AM56
N63
AM58
VCCGT
VCCGTX_AM58
N64
AU58
VCCGT
VCCGTX_AU58
R155
N66
AU63
VCCGT
VCCGTX_AU63
100 ohm Near CPU
100/F_4
N67
BB57
VCCGT
VCCGTX_BB57
N69
BB66
VCCGT
VCCGTX_BB66
B
B
J70
AK62
(36)
VCCGT_SENSE
TP86
VCCGT_SENSE
VCCGTX_SENSE
J69
AL61
(36)
VSSGT_SENSE
VSSGT_SENSE
VSSGTX_SENSE
TP87
13
OF 20
R161
100/F_4
SKL_ULT/BGA
REV = 1
?
?
+1.35VSUS
U35N
SKL_ULT
+VCCIO
S0
Backside cap
CPU POWER 3 OF 4
S3
0.85V/0.95V
Backside cap
Imax 3(A)
AU23
AK28
DDR3L
VDDQ_AU23
VCCIO
AU28
AK30
3.0A
VDDQ_AU28
1.35V
VCCIO
AU35
AL30
VDDQ_AU35
VCCIO
C313
C308
C311
C312
AU42
AL42
2A
C266
C297
C264
C298
VDDQ_AU42
VCCIO
C318
C328
BB23
AM28
C284
C283
VDDQ_BB23
VCCIO
10u/6.3V_4
10u/6.3V_4
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
BB32
AM30
10u/6.3V_4
10u/6.3V_4
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
VDDQ_BB32
VCCIO
BB41
AM42
VDDQ_BB41
VCCIO
BB47
VDDQ_BB47
Primary side cap
BB51
AK23
S0
1.15V
Primary side cap
VDDQ_BB51
VCCSA
AK25
2+2 peak 5A
VCCSA
G23
2+2 TPY 4A
AM40
VCCSA
G25
2+3e peak 5.1A
C701
C710
C700
C711
VDDQC
VCCSA
G27
VCCSA
A18
G28
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
VCCST
S3
2+3e TPY 5A
1.0V 120mA
VCCSA
C326
C323
C325
C327
J22
VCCSA
A22
J23
+VCCSA
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
VCCSTG_A22
1.0V 40mA
VCCSA
J27
S0
VCCSA
Backside cap
AL23
K23
+VDDQC
VCCPLL_OC
VCCSA
K25
S0
1.0V
260mA
VCCSA
R194
*short_4
K20
K27
K21
VCCPLL_K20
VCCSA
1
2
K28
C254
C238
C247
C229
C221
C263
C288
+1.35VSUS
VCCPLL_K21
VCCSA
K30
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
Backside cap
+1V_VCCST
VCCSA
C299
S3
1.0V
120mA
C286
AM23
TP17
VCCIO_SENSE
1U/6.3V_2
10u/6.3V_4
AM22
TP14
VSSIO_SENSE
Backside cap
C677
H21
+VCCSTG
VSSSA_SENSE
R550
*short_6
H20
C207
C278
C216
C242
C260
C267
C249
+1V_SUS
VCCSA_SENSE
Rev:F change to Shortpad
1U/6.3V_4
R109
100/F_4
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
1U/6.3V_2
Primary side cap
14
OF 20
VSASS_SENSE
(36)
SKL_ULT/BGA
?
C176
REV = 1
VSA_SENSE
(36)
R135
*short_6
A
+VCCIO
A
Primary side cap
1U/6.3V_4
Backside cap
+VCCSA
Rev:F change to Shortpad
+VCCPLL
R122
100/F_4
C114
C643
C641
C165
C642
C157
R112
*short_6
100 ohm near CPU
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
10u/6.3V_4
+1V_SUS
Rev:F change to Shortpad
C172
Primary side cap
1U/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Dr-Bios.com
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
5
5
5
of
of
of
48
48
48
5
4
3
2
1
5 4 3 2 1 Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3) 06 ?
5
4
3
2
1
Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)
06
?
SKL_ULT
U35H
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_RXN0
(28)
PCH PU/PD
USB3_1_RXN
G8
+3V_S5
USB3_RXP0
(28)
USB3_1_RXP
H13
C13
MB USB3.0
CN16 ( Charger IC ) Down
(14)
PEG_RX#0
USB3_TXN0
(28)
PCIE1_RXN/USB3_5_RXN
USB3_1_TXN
G13
D13
(14)
PEG_RX0
USB3_TXP0
(28)
PCIE1_RXP/USB3_5_RXP
USB3_1_TXP
C653
EV@0.22u/10V_4
C_PEG_TX#0
B17
(14)
PEG_TX#0
D
PCIE1_TXN/USB3_5_TXN
D
C652
EV@0.22u/10V_4
C_PEG_TX0
A17
J6
USB_OC0#
R541
10K_4
(14)
PEG_TX0
USB3_RXN1
(28)
PCIE1_TXP/USB3_5_TXP
USB3_2_RXN/SSIC_1_RXN
H6
USB_OC1#
R540
10K_4
USB3_RXP1
(28)
USB3_2_RXP/SSIC_1_RXP
G11
B13
MB USB3.0
CN13 -> Up
USB_OC2#
R543
10K_4
(14)
PEG_RX#1
USB3_TXN1
(28)
PCIE2_RXN/USB3_6_RXN
USB3_2_TXN/SSIC_1_TXN
F11
A13
USB_OC3#
R542
10K_4
(14)
PEG_RX1
USB3_TXP1
(28)
PCIE2_RXP/USB3_6_RXP
USB3_2_TXP/SSIC_1_TXP
C656
EV@0.22u/10V_4
C_PEG_TX#1
D16
(14)
PEG_TX#1
PCIE2_TXN/USB3_6_TXN
C_PEG_TX1
C16
dGPU PEG*4
C655
EV@0.22u/10V_4
J10
(14)
PEG_TX1
PCIE2_TXP/USB3_6_TXP
USB3_3_RXN/SSIC_2_RXN
H10
USB3_3_RXP/SSIC_2_RXP
H16
B15
(14)
PEG_RX#2
PCIE3_RXN
USB3_3_TXN/SSIC_2_TXN
G16
A15
+3V
(14)
PEG_RX2
PCIE3_RXP
USB3_3_TXP/SSIC_2_TXP
C661
EV@0.22u/10V_4
C_PEG_TX#2
D17
(14)
PEG_TX#2
PCIE3_TXN
C662
EV@0.22u/10V_4
C_PEG_TX2
C17
E10
(14)
PEG_TX2
PCIE3_TXP
USB3_4_RXN
F10
USB3_4_RXP
G15
C15
1A-1
SATA_DEVSLP0
R573
*10K_4
(14)
PEG_RX#3
PCIE4_RXN
USB3_4_TXN
F15
D15
SATA_DEVSLP1
R574
*10K_4
(14)
PEG_RX3
PCIE4_RXP
USB3_4_TXP
C654
EV@0.22u/10V_4
C_PEG_TX#3
B19
SATA_DEVSLP2
R575
*10K_4
(14)
PEG_TX#3
PCIE4_TXN
C660
EV@0.22u/10V_4
C_PEG_TX3
A19
AB9
PIRQA#
R631
*10K_4
(14)
PEG_TX3
USBP0-
(28)
PCIE4_TXP
USB2N_1
AB10
MB USB3.0
CN16 ( Charger IC ) Down
USBP0+
(28)
USB2P_1
F16
(23)
PCIE_RX5-_LAN
PCIE5_RXN
E16
AD6
SATAGP1
R569
*10K_4
(23)
PCIE_RX5+_LAN
USBP1-
(28)
PCIE5_RXP
USB2N_2
LAN
C668
0.1u/16V_4
PCIE_TX5-
C19
AD7
MB USB3.0
CN13 -> Up
SATAGP2
R566
*10K_4
(23)
PCIE_TX5-_LAN
USBP1+
(28)
PCIE5_TXN
USB2P_2
C669
0.1u/16V_4
PCIE_TX5+
D19
(23)
PCIE_TX5+_LAN
PCIE5_TXP
AH3
USB2N_3
G18
AJ3
(26)
PCIE_RX6-_WLAN
PCIE6_RXN
USB2P_3
F18
(26)
PCIE_RX6+_WLAN
PCIE6_RXP
WIFI
C648
0.1u/16V_4
PCIE_TX6-
D20
AD9
(26)
PCIE_TX6-_WLAN
PCIE6_TXN
USB2N_4
USBP3-
(28)
C649
0.1u/16V_4
PCIE_TX6+
C20
AD10
DB USB2.0
(26)
PCIE_TX6+_WLAN
PCIE6_TXP
USB2P_4
USBP3+
(28)
+3V_S5
Add SSD ID 1/14
F20
AJ1
(25)
SATA_RXN0
USBP4-
(26)
PCIE7_RXN/SATA0_RXN
USB2N_5
E20
AJ2
BT
Hight is SSD , Low is ODD
(25)
SATA_RXP0
USBP4+
(26)
PCIE7_RXP/SATA0_RXP
USB2P_5
HDD
B21
USB2
(25)
SATA_TXN0
PCIE7_TXN/SATA0_TXN
A21
AF6
(25)
SATA_TXP0
PCIE7_TXP/SATA0_TXP
USB2N_6
USBP5-
(21)
AF7
Touch Screen
R568
10K_4
SATAGP0
R570
100K_4
USBP5+
(21)
(25)
SSD_ID
USB2P_6
G21
(25)
SATA_RXN1
PCIE8_RXN/SATA1A_RXN
F21
AH1
(25)
SATA_RXP1
USBP6-
(21)
PCIE8_RXP/SATA1A_RXP
USB2N_7
ODD
D21
AH2
CCD
(25)
SATA_TXN1
USBP6+
(21)
PCIE8_TXN/SATA1A_TXN
USB2P_7
C21
(25)
SATA_TXP1
PCIE8_TXP/SATA1A_TXP
AF8
USBP7-
(28)
USB2N_8
E22
AF9
C
Card reader
C
USBP7+
(28)
PCIE9_RXN
USB2P_8
E23
PCIE9_RXP
B23
AG1
PCIE9_TXN
USB2N_9
A23
AG2
Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
PCIE9_TXP
USB2P_9
F25
AH7
PCIE10_RXN
USB2N_10
E25
AH8
PCIE10_RXP
USB2P_10
D23
USBCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils
C665
10P/50V_4
PCIE10_TXN
C23
AB6
USBCOMP
R178
113/F_4
24MHz: BG624000078
PCIE10_TXP
USB2_COMP
AG3
USB2_ID
R587
1K_4
USB2_ID
R562
100/F_4 PCIE_RCOMPN
F5
AG4
R778
1K_4
38.4MHz : ?
PCIE_RCOMPN
USB2_VBUSSENSE
PCIE_RCOMPP
E5
Y4
PCIE_RCOMPP
+3V_S5
A9
USB_OC0#
MB U3
R536
24MHz
USB_OC0#
(28)
GPP_E9/USB2_OC0#
XDP_PRDY#
D56
+3V_S5
C9
USB_OC1#
MB U3
1M_4
TP91
USB_OC1#
(28)
PROC_PRDY#
GPP_E10/USB2_OC1#
XDP_PREQ#
D61
D9
USB_OC2#
+3V_S5
DB U2
TP92
USB_OC2#
(28)
PROC_PREQ#
GPP_E11/USB2_OC2#
PIRQA#
BB11
+3V_S5
B9
USB_OC3#
XTAL24_IN
+3V_S5
GPP_A7/PIRQA#
GPP_E12/USB2_OC3#
XTAL24_OUT
C658
10P/50V_4
E28
+3V_S5
J1
SATA_DEVSLP0
DEVSLP0
(25)
PCIE11_RXN/SATA1B_RXN
GPP_E4/DEVSLP0
E27
J2
SATA_DEVSLP1
+3V_S5
PCIE11_RXP/SATA1B_RXP
GPP_E5/DEVSLP1
D24
J3
SATA_DEVSLP2
PCIE11_TXN/SATA1B_TXN
+3V_S5
GPP_E6/DEVSLP2
C24
PCIE11_TXP/SATA1B_TXP
E30
H2
SATAGP0
+3V_S5
Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U
PCIE12_RXN/SATA2_RXN
GPP_E0/SATAXPCIE0/SATAGP0
F30
H3
SATAGP1
PCIE12_RXP/SATA2_RXP
+3V_S5
GPP_E1/SATAXPCIE1/SATAGP1
A25
G4
SATAGP2
PCIE12_TXN/SATA2_TXN
+3V_S5
GPP_E2/SATAXPCIE2/SATAGP2
B25
PCIE12_TXP/SATA2_TXP
H1
+3V_S5
GPP_E8/SATALED#
RTC Clock 32.768KHz (RTC)
8 OF 20
SKL_ULT/BGA
REV = 1
CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p
?
C351
6.8p/50V_4
Trace length < 1000 mils
RTC_X1
Y2
R255
32.768KHZ
10M_4
BG332768453 -> SEG
?
SKL_ULT
U35J
B
B
C362
6.8p/50V_4
RTC_X2
BG332768104 -> TXC
CLOCK SIGNALS
D42
(14)
CLK_PCIE_VGA#
CLKOUT_PCIE_N0
C42
(14)
CLK_PCIE_VGA
CLKOUT_PCIE_P0
R235
CLK_PCIE_REQ0#
AR10
(14)
CLK_PEGA_REQ#
GPP_B5/SRCCLKREQ0#
+3V_S5
*short_4
B42
CLKOUT_PCIE_N1
A42
F43
CLK_PCIE_XDPN
CLKOUT_PCIE_P1
CLKOUT_ITPXDP_N
TP93
CLK_PCIE_REQ1#
AT7
E43
CLK_PCIE_XDPP
TP22
+3V_S5
TP94
RTC Circuitry (RTC)
GPP_B6/SRCCLKREQ1#
CLKOUT_ITPXDP_P
D41
BA17
SUSCLK
CLKOUT_PCIE_N2
+3V_S5
SUSCLK
(26)
GPD8/SUSCLK
C41
+3VPCU
1B-1
CLKOUT_PCIE_P2
CLK_PCIE_REQ2#
AT8
E37
XTAL24_IN
TP25
GPP_B7/SRCCLKREQ2#
+3V_S5
XTAL24_IN
E35
XTAL24_OUT
On SKL voltage at VCCRTC does not exceed 3.2V
XTAL24_OUT
D40
CLKOUT_PCIE_N3
C40
E42
XCLK_BIASREF
R512
2.7K/F_4
+1V_S5
CLKOUT_PCIE_P3
XCLK_BIASREF
CLK_PCIE_REQ3#
AT10
R768
*60.4/F_4
R304
TP73
GPP_B8/SRCCLKREQ3#
+3V_S5
AM18 RTC_X1
1.5K/F_4
+3V_RTC
RTCX1
B40
+3V_RTC
AM20 RTC_X2
(23)
CLK_PCIE_LANN
Trace width = 30 mils
CLKOUT_PCIE_N4
RTCX2
A40
Reserve PD 60 ohm in E42
ball for Cannonlake U
D7
(23)
CLK_PCIE_LANP
CLKOUT_PCIE_P4
R229
CLK_PCIE_REQ4#
AU8
AN18 SRTC_RST#
+3V_RTC_2
R299
CLK_PCIE_LAN_REQ#
(23)
GPP_B9/SRCCLKREQ4#
+3V_S5
SRTCRST#
*short_4
AM16 RTC_RST#
RTC_RST#
RTC_RST#
(11)
RTCRST#
E40
R308
1K_4 +3V_RTC_1
(26)
CLK_PCIE_WLANN
VCCRTC_2
CLKOUT_PCIE_N5
E38
20K/F_4
(26)
CLK_PCIE_WLANP
CLKOUT_PCIE_P5
R224
CLK_PCIE_REQ5#
AU7
R301
BAT54C
PCIE_CLKREQ_WLAN#
(26)
GPP_B10/SRCCLKREQ5#
+3V_S5
*short_4
1V power plane
0.71 checklist p14
45.3K/F_4
C380
J1
+3V_RTC_[0:2]
1u/6.3V_4
*JUMP
Trace width = 20 mils
Rev:D change to shortpad
R300
10 OF 20
BT1
SRTC_RST#
SKL_ULT/BGA
REV = 1
?
20K/F_4
BAT_CONN
C381
C382
+3V
Rev:D add for EC reset RTC
1u/6.3V_4
1u/6.3V_4
A
SRTC_RST#
RTC_RST#
A
1A-22013/10/16 Chage +3V_RTC_0 to VCCTC_2.
CLK_PCIE_REQ0#
R234
10K_4
CLK_PCIE_REQ1#
R215
10K_4
CLK_PCIE_REQ2#
R227
10K_4
1.
AHL03003057 DBV CR2032
CLK_PCIE_REQ3#
R618
10K_4
CLK_PCIE_REQ4#
R228
10K_4
2
EC_RTCRST
2
2.
AHL03003003 VDE CR2032
(29)
EC_RTCRST
CLK_PCIE_REQ5#
R223
10K_4
PQ6059
PQ6060
*2N7002K
*2N7002K
R786
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
100K_4
Rev:E Reserve only
Rev:E Reserve only
Dr-Bios.com
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
6
6
6
of
of
of
48
48
48
5
4
3
2
1
N16S VGALANWLAN
1
3
1
3
12
1
3
2
4
12
12
5 4 3 2 1 07 ? SKL_ULT U35E SPI - FLASH SMBUS, SMLINK Strapping
5
4
3
2
1
07
?
SKL_ULT
U35E
SPI - FLASH
SMBUS, SMLINK
Strapping
PCH_SPI_CLK
AV2
R7
PCH_MBCLK0_R
+3V_S5
SPI0_CLK
GPP_C0/SMBCLK
PCH_SPI_SO
AW3
R8
PCH_MBDAT0_R
+3V_S5
SPI0_MISO
GPP_C1/SMBDATA
PCH_SPI_SI
AV3
R10
SMBALERT#
SPI0_MOSI
+3V_S5
GPP_C2/SMBALERT#
SMBALERT#
(4)
PCH_SPI_IO2
AW2
+3V_S5
SPI0_IO2
PCH_SPI_IO3
AU4
R9
VGA_MBCLK
D
+3V_S5
D
SPI0_IO3
GPP_C3/SML0CLK
PCH_SPI_CS0#
AU3
W2
VGA_MBDATA
+3V
SPI0_CS0#
+3V_S5
GPP_C4/SML0DATA
PCH_SPI_CS1#
AU2
W1
SML0ALERT#
SML0ALERT#
(4)
SPI0_CS1#
+3V_S5
GPP_C5/SML0ALERT#
AU1
SPI0_CS2#
W3
SMB_ME1_CLK
CLKRUN#
R630
8.2K/F_4
+3V_S5
GPP_C6/SML1CLK
V3
SMB_ME1_DAT
IRQ_SERIRQ
R629
10K_4
+3V_S5
SPI - TOUCH
GPP_C7/SML1DATA
AM7
SML1ALERT#
EC_RCIN#
R639
10K_4
SMB1ALERT#
(27)
+3V_S5
GPP_B23/SML1ALERT#/PCHHOT#
M2
+3V_S5
GPP_D1/SPI1_CLK
M3
+3V_S5
GPP_D2/SPI1_MISO
J4
+3V_S5
Rev:D change to shortpad
GPP_D3/SPI1_MOSI
V1
+3V_S5
eSPI change to 15 ohm ckl v0.71 p.24
GPP_D21/SPI1_IO2
V2
+3V_S5
GPP_D22/SPI1_IO3
M1
AY13
+3V_S5
R659
*short_4
LPC
GPP_D0/SPI1_CS#
+3V_S5
+3V_S5
GPP_A1/LAD0/ESPI_IO0
LPC_LAD0
(25,26,29)
BA13
R640
*short_4
+3V_S5
LPC_LAD1
(25,26,29)
SMBus
GPP_A2/LAD1/ESPI_IO1
BB13
R653
*short_4
+3V_S5
LPC_LAD2
(25,26,29)
C LINK
GPP_A3/LAD2/ESPI_IO2
AY12
R668
*short_4
LPC_LAD3
(25,26,29)
+3V_S5
GPP_A4/LAD3/ESPI_IO3
TP68
CL_CLK
G3
BA12
PCH_MBCLK0_R
2.2K_4
R578
LPC_LFRAME#
(25,26,29)
CL_CLK
GPP_A5/LFRAME#/ESPI_CS#
For M.2 wifi module must
TP66
CL_DAT
G2
+3V_S5
BA11
R748
*0_4
PCH_MBDAT0_R
2.2K_4
R580
ESPI_RST#
(29)
CL_DATA
GPP_A14/SUS_STAT#/ESPI_RESET#
TP67
CL_RST#
G1
+3V_S5
C806
0.1u/16V_4
VGA_MBDATA
2.2K_4
R585
CL_RST#
eSPI
change to 15 ohm
VGA_MBCLK
2.2K_4
R582
Rev:D change to shortpad
AW9
R623
22/J_4
+3V_S5
CLK_PCI_EC
(29)
GPP_A9/CLKOUT_LPC0/ESPI_CLK
R652
*short_4
EC_RCIN#
AW13
AY9
(29)
SIO_RCIN#
GPP_A0/RCIN#
+3V_S5
+3V_S5
GPP_A10/CLKOUT_LPC1
AW11
+3V_S5
R626
22/J_4
PCLK_TPM
(25)
+3V_S5
GPP_A8/CLKRUN#
IRQ_SERIRQ
AY11
R627
22/J_4
(25,29)
IRQ_SERIRQ
+3V_S5
GPP_A6/SERIRQ
CLK_PCI_LPC
(26)
CLKRUN#
CLKRUN#
(25,29)
SML1ALERT#
*150K_4
R205
5 OF 20
SKL_ULT/BGA
2/10 add C806 for EMI request ,
?
REV = 1
R748 no stuiff from EC site
move at CPU site
Termination Resistor Requirement for PCH PCHHOT# Pin
Reserve PU 150K resister
Rev:D change to shortpad
C
C
SPI ROM
Vender
Size
Quanta P/N
Vender P/N
PCH SPI ROM(8M+4M)
15ohm CS01502JB12
33ohm CS03302JB29
R700
*short_6
+3V
+3V_S5
+3V_PCH_ME
+3V_PCH_ME
WND
8M
AKE3EFP0N07
W25Q64FVSSIQ
D2B change to 2.2k
Skylake
GGD
8M
AKE2EZN0Q00
GD25B64CSIGR
U41
C754
0.1u/16V_4
3.3V
1A-13
PCH_SPI_CS0#
1
CS#
8
VCC
R576
R572
SMBus(PCH)
PCH_SPI_SO
R650
8M4M@15_4
SPI_SO_8M
2 SPI_HOLD_IO3_ME
7
R698
1K_4
2.2K_4
2.2K_4
IO1/DO
IO3/HOLD#
PCH_SPI_SO_EC
R588
8M@15_4
Q32
S5
S0
3
CLK
6
SPI_CLK_8M
R684
8M4M@15_4
PCH_SPI_CLK
5
IO2/WP#
5
SPI_SI_8M
R691
8M4M@15_4
PCH_SPI_SI
PCH_MBDAT0_R
3
4 CLK_SDATA
4 IO0/DI
GND
(12,13,27)
C747
2
W25Q64FV -- 8MB
PCH_SPI_CLK_EC
*22p/50V_4
R687
8M@15_4
PCH_MBCLK0_R
6
1 CLK_SCLK
(12,13,27)
PCH_SPI_SI_EC
R654
8M@15_4
PCH_XDP_WLAN/S5
DDR_TP/S0
R649
1K_4
SPI_WP_IO2_ME
2N7002DW
+3V_PCH_ME
R596
*4M@33_4
SPI_WP_IO2_EC
3.3K is original and for no
support fast read function
PCH_SPI_IO2
R589
8M4M@15_4
SPI_WP_IO2_ME
SMBus(EC)
R238
*4M@33_4
SPI_HOLD_IO3_EC
reserve for SPI fast read
PCH_SPI_IO3
R239
8M4M@15_4
SPI_HOLD_IO3_ME
+3V_PCH_ME
R689
*4M@33_4
PCH_SPI_CLK_R
U39
(29)
PCH_SPI_CLK_EC
R641
*4M@33_4
PCH_SPI_SI_R
PCH_SPI_CS1#
1
8
(29)
PCH_SPI_SI_EC
CE#
VDD
R594
*4M@33_4
PCH_SPI_SO_R
PCH_SPI_CLK
R669
*4M@33_4
6
(29)
PCH_SPI_SO_EC
SCK
PCH_SPI_SI
R658
*4M@33_4
5
SI
PCH_SPI_SO
R604
*4M@33_4
2
7
SPI_HOLD_IO3_EC
R232
*1K_4
SO
HOLD#
2ND_MBCLK
R171
*short_4
SMB_ME1_CLK
(17,29)
2ND_MBCLK
R602
8M@0_4
PCH_SPI_CS0#
C745
*22p/50V_4
3
4
2ND_MBDATA
R175
*short_4
SMB_ME1_DAT
B
(29)
SPI_CS0#_UR_ME
(17,29)
2ND_MBDATA
B
WP#
VSS
R603
*4M@0_4 PCH_SPI_CS1#
PCH_SPI_CLK_R
C741
PCH_SPI_SI_R
*4M@ROM-4M_EC
*4M@0.1u/16V_4
only 0ohm option
PCH_SPI_SO_R
Rev:D change to shortpad
EC/S5
+3V_PCH_ME
R597
*1K_4
SPI_WP_IO2_EC
+3V_PCH_ME
R591
10K_4
SPI_CS0#_UR_ME
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
A
A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Dr-Bios.com
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
7
7
7
of
of
of
48
48
48
5
4
3
2
1
5 4 3 2 1 PCI_PLTRST# 08 ? SKL_ULT SYS_RESET# U35K (11) SYS_RESET# SUS0# (29)
5
4
3
2
1
PCI_PLTRST#
08
?
SKL_ULT
SYS_RESET#
U35K
(11)
SYS_RESET#
SUS0#
(29)
SYSTEM POWER MANAGEMENT
R655
*short_4
PCH_RSMRST#
(29)
RSMRST#
AT11
+3V_S5
SUSB#
(11,29,31)
GPP_B12/SLP_S0#
+3V
R554
10K_4
AP15
SUSB#
SUSC#
(11,29)
Rev:D change to shortpad
+3V_S5
GPD4/SLP_S3#
+VCCIO
AN10
BA16
SUSC#
+3V_S5
PCH_SLP_S5#
(11)
GPP_B13/PLTRST#
GPD5/SLP_S4#
11/12 Reserve PU 10K
B5
+3V_S5
AY16
PCH_SLP_S5#
SYS_RESET#
GPD10/SLP_S5#
VCCST_PWRGD
AY17
+3V_S5
PCH_VRALERT#
R211
10K_4
RSMRST#
PCH_SLP_SUS#
(29)
AN15
PCH_SLP_SUS#
SYS_RESET#
I
R561
10K_4
SLP_SUS#
R544
*10K_4
PROC_PWRGD
PROC_PWRGD
A68
AW15
PCH_SLP_LAN#
PROCPWRGD
I
SLP_LAN#
TP30
SYS_PWROK
R556
*short_4
B65
BB17
PCH_SLP_WLAN#
Rev:D change to shortpad
+3V_S5
VCCST_PWRGD
GPD9/SLP_WLAN#
TP23
R643
*0_4
AN16
PCH_SLP_A#
+3V_S5
PCH_SLP_A#
(11)
D
GPD6/SLP_A#
D
SYS_PWROK_R
B6
*short_4
R677
DNBSWON#
(29)
SYS_PWROK
+3V_S5
Rev:D change to shortpad
EC_PWROK_R
BA20
BA15
PCH_PWRBTN#
PCH_PWROK
+3V_S5
GPD3/PWRBTN#
DPWROK_R
BB20
AY15
PCH_ACPRESENT
*short_4
R676
ACPRESENT
(29)
DSW_PWROK
+3V_S5
GPD1/ACPRESENT
AU13
PCH_BATLOW#
PCH_ACPRESENT
R651
8.2K/F_4
(29)
PCH_SUSPWRACK_R
+3V_S5
GPD0/BATLOW#
TP74
R622
*0_4
PCH_SUSPWRACK
AR13
PCH_BATLOW#
R628
8.2K/F_4
GPP_A13/SUSWARN#/SUSPWRDNACK
+3V_S5
TP29
R617
*0_4
SUSACK#_R
AP11
(29)
PCH_SUSACK#
GPP_A15/SUSACK#
+3V_S5
AU11
R249
1M_4
PCIE_LAN_WAKE#
R250
10K_4
+3V_S5
+3V_RTC
GPP_A11/PME#
PCIE_LAN_WAKE#
BB15
AP16
INTRUDER#
(23,26)
PCIE_LAN_WAKE#
WAKE#
INTRUDER#
AM15
MPHY_EXT_PWR
R195
*1K_4
+3V_S5
Rev:F add
GPD2/LAN_WAKE#
TP84
AW17
AM10 MPHY_EXT_PWR
GPD11/LANPHYPC
+3V_S5
+3V_S5
GPP_B11/EXT_PWR_GATE#
AT15
AM11
PCH_VRALERT#
GPD7/RSVD
GPP_B2/VRALERT#
+3V_S5
TP19
+3V_S5
PCH_RSMRST#
R642
10K_4
PCH_PWROK
R648
10K_4
11 OF 20
SYS_PWROK_R
R555
10K_4
SKL_ULT/BGA
REV = 1
DPWROK_C
R675
100K_4
?
SKL_ULT
?
U35I
CSI-2
A36
C37
+3V_S5
CSI2_DN0
CSI2_CLKN0
B36
D37
REV:E
tPLT15(max 200us)
CSI2_DP0
CSI2_CLKP0
C38
C32
CSI2_DN1
CSI2_CLKN1
D38
D32
CSI2_DP1
CSI2_CLKP1
C36
C29
C811
*0.1u/16V_4
CSI2_DN2
CSI2_CLKN2
D36
D29
->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)
CSI2_DP2
CSI2_CLKP2
A38
B26
CSI2_DN3
CSI2_CLKN3
B38
A26
CSI2_DP3
CSI2_CLKP3
2
SUSC#
C31
E13
R145
100/F_4
SUSON
4
CSI2_DN4
CSI2_COMP
D31
B7
(32,35)
SUSON
1
SUSON_EC
+3V_S5
SUSON_EC
(29)
CSI2_DP4
GPP_D4/FLASHTRIG
C33
TP63
Board ID
CSI2_DN5
+1.8V_S5
D33
U48
CSI2_DP5
EMMC
A31
*TC7SH08FU
CSI2_DN6
B31
AP2
RAM_ID1
CSI2_DP6
+1.8V_S5
GPP_F13/EMMC_DATA0
R610
10K_4
RAM_ID1
R611
*10K_4
A33
AP1
C
RAM_ID2
C
CSI2_DN7
+1.8V_S5
GPP_F14/EMMC_DATA1
R612
10K_4
RAM_ID2
R613
*10K_4
B33
AP3
RAM_ID3
CSI2_DP7
+1.8V_S5
GPP_F15/EMMC_DATA2
R614
10K_4
RAM_ID3
R615
*10K_4
AN3
Board_ID0
+1.8V_S5
GPP_F16/EMMC_DATA3
R595
10K_4
Board_ID0
R600
*10K_4
A29
AN1
Board_ID1
REV:F Stuff R790
R790
0_4
CSI2_DN8
+1.8V_S5
GPP_F17/EMMC_DATA4
R598
10K_4
Board_ID1
R599
*10K_4
B29
AN2
Board_ID2
CSI2_DP8
+1.8V_S5
GPP_F18/EMMC_DATA5
R605
10K_4
Board_ID2
R608
*10K_4
C28
AM4
Board_ID3
CSI2_DN9
+1.8V_S5
GPP_F19/EMMC_DATA6
R592
10K_4
Board_ID3
R590
*10K_4
D28
AM1
Board_ID4
+1.8V_S5
Board_ID4
(21)
CSI2_DP9
GPP_F20/EMMC_DATA7
Board_ID4
R593
10K_4
A27
CSI2_DN10
B27
AM2
Board_ID5
CSI2_DP10
+1.8V_S5
GPP_F21/EMMC_RCLK
R606
10K_4
Board_ID5
R607
*10K_4
C27
AM3
Board_ID6
CSI2_DN11
+1.8V_S5
GPP_F22/EMMC_CLK
R764
10K_4
Board_ID6
R765
*10K_4
D27
AP4
Board_ID7
CSI2_DP11
+1.8V_S5
GPP_F12/EMMC_CMD
R766
10K_4
Board_ID7
R767
*10K_4
AT1
200/F_4
R616
EMMC_RCOMP
9 OF 20
+3V_S5
SKL_ULT/BGA
REV = 1
+3V_S5
?
REV:E tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassertion
REV:E
tPLT18(max 200 us)
C812
*0.1u/16V_4
->SLP_S3# assertion to
Low
High
Low
High
C813
*0.1u/16V_4
VCCIO VR(MAIND for +1V_S5
to +VCCIO) disabled
2
SUSB#
BOARD_ID0
VRAM 2GB
VRAM 4GB
BOARD_ID5
Realtek
CPU DSP
2
SUSB#
4
Audio codec
4
(35,40)
MAINON
1
MAINON_EC
MAINON_EC
(29)
(33,36)
VRON
1
VRON_EC
VRON_EC
(29)
BOARD_ID1
Non IOAC
IOAC
BOARD_ID6
Reserved
Reserve
U49
U50
*TC7SH08FU
(Default)
*TC7SH08FU
BOARD_ID2
No G-sensor
G-sensor
BOARD_ID7
Reserved
Reserve
(Default)
REV:F Stuff R791
R791
0_4
REV:F Stuff R792
R792
0_4
BOARD_ID3
No TPM
TPM
BOARD_ID4
No touch panel
touch panel
Power Sequence
B
B
Non Deep Sx
Rev:D change to shortpad
R647
*short_4
EC_PWROK_R
(29)
PCH_PWROK
EC_PWROK
R131
*0_4
SYS_PWROK_R
For platforms not supporting Deep
Sx, connect directly to RSMRST#
B2A
No Deep Sx
Rev:D change to shortpad
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD
DPWROK_R
R661
*short_4
PCH_RSMRST#
VCCST PWRGD
CRB is via +1.05V PG
+3V_S5
DPWROK_R
R674
*0_4
DPWROK_C
(29)
+3V_S5
U6
C808
0.1u/16V_4
+1V_VCCST
5
1
VCC
NC
C164
2
SUSB#
R85
0.1u/16V_4
2
VCCST_PWRGD_EN_L
4
A
1 VCCST_PWRGD_EN
1K_4
VCCST_PWRGD
VCCST_PWRGD_R
4
3
U47
Y
GND
TC7SH08FU
R89
60.4/F_4
C136
74AUP1G07GW
+3V_S5
*0.1u/16V_4
+3V
SYSPWOK
PLTRST# Buffer
Shortpad change
to 60.4 ohm. 11/6
R777
*0_4
C168
*0.1u/16V_4
C332
0.1u/16V_4
R103
*0_4
PCH_PWROK
VCCST_PWRGD_EN
R102
0_4
HWPG
HWPG
(29)
2
2
EC_PWROK
EC_PWROK
(29)
Rev:D change
netmane for HWPG
4
SYS_PWROK
4
1A-6 2013/10/21 Del APWORK.
PLTRST#
(14,23,25,26,29)
A
PCI_PLTRST#
1
1
A
IMVP_PWRGD_3V
(2)
U14
U8
TC7SH08FU
R214
*TC7SH08FU
R130
100K_4
*10K_4
R113
*0_4
R560
*short_4
Rev:D change to shortpad
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Dr-Bios.com
PROJECT : ZRW
PROJECT : ZRW
PROJECT : ZRW
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
3A
3A
3A
Date:
Date:
Date:
Monday, July 20, 2015
Monday, July 20, 2015
Monday, July 20, 2015
Sheet
Sheet
Sheet
8
8
8
of
of
of
48
48
48
5
4
3
2
1
3
5
3
5
3
5
3
5
3
5
3
5
5 4 3 2 1 09 GPIO Group Power Plane VCCPRIM_1P0 & VCCPRIM_CORE Short ?
5
4
3
2
1
09
GPIO Group Power Plane
VCCPRIM_1P0 & VCCPRIM_CORE Short
?
U35S
SKL_ULT
?
Rev:D change to shortpad
SKL_ULT
U35O
C292
*1U/6.3V_4
RESERVED SIGNALS-1
Rev:F Remove Short Jumper for all +1V_S5
C268
1U/6.3V_4
CPU POWER 4 OF 4
C230
1U/6.3V_4
Rev:D change to shortpad
E68
BB68
AB19
C265
*1U/6.3V_4
CFG[0]
RSVD_TP_BB68
+1V_S5
VCCPRIM_1P0
D
B67
BB69
AB20
AK15
1.0V
696mA
+VCCPGPPA
*short_6
R198
D
CFG[1]
RSVD_TP_BB69
VCCPRIM_1P0
VCCPGPPA
+3V_S5
D65
C217
1U/6.3V_4
P18
AG15
+VCCPGPPB
S5
*short_6
R185
CFG[2]
VCCPRIM_1P0
VCCPGPPB
+3V_S5
D67
AK13
Y16
+VCCPGPPC
44mA
*short_6
R182
CFG[3]
RSVD_TP_AK13
+3V_S5
TP95
VCCPGPPC
CFG4
E70
AK12
AF18
Y15
+VCCPGPPD
S5
*short_6
R187
CFG[4]
RSVD_TP_AK12
+1V_S5
VCCPRIM_CORE
VCCPGPPD
+3V_S5
C68
C698
1U/6.3V_4
AF19
T16
Rev:F reserve TP
+VCCPGPPE
1.0V
2.574A
*short_6
R179
CFG[5]
VCCPRIM_CORE
VCCPGPPE
+3V_S5
D68
BB2
V20
AF16
+VCCPGPPF
S5
33mA
*short_6
R192
CFG[6]
RSVD_BB2
VCCPRIM_CORE
VCCPGPPF
+1.8V_S5
C67
BA3
Rev:F Stuff C699
C699
47u/6.3V_8
V21
AD15
41mA
+VCCPGPPG
*short_6
R188
CFG[7]
RSVD_BA3
VCCPRIM_CORE
VCCPGPPG
+3V_S5
F71
C256
1U/6.3V_4
CFG[8]
G69
1U/6.3V_4
C712
+VCCDSW_1P0
AL1
75mA with AJ21 pin
V19
+VCCPRIM_3P3
1.0V
C270
*1U/6.3V_4
CFG[9]
DCPDSW_1P0
VCCPRIM_3P3_V19
F70
AU5
CFG[10]
TP5
G68
AT5
K17
T1
+VCCPRIM_1P0
+1V_S5
1.0V
1.0V
+1V_S5
CFG[11]
TP6
VCCMPHYAON_1P0
VCCPRIM_1P0_T1
H70
C695
1U/6.3V_4
C793
1U/6.3V_4
L1
22mA
C250
1U/6.3V_4
CFG[12]
VCCMPHYAON_1P0
G71
AA1
+VCCATS_1P8
S5
6mA
1.8V
*short_6
R180
CFG[13]
VCCATS_1P8
+1.8V_S5
H69
D5
N15
*short_6
R240
CFG[14]
RSVD_D5
+1V_S5
VCCMPHYGT_1P0_N15
+3V_S5
G70
D4
C191
1U/6.3V_4
N16
AK17
+VCCPRTCPRIM_3P3
1.0V
<1mA
C348
0.1U/16V_4
CFG[15]
RSVD_D4
VCCMPHYGT_1P0_N16
VCCRTCPRIM_3P3
B2
N17
C349
1U/6.3V_4
RSVD_B2
VCCMPHYGT_1P0_N17
E63
C2
C182
47u/6.3V_8
P15
AK19
1.258A
+VCCPRTC
*short_6
R252
CFG[16]
RSVD_C2
VCCMPHYGT_1P0_P15
VCCRTC_AK19
+3V_RTC
F63
P16
3.0V+
BB14
C322
1U/6.3V_4
CFG[17]
VCCMPHYGT_1P0_P16
VCCRTC_BB14
B3
RTC
C352
0.1U/16V_4
RSVD_B3
E66
A3
K15
BB10
DCPRTC
C732
0.1U/16V_4
CFG[18]
RSVD_A3
VCCAMPHYPLL_1P0
DCPRTC
F66
C179
1U/6.3V_4
L15
1.0V
CFG[19]
VCCAMPHYPLL_1P0
AW1
A14
RSVD_AW1
VCCCLK1
+1V_S5
R156
49.9/F_4
CFG_RCOMP
E60
V15
1.0V
26mA
CFG_RCOMP
+1V_S5
1.0V
VCCAPLL_1P0
E1
K19
S5
RSVD_E1
VCCCLK2
R153
1.5K/F_4
E8
E2
AB17
135mA
C680
*1U/6.3V_4
+1V_S5
ITP_PMODE
RSVD_E2
+1V_S5
VCCPRIM_1P0_AB17
C225
*1U/6.3V_4
Y18
L21
1.0V
696mA
VCCPRIM_1P0_Y18
VCCCLK3
AY2
BA4
S5
S5
RSVD_AY2
RSVD_BA4
AY1
BB4
R210
*0_6
+VCCPDSW_3P3
AD17
N20
RSVD_AY1
RSVD_BB4
+3VPCU
VCCDSW_3P3_AD17
VCCCLK4
R212
*short_6
AD18
3.3V
S5
+3V_S5
VCCDSW_3P3_AD18
D1
A4
*0.1U/16V_4
C314
AJ17
L19
118mA
RSVD_D1
RSVD_A4
VCCDSW_3P3_AJ17
VCCCLK5
C
D3
C4
R789
0_6
C
RSVD_D3
RSVD_C4
+3V
R683
*0_6
+VCCHDA
AJ19
A10
1.5V
30mA
+1.5V
VCCHDA
VCCCLK6
K46
BB5
C748
1U/6.3V_4
C672
1U/6.3V_4
RSVD_K46
TP4
K45
R193
*short_6
+VCCPSPI
AJ16
AN11
V0P85A_VID0
3.3V11mA
S5
RSVD_K45
+3V_S5
VCCSPI
GPP_B0/CORE_VID0
TP31
A69
AN13
V0P85A_VID1
+3V
RSVD_A69
GPP_B1/CORE_VID1
TP16
AL25
B69
AF20
RSVD_AL25
RSVD_B69
VCCSRAM_1P0
AL27
AF21
1.0V
RSVD_AL27
+1V_S5
VCCSRAM_1P0
AY3
R759
*short_4
T19
642mA
RSVD_AY3
VCCSRAM_1P0
C71
C192
1U/6.3V_4
T20
RSVD_C71
VCCSRAM_1P0
B70
D71
RSVD_B70
RSVD_D71
C70
R186
*short_6
+VCCPRIM_3P3
AJ21
+3V_S5
3.3V
75mA
S5
RSVD_C70
VCCPRIM_3P3_AJ21
F60
Rev:D change to
shortpad
C261
1U/6.3V_4
RSVD_F60
C54
AK20
1.0V
696mA
+1V_S5
S5
RSVD_C54
VCCPRIM_1P0_AK20
A52
D54
RSVD_A52
RSVD_D54
N18
+1V_S5
VCCAPLLEBB
BA70
AY4
C173
1U/6.3V_4
1.0V
33mA
RSVD_TP_BA70
TP1
BA68
BB3
RSVD_TP_BA68
TP2
15 OF 20
J71
AY71
R760
*short_4
RSVD_J71
VSS_AY71
SKL_ULT/BGA
REV = 1
?
J68
AR56
R762
*GT3@0_4
RSVD_J68
ZVM#
LPM_ZVM_N
(33)
F65
AW71
VSS_F65
RSVD_TP_AW71
G65
AW70
For 2+3e CPU No Stuff
VSS_G65
RSVD_TP_AW70
F61
AP56
RSVD_F61
MSM#
TP88
E61
C64
R761
100K_4
RSVD_E61
PROC_SELECT#
19 OF 20
+1V_VCCST
REV SKL_ULT/BGA = 1
B
B
?
Pin Name
Strap description
Configuration
Note
1 = *Normal Operation; No stall (iPU 3K)
CFG[0]
Stall reset sequence after PCU PLL lock until de-asserted
0
= Stall
CFG[1]
Reserved Configuration lane
1 = *Normal Operation(iPU 3K)
CFG[2]
PCI Express* Static x16 Lane Numbering Reversal
H
& S processor used only
0 = Lan number reversed
CFG[3]
Reserved Configuration lane
1
= Disabled (iPU 3K)
CFG[4]
eDP enable
CFG4
R548
1K_4
0 = *Enabled
00
= 1x8, 2x4 PCI Express*
01
= reserved
CFG[6:5]
PCI Express* Bifunction
H
& S processor used only
A
10
= 2x8 PCI Express*
A
11
= 1x16 PCI Express*
CFG[7]
PEG Training
1 = *PEG Train immediatedly follow
RESET# de-assertion (iPU 3K)
0 = PEG wait for BIOS for training
H
& S processor used only
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
CFG[19:8]