CMOS Inverter Design Using Cadence Virtuoso

13/10/2021 14:42 CMOS Inverter Design Using Cadence Virtuoso | vlsi4freshers
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 Physical Design STA Frontend Design DFT Verification CMOS Basics Li
CMOS Inverter Design Using Cadence Virtuoso
vlsi4freshers
July 17, 2021
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
CMOS Basics
,
CMOS Concepts
,
Digital Design
Introduction
The objective of this post session is to familiar with the Cadence CAD tools using Virtuoso Schematic
Spectre Simulation. We will practice the design of CMOS Inverter (Schematic & Layout) and its pr
postlayout simulation.
Getting Started
These are the following steps involve to proceed with Cadence Virtuoso tool:
1. Go to root→Cadence_design
2. By right click on Cadence_design, Go to Open in terminal
3. Enter these Commands:
csh ↲
source /cad/cshrc ↲
virtuoso ↲
https://www.vlsi4freshers.com/2021/07/cmos-inverter-design-using-cadence.html 1/20
4. The virtuoso or Command Interpreter Window (CIW) will open

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SAIBA MAIS OK
Create Library
5. To create library, In Virtuoso window, Go to Tools→Library Manager
6. In LibraryManager Window, Go to File → New→enter new library name.
7. Select option “Attach technology library” and Click OK
8. Here, we are designing inverter in UMC180nm technology. So, select UMC_18_CMOS from option an
Create Schematic
9. In this Section, We will create a cell that consists of Schematic view of Inverter in our new library.
desempenho,
10. In Virtuosopara garantir
window a qualidade
or Library dewindow,
manager serviço,Go
gerar
to estatísticas de uso e detectar e
eliminar abusos.
File → New → Cell view SAIBA MAIS OK
11. New file window will be open:
Give Cell name (for example:inverter) in your library.
12. After above settings, Click OK
13. A blank Schematic window will be open
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SAIBA MAIS OK
Add Components for Schematic Design
14. To add components, Go to Instance option or Press “ I ”
15. In Library browser window, different components can be selected that is required to design
Schematic.
16. To take wire→ Go to or Press “ W ”
17. To give net name → Go to
18. To insert pin → Go to or Press “ P “
19. To copy any component in Schematic or layout window
Select component →Press “C” and Click on the component
20. To see the properties of Component
Select Component → Press “Q”
21. The table shows the Components properties to design an Inverter
Library Name Cell Name Properties

desempenho,
UMC_18_CMOS para garantir
a qualidade de serviço,
P_18_MM gerar
estatísticas de uso
L= 180nm W= e detectar e
480nm
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SAIBA
UMC_18_CMOS N_18_MM MAIS
OK
L= 180nm W= 240nm
22. Add Pins to the Schematic
Pins Name Direction
in Input
out Output
vdd Input
gnd Input
23. Click Check & Save icon
After Check & Save, if there is any warning, Virtuoso window will show its description
Create Symbol
24. In Schematic window of Inverter, Go to
Create → cell view → From cell view. In Cell view from cell view window, verify the library name and c
25. Click OK
26. In symbol generation window, Modify the pins specifications and Click OK.
desempenho, para Specifications,
Note: During Pins garantir a qualidade de serviço,
the namings of pinsgerar
must estatísticas de uso e detectar e
be same as in schematics.
eliminar abusos.
SAIBA MAIS OK
27. The symbol of inverter can be edited to look like a Inverter gate by using different shapes.
28. After creating Symbol, Click on Save icon to save the Inverter symbol.
29. Close the Symbol window.
Inverter _test Design
30. In virtuoso window or Library manager window, Go to
File → New → cell view
31. In new file window, verify the library name and give the cell name in “ _test” form.
32. Click OK
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33. A blank schematic window for test circuit will be open.
34. Instance the symbol of that schematic for testing.
To Instance the symbol, follow “step (14)” and browse the library
35. These are the following properties of components to be used in test circuit.
Library Name Cell Name Properties
warm2017 inverter Symbol
analogLib vpulse v1=0v, v2= 1.8,
tr=tf=1p, Period=20n,
Pulse width= 10n
analogLib gnd symbol
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36. CIick on Check & save icon to Save design.
Spectre Simulation
37. In Inverter_test schematic window Go to Launch → ADEL
38. ADE (Analog Design Environment) window will be open.
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39. In ADE window, Go to Set up → Model Libraries
40. In Model library Set up window, Check whether the model libraries for UMC_18_CMOS is attached o
Choosing Analysis
41. In ADE window, click Choose → Analysis icon
42. The Choosing Analyses window will open
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SAIBA MAIS OK
43. For transient Analyses, select tran option
44. Set stop time as 200n
45. Click moderate, enable option and click on apply.
46. For DC Analyses, select dc option
47. Click save DC operating point and component parameter options
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SAIBA MAIS OK
48. Click on Select component, schematic window will be open
49. In schematic window, select vpulse source test schematic window and select “ DC voltage “.
50. In DC analyses, give start and stop voltages 0 to 1.8 respectively.
51. Click OK.
52. In ADE window, Go to outputs → to be plotted the select the terminals of Vin and Vout from
window.
53. To Execute the Simulation

desempenho, para→
Go to Simulation garantir
Netlistaand
qualidade
Run or de serviço,
click on this gerar
icon. estatísticas de uso e detectar e
eliminar abusos.
SAIBA MAIS OK
Save Session (for saving the settings in ADE window for later use)
To save the current session,
In ADE window, Go to session → Save state
Click OK
Load Session
To load the previous session
In ADE window, Go to session → Load state

Layout of Inverter
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54. In inverter schematic window, SAIBA MAIS OK
Go to Launch → Layout XL
55. Select create new option, Cell name and View name (Layout)
56. Click OK.
57. Layout window will be open
58. For adding the components to layout window, In layout window
In layout window
Go to Connectivity → Generate → All from source . Click OK
59. Place the components in PR (Placement & Routing) boundary.
● To see layout view (in layers form)→ Press “ Shift + F ”
● To take rectangle shape → Press “ R ” and select layer
● To Move → Select component and Press “ M ”
● To Stretch→ Press “ ctrl+shift+X ” or (Press “S ” and place arrow on edge of the layer to be stretch)
60. From the layout window, to take shape Go to create → shape
61. To create via, Go to Create → via
Connection Via type
Metal1Poly ME1Poly
Metal1Psubstrate ME1Psub
Metal1Nwell ME1Nwell
62. To Label the pins, press “ L “ (Labelling of pins in layout will be same as in schematic )
desempenho, para garantir
63. Save the Layout Design a qualidade de serviço, gerar estatísticas de uso e detectar e
eliminar abusos.
SAIBA MAIS OK
Layout Verification Steps
1. DRC (Design Rule Check)
2. LVS (Layout vs SChematic)

3. QRC (RC Extraction)
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SAIBA
64. Go to Assura → technology from Layout MAISto select
window OK the technology
The technology path will be
/root/cadence_design/UMC 180/assura tech.lib
DRC
65. For DRC, Go to Assura → Run DRC
66. In DRC window, Settings :set technology UMC_ 18_CMOS and Rule setDRC
67. Click OK to check DRC
68. If there is any error in Layout, then it will appear in ELW (Error Layer Window)
69. If there is no error, it will show no drc error found .
LVS
70. For LVS, Go to Assura → LVS
Technology UMC_18_CMOS and Rule set LVS
71. Click OK . It will compare both Schematic and Layout.
QRC
72. For QRC, Go to Assura → QRC
73. In Setup, output = Extracted view
74. In extraction tab, Set Extraction type= RC and reference node=gnd.
75. Click OK.
76. To see the extracted view,
select your created library in Library manager window, it will show av_extacted view of inverter cell.
desempenho,
77. To see RCpara garantir aPress
components, qualidade de) serviço,
( ctrl+A gerarwindow.
in extraction estatísticas de uso e detectar e
eliminar abusos.
Configuration View SAIBA MAIS OK
78. In Virtuoso window or library manager window,
Go to File → New → cell view
79. Check the following settings in new file window
In config setting, typeconfig type and cell name will be in “ test ” form.
80. Click OK
The Hierarchy Editor window will open and a New Configuration window open in front of it.
81. Set view as Schematic
82. Click on use template and select spectre in use template window.
83. Click OK in New Configuration form.
84. The hierarchy editor displays the hierarchy for this design using table format
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85. Click on Tree View
86. Save the Current configuration
Simulation of circuit
Without Parasitics
87. From the Library Manager open Inverter_Test Config view.
88. The schematic window of config view will be open
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SAIBA MAIS OK
89. Go to Launch → ADEL in Schematic window
90. In ADE window , Go to Session → load state and simulate it.
With Parasitics
91. From the Library Manager open Inverter_Test Config view.
92. Click OK .
The Hierarchy Editor window will open and a New Configuration window open in front of it.
93. Select Tree view
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94. Right click on the Inverter schematic.
SAIBA MAIS OK
95. Select av_extracted view from the Set Instance view menu.
96. Save the Current configuration
97. Again, Simulate it from ADE window
98. In this case it will show the simulation of inverter with parasitic.
Create GDS file
99. Select File – Export – Stream in the virtuoso window.
100. In stream file option, specify the path of .gds file.
100. Click on the Show Options button.
101. In the StreamOut Options window, select in Layers tab and click OK.
102. Click Translate button to start the stream translator. .gds file have been created and it will be stor
specified location.
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13/10/2021 14:42 CMOS Inverter Design Using Cadence Virtuoso | vlsi4freshers

 Physical Design STA Frontend Design DFT Verification CMOS Basics Li

2. By right click on Cadence_design, Go to Open in terminal

3. Enter these Commands:

4. The virtuoso or Command Interpreter Window (CIW) will open

5. To create library, In Virtuoso window, Go to Tools→Library Manager

6. In LibraryManager Window, Go to File → New→enter new library name.

7. Select option “Attach technology library” and Click OK

11. New file window will be open:

Give Cell name (for example:inverter) in your library.

12. After above settings, Click OK

13. A blank Schematic window will be open

Add Components for Schematic Design

14. To add components, Go to Instance option or Press “ I ”

16. To take wire→ Go to or Press “ W ”

17. To give net name → Go to

18. To insert pin → Go to or Press “ P “

19. To copy any component in Schematic or layout window

Select component →Press “C” and Click on the component

20. To see the properties of Component

Select Component → Press “Q”

21. The table shows the Components properties to design an Inverter

Library Name Cell Name Properties

22. Add Pins to the Schematic

Pins Name Direction

23. Click Check & Save icon

24. In Schematic window of Inverter, Go to

29. Close the Symbol window.

Inverter _test Design

30. In virtuoso window or Library manager window, Go to

File → New → cell view

33. A blank schematic window for test circuit will be open.

34. Instance the symbol of that schematic for testing.

Library Name Cell Name Properties

warm2017 inverter Symbol

analogLib vpulse v1=0v, v2= 1.8,

Pulse width= 10n

analogLib gnd symbol

36. CIick on Check & save icon to Save design.

37. In Inverter_test schematic window Go to Launch → ADEL

38. ADE (Analog Design Environment) window will be open.

39. In ADE window, Go to Set up → Model Libraries

41. In ADE window, click Choose → Analysis icon

42. The Choosing Analyses window will open

43. For transient Analyses, select tran option

44. Set stop time as 200n

45. Click moderate, enable option and click on apply.

46. For DC Analyses, select dc option

47. Click save DC operating point and component parameter options

48. Click on Select component, schematic window will be open

50. In DC analyses, give start and stop voltages 0 to 1.8 respectively.

51. Click OK.

53. To Execute the Simulation

To save the current session,

In ADE window, Go to session → Save state

To load the previous session

In ADE window, Go to session → Load state

54. In inverter schematic window, SAIBA MAIS OK

56. Click OK.

57. Layout window will be open

58. For adding the components to layout window, In layout window

Go to Connectivity → Generate → All from source . Click OK