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CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1
A RD 0
ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 File WD
20:16
0
15:11
1
WriteReg4:0
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
PCPlus4
Result
1
04/06/2021
4. Unidade de Controlo
A Unidade de Controlo (UC)
Gera os sinais de controlo do datapath, usando como entradas
os bits de opcode e de funct da instrução.
Control • A maior parte das saídas de controlo
Unit MemToReg
é derivada do opcode; as instruções
MemWrite
Opcode5:0 Main Branch do tipo-R precisam ainda de usar o
Decoder ALUSrc campo funct para determinar a ope-
RegDst
ração da ALU.
RegWrite
ALUOp1:0 31:26 25:21 20:16 15:11 10:6 5:0
0 rs rt rd shamt funct Tipo-R
31:26 25:21 20:16 15:0
Funct5:0 ALU
ALUControl2:0 opcode rs rt imm16 Tipo-I
Decoder
31:26 25:0
opcode imm26 Tipo-J
2
04/06/2021
Control
Unit MemToReg ALUOp1:0
MemWrite
Opcode5:0 Main Branch
Decoder ALUSrc
RegDst Funct5:0 ALU ALUControl2:0
RegWrite Decoder
ALUOp1:0
32 Zero
ALU
3
04/06/2021
Y 100 A ^ B
32 Zero
ALU
Control Unit 32
N
A 101 ~(A | B) 32 ALUResult
110 A - B
111 SLT
A ALU pode facilmente ser implementada em linguagens de descrição de hardware (HDL) do tipo VHDL
ou Verilog.
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 6/28
(Para as instruções do tipo-R, os dois primeiros bits do campo Funct são sempre 10, poden-
do ser ignorados aquando da implementação).
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 7/28
4
04/06/2021
rt 0
Control Mux WriteReg RegDst: Activo seleciona rd
5
Unit RegDst como WriteReg do RF.
5
rd 1
ALUSrc
5
Opcode5:0 Main MemToReg
ALUSrc
Decoder MemWrite
RegWrite
RD2 0 SrcB
Branch 32 ALUSrc: Activo seleciona SignImm
ALUOp1:0 Enable SignImm 32 como SrcB da ALU.
1
32
Os sinais de controlo necessários a cada instrução já foram vistos durante a construção do datapath.
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 8/28
Control
Unit RegDst
Mux • MemWrite - Enable de escrita da
ALUSrc Memória de Dados
Opcode5:0 Main MemToReg
Decoder MemWrite
RegWrite
Branch
• RegWrite - Enable de escrita do
ALUOp1:0 Enable Banco de Registos
Funct5:0 ALU
Decoder
ALUControl2:0 • Branch - Activo só para a instrução
beq (ou bne)
5
04/06/2021
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 File WD
1
20:16
0
15:11
1
WriteReg4:0
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
PCPlus4
Result
6
04/06/2021
ALU
1 1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 0
20:16
0
15:11
1
WriteReg4:0
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
PCPlus4
Result
lw rt, imm(rs)
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 12/28
010
CLK 0 (add) CLK 1
0 CLK
SrcA X
25:21 WE3 Zero WE
0 PC' PC Instr A1 RD1 0
A RD
ALU
1 1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File X
20:16
0
15:11
1
WriteReg4:0
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
PCPlus4
Result
sw rt, imm(rs)
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 13/28
7
04/06/2021
110
CLK (sub) CLK 0
CLK 0
1
SrcA Zero WE X
Instr 25:21 WE3
0 PC' PC A1 RD1 0
A RD
ALU
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 File X WD
20:16
0
15:11
1
WriteReg4:0
BTA = (PC+4) + (SignImm<<2)
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
PCPlus4
Result
beq rs,rt,imm
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 14/28
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 File WD
1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
or rd, rs, rt
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 15/28
8
04/06/2021
ALU
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
10:6
Exercício - OR (3) - Ler Operandos
31:26 25:21 20:16 15:11 5:0
0 rs rt rd 0 37
MemToReg
or rd, rs, rt
Control
MemWrite
Unit
Branch 0
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
9
04/06/2021
MemToReg
or rd, rs, rt
Control
MemWrite
Unit
Branch 0
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite
ALU
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
10:6
Exercício - OR (5) - Escrita no RF
31:26 25:21 20:16 15:11 5:0
0 rs rt rd 0 37
MemToReg
or rd, rs, rt
Control
MemWrite
Unit
Branch 0
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
10
04/06/2021
ALU
1 0 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
11
04/06/2021
CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1
A RD 0
ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
12
04/06/2021
1 1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File 0
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 Sign Extend <<2
PCBranch
+
Result
13
04/06/2021
CLK CLK
CLK
0 PC' 25:21 WE3 SrcA Zero WE
0 PC Instr A1 RD1 0 Result
1 A RD
ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
JTA Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
PCJump 0
15:11
1
WriteReg4:0
PCPlus4
+
SignImm
4 15:0 <<2
Sign Extend PCBranch
+
27:0 31:28
25:0
<<2 JTA = Concatenação de (PC+4)31:28 com Imm27:0
(note-se o SLL (<<2) extra para gerar Imm27:0)
© A. Nunes da Cruz IAC - MIPS - Single-cycle - II 27/28
14
04/06/2021
15