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bypass
bypass
Zin b Zin e
Zin b
Configurações e Modelos para o BJT.
Circuito Emissor Comum, sem carga e fonte de sinal com impedância interna zero.
O equivalente DC mostra as características de polarização do amplificador. É
obtido abrindo-se TODOS os capacitores - o circuito que restar é o equivalente DC.
Vcc/2
Zin R1 || R2 || Zinbase
Zinbase .re
'
ZO RC || ZCE RC
Equivalente AC para o circuito EC, mostrando detalhes das
impedâncias de entrada e saída.
Zinbase .re
'
,
Geração do Modelo para Pequenos Sinais (MPS)
vo iC .RC RC
Zin R1 || R2 || .re, Av , Z O RC
vi ie .re, re
Geração do Modelo para Pequenos Sinais (MPS)
vo .ib RC RC
Av
vi ib .r 'e r 'e
ou
RC
vo .vi
r 'e
RC
vo A.vi .vi
r 'e
Exemplo 1 – Para o circuito EC da figura 1, polarize os o transistor utilizando
DTF. Considere todos os capacitores infinitos, V CC = 12V, IC = 2mA , β = 100 e
VS = 5mV.
A polarização é obtida a partir do equivalente DC.
0,1VCC 1,2V
RE 600
IC 2mA
12V
0,4VCC 4,8V
RC 2.400
IC 2mA
2mA
ou
RC 4 RE 2.400
V1 (12V 1,9V )
R1 .R2 .(6k) 31,9k
V2 1,9V
Circuito Polarizado
Equivalente AC
iC
2,4k
RB
(31,9k || 6k)
26mV
r 'e 13
Equivalente AC 2mA
iC r 'e 1.300
Z in (5k || 1,3k) 1k
2,4k Z O 2,4k
RB
5k
(31,9k || 6k) ib .(5A) 3,97 A
6,3k
ib 397 A
vO (3,97 A).(2,4k)
Modelo para Pequenos Sinais (MPS) vO 953mV
ib ic vo
vo 953mV
A 190
5 mV vi 5mV
5 kΩ 2,4 kΩ
vi A 45,6dB
Circuito Simulado
Condições Quiescente
( esperado - 2mA )
2mA
(esperado 1,2V)
vo 953mV
A 190 Condições AC e DC A
vo
613mV
175
vi 5mV vi 3,5mV
(esperado)
A 45,6dB A 44,8dB (obtido)
867mV
Exemplo 2 – O circuito da figura abaixo já está Polarizado. Considere todos os
capacitores infinitos, VCC = 12V, β = 100, RL = 4k7 e VS = 5mVP. Determine o valor da
tensão AC na carga (VO ) , o ganho de tensão do circuito em dB (VO /VS ), e as
impedâncias de entrada e saída do circito (Zin e ZO ).
1) Polarização : V 12k x12V 1,8V 2) Impedâncias :
B
80k
VT 26mV
1,1V r 'e 24
VE (1,8V 0,7V ) 1,1V IC I E 1,1mA I E 1,1mA
1k
ZO RC 4,7k
VB
Av 40dB
IC VRE VB
VB
VO
Circuito Emissor Comum Linearizado, sem carga e fonte
de sinal com impedância de saída zero.
A Linearização é uma técnica que visa Reduzir o Ganho de Tensão do circuito a fim de
aumentar a Estabilidade. Tem como consequência o aumento da Impedância de
Entrada e da Banda passante do circuito.
A linearização não deve alterar as condições DC do circuito. Para tanto, após
determinado o valor necessário de RE , fazemos o resistor de linearização com valor entre
10 e 30% deste valor, e acrescentamos em série um resistor com valor igual ao
complemento do valor de RE .
10 a 30% do
valor total
valor total
complemento
Equivalente AC para o circuito EC Lin.
ZO RC || ZCE RC
Zin R1 || R2 || Zinbase
Zinbase .(re re )
'
vo .ib RC RC
Av
vi ib . (r 'e re ) (r 'e re )
ou
RC
vo .vi
(r 'e re )
(r 'e RE )
RC
vo A.vi .vi
(r 'e re )
Circuito com impedância interna da fonte de sinal
VB
Condições DC:
2,2
VB .10V 1,8V
12,2
VE (1,8 0,7) 1,1V
1.1V
I E IC 1,1mA
1k
26mV
r 'e 24
1,1mA
Condições AC:
Z in R1 || R2 || .r 'e 1,8k || 2,4k ZO 3,6k
1mV
Z in 1k ii 0,625A
1,6k
vb 0,625Ax1k 0,625mV
0,625mV
ib 0,260A
2,4k
vO .ib .RC (100 x0,260A) x3,6k 94
vO 94
RC 3,6k
A 150
r 'e 24
1k
vi .(1mV ) 0,625mV
1,6k
vo 94mV
SE
Em muitas situações, não estamos interessados na composição interna de um
circuito ou sistema. Conhecer apenas como as variáveis de entrada e saída se
relacionam pode ser suficiente.
Um modelo Quadripolo é uma descrição da rede que relaciona tensão e
corrente entre os terminais de entrada e saída.
Considere o Quadripolo genérico mostrado acima. Existem várias formas de
relacionar as grandezas de entrada e saída:
V1
h11 V2 0 [ hie ]
I1
V1
h12 I1 0 [ hre ]
V2
I2
h21 V2 0 [ h fe ]
I1
I2
h22 I1 0
V2 [ hoe ]
FIGURE 7-7 Determining Zi.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-8 Demonstrating the impact of Zi on an amplifier’s response.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-9 Example 7.1.
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FIGURE 7-10 Determining Zo.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-11 Effect of Zo = Ro on the load or output current IL.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-12 Example 7.2.
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FIGURE 7-13 Determining the no-load voltage gain.
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FIGURE 7-14 Example 7.3.
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FIGURE 7-15 Determining the loaded current gain.
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FIGURE 7-16a Common-base BJT transistor.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-16b re model for the configuration of Fig. 7-16a.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-17 Common-base re equivalent circuit.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-18 Defining Zo.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-19 Defining Av = Vo/Vi for the common-base configuration.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-20 Approximate model for a common-base npn transistor configuration.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-21a Common-emitter BJT transistor.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-21b Approximate model for the configuration of Fig. 7-21a.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-22 Determining Zi using the approximate model.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-23 Impact of re on input impedance.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-24 Defining ro for the common-emitter configuration.
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FIGURE 7-25 Including ro in the transistor equivalent circuit.
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FIGURE 7-26 Determining the voltage and current gain for the common-emitter transistor amplifier.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-27 re model for the common-emitter transistor configuration.
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FIGURE 7-28 Hybrid parameters for the 2N4400 transistor.
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FIGURE 7-29 Two-port system.
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FIGURE 7-30 Hybrid input equivalent circuit.
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FIGURE 7-31 Hybrid output equivalent circuit.
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FIGURE 7-32 Complete hybrid equivalent circuit.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-33a Common-emitter configuration: graphical symbol.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-33b Common-emitter configuration: hybrid equivalent circuit.
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FIGURE 7-34a Common-base configuration: graphical symbol.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-34b Common-base configuration: hybrid equivalent circuit.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-35 Effect of removing hre and hoe from the hybrid equivalent circuit.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
Electronic Devices and Circuit Theory, 8e Upper Saddle River, New Jersey 07458
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FIGURE 7-36 Approximate hybrid equivalent model.
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FIGURE 7-37 Hybrid versus re model: (a) common-emitter configuration; (b) common-base configuration.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-38 Common-emitter hybrid equivalent circuit for the parameters of Example 7.6.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-39 Common-base re model for the parameters of Example 7.6.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-40 hfe determination.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-41 hoe determination.
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FIGURE 7-42 hie determination.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-43 hre determination.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-44 Complete hybrid equivalent circuit for a transistor having the characteristics that appear in Figs. 7-40 through 7-43.
Robert L. Boylestad and Louis Nashelsky Copyright ©2002 by Pearson Education, Inc.
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FIGURE 7-45 Hybrid parameter variations with collector current.
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FIGURE 7-46 Hybrid parameter variations with collector-emitter potential.
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FIGURE 7-47 Hybrid parameter variations with temperature.
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FIGURE 7-48 Problem 4
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FIGURE 7-49 Problem 8
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FIGURE 7-50 Problem 9
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FIGURE 7-51 Problem 17
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FIGURE 7-52 Problem 18
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FIGURE 7-53 Problems 19, 21