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THREE-PHASE POWER ELECTRONIC LOAD FOR

BURN-IN-TEST

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Bruno França Leonardo Francisco Silva

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M. Aredes
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XVIII Congresso Brasileiro de Automática / 12 a 16-setembro-2010, Bonito-MS

THREE-PHASE POWER ELECTRONIC LOAD FOR BURN-IN-TEST

Bruno W. França, Leonardo F. da Silva, Maurício Aredes

LEMT – Laboratório de Eletrônica de Potência e Média Tensão, Programa de Engenharia Elétrica,

COPPE/UFRJ
Centro de Tecnologia, Bloco I, sala I-156, Cidade Universitária, Rio de Janeiro, RJ, Brasil
CEP: 21.949-900 Caixa Postal 68504

E-mails: bruno@lemt.ufrj.br, leonardo@lemt.ufrj.br, aredes@lemt.ufrj.br

Abstract – In this paper is proposed a Power Electronic Load (PEL), which simulates four load configurations: balanced, unbalanced,
harmonic and unbalanced harmonic. Thus, this PEL is able to burn-in-test not only series equipment as AC power sources, but also shunt
equipment as shunt Power Conditioning. In this way, the control strategy is presented based on the p-q Theory, that allows recover the
average active power to the electric network bus as an ideal source connected to this bus. PSCAD/EMTDC simulation results are provided in
order to show the fast dynamic and the robustness algorithm.

Keywords – Power Electronic Load, p-q Theory, PSCAD/EMTDC, burn-in-test.

Resumo – Neste artigo é proposto uma Carga Eletrônica, a qual simula quatro tipos de configuração de carga: equilibrada,
desequilibrada, harmônica e harmônica desequilibrada. Desta forma, essa Carga Eletrônica é capaz de avaliar não somente equipamentos
conectados em série, tal como fontes CA, mas também equipamentos conectados em paralelo, como por exemplo, equipamentos
condicionadores de energia conectados em paralelo. Assim sendo, a estratégia de controle é apresentada baseada na Teoria p-q, que permite
restituir a potência ativa média consumida para a rede elétrica como uma fonte ideal conectada a mesma. Por fim, são apresentados
resultados de simulação utilizando o PSCAD/EMTDC, com o intuito de mostrar a dinâmica e robustez do algoritmo de controle
desenvolvido.

Palavras-chave – Carga Eletrônica, Teoria p-q, PSCAD/EMTDC, teste sob carga.

example, then the PEL has to drain a harmonic current

1. Introduction
Power Electronic Load (PEL) is traditionally
employed to burn-in-test AC power sources, motor
drives etc. The main characteristic of PEL is the
capability of reproduce different kinds of load without
expressive power losses, recovering the energy that
would be dissipated if the original load were used.
On this way, researches have been done using
single-phase converter as well three-phase converter,
depending on the PEL purpose. Besides, many types
of control strategy have been developed to reproduce
the original load behavior recovering the power to the
electric network (Li, et al., 2008), (Zheyu, et al.,
2009) and (She, et al., 2009).
This paper presents a new functionality for PEL,
using this to burn-in-test Power Conditioning
prototypes or equipment. These are usually used
connected to the grid as custom power and/or FACTS
controllers (Akagi, et al., 2007). Sometimes, they can
attend specific high power loads with non-linear
characteristics, which need support to be according to
the electrical standards. In other words, they should be
able to filtering harmonic currents, regulating the bus
voltage, controlling the power flows, compensating
unbalanced systems at all, depending on its purpose.
In this case, the PEL would be able to reproduce the
high power load behavior. Therefore, if the Power
Conditioning in test is a Harmonic Compensator, for
to test the Power Conditioning adequately.
The Instantaneous Power Theory (p-q Theory)
(Akagi, et al., 2007) has been expressively used in
recent researches to develop control strategies, as in
(Akagi, et al., 2007), (Watanabe, et al., 2008) and
(Aredes, et al., 2009). The control strategy developed
in this paper is based on the p-q Theory and will be
presented through equations and block diagrams.
The Section 2 will describe the PEL topology,
based on a back-to-back three-phase PWM rectifier
and its connection with the tested element (AC power
source or Power Conditioning). Then, in Section 3,
the control strategy is shown in two parts, the Power
Recovery and Link dc Controller and the Load
Simulator Controller. The simulation results are
presented in Section 4 and, at last, Section 5 presents
the conclusions.
2. Electronic Load Conception
Figure 1 illustrates a typical system to burn-in-test
an AC power source. According to the features
required, a PEL should be able to drain a specific
current, recovering the average active power to the
electric network. To make it possible, the recovered
power current (iGPEL) must be a sinusoidal current,
balanced, with unity power factor, phase angle of 180
degrees, and compounds only the fundamental
frequency component.

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XVIII Congresso Brasileiro de Automática / 12 a 16-setembro-2010, Bonito-MS
Figure 1: PEL burning-in-test an AC Power Source.
The same configuration can be utilized for burn-
in-test a Power Conditioning. For example, Figure 2
shows a Combined Series and Shunt Power
conditioner under test. In this figure, the PEL is
detailed and separated in three parts: the power
recovery converter, the load simulator converter and
the link dc.
Figure 2: PEL burning-in-test a Combined Series and
Shunt Power Conditioner.
Figure 3 shows the Switching Filter configuration,
which is the same for the power recovery converter
and for the load simulator converter.
Figure 3: Switching Filter configuration.
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3. Control Strategy
The presented control strategy is separated in two
independent parts, the Power Recovery and Link dc
Controller and the Load Simulator Controller. The
former is responsible for control the link dc voltage
and, consequently, controls the average active power
flow. The latter is responsible for reproduce the load
behavior. All this information will be better explained
in this section.
3.1 Power Recovery and Link dc Controller
In order to agree with the idea that the electrical
equivalent of the power recovery converter is an ideal
source connected to the electrical network bus, the
power delivered by this converter must contain only
the average active power component, in positive
sequence and fundamental frequency, as assumed
previously. Hence, according to the p-q Theory, this
power will be referenced as p GPEL . Assuming the
back-to-back converter in steady-state, the link dc
voltage is strictly related to the average active power
flow. In other words, regulating the link dc voltage is
the same as achieving the average active power
balance.
For example, if the input power is:
pPEL = p PEL +
p PEL (1)
To achieve the power balance in steady-state:
pGPEL = p GPEL = p PEL (2)
p = p =
p
DC REF PEL (3)
Where pDC is the link dc power and p REF is the
average active power necessary to obtain the link dc
voltage reference vDCREF . Note that an oscillating
input power
p PEL will appear in the link dc, producing
an oscillating voltage ( v DC ) added to the continuous
vDCREF , but it cannot be developed by the power
recovery converter. Thus, the vDCREF must be high
sufficiently to avoid that v DC affect the iGPEL
generation.
Figure 4 shows the Power Recovery and Link dc
Controller. As in (Borré, et al., 2006), the link dc
voltage regulation is a simple Proportional and
Integral Controller (PI Controller) that compares
vDCREF with the measured voltage ( vDC ), generating
the input error signal. However, if v DC is present, it is
necessary to filter vDC before set the signal in the PI
controller. In this way, only the continuous portion is
controlled, keeping
p PEL in link dc.
XVIII Congresso Brasileiro de Automática / 12 a 16-setembro-2010, Bonito-MS
Figure 4: Power Recovery and Link dc Controller.
The output PI controller signal is the average
active power ( pGPEL = p GPEL ) that must be
compensated, used in the following equation that
determines the compensation current in αβ
components (iGPEL-αβ).
iGPEL −α  pGPEL  v 'ENB −α 
i = 2 2 v '  (4)
 GPEL − β  v 'ENB −α + v 'ENB − β  ENB − β 
∆ = v '2ENB −α + v '2ENB − β
Where v 'ENB−α and v 'ENB − β are the instantaneous
voltages of the fundamental positive-sequence
component, in αβ reference frame, obtained through a
positive sequence detector (Neto, et al., 2009 ) and
(Padua, et al., 2007), in the electrical network bus. To
generate the PWM reference, iGPEL-α and iGPEL-β are
compared with the measured currents i'GPEL-α and
i'GPEL-β, in αβ reference frame, and the error signals
are used to input the respective PI Controller (Figure
5). The PI controller outputs are subtracted from
v 'ENB−α and v 'ENB − β to produce the reference PWM
signals.
Once that the Power Recovery and Link dc
Controller is working, it will take over the average
Figure 5: Power Recovery and Link dc PWM generation.
active power flows drained from the PEL bus and
deliver it back to the grid in the source bus.
3.2 Load Simulator Controller
In order to set a current (iPEL) that produces an
active and a reactive power from the PEL bus, a Load
Simulator Controller was developed. Furthermore,
with this controller is possible to set specific harmonic
currents in iPEL. Thus, the PEL is able to reproduce
harmonic loads behavior.
Figure 6 shows the Load Simulator Controller
block diagram, where v 'PEL −α and v 'PEL − β are the PEL
bus instantaneous voltages of the fundamental
positive-sequence component, in αβ reference frame.
ωtPEL is the fundamental phase angle. All this signals
were obtained through a positive sequence detector in
the PEL bus. The amplitude of each line current
(iPEL-a, iPEL-b and iPEL-c) and the fundamental power
factor, or displacement factor, as in (Akagi, et al.,
2007), are set by the user. Note the amplitudes are
(5) composed by all harmonics components and also by
the fundamental negative sequence component (to
simulate harmonic and unbalanced loads,
respectively). These information are used to generate
the load current signals in αβ reference frame iPEL-α
and iPEL-β.
To generate the PWM reference was utilized the
same strategy shown in the Power Recovery and Link
dc PWM generation. The currents iPEL-α and iPEL-β are
compared with the measured currents i’PEL-α and i’PEL-
β, in αβ reference frame, and the error signals are used
to input the respective PI Controller (Figure 6). The PI
controller outputs are subtracted from v 'PEL −α and
v 'PEL − β to produce the reference PWM signals.
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XVIII Congresso Brasileiro de Automática / 12 a 16-setembro-2010, Bonito-MS

Figure 6: Load Simulator Controller and PWM generation.

from Harmonic Load to Unbalanced Harmonic Load

at 1.1 seconds.
4. Simulation Results Finally, the FFT analysis of the Harmonic Load is
shown in Figure 10 to illustrate that only the harmonic
To validate the developed control strategy, a components required are drained by the PEL.
PSCAD/EMTDC simulation is presented in this
section. The Switching Filter parameters are the same
in both converters: L = 1 mH, C = 25 µF and
R = 0.3 Ω.
Table 1 shows the load type simulated by the PEL.
It changes through the simulation to reproduce all the
loads behaviors proposed. In addition, each load type
is simulated with three kinds of fundamental power
factor.

Table 1: Simulated Load Type.

Load Type Fundamental Power Factor THD Time Simulation Figure 7: Balanced Load.
1 0.10% 0.2 - 0.3 sec.
Balanced 0.8 (inductive) 0.09% 0.3 - 0.4 sec.
0.8 (capacitive) 0.10% 0.4 - 0.5 sec.
1 0.07% 0.5 - 0.6 sec.
Unbalanced 0.8 (inductive) 0.06% 0.6 - 0.7 sec.
0.8 (capacitive) 0.08% 0.7 - 0.8 sec.
1 36.26% 0.8 - 0.9 sec.
Harmonic 0.8 (inductive) 36.04% 0.9 - 1.0 sec.
0.8 (capacitive) 36.24% 1.0 - 1.1 sec.
1 27.92% 1.1 - 1.2 sec.
Unbalanced Harmonic 0.8 (inductive) 27.73% 1.2 - 1.3 sec.
0.8 (capacitive) 27.87% 1.3 - 1.4 sec.

4.1 Load Simulator results (a)

At 0.3 seconds, the fundamental power factor
changes from 1 to 0.8 inductive, as shown in Figure 7.
In Figure 8 the Unbalanced Load current is presented.
To compose this load, there is a fundamental negative
sequence component, whose amplitude is 0.3 p.u. In
the same way, at 0.7 seconds the fundamental power
factor changes from 0.8 inductive to 0.8 capacitive.
As example, the Harmonic Load currents
simulated are composed by: 1 p.u. of fundamental
component, 0.3 p.u. of 5th harmonic and 0.2 p.u. of 7th
harmonic. Figure 9 presents these currents changing (b)
Figure 8: Unbalanced Load: (a) Comparison between
Van and iPEL-a (b) Three-phase iPEL.

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XVIII Congresso Brasileiro de Automática / 12 a 16-setembro-2010, Bonito-MS
(a)
(b)
Figure 9: Harmonic and Unbalanced Harmonic Loads:
(a) Comparison between Van and iPEL-a (b) Three-phase
iPEL.
Figure 10: FFT analysis of the Harmonic Load.
4.2 Power Recovery and Link dc results
Figure 11 shows the Link dc voltage during all the
simulation. The Power Recovery and Link dc
Controller is set at 0.1 seconds. The link dc voltage
reference is vDCREF =560 V. Note that after 0.5 seconds
there is
p drained by the PEL. Therefore, after 0.5
PEL
seconds vDC is composed by vDCREF and v DC , but it
not affects the Power Recovery current, as shown in
Figure 12.
Figure 11: Link dc voltage.
140
Figure 12: Power Recovery current.
5. Conclusions
Based on the simulation results, the PEL proposed
is able to reproduce all load behaviors proposed,
recovering the average active power to the electric
network bus.
The robustness of the Power Recovery and Link
dc Controller was investigated, proving that it
recovers the energy to the electronic network bus with
very good accuracy, as an ideal source, even if
p PEL
is drained by the load simulator converter. The link dc
voltage was regulated during all the simulation.
The control strategy developed in the Load
Simulator Controller provides fast dynamic response
to change the load type and can be configured to
reproduce a specific load required, with specific
unbalance and/or harmonic components.
References
Akagi, H., Watanabe, E. H. and Aredes, M. 2007.
Instantaneous Power Theory and Applications to
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Aredes, M. e Fernandes, R.M. 2009. A unified power
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Borré, Antônio Carlos, et al. 2006. Análise
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Injeção de Corrente em um D-STATCOM.
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Li, F., et al. 2008. Research on AC electronic load
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rectifiers. Applied Power Electronics Conference
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Padua, M.S., et al. 2007. Comparative analysis of

Synchronization Algorithms based on PLL,
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