TRANSISTORES DE EFEITO DE

CAMPO- FET
 FET X BJT (NPN)
Drain Collector

Gate Base

Source Emitter

 Tensão nos terminas controla a corrente no 3º

terminal;
 Pode ser usado como chave e amplificador;
 Controle baseado no campo elétrico pela tensão
aplicada no terminal de controle;
 Condução apenas em um tipo de portador (elétrons ou
lacunas) – Unipolar;
1
Field Effect Transistors
CCT - UDESC
 Types of FETs
• Além do tipo de portador (canal N ou P), existem diferenças
como o elemento de controle é construído (junção x isolamento)
sendo usados de forma diferente
npn
Depletion mode junction FETs (JFET)
pnp
npn
Metal oxide semi-conductor FET (MOSFET)
pnp
– depletion/enhancement mode
– enhancement mode

(insulated (isolada) gate FETs, IGFETs, are the same as MOSFETs)

2
Field Effect Transistors
CCT - UDESC
 Enriquecimento(tipo N):
 Substrato tipo p (corpo);
 Duas regiões dopadas “n”;
 Camada dióxido de silício;
 Metal por cima do SiO2;
 Metal no dreno e fonte;
 4 terminais: Porta(G), Dreno
(D), Fonte (S) e Corpo (B);
 Região do D p/ S, região do
canal;
 Resistência porta – 1012 Ω.

NMOS
3
Field Effect Transistors
CCT - UDESC
 4
Field Effect Transistors
CCT - UDESC
 5
Field Effect Transistors
CCT - UDESC
 Criando o canal – canal induzido

 Operação normal –
junções “p n” são
mantidas reversamente
polarizadas.
 Tensão do dreno positiva
em relação à fonte.
 As duas junções podem
estar reversamente
polarizadas conectando-se
os terminais da fonte e
substrato – operação
normal. 6
Field Effect Transistors
CCT - UDESC
 7
Field Effect Transistors
CCT - UDESC
 Para VGS  0 o NMOS não conduz
ID  0

I D  0  REGIÃO DE CORTE
8
Field Effect Transistors
CCT - UDESC
 MOSFET tipo Enriquecimento (NMOS)
VGS  0 e VDS  0, com VGS pequeno

9
Field Effect Transistors
CCT - UDESC
 MOSFET tipo Enriquecimento (NMOS)
VGS  0 e VDS  0, com VGS crescendo

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Field Effect Transistors
CCT - UDESC
 MOSFET tipo Enriquecimento (NMOS)
VGS  Vth e VDS  0

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Field Effect Transistors
CCT - UDESC
 Corrente fluindo

Efeito de campo:
Porta e corpo – capacitor de
placas paralelas: cargas positivas
na parte de cima, cargas
negativas em baixo (canal
induzido)
Campo elétrico – controla a
quantidade de cargas no canal,
condutividade, corrente de
circulação. 12
Field Effect Transistors
CCT - UDESC
 G v GS > V TN
S D vDS Small Waterfalls analogy
+ + Water
n n

De pletio n p Acce pto r Io n

Re gion

S G v GS > V TN v =v - V TN
D DS GS

+ +
n n

De pletio n p
Re gion

S G v GS > V TN v > vGS - V TN

D DS

+ +
n n

De pletio n p
Re gion Pinch-o ff Po int

( a ) MOSFET in the linear region

( b ) MOSFET with channel just pinched
off at the drain.
( c ) Channel pinch off for vDS > vGS - VTN

13
Field Effect Transistors
CCT - UDESC
 VDS pequeno: vGS  Vtn

vDS variando 0,1 a 0,2 V

8.00e-4

V =5V
GS 0  vDS  vDSSAT= vGS-Vtn
6.00e-4
Drain-Source Current (A)

VGS= 4 V
W vDS 
2
VTN =1V iD  μnCOX vGS  Vtn vDS  
4.00e-4
L 2 
VGS= 3 V

small vDS
W
vGS  Vtn vDS
2.00e-4
V
GS
=2V iD  k n'
L

0.00e+0
diD
 k n'
W
vGS  Vtn 
0.0 0.2 0.4 0.6 0.8 dvDS L
Drain-Source Voltage (V)
NMOS i-v characteristics in the linear region (VSB = 0)
kn'  μnCOX

Linear Region (small vDS) 14

Field Effect Transistors
CCT - UDESC
 Aumento de VDS : vGS constante e vGS > Vtn

Maior tensão no canal, canal mais estreito próximo ao

Dreno.
Curva iD – vDS ilustra regiões
Triodo e Saturação

vDS = vGS – Vtn profundidade

do canal no dreno diminui até
próximo de zero, canal
estrangulado (“pinched-off”)

Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape and its resistance
increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

15
Field Effect Transistors
CCT - UDESC
 Curva característica iD x vGS

The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

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Field Effect Transistors
CCT - UDESC
 Curva característica iD x vGS
2.20e-4
iD  0 for vGS  Vtn
Linea r VGS = 5 V
2.00e-4 Re gion
 2

iD  k n vGS  Vtn vDS 
W v
Drain-Source Current (A)

'

1.80e-4 DS
Pincho ff Locus

1.60e-4
L 2 
vGS  Vtn
Sa turation Regio n
1.40e-4

VGS = 4 V for 
vDS  vDSSAT  vGS  Vtn
1.20e-4

1.00e-4

k n' W
vGS  Vtn 2
8.00e-5

V =3V
iD 
6.00e-5 GS 2 L
4.00e-5
V Š1V vGS  Vtn
VGS = 2 V GS for 
vDS  vDSSAT  vGS  Vtn
2.00e-5

0.00e+0
0 2 4 6 8 10 12

Drain-Source Vo ltage (V) D

ID
Output characteristics G
for an NMOS transistor with vD  vS
Vtn = 1 V and k’n (W/L)= 25 x 10-6 A/V2

SB
17
Field Effect Transistors
CCT - UDESC
Equação

W vDS 
2
iD  μnCOX vGS  Vtn vDS  
L 2 

kn'  μnCOX

Derivation of the iD - vDS characteristic of the NMOS transistor.

18
Field Effect Transistors
CCT - UDESC
 The PMOS Transistor
v v <0
S G v <0
D
i Gate
iS G iD Drain
Source

p+ Channel Region p+

N-Type Substrate

Body
i v >0
B B
Cross section of an enhancement-mode PMOS transistor

B
S D
S D

ID
ID

G G
19
Field Effect Transistors
CCT - UDESC
 2.50e-4 iD  0 for vGS  Vtp
 
iD  k p vGS  Vtp vDS 
V = 5 V (V = -5 V) 2
SG GS ' W v

DS
2.00e-4
Source-Drain Current (A)

L 2 
1.50e-4 vGS  Vtp
V = 4 V (V = -4 V) for 
vDS  vDSSAT  vGS  Vtp
SG GS

1.00e-4

k p' W
5.00e-5
V
SG
= 3 V (V
GS
= -3 V)
iD  vGS  Vtp 2
V
SG
= 2 V (V
GS
= -2 V) 2 L
0.00e+0
vGS  Vtp
V Š1V (V •-1 V) for 
vDS  vDSSAT  vGS  Vtp
SG GS

-5.00e -5
-2 0 2 4 6 8 10 12
Source -Drain Vo ltage (V)
SB
Output characteristics for a
PMOS transistor with
G
Vtp = -1V and k’P (W/L)= 25 x 10-6 A/V2 vS  vD
ID
D

20
Field Effect Transistors
CCT - UDESC
 Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well.
Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

21
Field Effect Transistors
CCT - UDESC
 (d)
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated.
(b)The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2 (d) The iD - vGS characteristic for an enhancement-
type NMOS transistor in saturation.
22
Field Effect Transistors
CCT - UDESC
 Channel Length Modulation
 Cox W
iD  vGS  Vt 2  I D  L  LM L   vDS 
1
 VA  L
2 L 
SAT
LM
I DSAT
 I DSAT 1  L   Cox W
iD  iD  vGS  Vt 2 1   vDS 
1  L  LM  2 L
LM

LM

Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective
channel length (by L).

23
Field Effect Transistors
CCT - UDESC
  Cox W
iD  vGS  Vt 2 1   vDS   Saturation
2 L

Output Resistance:
-1
 i  vDS  1
ro   D   
 vDS vGS  constant 

ID

ro   I D  
1 VA
 VDS  VA
ID

VA is directly proportional to L; thus two devices with the same process, and having channel lengths L1 e L2,
will have Early voltage VA1 and VA2,.
V A1 L1

V A 2 L2
Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.

24
Field Effect Transistors
CCT - UDESC
 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output
resistance models the linear dependence of iD on vDS and is given by ro  VA/ID.

25
Field Effect Transistors
CCT - UDESC
 Resumo das equações para o MOSFET enriquecimento
D D D P-channel S
N-channel ID
G B G G B G
or or
ID
Vtp < 0
Vtn > 0
vDS  0 D
S vDS  0 S S

k n'  μnCox k p'  μ pCox

Region N - Type P - Type

vGS  Vtn vSG  Vtp
Cutoff
iD  0 iD  0
vGS  Vtn and vDS  vGS  Vtn vSG  Vtp and vSD  vSG  Vtp
Triodo
  
 

2
  vDS 2
(Linear) iD  k n' W v  V v  iD  k p
' W
 
vSD
L  GS tn DS 2  L 
v SG Vtp v SD 2 
vGS  Vtn and vDS  vGS  Vtn vSG  Vtp and vSD  vSG  Vtp
2 V  2 VSD 
k n' W
v 
Saturation k p' W
iD  vGS  Vtn  1  DS  iD   V  1 
2 L  VA  2 L SG tp  V 
 A 

26
Field Effect Transistors
CCT - UDESC
 Resumo da característica para o MOSET enriquecimento
D N-channel D
ID

G B G
ou

Vtn > 0
S vDS  0 S
k n'  μnCox

D S
P-channel

G B G
ou
ID
Vtp < 0
S vDS  0 D

k p'  μ pCox
27
Field Effect Transistors
CCT - UDESC
MOSFET - Depleção

The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2:
(a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.
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Field Effect Transistors
CCT - UDESC
 Bias Circuits 1
-  usually neglected ( 1/  =VA)
- Q-point most often located in saturation for analog circuits
R2
VG  VDD
R1  R2 R2
VDD
VGS  VDD  RS I D
VS  RS I D R1  R2
RD
R1
ID
VDS  VDD  RD  RS I D
VG
k n' W
ID  VGS  Vt  ( assuming the MOSFET to be
2
R2 RG 2 L in the saturation region )
RS
2
k n' W  R2  ( two solutions  only one
ID   V  V  RS D
I
2 L  R1  R2
DD t
 is possible )

Ex: VDD = 10 V R1 = 150 k R2 = 100 k RS = 10 k

RD = 50 k k’n(W/L) = 50 A/V2 Vt = 1 V

Solution: ID = 100 A VDS = 4 V

29
Field Effect Transistors
CCT - UDESC
 Bias Circuits 2
VDD VDD Analysis
k n' W
RD
RG
RD
ID  VGS  Vt 
2

ID
2 L
RG
RS
VGS  VDD  RD I D
kn'
I D  VDD  Vt  RD I D 
-VSS
2

Two power supplies are 2

available
VGS  VDS I G  0
VDD
V DD / RD
RD
load line
curve VDS = VGS

V GS1
Q
RG
I V GS2
V GS3
-VSS
A simple circuit utilizing V DS = VGS2 V DD
a current source
30
Field Effect Transistors
CCT - UDESC
 Example: VDD = 5V ;IREF=100A; Q1 and Q2 are
matched ; L=10 m and W=100 m; Vt = 1V ;
k’n=20  A/V2 VA = 10L; Vo=+3V

I D1  I REF  100 
1 100
20 VGS  12
2 10
Q1: I  V converter VGS  2V
Q2: V  I converter 52
R  30 K
If Q2 in saturation 100
v omin  VGS  Vt  vomin  2  1  1V
100V
VA  10 x 10  100V  ro   1M


W 
then 100 μA
Vo 3V
Io
W L
I o    3 μA  3%
 L 2
ro 1M
I REF
1 Basic MOSFET current mirror.

31
Field Effect Transistors
CCT - UDESC
 DC Bias Point
1 W
I D  k n' VGS  Vt 2    0
2 L
VD  VDD  RD I D  VD  VGS  Vt
The signal Current in the Drain Terminal

vGS  VGS  v gs  iD  k n'

1 W
VGS  vgs  Vt 2
2 L
1 W
iD  k n' VGS  Vt 2  kn' W VGS  Vt vgs  1 kn' W vgs2
2 L L 2 L
1 'W 2
k n v gs  k n'
W
VGS  Vt vgs  vgs  2(VGS  Vt )
2 L
 L  
small signal

W
iD  I D  id  id  k n'VGS  Vt vgs
L
i
gm  D
i
 d  k n'
W
VGS  Vt   2kn' W L I D
vGS v V v gs L
 GS
GS

transconductance

Voltage Gain
vD  VDD  RD iD  VDD  RD ( I D  id )  VD  RD id
vd
vd  id RD   g m RD v gs  Av    g m RD
v gs

The operation of the MOSFET as an amplifier. 32

Field Effect Transistors
CCT - UDESC
 (b.1) -Model
(a.1) -Model

(a.2) T-Model (b.2) T-Model

Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation effect); and
(b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
33
Field Effect Transistors
CCT - UDESC
 Example: Vt = 1.5V ; k’n(W/L)=0.25 mA/V2 VA = 50V

DC Analysis

0.25mVD  1.5
1
VGS  VD  I D 
2

2
VD  15  RD I D  15  10K I D
I D  1.06mA and VD  4.4V  Physically Meaningful
g m  0.25m(4.4  1.5)  0.725mA/V
50
ro   47KΩ
1.06m
AC Analysis
vo v v
 g m vi  o i  0
ro // RD // RL RG
Voltage Gain

Av  o   g m  1 ro // RD // RL // RG   3.37 V

v
vi  RG  V
Input Resistance
 vo  4.3vi
ii  vi  vo  RG 
vi
1   
RG  vi  RG
vi RG
Rin    2.33MΩ
ii 4.3

34
Field Effect Transistors
CCT - UDESC
 Body Transcondu ctance
iD
g mb    gm
vBS vGS  constante
v DS  constante

0.1  χ  0.3

Small-signal equivalent-circuit model of a MOSFET in which the body is not connected to the source.
35
Field Effect Transistors
CCT - UDESC
 Basic amplifier configurations with current sources

VDD VDD
VDD
I
I
vo
vo
vI
vo
vI
I
vI
-VSS

Source follower Common-source Common-gate

or common-drain amplifier amplifier
amplifier

36
Field Effect Transistors
CCT - UDESC
 ID2

ID2

Ri   Ro  ro1 // ro 2
Av   g m1 ro1 // ro 2 

The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to determine
the transfer characteristic; and transfer characteristic.
37
Field Effect Transistors
CCT - UDESC
 Example: VDD=10V;Vtn = | Vtp| = 1V ; k’n= 2 k’p= 20 A/V2
(W=100 m; L =10 m |VA|= 100V for both the n and p device)
IREF=100 A.

vO
I REF  I D 2  I D1  100 μA 10
Slope = -100V/V

I D 3  I REF  100 μA 
1 ' W 

k p   VSG  Vtp
2  L 3
 V
2
SG  2.41V
8.59

Bias Point
vOmax  10  (VSG  Vtp )  8.59V
vOmin  VI  Vtn  1V
4.795

VO  vOmax  vOmin  ro1
ro1  ro 2
 vOmin  4.795V

1 ' W 
I D1  I REF  100 μA  k n   VI  Vtn   VI  2V
2

2  L 1
1
W 
g m1  2k   I REF  0.2m A
'
n
 L 1 V
1.96 2 2.04 vI
VA
ro1  ro 2   1MΩ
I REF
^ ^

Av  o   g m1 ro1 // ro 2   100 V
v v o  3.795Vp  v i  40mVp
vi V
Rin    Ro  ro1 // ro 2   0.5MΩ
38
Field Effect Transistors
CCT - UDESC
 vo  1
Av    g m1  g mb1  ro1 // ro 2 
vi  ro1 
Av   g m1  g mb1 ro1 // ro 2 
vi 1  ro 2 
Ri   1  
ii g  g  1  ro1 
m1 mb1
ro1
1  ro 2 
Ri  1  
g m1  g mb1  ro1 
The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

39
Field Effect Transistors
CCT - UDESC
 vo g m1 RS g m1
Av   
vi 1  g m1 RS g  g  1  1
m1 mb1
ro1 ro 2
g m1 1
Av  
g m1  g mb1 1  χ

Ro   1  //  1  // r // r
 o1 o 2
 g m1   g mb1 

Ro   1  //  1  1

 g m1   g mb1  g m1 1  χ 

The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
40
Field Effect Transistors
CCT - UDESC
  W L 1  W L 1
vO  VDD  Vt  V  v

 W L 2 t  W L 2 I
W L 1 1 W L 1
Av   
W L 2 1   2 W L 2

(a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.
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Field Effect Transistors
CCT - UDESC
 vo  1  
Av    g m1   // ro1 // ro 2 
vi  g mb1  

Av  
g m1

W L 1 1
g mb2 W L 2 χ

The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic. 42
Field Effect Transistors
CCT - UDESC
 rDSN  1
 ' W  

 n L
k  VDD  V 
tn 
  n 

Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
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Field Effect Transistors
CCT - UDESC
 rDSP  1
 ' W 

k p   VDD  Vtp 
  L  p 

Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
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Field Effect Transistors
CCT - UDESC
 VIH 
1
5VDD  2Vt 
8
VIL  3VDD  2Vt 
1
8

Noise Margins

NM H  3VDD  2Vt 
1
8
NM L  3VDD  2Vt 
1
8

The voltage transfer characteristic of the CMOS inverter.

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Field Effect Transistors
CCT - UDESC
 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating
point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.
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Field Effect Transistors
CCT - UDESC
 Strong inversion and saturation:

VGS – Vt > 200 mV

g m  2 k W LI D
VA  VDS
ro 
ID
2
C gs  CoxW L
3
(a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the
substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
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Field Effect Transistors
CCT - UDESC
 Io gm

I i sCgs  Cgd 
For physical frequencies s = j, it cam be seen that the magnitude of the current gain
becomes unity at the frequency:
gm
fT 
2πCgs  Cgd 

Determining the short-circuit current gain Io/Ii.

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Field Effect Transistors
CCT - UDESC
 The Junction Field-Effect Transistor
G De pletio n
G De pletio n
re gion
re gion

p
p

p
p
vGS = 0 VP < vGS < 0
S D W'
S D
n W
+- n
i
G

p
p

p
De pletio n
De pletio n
re gion
G G re gion

G De pletio n
re gion

vGS = VP < 0
p

p ( a ) JFET with zero gate-source bias

n
D
( b ) JFET with negative gate-source voltage
S Pinche d-O ff Channe l
+- that is less negative than the pinch-off
voltage VP. Note W’ < W
p ( c ) JFET at pinch-off with VGS = VP
p

De pletio n
G re gion

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Field Effect Transistors
CCT - UDESC
 De pletion
G
re gion

p
vGS < 0

S D
+- n i DS
( a ) JFET with small drain-source
v
DS

De pletion
G re gion

De pletio n
G re gion

p
p

vGS

S D
+- n i DS
( b ) JFET with channel just at
v =v
DS DSP
pinch-off with vDS = vDSP
p

De pletio n
G re gion

The Junction Field-Effect Transistor ( a ) JFET with small drain-source ( b ) JFET with channel just at
pinch-off with vDS = vDSP 50
Field Effect Transistors
CCT - UDESC
 Summary of equations for the JFET
D
S P-channel
iD N-channel G

G VP  0 VP  0
vGSmin  0
iD
vGSmax  0
S D

Region N - Type P - Type

vGS  VP vGS  VP
Cutoff
iD  0 iD  0
VP  vGS  0 and vDS  vGS  VP 0  vGS  VP and vDS  vGS  VP
Triodo
  v v  v 
2
   v v  v 
2

(Linear) iD  I DSS 21  GS
 DS
  DS
  iD  I DSS 21  GS
 DS
  DS
 
  VP   VP  VP     VP   VP  VP  
VP  vGS  0 and vDS  vGS  VP 0  vGS  VP and vDS  vGS  VP
 VDS   VDS 
2 2
Saturation  v   v 
iD  I DSS 1  GS  1   iD  I DSS 1  GS  1  
 VA   VA 
 VP    VP  

 2 I DSS  VGS   2 I DSS  I D VA

g m   1 
   


  ro 
 VP  VP   VP  I DSS ID

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Field Effect Transistors
CCT - UDESC
 2.20e-4
Linea r VGS = 0 V
2.00e-4 Re gion I DSS

1.80e-4 Pinch-off Locus

Drain-Source Current (A)

D 1.60e-4 S
+ Pinch-off Region
v SG (Satura tion)
i DS 1.40e-4
+ + V = -1 V
1.20e-4 - GS
G v v
DS SD
1.00e-4
G -
+ - 8.00e-5
i SD
vGS
6.00e-5 V GS = -2 V
- S D
4.00e-5
n-channel JFET p-channel JFET VGS Š V
P
2.00e-5 VGS = -3 V

0.00e+0
0 2 4 6 8 10 12

Drain-Source Vo ltage (V)

Output characteristics for a JFET with IDSS = 200 A and VP = -4V

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Field Effect Transistors
CCT - UDESC
 1.50e-3

Drain-Source Current (A) 1.00e-3 I DSS

5.00e-4

0.00e+0
V
P

-5.00e -4
-6 -5 -4 -3 -2 -1 0 1 2 3

Gate-Source Voltage (V)

Transfer characteristic for a saturated JFET with IDSS = 1 mA and VP = -3.5V

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Field Effect Transistors
CCT - UDESC
 When to use JFETs
 JFET have much higher input impedances
and much lower input currents than BJTs.
 BJTs are more linear than JFETs.
 The gain of a BJT is much higher than that
of a JFET.

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Field Effect Transistors
CCT - UDESC
 JFET (Example)
The JFET in the circuit below has VP=-3V, IDSS=9mA, For the JFET circuit designed in the former exercise,
and =0. Find the values of all resistors so that VG=5V, let an input signal vi be capacitively coupled to the
ID=4mA, and VD=11V. Design for 0.05mA in the gate, a large bypass capacitor be connected between
voltage divider. the source and ground, and the output signal vo be
taken from the drain through a large coupling
capacitor. The resulting common-source amplifier is
shown below. Calculate gm and ro (assuming
VA=100V). Also find Ri and Ro.

R G2
5  5  VS 
2
15
R G2  R G1 4m  9m1  
  3 
15  2x9m  4m
 0.05m Saturation
g m     4m A  ro  100  25KΩ

R G2  R G1 VS'  6V  VS''  10V   3  9m
V 4m
 
R G1  200KΩ Ok

R G2  100KΩ R S  1.5KΩ
  g m ro // R D   3.85 V
vo
15  11 Av 
V
RD   1KΩ vi
4m Ro  ro // R D  962  Ri  R G1//R G2  66.7KΩ
55
Field Effect Transistors
CCT - UDESC
 References
 SEDRA. Adel S. e SMITH, Kenneth C. Microelectronic
Circuits. Oxford University Press.
 BOYLESTAD, Robert e NASHELSKY, Louis.
Dispositivos Eletrônicos e Teoria de Circuitos. Prentice
Hall do Brasil.
 SZE, S. M. Physics of Semiconductor Devices. John Wiley
& Sons.
 SCHILLING, Donald L. e BELOVE, Charles. Circuitos
Eletrônicos Discretos e Integrados. Guanabara Dois.
 COMER, David J. Introduction to Semiconductor
Circuits Design. Addison Wesley Publishing Company.
 MALVINO, Albert P. Eletrônica. Volume I. McGraw-Hill.

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Field Effect Transistors
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